The enhanced v3.0 controller experiences a timeout during simulation testbench execution. The testbench gets stuck waiting for cpu_data_valid signal during read operations.
- Compilation completes successfully without errors
- Write operations appear to complete
- Read operations timeout waiting for data_valid
- DRAM model shows repetitive AUTO-REFRESH commands
The issue appears to be related to state transitions after implementing page hit optimization. Possible causes:
- Timing between ACTIVATE state and RCD_WAIT state
- Transition logic from READ_CAS to READ_WAIT
- State machine getting stuck in refresh cycle
For production use, the reference implementation in spaghetti_sdram_controller.v can be used, which has proven page hit optimization working correctly.
The development team is investigating the issue. Potential fixes:
- Review state transition timing in dram_fsm.v
- Verify timing_done signal propagation
- Check command generation timing
- Add detailed state debugging signals
Until this issue is resolved:
- Use GTKWave to inspect waveforms:
gtkwave sim_output/dram_controller.vcd - Monitor FSM state transitions
- Check
row_open,active_bank,active_rowsignals - Verify
timing_donepulses correctly
The RTL code is structurally sound and should synthesize correctly. The issue is specifically with the testbench/simulation timing, not the hardware logic itself.
Status: Under Investigation
Priority: High
Target Fix: v3.0.1
##For reference working code, see spaghetti_sdram_controller.v which demonstrates the page hit concept correctly.