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37 lines (32 loc) · 1.27 KB
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/******************************************************************************
* Copyright (c) 2020 ASIX Electronic Corporation All rights reserved.
*
* This is unpublished proprietary source code of ASIX Electronic
* Corporation
*
* The copyright notice above does not evidence any actual or intended
* publication of such source code.
*****************************************************************************/
/*
* This file is part of the Xilinx DMA IP Core driver for Linux
*
* Copyright (c) 2016-present, Xilinx, Inc.
* All rights reserved.
*
* This source code is licensed under both the BSD-style license (found in the
* LICENSE file in the root directory of this source tree) and the GPLv2 (found
* in the COPYING file in the root directory of this source tree).
* You may select, at your option, one of the above-listed licenses.
*/
#ifndef __XDMA_VERSION_H__
#define __XDMA_VERSION_H__
#define DRV_MOD_MAJOR 1
#define DRV_MOD_MINOR 0
#define DRV_MOD_PATCHLEVEL 1
#define DRV_MODULE_VERSION \
__stringify(DRV_MOD_MAJOR) "." \
__stringify(DRV_MOD_MINOR) "." \
__stringify(DRV_MOD_PATCHLEVEL)
#define DRV_MOD_VERSION_NUMBER \
((DRV_MOD_MAJOR)*1000 + (DRV_MOD_MINOR)*100 + DRV_MOD_PATCHLEVEL)
#endif /* ifndef __XDMA_VERSION_H__ */