ALU.vhd.bak

library IEEE;
use ieee.std_logic_1164.all;

entity ALU is 
	PORT(
	A,B : IN STD_LOGIC(31 DOWNTO 0);
	clk :IN STD_LOGIC;
	C : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
	cs : IN (STD_LOGIC_VECTOR 3 DOWNTo 0)
);
END ALU;

architecture behavioral of ALU is 
begin
	process(clk)
	variable temp : std_logic_vector (63 downto 0);
		begin
		if (rising_edge(clk)) then
			case cs is 
				when "0000" => temp:= A + B; --add
				when "0001" => temp:= A - B; --sub
				when "0010" --mul
				when "0011" --div
				when "0100" => temp:= A and B; --and
				when "0101" => temp:= A or B; --or
				when "0110" --shr
				when "0111" --shl
				when "1000" --ror
				when "1001" --rol
				when "1010" --neg
				when "1011" => temp := not A; --not
				when Others => NULL;
						
			end case
			C <= temp;
		end if;
				
		end process;
end behavioral;