feat: add pegasus

feat: replace verilog generation with bdb

Author: shirohasuki

api/steps/pegasus/01_verilog_api_step.py

@@ -0,0 +1,35 @@
+import asyncio
+from utils.event_common import wait_for_result
+from utils.path import get_buckyball_path
+
+
+config = {
+    "type": "api",
+    "name": "Pegasus Verilog",
+    "description": "Generate SystemVerilog for Pegasus FPGA (PegasusHarness + ChipTop)",
+    "path": "/pegasus/verilog",
+    "method": "POST",
+    "emits": ["pegasus.verilog"],
+    "flows": ["pegasus"],
+}
+
+
+async def handler(req, context):
+    bbdir = get_buckyball_path()
+    body = req.get("body") or {}
+
+    # Default config for Pegasus; allow override
+    config_name = body.get("config", "sims.pegasus.PegasusConfig")
+
+    data = {
+        "config": config_name,
+        "output_dir": body.get("output_dir", f"{bbdir}/arch/build/pegasus/"),
+    }
+
+    await context.emit({"topic": "pegasus.verilog", "data": data})
+
+    while True:
+        result = await wait_for_result(context)
+        if result is not None:
+            return result
+        await asyncio.sleep(1)

api/steps/pegasus/01_verilog_event_step.py

@@ -0,0 +1,81 @@
+import os
+import sys
+
+utils_path = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", ".."))
+if utils_path not in sys.path:
+    sys.path.insert(0, utils_path)
+
+from utils.path import get_buckyball_path
+from utils.stream_run import stream_run_logger
+from utils.event_common import check_result
+
+
+config = {
+    "type": "event",
+    "name": "make pegasus verilog",
+    "description": "Generate SystemVerilog from Chisel using ElaboratePegasus",
+    "subscribes": ["pegasus.verilog"],
+    "emits": [],
+    "flows": ["pegasus"],
+}
+
+
+async def handler(data, context):
+    bbdir = get_buckyball_path()
+    arch_dir = f"{bbdir}/arch"
+    build_dir = data.get("output_dir", f"{bbdir}/arch/build/pegasus/")
+
+    config_name = data.get("config", "sims.pegasus.PegasusConfig")
+    context.logger.info(f"[pegasus] Elaborating config: {config_name}")
+    context.logger.info(f"[pegasus] Output directory: {build_dir}")
+
+    os.makedirs(build_dir, exist_ok=True)
+
+    # Use ElaboratePegasus (not the generic sims.verilator.Elaborate)
+    # ElaboratePegasus instantiates PegasusHarness directly, bypassing TestHarness
+    command = (
+        f"mill -i __.test.runMain sims.pegasus.ElaboratePegasus "
+        f"--disable-annotation-unknown "
+        f"-strip-debug-info "
+        f"-O=debug "
+        f"--split-verilog "
+        f"-o={build_dir}"
+    )
+
+    result = stream_run_logger(
+        cmd=command,
+        logger=context.logger,
+        cwd=arch_dir,
+        stdout_prefix="pegasus verilog",
+        stderr_prefix="pegasus verilog",
+    )
+
+    # Clean up stray top-level file if emitted next to arch/
+    for stray in ["PegasusHarness.sv", "TestHarness.sv"]:
+        stray_path = f"{arch_dir}/{stray}"
+        if os.path.exists(stray_path):
+            os.remove(stray_path)
+
+    # Copy generated SV files to pegasus/vivado/generated/ for Vivado build
+    vivado_gen_dir = f"{bbdir}/pegasus/vivado/generated"
+    if result.returncode == 0 and os.path.isdir(build_dir):
+        import shutil
+        os.makedirs(vivado_gen_dir, exist_ok=True)
+        sv_files = [f for f in os.listdir(build_dir) if f.endswith(".sv") or f.endswith(".v")]
+        for f in sv_files:
+            shutil.copy2(os.path.join(build_dir, f), os.path.join(vivado_gen_dir, f))
+        context.logger.info(f"[pegasus] Copied {len(sv_files)} files to {vivado_gen_dir}")
+
+    success_result, failure_result = await check_result(
+        context,
+        result.returncode,
+        continue_run=False,
+        extra_fields={
+            "task": "verilog",
+            "output_dir": build_dir,
+            "vivado_gen_dir": vivado_gen_dir,
+            "top_module": "PegasusHarness",
+        },
+    )
+
+    return

api/steps/verilator/02_verilog_event_step.py

@@ -52,7 +52,7 @@ async def handler(data, context):
             f"mill -i __.test.runMain sims.verify.BallTopMain {data.get('balltype')} "
         )
     else:
-        command = f"mill -i __.test.runMain sims.verilator.Elaborate {config_name} "
+        command = f"mill -i __.test.runMain sims.verilator.BBSimElaborate {config_name} "
 
     command += "--disable-annotation-unknown -strip-debug-info -O=debug "
     command += f"--split-verilog -o={build_dir}"
@@ -66,7 +66,7 @@ async def handler(data, context):
     )
 
     # Remove unwanted file
-    topname_file = f"{arch_dir}/TestHarness.sv"
+    topname_file = f"{arch_dir}/BBSimHarness.sv"
     if os.path.exists(topname_file):
         os.remove(topname_file)
 

api/steps/verilator/03_build_event_step.py

@@ -17,7 +17,7 @@
     "name": "make build",
     "description": "build verilator executable",
     "subscribes": ["verilator.build"],
-    "emits": ["verilator.sim", "verilator.cosim"],
+    "emits": ["verilator.sim"],
     "flows": ["verilator"],
 }
 
@@ -26,15 +26,11 @@ async def handler(data, context):
     bbdir = get_buckyball_path()
     arch_dir = f"{bbdir}/arch"
     build_dir = f"{arch_dir}/build"
-    waveform_dir = f"{arch_dir}/waveform"
-    log_dir = f"{arch_dir}/log"
-    cosim = data.get("cosim", False)
     coverage = data.get("coverage", False)
 
-    # ==================================================================================
-    # Execute operation
     # ==================================================================================
     # Find sources
+    # ==================================================================================
     vsrcs = glob.glob(f"{build_dir}/**/*.v", recursive=True) + glob.glob(
         f"{build_dir}/**/*.sv", recursive=True
     )
@@ -47,33 +43,71 @@ async def handler(data, context):
         + glob.glob(f"{build_dir}/**/*.cpp", recursive=True)
     )
 
-    # Setup paths: fesvr from bebop/host/spike/riscv-isa-sim (install/include, install/lib)
-    bebop_isa_sim = f"{bbdir}/bebop/host/spike/riscv-isa-sim"
+    # Exclude testchipip's SimDRAM.cc — our SimDRAM_bb.cc overrides memory_init
+    csrcs = [f for f in csrcs if not f.endswith("SimDRAM.cc") or "src/csrc" in f]
+
+    # Patch fesvr includes out of build/mm.h and build/mm.cc.
+    # These files are auto-copied from testchipip by Verilator as SimDRAM.v
+    # companion sources. They reference fesvr/memif.h which we don't have
+    # (fesvr is removed). The memif_t dependency was only used by SimDRAM.cc's
+    # load_elf — our SimDRAM_bb.cc doesn't use it.
+    for patch_file in [f"{build_dir}/mm.h", f"{build_dir}/mm.cc"]:
+        if os.path.exists(patch_file):
+            with open(patch_file, "r") as f:
+                content = f.read()
+            patched = "\n".join(
+                line for line in content.splitlines()
+                if "fesvr/memif.h" not in line and "fesvr/elfloader.h" not in line
+            )
+            if patched != content:
+                with open(patch_file, "w") as f:
+                    f.write(patched)
+                context.logger.info(f"Patched fesvr includes from {patch_file}")
+
+    topname = "BBSimHarness"
+
+    # ==================================================================================
+    # Build flags
+    # ==================================================================================
+    dramsim2_dir = f"{arch_dir}/thirdparty/chipyard/tools/DRAMSim2"
+
+    # Find readline headers/libs in nix store (not in standard paths under nix)
+    rl_headers = glob.glob("/nix/store/*readline*-dev/include/readline/readline.h")
+    readline_inc = os.path.dirname(os.path.dirname(rl_headers[0])) if rl_headers else ""
+    rl_libs = glob.glob("/nix/store/*readline*/lib/libreadline.so")
+    readline_lib = os.path.dirname(rl_libs[0]) if rl_libs else ""
+
+    # Find zlib headers/libs in nix store
+    zlib_headers = glob.glob("/nix/store/*zlib*-dev/include/zlib.h")
+    if not zlib_headers:
+        zlib_headers = glob.glob("/nix/store/*zlib*/include/zlib.h")
+    zlib_inc = os.path.dirname(zlib_headers[0]) if zlib_headers else ""
+    zlib_libs = glob.glob("/nix/store/*zlib*/lib/libz.so")
+    zlib_lib = os.path.dirname(zlib_libs[0]) if zlib_libs else ""
+
     inc_paths = [
-        os.environ.get("RISCV", "") + "/include" if os.environ.get("RISCV") else "",
-        f"{arch_dir}/thirdparty/chipyard/tools/DRAMSim2",
-        f"{bebop_isa_sim}/install/include",
+        dramsim2_dir,
         build_dir,
         f"{arch_dir}/src/csrc/include",
     ]
+    if readline_inc:
+        inc_paths.append(readline_inc)
+    if zlib_inc:
+        inc_paths.append(zlib_inc)
     inc_flags = " ".join([f"-I{p}" for p in inc_paths if p])
 
-    if cosim:
-        topname = "ToyBuckyball"
-    else:
-        topname = "TestHarness"
+    # -DBBSIM: selects VBBSimHarness in bdb.h / main.cc
+    cflags = f"{inc_flags} -DBBSIM -DTOP_NAME='\"V{topname}\"' -std=c++17"
 
-    cflags = f"{inc_flags} -DTOP_NAME='\"V{topname}\"' -std=c++17 "
-    if cosim:
-        cflags += " -DCOSIM"
     ldflags = (
-        f"-lreadline -ldramsim -lfesvr -lstdc++ "
-        f"-L{bebop_isa_sim}/install/lib "
+        f"-lreadline -ldramsim -lstdc++ -lz "
         f"-L{bbdir}/result/lib "
-        f"-L{arch_dir}/thirdparty/chipyard/tools/DRAMSim2 "
-        f"-L{arch_dir}/thirdparty/chipyard/toolchains/riscv-tools/riscv-isa-sim/build "
-        f"-L{arch_dir}/thirdparty/chipyard/toolchains/riscv-tools/riscv-isa-sim/build/lib"
+        f"-L{dramsim2_dir} "
     )
+    if readline_lib:
+        ldflags += f"-L{readline_lib} -Wl,-rpath,{readline_lib} "
+    if zlib_lib:
+        ldflags += f"-L{zlib_lib} -Wl,-rpath,{zlib_lib} "
 
     obj_dir = f"{build_dir}/obj_dir"
     subprocess.run(f"rm -rf {obj_dir}", shell=True)
@@ -82,23 +116,26 @@ async def handler(data, context):
     sources = " ".join(vsrcs + csrcs)
     jobs = data.get("jobs", "")
 
-    # Fix nix runtime library paths: embed rpath so binary finds nix libstdc++/glibc
+    # Fix nix runtime library paths
     libstdcpp_path = subprocess.run(
         "g++ -print-file-name=libstdc++.so", shell=True, capture_output=True, text=True
     ).stdout.strip()
     if libstdcpp_path and "/" in libstdcpp_path:
         nix_lib_dir = os.path.dirname(os.path.realpath(libstdcpp_path))
         ldflags += f" -Wl,-rpath,{nix_lib_dir}"
 
-    # Enable ccache for verilator C++ compilation via OBJCACHE
+    # Enable ccache if available
     if subprocess.run("command -v ccache", shell=True, capture_output=True).returncode == 0:
         os.environ["OBJCACHE"] = "ccache"
 
-    # Build acceleration: lld for faster linking (available in nix env)
+    # Use lld for faster linking if available
     use_lld = subprocess.run("command -v ld.lld", shell=True, capture_output=True).returncode == 0
     if use_lld:
         ldflags += " -fuse-ld=lld"
 
+    # ==================================================================================
+    # Run verilator
+    # ==================================================================================
     verilator_cmd = (
         f"verilator -MMD -cc --vpi --trace -O3 --x-assign fast --x-initial fast --noassert -Wno-fatal "
         f"--trace-fst --trace-threads 1 --output-split 10000 --output-split-cfuncs 100 "
@@ -148,17 +185,9 @@ async def handler(data, context):
         extra_fields={"task": "build"},
     )
 
-    # ==================================================================================
-    # Continue routing
-    # ==================================================================================
     if data.get("from_run_workflow"):
-        if cosim:
-            await context.emit(
-                {"topic": "verilator.cosim", "data": {**data, "task": "run"}}
-            )
-        else:
-            await context.emit(
-                {"topic": "verilator.sim", "data": {**data, "task": "run"}}
-            )
+        await context.emit(
+            {"topic": "verilator.sim", "data": {**data, "task": "run"}}
+        )
 
     return