Support for interrupts

[DavePearce]

Need to add support for interrupts. This can done by checking whether an interrupt is triggered before executing an instruction, and the Global Interrupt Enable flag is set.

[DavePearce]

One of the big challenges is how to determine when an interrupt has occurred. Always, the lowest interrupt vector is triggered first. There are some registers related to interrupt handling, such as MCUCR, GIFR and GIMSK and PCMSK. These seem primarily related to external interrupts which are detected using INT0 and PCINT0. Other relevant registers are the TIFR which is the Timer/Counter Interrupt Flag Register. This is used to signal when a timer-related interrupt has occurred.

As an example, for the INT0 interrupt this is the process:

• Depending on MCUCR, an event (e.g. pin LOW) occurs which might trigger interrupt

• If INT0 is set in GIMSK, then interrupt is enabled and INTF0 flag in GIFR is set.

• Upon next instruction GIFR is checked and, if set, then interrupts are disabled, the PC is pushed on the stack and we branch to the interrupt vector. At some point, the corresponding bit in GIFR is unset by the hardware.

One problem is that the exact mechanism for determining which interrupt vector is triggered is CPU dependent. For example, ATtiny85 has 15 vectors whereas ATmega328 as 26. Realistically, what we want is a "virtual" bit for each possible vector indicating the vector is set. Then, can configure this virtual register differently for different hardware.

[DavePearce]

Have now added concept of an interrupt table which provides a mapping from status registers to the interrupt dispatch mechanism. That seems to work quite well. However, I haven't connected any interrupt generators yet, or really tested it!!!