I feel like there's more to be learnt (after #82 and the NBA irq delay rom) about how the various registers that affect IRQ latch and affect the synchronizer.
I'd like a test which proves which cycle IME, IE and CPSR being enabled/disabled on affects an IRQ going through. I think this should be achievable with a TM0 IRQ, code in IWRAM and nop spam followed by a set instruction IME, IE or CPSR)
Hypothesis is that IME,IE only affect entrance into the synchronizer but CPSR affects the IRQ all the way through it until the last cycle. But then the question is how long it takes each of those registers to latch at all.
So need to test IRQ firing when IME/IE are set on the previous cycle then test IRQ firing when IME/IE are unset on various cycles, then need to test same for CPSR.
I feel like there's more to be learnt (after #82 and the NBA irq delay rom) about how the various registers that affect IRQ latch and affect the synchronizer.
I'd like a test which proves which cycle IME, IE and CPSR being enabled/disabled on affects an IRQ going through. I think this should be achievable with a TM0 IRQ, code in IWRAM and nop spam followed by a set instruction IME, IE or CPSR)
Hypothesis is that IME,IE only affect entrance into the synchronizer but CPSR affects the IRQ all the way through it until the last cycle. But then the question is how long it takes each of those registers to latch at all.
So need to test IRQ firing when IME/IE are set on the previous cycle then test IRQ firing when IME/IE are unset on various cycles, then need to test same for CPSR.