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Retract Step-1 'recall 5/5 / 1.0x AR' as Gemma-4 native behaviour, not architecture evidence
Per 2026-06-13 directive: Step-1 / native-cache recall comes from Gemma-4's native full-attn layers + sliding eviction, never exercising f_theta/proposer KV restoration -> structurally incapable of testing the architecture. Forbidden for architecture validation; re-validate on a pure sliding-window model (Qwen3). See ADR 0012 revision 2026-06-13. Co-authored-by: FluffyAIcode <FluffyAIcode@users.noreply.github.com>
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docs/mlx-port-lessons.md

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# Porting the K3 GPU beta (#107) to MLX — lessons & plan
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> ## ⛔ RETRACTION (2026-06-13) — Step-1 / native-cache "recall 5/5 / 1.0× AR" is NOT architecture evidence
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>
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> The Step-1 incremental path and the native-cache path get their recall from
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> **Gemma-4's native retained full-attention layers + native sliding-window
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> eviction** — they **never exercise f_θ or proposer K/V restoration** (ADR 0008
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> §11). So every "recall 5/5 / 1.0× AR / collapse fixed" claim about Step-1 in
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> this doc is **Gemma-4 native behaviour, not evidence the K/V-Restoration
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> architecture works**. The path is structurally **incapable of failing in a way
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> that tests the architecture** (the full-attn coupon always carries recall).
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>
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> **Step-1 / native-cache bypass is forbidden for any architecture-validation
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> attempt** (2026-06-13 directive; ADR 0012 revision). The bounded-memory +
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> recall *architecture* claim is **unvalidated on a falsifiable model** and must
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> be re-validated on a **pure sliding-window model (Qwen3, K1/K2)** where recall
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> is impossible without proposer/f_θ restoration. Read everything below through
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> this retraction: the throughput/memory plumbing notes are still useful, but
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> the Step-1 *results* are not architectural validation.
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Audience: whoever ports the validated CUDA restored-verifier engine
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(`inference_engine/v04/…`, PR #107) to the Apple-Silicon MLX backend
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(`inference_engine/backends/mlx/…`). The current MLX blocker is **decode

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