ck37-core/Makefile at main · FormerLab/ck37-core · GitHub

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# ============================================================
# CK37 Soft-Core — Makefile
# ============================================================
# Targets:
#   make sim      — assemble kernel + run iverilog testbench
#   make labels   — regenerate nav/nav_labels.vh only
#   make synth    — Yosys synthesis (check LUT count)
#   make pnr      — nextpnr place-and-route (OrangeCrab ECP5-25F)
#   make bit      — generate .bit bitstream (ecppack)
#   make flash    — flash to OrangeCrab via DFU (ecpdfu)
#   make clean    — remove build artefacts
# ============================================================

# ─── Tools ───────────────────────────────────────────────────
IVERILOG   = iverilog
VVP        = vvp
PYTHON     = python3
YOSYS      = yosys
NEXTPNR    = nextpnr-ecp5
ECPPACK    = ecppack
ECPDFU     = ecpdfu

# ─── Sources ─────────────────────────────────────────────────
RTL_SRCS   = rtl/ck37_cpu.v \
             rtl/ck37_mem.v \
             rtl/ck37_aio.v \
             rtl/ck37_dio.v \
             rtl/ck37_clk_irq.v \
             rtl/ck37_top.v \
             syn/ck37_syn_top.v

SIM_SRCS   = sim/nav_tb.v rtl/ck37_cpu.v

ASM_SRC    = nav/nav_kernel.asm
HEX        = nav/nav_kernel.hex
LST        = nav/nav_kernel.lst
LABELS_VH  = nav/nav_labels.vh

LPF        = syn/ck37_orangecrab.lpf
TOP        = ck37_syn_top

# ─── Build outputs ───────────────────────────────────────────
BUILD      = build
JSON       = $(BUILD)/ck37.json
ROUTED     = $(BUILD)/ck37_routed.config
BITSTREAM  = $(BUILD)/ck37.bit

# ─── Phony targets ───────────────────────────────────────────
.PHONY: all sim labels synth pnr bit flash clean

all: sim

# ─── Assembly ────────────────────────────────────────────────
$(HEX) $(LST): $(ASM_SRC)
	$(PYTHON) asm/ck37asm.py $(ASM_SRC) --memh -o $(HEX)
	$(PYTHON) asm/ck37asm.py $(ASM_SRC) -o $(LST)

labels: $(ASM_SRC)
	$(PYTHON) asm/gen_labels.py

$(LABELS_VH): $(HEX)
	$(MAKE) labels

# ─── Simulation ──────────────────────────────────────────────
SIM_BIN    = build/nav_tb

sim: $(HEX) $(LABELS_VH)
	@mkdir -p $(BUILD)
	$(IVERILOG) -g2012 -I. -o $(SIM_BIN) $(SIM_SRCS)
	cd sim && $(VVP) ../$(SIM_BIN)

# ─── Synthesis (Yosys) ───────────────────────────────────────
# LFE5U-25F = ECP5 25K LUT device
$(JSON): $(RTL_SRCS) $(HEX)
	@mkdir -p $(BUILD)
	$(YOSYS) -p "read_verilog -sv -D SYNTHESIS $(RTL_SRCS); synth_ecp5 -top $(TOP) -json $(JSON)" \
		2>&1 | tee $(BUILD)/yosys.log
	@echo ""
	@echo "=== Synthesis summary ==="
	@grep -A 12 'Printing statistics' $(BUILD)/yosys.log | tail -12

synth: $(JSON)

# ─── Place and Route (nextpnr-ecp5) ──────────────────────────
$(ROUTED): $(JSON) $(LPF)
	$(NEXTPNR) \
	  --25k \
	  --package CSFBGA285 \
	  --speed 8 \
	  --json $(JSON) \
	  --lpf $(LPF) \
	  --textcfg $(ROUTED) \
	  --freq 10 \
	  --lpf-allow-unconstrained \
	  2>&1 | tee $(BUILD)/nextpnr.log
	@echo ""
	@echo "=== Timing summary ==="
	@grep -E 'Max frequency|Slack|PASS|FAIL' $(BUILD)/nextpnr.log | tail -10

pnr: $(ROUTED)

# ─── Bitstream (ecppack) ─────────────────────────────────────
$(BITSTREAM): $(ROUTED)
	$(ECPPACK) --compress $(ROUTED) $(BITSTREAM)
	@ls -lh $(BITSTREAM)

bit: $(BITSTREAM)

# ─── Flash (DFU bootloader on OrangeCrab) ────────────────────
flash: $(BITSTREAM)
	$(ECPDFU) --vid 1209 --pid 5af0 $(BITSTREAM)

# ─── Clean ───────────────────────────────────────────────────
clean:
	rm -rf $(BUILD)
	rm -f sim/nav_tb.vcd