GATE CHECKPOINT: Phase 3 - epi-meter Breadboard

[Franzabner]

Phase 3 Gate Checkpoint (CRITICAL PATH)

Weeks 2-4 | Must pass before Phase 6 (PCB Design)

• Metering IC communicates over SPI: device ID reads correctly
• CT clamp + burden resistor produces measurable signal
• epi-meter reads within 2% of reference meter on known load
• Pi 5 power trace correlates with CPU load changes
• JSON output matches result schema format
• Firmware committed to epi-meter repo
• First real power trace CSV exported for epi-bench