From dc18d769827819afdc7f976772e6242ca80508eb Mon Sep 17 00:00:00 2001 From: Liu Yihua Date: Mon, 4 Jul 2022 00:18:36 +0800 Subject: [PATCH 1/3] Fix: typo in output of extio Fix typo in output of extio (IO Voltage Margin) --- extio.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/extio.cc b/extio.cc index 382a7a0..c1607a8 100644 --- a/extio.cc +++ b/extio.cc @@ -500,7 +500,7 @@ void Extio::extio_eye() printf("IO Timing Margin (ps) = "); cout << io_tmargin <data_arr_ram_cell_tech_type == 3) { - cout << "\n---------- CACTI (version "<< VER_MAJOR_CACTI <<"."<< VER_MINOR_CACTI<<"."VER_COMMENT_CACTI + cout << "\n---------- CACTI (version "<< VER_MAJOR_CACTI <<"."<< VER_MINOR_CACTI<<"." VER_COMMENT_CACTI << " of " << VER_UPDATE_CACTI << "), Uniform Cache Access " << "Logic Process Based DRAM Model ----------\n"; } else if (g_ip->data_arr_ram_cell_tech_type == 4) { - cout << "\n---------- CACTI (version "<< VER_MAJOR_CACTI <<"."<< VER_MINOR_CACTI<<"."VER_COMMENT_CACTI + cout << "\n---------- CACTI (version "<< VER_MAJOR_CACTI <<"."<< VER_MINOR_CACTI<<"." VER_COMMENT_CACTI << " of " << VER_UPDATE_CACTI << "), Uniform" << "Cache Access Commodity DRAM Model ----------\n"; } else { - cout << "\n---------- CACTI (version "<< VER_MAJOR_CACTI <<"."<< VER_MINOR_CACTI<<"."VER_COMMENT_CACTI + cout << "\n---------- CACTI (version "<< VER_MAJOR_CACTI <<"."<< VER_MINOR_CACTI<<"." VER_COMMENT_CACTI << " of " << VER_UPDATE_CACTI << "), Uniform Cache Access " "SRAM Model ----------\n"; } diff --git a/memcad.cc b/memcad.cc index 64bf32a..0f807ce 100644 --- a/memcad.cc +++ b/memcad.cc @@ -163,7 +163,7 @@ void find_all_channels(MemCadParameters * memcad_params) } } - if( (current_dimm_model== JUST_RDIMM) || (current_dimm_model== ALL) + if( ((current_dimm_model== JUST_RDIMM) || (current_dimm_model== ALL)) && ((d1==0) || (MemoryParameters::cost[current_io_type][1][d1-1]same_bw_in_bob) { sort(memcad_all_channels->begin(), memcad_all_channels->end(), compare_channels_bw); - vector start_index; start_index.push_back(0); + vector start_index; vector end_index; - int last_bw =(*memcad_all_channels)[0]->bandwidth; + int last_bw = 0; + if(memcad_all_channels->size() > 0){ + start_index.push_back(0); + last_bw =(*memcad_all_channels)[0]->bandwidth; + } for(unsigned int i=0;i< memcad_all_channels->size();i++) { if(last_bw!=(*memcad_all_channels)[i]->bandwidth) diff --git a/parameter.cc b/parameter.cc index 3300b95..7ab7b56 100644 --- a/parameter.cc +++ b/parameter.cc @@ -1621,15 +1621,15 @@ DynamicParameter::init_CAM() // calculate wire parameters - double c_b_metal = cell.h * wire_local.C_per_um; + //double c_b_metal = cell.h * wire_local.C_per_um; // double C_bl; - c_b_metal = cam_cell.h * wire_local.C_per_um;//IBM and SUN design, SRAM array uses dummy cells to fill the blank space due to mismatch on CAM-RAM + //c_b_metal = cam_cell.h * wire_local.C_per_um;//IBM and SUN design, SRAM array uses dummy cells to fill the blank space due to mismatch on CAM-RAM V_b_sense = (0.05 * g_tp.sram_cell.Vdd > VBITSENSEMIN) ? 0.05 * g_tp.sram_cell.Vdd : VBITSENSEMIN; deg_bl_muxing = 1;//FA fix as 1 // "/ 2.0" below is due to the fact that two adjacent access transistors share drain // contacts in a physical layout - double Cbitrow_drain_cap = drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / 2.0;//TODO: comment out these two lines + //double Cbitrow_drain_cap = drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / 2.0;//TODO: comment out these two lines // C_bl = num_r_subarray * (Cbitrow_drain_cap + c_b_metal); dram_refresh_period = 0; @@ -1782,15 +1782,15 @@ DynamicParameter::init_FA() cell.w = g_tp.sram.b_w + 2 * wire_local.pitch * (g_ip->num_rw_ports -1 + (g_ip->num_rd_ports - g_ip->num_se_rd_ports) + g_ip->num_wr_ports) + g_tp.wire_local.pitch * g_ip->num_se_rd_ports + 2 * wire_local.pitch*(g_ip->num_search_ports-1); - double c_b_metal = cell.h * wire_local.C_per_um; + //double c_b_metal = cell.h * wire_local.C_per_um; // double C_bl; - c_b_metal = cam_cell.h * wire_local.C_per_um;//IBM and SUN design, SRAM array uses dummy cells to fill the blank space due to mismatch on CAM-RAM + //c_b_metal = cam_cell.h * wire_local.C_per_um;//IBM and SUN design, SRAM array uses dummy cells to fill the blank space due to mismatch on CAM-RAM V_b_sense = (0.05 * g_tp.sram_cell.Vdd > VBITSENSEMIN) ? 0.05 * g_tp.sram_cell.Vdd : VBITSENSEMIN; deg_bl_muxing = 1;//FA fix as 1 // "/ 2.0" below is due to the fact that two adjacent access transistors share drain // contacts in a physical layout - double Cbitrow_drain_cap = drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / 2.0;//TODO: comment out these two lines + //double Cbitrow_drain_cap = drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / 2.0;//TODO: comment out these two lines // C_bl = num_r_subarray * (Cbitrow_drain_cap + c_b_metal); dram_refresh_period = 0; From 106de4b57c4ba490bdd0f18a94c015f6a9be9d4d Mon Sep 17 00:00:00 2001 From: Jaime Roelandts Date: Fri, 28 Mar 2025 10:14:51 +0100 Subject: [PATCH 3/3] Changed double backed to integer division as this is probably more correct. (Marking anyway for the compiler warnings) --- extio_technology.cc | 82 ++++++++++++++++++++++----------------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/extio_technology.cc b/extio_technology.cc index 56d5df8..b391219 100644 --- a/extio_technology.cc +++ b/extio_technology.cc @@ -268,9 +268,9 @@ int IOTechParam::frequnecy_index(Mem_IO_type type) IOTechParam::IOTechParam(InputParameter * g_ip) { - num_mem_ca = g_ip->num_mem_dq * ((double)g_ip->num_dq/g_ip->mem_data_width); - num_mem_clk = g_ip->num_mem_dq * - ((double)g_ip->num_dq/g_ip->mem_data_width)/((double)g_ip->num_clk/2); + num_mem_ca = g_ip->num_mem_dq * (int)(g_ip->num_dq/g_ip->mem_data_width); + num_mem_clk = (int)(g_ip->num_mem_dq * + (g_ip->num_dq/g_ip->mem_data_width)/(g_ip->num_clk/2)); if (g_ip->io_type == LPDDR2) { //LPDDR @@ -354,16 +354,16 @@ IOTechParam::IOTechParam(InputParameter * g_ip) * of experiments method shown in the technical report (), in Chapter 2.2. */ k_noise_write_sen = k_noise_write * (1 + 0.2*(r_on/34 - 1) + - 0.2*((double)g_ip->num_mem_dq/2 - 1)); + 0.2*(int)(g_ip->num_mem_dq/2 - 1)); k_noise_read_sen = k_noise_read * (1 + 0.2*(r_on/34 - 1) + - 0.2*((double)g_ip->num_mem_dq/2 - 1)); + 0.2*(int)(g_ip->num_mem_dq/2 - 1)); k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/100 - 1) + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); t_jitter_setup_sen = t_jitter_setup * (1 + 0.1*(r_on/34 - 1) + - 0.3*((double)g_ip->num_mem_dq/2 - 1)); + 0.3*(int)(g_ip->num_mem_dq/2 - 1)); t_jitter_hold_sen = t_jitter_hold * (1 + 0.1*(r_on/34 - 1) + - 0.3*((double)g_ip->num_mem_dq/2 - 1)); + 0.3*(int)(g_ip->num_mem_dq/2 - 1)); t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/100 - 1) + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.2*(rtt_ca/100 - 1) + @@ -483,17 +483,17 @@ IOTechParam::IOTechParam(InputParameter * g_ip) * of experiments method shown in the technical report (), in Chapter 2.2. */ k_noise_write_sen = k_noise_write * (1 + 0.2*(r_on/50 - 1) + - 0.2*((double)g_ip->num_mem_dq/2 - 1)); + 0.2*(int)(g_ip->num_mem_dq/2 - 1)); k_noise_read_sen = k_noise_read * (1 + 0.2*(r_on/50 - 1) + - 0.2*((double)g_ip->num_mem_dq/2 - 1)); + 0.2*(int)(g_ip->num_mem_dq/2 - 1)); k_noise_addr_sen = k_noise_addr * (1 + 0.2*(r_on/50 - 1) + 0.2*(num_mem_ca/16 - 1)); t_jitter_setup_sen = t_jitter_setup * (1 + 0.1*(r_on/50 - 1) + - 0.3*((double)g_ip->num_mem_dq/2 - 1)); + 0.3*(int)(g_ip->num_mem_dq/2 - 1)); t_jitter_hold_sen = t_jitter_hold * (1 + 0.1*(r_on/50 - 1) + - 0.3*((double)g_ip->num_mem_dq/2 - 1)); + 0.3*(int)(g_ip->num_mem_dq/2 - 1)); t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.1*(r_on/50 - 1) + 0.4*(num_mem_ca/16 - 1)); t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.1*(r_on/50 - 1) + @@ -614,11 +614,11 @@ IOTechParam::IOTechParam(InputParameter * g_ip) k_noise_write_sen = k_noise_write * (1 + 0.1*(rtt1_dq_write/60 - 1) + 0.2*(rtt2_dq_write/60 - 1) + 0.2*(r_on/34 - 1) + - 0.2*((double)g_ip->num_mem_dq/2 - 1)); + 0.2*(int)(g_ip->num_mem_dq/2 - 1)); k_noise_read_sen = k_noise_read * (1 + 0.1*(rtt1_dq_read/60 - 1) + 0.2*(rtt2_dq_read/60 - 1) + 0.2*(r_on/34 - 1) + - 0.2*((double)g_ip->num_mem_dq/2 - 1)); + 0.2*(int)(g_ip->num_mem_dq/2 - 1)); k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/50 - 1) + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); @@ -626,11 +626,11 @@ IOTechParam::IOTechParam(InputParameter * g_ip) t_jitter_setup_sen = t_jitter_setup * (1 + 0.2*(rtt1_dq_write/60 - 1) + 0.3*(rtt2_dq_write/60 - 1) + 0.1*(r_on/34 - 1) + - 0.3*((double)g_ip->num_mem_dq/2 - 1)); + 0.3*(int)(g_ip->num_mem_dq/2 - 1)); t_jitter_hold_sen = t_jitter_hold * (1 + 0.2*(rtt1_dq_write/60 - 1) + 0.3*(rtt2_dq_write/60 - 1) + - 0.1*(r_on/34 - 1) + 0.3*((double)g_ip->num_mem_dq/2 - 1)); + 0.1*(r_on/34 - 1) + 0.3*(int)(g_ip->num_mem_dq/2 - 1)); t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/50 - 1) + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); @@ -752,11 +752,11 @@ IOTechParam::IOTechParam(InputParameter * g_ip) k_noise_write_sen = k_noise_write * (1 + 0.1*(rtt1_dq_write/60 - 1) + 0.2*(rtt2_dq_write/60 - 1) + 0.2*(r_on/34 - 1) + - 0.2*((double)g_ip->num_mem_dq/2 - 1)); + 0.2*(int)(g_ip->num_mem_dq/2 - 1)); k_noise_read_sen = k_noise_read * (1 + 0.1*(rtt1_dq_read/60 - 1) + 0.2*(rtt2_dq_read/60 - 1) + 0.2*(r_on/34 - 1) + - 0.2*((double)g_ip->num_mem_dq/2 - 1)); + 0.2*(int)(g_ip->num_mem_dq/2 - 1)); k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/50 - 1) + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); @@ -764,11 +764,11 @@ IOTechParam::IOTechParam(InputParameter * g_ip) t_jitter_setup_sen = t_jitter_setup * (1 + 0.2*(rtt1_dq_write/60 - 1) + 0.3*(rtt2_dq_write/60 - 1) + 0.1*(r_on/34 - 1) + - 0.3*((double)g_ip->num_mem_dq/2 - 1)); + 0.3*(int)(g_ip->num_mem_dq/2 - 1)); t_jitter_hold_sen = t_jitter_hold * (1 + 0.2*(rtt1_dq_write/60 - 1) + 0.3*(rtt2_dq_write/60 - 1) + - 0.1*(r_on/34 - 1) + 0.3*((double)g_ip->num_mem_dq/2 - 1)); + 0.1*(r_on/34 - 1) + 0.3*(int)(g_ip->num_mem_dq/2 - 1)); t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/50 - 1) + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); @@ -876,7 +876,7 @@ IOTechParam::IOTechParam(InputParameter * g_ip) } - else + else { cout << "Not Yet supported" << endl; exit(1); @@ -916,8 +916,8 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me , int num_dq, int connection, int num_loads, double freq) { num_mem_ca = num_mem_dq * (mem_data_width); - num_mem_clk = num_mem_dq * - ((double)num_dq/mem_data_width)/((double)g_ip->num_clk/2); + num_mem_clk = (int)(num_mem_dq * + (num_dq/mem_data_width)/(g_ip->num_clk/2)); io_type = io_type1; frequency = freq; @@ -1006,16 +1006,16 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me * of experiments method shown in the technical report (), in Chapter 2.2. */ k_noise_write_sen = k_noise_write * (1 + 0.2*(r_on/34 - 1) + - 0.2*((double)num_mem_dq/2 - 1)); + 0.2*(int)(num_mem_dq/2 - 1)); k_noise_read_sen = k_noise_read * (1 + 0.2*(r_on/34 - 1) + - 0.2*((double)num_mem_dq/2 - 1)); + 0.2*(int)(num_mem_dq/2 - 1)); k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/100 - 1) + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); t_jitter_setup_sen = t_jitter_setup * (1 + 0.1*(r_on/34 - 1) + - 0.3*((double)num_mem_dq/2 - 1)); + 0.3*(int)(num_mem_dq/2 - 1)); t_jitter_hold_sen = t_jitter_hold * (1 + 0.1*(r_on/34 - 1) + - 0.3*((double)num_mem_dq/2 - 1)); + 0.3*(int)(num_mem_dq/2 - 1)); t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/100 - 1) + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.2*(rtt_ca/100 - 1) + @@ -1056,7 +1056,7 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me } - else if (io_type == WideIO) { //WIDEIO + else if (io_type == WideIO) { //WIDEIO //Technology Parameters vdd_io = 1.2; v_sw_clk = 1.2; @@ -1135,17 +1135,17 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me * of experiments method shown in the technical report (), in Chapter 2.2. */ k_noise_write_sen = k_noise_write * (1 + 0.2*(r_on/50 - 1) + - 0.2*((double)num_mem_dq/2 - 1)); + 0.2*(int)(num_mem_dq/2 - 1)); k_noise_read_sen = k_noise_read * (1 + 0.2*(r_on/50 - 1) + - 0.2*((double)num_mem_dq/2 - 1)); + 0.2*(int)(num_mem_dq/2 - 1)); k_noise_addr_sen = k_noise_addr * (1 + 0.2*(r_on/50 - 1) + 0.2*(num_mem_ca/16 - 1)); t_jitter_setup_sen = t_jitter_setup * (1 + 0.1*(r_on/50 - 1) + - 0.3*((double)num_mem_dq/2 - 1)); + 0.3*(int)(num_mem_dq/2 - 1)); t_jitter_hold_sen = t_jitter_hold * (1 + 0.1*(r_on/50 - 1) + - 0.3*((double)num_mem_dq/2 - 1)); + 0.3*(int)(num_mem_dq/2 - 1)); t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.1*(r_on/50 - 1) + 0.4*(num_mem_ca/16 - 1)); t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.1*(r_on/50 - 1) + @@ -1294,11 +1294,11 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me k_noise_write_sen = k_noise_write * (1 + 0.1*(rtt1_dq_write/60 - 1) + 0.2*(rtt2_dq_write/60 - 1) + 0.2*(r_on/34 - 1) + - 0.2*((double)num_mem_dq/2 - 1)); + 0.2*(int)(num_mem_dq/2 - 1)); k_noise_read_sen = k_noise_read * (1 + 0.1*(rtt1_dq_read/60 - 1) + 0.2*(rtt2_dq_read/60 - 1) + 0.2*(r_on/34 - 1) + - 0.2*((double)num_mem_dq/2 - 1)); + 0.2*(int)(num_mem_dq/2 - 1)); k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/50 - 1) + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); @@ -1306,11 +1306,11 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me t_jitter_setup_sen = t_jitter_setup * (1 + 0.2*(rtt1_dq_write/60 - 1) + 0.3*(rtt2_dq_write/60 - 1) + 0.1*(r_on/34 - 1) + - 0.3*((double)num_mem_dq/2 - 1)); + 0.3*(int)(num_mem_dq/2 - 1)); t_jitter_hold_sen = t_jitter_hold * (1 + 0.2*(rtt1_dq_write/60 - 1) + 0.3*(rtt2_dq_write/60 - 1) + - 0.1*(r_on/34 - 1) + 0.3*((double)num_mem_dq/2 - 1)); + 0.1*(r_on/34 - 1) + 0.3*(int)(num_mem_dq/2 - 1)); t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/50 - 1) + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); @@ -1349,7 +1349,7 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me } - else if (io_type == DDR4) + else if (io_type == DDR4) { //Default parameters for DDR4 // IO Supply voltage (V) vdd_io = 1.2; @@ -1459,11 +1459,11 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me k_noise_write_sen = k_noise_write * (1 + 0.1*(rtt1_dq_write/60 - 1) + 0.2*(rtt2_dq_write/60 - 1) + 0.2*(r_on/34 - 1) + - 0.2*((double)num_mem_dq/2 - 1)); + 0.2*(int)(num_mem_dq/2 - 1)); k_noise_read_sen = k_noise_read * (1 + 0.1*(rtt1_dq_read/60 - 1) + 0.2*(rtt2_dq_read/60 - 1) + 0.2*(r_on/34 - 1) + - 0.2*((double)num_mem_dq/2 - 1)); + 0.2*(int)(num_mem_dq/2 - 1)); k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/50 - 1) + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); @@ -1471,11 +1471,11 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me t_jitter_setup_sen = t_jitter_setup * (1 + 0.2*(rtt1_dq_write/60 - 1) + 0.3*(rtt2_dq_write/60 - 1) + 0.1*(r_on/34 - 1) + - 0.3*((double)num_mem_dq/2 - 1)); + 0.3*(int)(num_mem_dq/2 - 1)); t_jitter_hold_sen = t_jitter_hold * (1 + 0.2*(rtt1_dq_write/60 - 1) + 0.3*(rtt2_dq_write/60 - 1) + - 0.1*(r_on/34 - 1) + 0.3*((double)num_mem_dq/2 - 1)); + 0.1*(r_on/34 - 1) + 0.3*(int)(num_mem_dq/2 - 1)); t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/50 - 1) + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); @@ -1585,7 +1585,7 @@ IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_me } - else + else { cout << "Not Yet supported" << endl; exit(1);