report/dictionary.txt at master · LogicAnalyzer/report · GitHub

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personal_ws-1.1 en 0
Verilog
Digilent
Vivado
Xilinx
Nexys
Artix
FPGA
sigrok
pulseView
DDR
UART
GitHub
RTL
pandoc
LaTeX
macOS
subgoals
microcontroller
compilable
synthesizable
deliverables
precompiled
PHP
MySQL
UVM
SystemVerilog
FX
Nyquist
MHz
HDL
middleware
CPUs
IPs
Digikey
EZ
bitstream
SPI
testbench
xUnit
Cocotb
bitstreams
DSLogic
metastable
PMODs
SJOne
LPC
datavalid
libsigrok
UML
UI
FPGAs
viewable
waveforms
rdy
tx
mux
rnw
trigs
cnt
clr
wr
sel
CMD
XXXX
XXXXXXXX
DLYCNT
parameterized
trigRising
trigFalling
py
pdf
trigs
triggering
dataIn
dataOut
validOut
Nitty
Tx
DV
clk
fifo
pre
cmd
CLKS
DUT
tran
deassert
deasserted
TODO
num
leds
ACSP