From a48c53e8c8cea5a5edb3e31783f45fe6667edc75 Mon Sep 17 00:00:00 2001
From: Canberk Pitirli <canberkpitirli@gmail.com>
Date: Wed, 28 Oct 2026 23:56:02 +0300
Subject: [PATCH] perf(cuda-oxide): lower f32 max/min to native max.f32/min.f32

Refs #1594.

Co-authored-by: imanolgo <858793+ImanolGo@users.noreply.github.com>
Signed-off-by: Canberk Pitirli <canberkpitirli@gmail.com>
---
 .../crates/dialect-mir/src/rust_intrinsics.rs |   7 +-
 .../crates/mir-lower/src/convert/ops/call.rs  |  65 +-
 .../tests/lowering_test/math_conversions.rs   | 111 +++
 .../examples/float_minmax/Cargo.lock          | 761 ++++++++++++++++++
 .../examples/float_minmax/Cargo.toml          |  21 +
 .../examples/float_minmax/src/main.rs         | 249 ++++++
 6 files changed, 1198 insertions(+), 16 deletions(-)
 create mode 100644 cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/Cargo.lock
 create mode 100644 cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/Cargo.toml
 create mode 100644 cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/src/main.rs

diff --git a/cuda-oxide/crates/dialect-mir/src/rust_intrinsics.rs b/cuda-oxide/crates/dialect-mir/src/rust_intrinsics.rs
index 43d7241f52..f17e34d74a 100644
--- a/cuda-oxide/crates/dialect-mir/src/rust_intrinsics.rs
+++ b/cuda-oxide/crates/dialect-mir/src/rust_intrinsics.rs
@@ -288,9 +288,10 @@ pub fn is_known_placeholder(callee: &str) -> bool {
 /// [`is_backend_dependent_libdevice_placeholder`].
 ///
 /// The `max`/`min` placeholders (`maximum_number_nsz_*` /
-/// `minimum_number_nsz_*`) are in NEITHER list: they lower to an ordered
-/// compare/select expansion under every intrinsic backend, so they never
-/// produce a `__nv_*` call. (`llvm.maxnum`/`llvm.minnum` are unusable
+/// `minimum_number_nsz_*`) are in NEITHER list: they never produce a
+/// `__nv_*` call. Under the LLVM NVPTX backend f32 lowers to the native
+/// `llvm.nvvm.fmax.f` / `llvm.nvvm.fmin.f`; f64 and the libNVVM backend use an
+/// ordered compare/select expansion. (`llvm.maxnum`/`llvm.minnum` are unusable
 /// because under LLVM 21 they propagate signaling NaNs, contradicting
 /// Rust's ignore-any-NaN contract; see #390.)
 pub fn is_libdevice_backed_placeholder(callee: &str) -> bool {
diff --git a/cuda-oxide/crates/mir-lower/src/convert/ops/call.rs b/cuda-oxide/crates/mir-lower/src/convert/ops/call.rs
index c5ae9f0325..4d5617f78b 100644
--- a/cuda-oxide/crates/mir-lower/src/convert/ops/call.rs
+++ b/cuda-oxide/crates/mir-lower/src/convert/ops/call.rs
@@ -362,6 +362,19 @@ impl RustFloatMathIntrinsic {
         }
     }
 
+    /// Whether this min/max lowers to a native NVVM intrinsic under the
+    /// active intrinsic backend, instead of the compare/select expansion.
+    ///
+    /// Only f32 has one (`llvm.nvvm.fmax.f` / `llvm.nvvm.fmin.f`), and only the
+    /// LLVM NVPTX backend accepts it; libNVVM keeps the expansion.
+    fn has_native_minmax(self, ctx: &Context) -> bool {
+        matches!(self, Self::MaxNumNszF32 | Self::MinNumNszF32)
+            && matches!(
+                crate::context::lowering_options(ctx).intrinsic_backend,
+                crate::IntrinsicBackend::LlvmNvptx
+            )
+    }
+
     /// CUDA libdevice function name for this Rust math intrinsic.
     fn libdevice_name(
         self,
@@ -409,10 +422,11 @@ impl RustFloatMathIntrinsic {
             Self::CopysignF64 => Ok("__nv_copysign"),
             // `f32::max` / `f32::min` (and the f64 forms) call the `_nsz`
             // intrinsics, i.e. IEEE-754 maxNum/minNum with the "no signed
-            // zero" relaxation. They expand to an ordered compare/select
-            // sequence under every intrinsic backend (the caller routes them
-            // through `lower_float_minmax_nsz` before any symbol lookup), so
-            // they must never reach a libdevice name.
+            // zero" relaxation. f32 lowers to a native NVVM intrinsic under
+            // the LLVM NVPTX backend (see `llvm_intrinsic_name`); everything
+            // else expands to an ordered compare/select sequence (the caller
+            // routes it through `lower_float_minmax_nsz` before any symbol
+            // lookup). Neither path may reach a libdevice name.
             Self::MaxNumNszF32 | Self::MaxNumNszF64 | Self::MinNumNszF32 | Self::MinNumNszF64 => {
                 pliron::input_err!(
                     loc,
@@ -515,11 +529,13 @@ impl RustFloatMathIntrinsic {
     /// Using LLVM intrinsics avoids a libdevice function call and removes the
     /// libNVVM dependency for kernels that only use these operations.
     ///
-    /// Scope: `max`/`min` deliberately return `None` here. They cannot use
-    /// `llvm.maxnum`/`llvm.minnum` at all, because under LLVM 21 those
-    /// propagate signaling NaNs and so contradict Rust's contract; they lower
-    /// as an ordered compare/select instead (`lower_float_minmax_nsz`, see
-    /// #390) and never reach this table.
+    /// Scope: f32 `max`/`min` map to `llvm.nvvm.fmax.f` / `llvm.nvvm.fmin.f`,
+    /// the non-`.NaN`, non-`.ftz` forms that select `max.f32` / `min.f32`.
+    /// They cannot use `llvm.maxnum`/`llvm.minnum`, because under LLVM 21 those
+    /// propagate signaling NaNs and so contradict Rust's contract (#390). f64
+    /// has no NVVM equivalent, so f64 `max`/`min` return `None` here and lower
+    /// as an ordered compare/select instead (`lower_float_minmax_nsz`). The
+    /// libNVVM backend never uses this table and keeps that expansion for f32.
     ///
     /// Naming: pliron identifiers cannot contain dots, so intrinsic symbols
     /// use the underscore encoding (`llvm_floor_f32`) that the textual `.ll`
@@ -551,6 +567,11 @@ impl RustFloatMathIntrinsic {
             Self::Fabs => fabs_llvm_intrinsic_name(ctx, result_ty, loc).map(Some),
             Self::CopysignF32 => Ok(Some("llvm_copysign_f32")),
             Self::CopysignF64 => Ok(Some("llvm_copysign_f64")),
+            // f32 min/max: the non-`.NaN`, non-`.ftz` NVVM forms select
+            // `max.f32` / `min.f32`. f64 has no NVVM equivalent and returns
+            // `None`; see the scope note above.
+            Self::MaxNumNszF32 => Ok(Some("llvm_nvvm_fmax_f")),
+            Self::MinNumNszF32 => Ok(Some("llvm_nvvm_fmin_f")),
             _ => Ok(None),
         }
     }
@@ -1291,7 +1312,12 @@ fn convert_rust_float_math_intrinsic(
         return lower_fast_binop(ctx, rewriter, op, &args, binop, loc);
     }
 
-    if let Some(predicate) = intrinsic.minmax_nsz_predicate() {
+    // f32 `max`/`min` with a native NVVM intrinsic fall through to the common
+    // intrinsic-call path below; every other min/max keeps the compare/select
+    // expansion.
+    if let Some(predicate) = intrinsic.minmax_nsz_predicate()
+        && !intrinsic.has_native_minmax(ctx)
+    {
         return lower_float_minmax_nsz(ctx, rewriter, op, &args, predicate);
     }
 
@@ -2453,13 +2479,26 @@ mod tests {
             Some("llvm_roundeven_f64")
         );
 
-        // max/min return None: LLVM 21's maxnum/minnum propagate signaling
-        // NaNs, which contradicts Rust's contract. These use compare/select
-        // lowering instead and never reach the intrinsic tables (see #390).
+        // f32 max/min use the native NVVM intrinsics (`max.f32` / `min.f32`).
+        // LLVM 21's maxnum/minnum propagate signaling NaNs, which contradicts
+        // Rust's contract, so they are not used (see #390).
         assert_eq!(
             RustFloatMathIntrinsic::MaxNumNszF32
                 .llvm_intrinsic_name(&ctx, f32_ty, loc.clone())
                 .unwrap(),
+            Some("llvm_nvvm_fmax_f")
+        );
+        assert_eq!(
+            RustFloatMathIntrinsic::MinNumNszF32
+                .llvm_intrinsic_name(&ctx, f32_ty, loc.clone())
+                .unwrap(),
+            Some("llvm_nvvm_fmin_f")
+        );
+        // f64 has no NVVM equivalent and keeps the compare/select expansion.
+        assert_eq!(
+            RustFloatMathIntrinsic::MaxNumNszF64
+                .llvm_intrinsic_name(&ctx, f64_ty, loc.clone())
+                .unwrap(),
             None
         );
         assert_eq!(
diff --git a/cuda-oxide/crates/mir-lower/tests/lowering_test/math_conversions.rs b/cuda-oxide/crates/mir-lower/tests/lowering_test/math_conversions.rs
index 95fbf7bd31..520e75e54a 100644
--- a/cuda-oxide/crates/mir-lower/tests/lowering_test/math_conversions.rs
+++ b/cuda-oxide/crates/mir-lower/tests/lowering_test/math_conversions.rs
@@ -1706,3 +1706,114 @@ fn test_scalar_arithmetic_libnvvm_uses_exact_inline_ptx() -> Result<(), anyhow::
     );
     Ok(())
 }
+
+/// Lower `max` and `min` calls on both f32 and f64 operands under `backend`.
+fn lower_float_minmax(
+    backend: mir_lower::IntrinsicBackend,
+) -> Result<(Context, pliron::context::Ptr<Operation>), anyhow::Error> {
+    use dialect_mir::rust_intrinsics;
+    use pliron::builtin::attributes::StringAttr;
+    use pliron::builtin::types::{FP32Type, FP64Type};
+    use pliron::r#type::TypeHandle;
+
+    let mut ctx = make_test_ctx();
+    let f32_ty: TypeHandle = FP32Type::get(&ctx).into();
+    let f64_ty: TypeHandle = FP64Type::get(&ctx).into();
+    let (module_ptr, entry) = build_test_kernel(&mut ctx, vec![f32_ty, f32_ty, f64_ty, f64_ty]);
+    let f32_args = [
+        entry.deref(&ctx).get_argument(0),
+        entry.deref(&ctx).get_argument(1),
+    ];
+    let f64_args = [
+        entry.deref(&ctx).get_argument(2),
+        entry.deref(&ctx).get_argument(3),
+    ];
+
+    for (callee, args, result_ty) in [
+        (rust_intrinsics::CALLEE_MAXNUM_NSZ_F32, f32_args, f32_ty),
+        (rust_intrinsics::CALLEE_MINNUM_NSZ_F32, f32_args, f32_ty),
+        (rust_intrinsics::CALLEE_MAXNUM_NSZ_F64, f64_args, f64_ty),
+        (rust_intrinsics::CALLEE_MINNUM_NSZ_F64, f64_args, f64_ty),
+    ] {
+        let call_ptr = Operation::new(
+            &mut ctx,
+            mir::MirCallOp::get_concrete_op_info(),
+            vec![result_ty],
+            args.to_vec(),
+            vec![],
+            0,
+        );
+        let call = mir::MirCallOp::new(call_ptr);
+        call.set_attr_callee(&ctx, StringAttr::new(callee.to_string()));
+        call_ptr.insert_at_back(entry, &ctx);
+    }
+    append_return(&mut ctx, entry);
+
+    mir_lower::lower_mir_to_llvm_with_options(
+        &mut ctx,
+        module_ptr,
+        mir_lower::LoweringOptions {
+            intrinsic_backend: backend,
+            ..Default::default()
+        },
+    )
+    .map_err(|error| anyhow::anyhow!("{error}"))?;
+    Ok((ctx, module_ptr))
+}
+
+/// Direct callee names, `fcmp` count and `select` count of a lowered body.
+fn minmax_lowering_shape(
+    ctx: &Context,
+    body: &[pliron::context::Ptr<Operation>],
+) -> (Vec<String>, usize, usize) {
+    let mut callees = Vec::new();
+    let (mut fcmps, mut selects) = (0, 0);
+    for &op in body {
+        assert!(
+            Operation::get_op::<mir::MirCallOp>(op, ctx).is_none(),
+            "max/min placeholder mir.call must not survive MIR lowering"
+        );
+        if let Some(call) = Operation::get_op::<llvm::CallOp>(op, ctx)
+            && let CallOpCallable::Direct(sym) = call.callee(ctx)
+        {
+            callees.push(sym.to_string());
+        }
+        fcmps += usize::from(Operation::get_op::<llvm::FCmpOp>(op, ctx).is_some());
+        selects += usize::from(Operation::get_op::<llvm::SelectOp>(op, ctx).is_some());
+    }
+    (callees, fcmps, selects)
+}
+
+#[test]
+fn test_float_minmax_llvm_nvptx_f32_uses_nvvm_intrinsics_f64_uses_compare_select()
+-> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) = lower_float_minmax(mir_lower::IntrinsicBackend::LlvmNvptx)?;
+    let (callees, fcmps, selects) =
+        minmax_lowering_shape(&ctx, &lowered_kernel_body(&ctx, module_ptr));
+
+    // f32 max/min: one native NVVM call each, no compare/select.
+    assert_eq!(
+        callees,
+        ["llvm_nvvm_fmax_f", "llvm_nvvm_fmin_f"],
+        "f32 max/min must call the non-.NaN, non-.ftz NVVM intrinsics"
+    );
+    // f64 max/min: the NaN-ignoring expansion, two fcmp + two select each.
+    assert_eq!(fcmps, 4, "only the two f64 ops keep the compare/select");
+    assert_eq!(selects, 4, "only the two f64 ops keep the compare/select");
+    Ok(())
+}
+
+#[test]
+fn test_float_minmax_libnvvm_keeps_compare_select_for_both_widths() -> Result<(), anyhow::Error> {
+    let (ctx, module_ptr) = lower_float_minmax(mir_lower::IntrinsicBackend::LibNvvm)?;
+    let (callees, fcmps, selects) =
+        minmax_lowering_shape(&ctx, &lowered_kernel_body(&ctx, module_ptr));
+
+    assert!(
+        callees.is_empty(),
+        "libNVVM max/min must not call an intrinsic, found {callees:?}"
+    );
+    assert_eq!(fcmps, 8, "all four ops expand to two fcmp each");
+    assert_eq!(selects, 8, "all four ops expand to two select each");
+    Ok(())
+}
diff --git a/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/Cargo.lock b/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/Cargo.lock
new file mode 100644
index 0000000000..6cfd632901
--- /dev/null
+++ b/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/Cargo.lock
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diff --git a/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/Cargo.toml b/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/Cargo.toml
new file mode 100644
index 0000000000..730aba3255
--- /dev/null
+++ b/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/Cargo.toml
@@ -0,0 +1,21 @@
+[package]
+name = "float_minmax"
+version = "0.1.0"
+edition = "2024"
+license = "Apache-2.0"
+
+[workspace]
+
+# f32 `max`/`min` lower to the native PTX `max.f32` / `min.f32`.
+# Checks Rust's NaN contract (a numeric operand wins over a quiet or
+# signaling NaN in either position) and that subnormals survive.
+#
+# Run with:
+#   cargo oxide run float_minmax
+#   cargo oxide inspect float_minmax    # PTX has max.f32 / min.f32, no setp/selp
+
+[dependencies]
+cuda-device = { path = "../../../cuda-device" }
+cuda-host = { path = "../../../cuda-host" }
+cuda-core = { path = "../../../../../cuda-core" }
+libm = "0.2"
diff --git a/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/src/main.rs b/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/src/main.rs
new file mode 100644
index 0000000000..39b9d9f3ef
--- /dev/null
+++ b/cuda-oxide/crates/rustc-codegen-cuda/examples/float_minmax/src/main.rs
@@ -0,0 +1,249 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//! f32 `max` / `min` on the device (#1594).
+//!
+//! `f32::max`, `f32::min`, `libm::fmaxf` and `libm::fminf` lower to the native
+//! PTX `max.f32` / `min.f32` (through `llvm.nvvm.fmax.f` / `llvm.nvvm.fmin.f`)
+//! instead of a `setp` + `selp` pair. `cargo oxide inspect float_minmax` shows
+//! the PTX.
+//!
+//! The host runs every pair of a value set that covers quiet and signaling
+//! NaNs of both signs, infinities, signed zeros and subnormals, so each NaN
+//! lands in both operand positions, and checks Rust's contract:
+//!
+//! - one operand is NaN: the other operand is returned bit for bit;
+//! - both are NaN: the result is a NaN;
+//! - otherwise: the larger (smaller) value, subnormals preserved.
+//!
+//! `max(-0.0, +0.0)` is unspecified in Rust, so the signed-zero results are
+//! printed and only required to be a zero.
+//!
+//! Run with:
+//!   cargo oxide run float_minmax
+
+use cuda_core::simt::LaunchConfig;
+use cuda_core::{CudaContext, DeviceBuffer};
+use cuda_device::{DisjointSlice, cuda_module, kernel, thread};
+
+#[cuda_module]
+mod kernels {
+    use super::*;
+
+    #[kernel]
+    pub fn std_max(a: &[f32], b: &[f32], mut out: DisjointSlice<f32>) {
+        let idx = thread::index_1d();
+        let i = idx.get();
+        if let Some(o) = out.get_mut(idx) {
+            *o = a[i].max(b[i]);
+        }
+    }
+
+    #[kernel]
+    pub fn std_min(a: &[f32], b: &[f32], mut out: DisjointSlice<f32>) {
+        let idx = thread::index_1d();
+        let i = idx.get();
+        if let Some(o) = out.get_mut(idx) {
+            *o = a[i].min(b[i]);
+        }
+    }
+
+    #[kernel]
+    pub fn libm_max(a: &[f32], b: &[f32], mut out: DisjointSlice<f32>) {
+        let idx = thread::index_1d();
+        let i = idx.get();
+        if let Some(o) = out.get_mut(idx) {
+            *o = libm::fmaxf(a[i], b[i]);
+        }
+    }
+
+    #[kernel]
+    pub fn libm_min(a: &[f32], b: &[f32], mut out: DisjointSlice<f32>) {
+        let idx = thread::index_1d();
+        let i = idx.get();
+        if let Some(o) = out.get_mut(idx) {
+            *o = libm::fminf(a[i], b[i]);
+        }
+    }
+
+    /// Both operations in one kernel, as in the report for #1594.
+    #[kernel]
+    pub fn std_minmax(a: &[f32], b: &[f32], mut out: DisjointSlice<f32>) {
+        let idx = thread::index_1d();
+        let i = idx.get();
+        if let Some(o) = out.get_mut(idx) {
+            *o = a[i].max(b[i]) + a[i].min(b[i]);
+        }
+    }
+
+    #[kernel]
+    pub fn libm_minmax(a: &[f32], b: &[f32], mut out: DisjointSlice<f32>) {
+        let idx = thread::index_1d();
+        let i = idx.get();
+        if let Some(o) = out.get_mut(idx) {
+            *o = libm::fmaxf(a[i], b[i]) + libm::fminf(a[i], b[i]);
+        }
+    }
+}
+
+/// Bit patterns: numbers, infinities, signed zeros, subnormals, and quiet and
+/// signaling NaNs of both signs.
+const VALUES: [u32; 16] = [
+    0x3f80_0000, // 1.0
+    0xbf80_0000, // -1.0
+    0x0000_0000, // +0.0
+    0x8000_0000, // -0.0
+    0x7f80_0000, // +inf
+    0xff80_0000, // -inf
+    0x7f7f_ffff, // f32::MAX
+    0x0080_0000, // smallest normal
+    0x0000_0001, // smallest subnormal
+    0x8000_0001, // -smallest subnormal
+    0x007f_ffff, // largest subnormal
+    0x7fc0_0000, // +qNaN
+    0xffc0_0000, // -qNaN
+    0x7fa0_0000, // +sNaN
+    0xffa0_0000, // -sNaN
+    0x7fc0_1234, // qNaN with a payload
+];
+
+fn is_zero(x: f32) -> bool {
+    x == 0.0
+}
+
+/// Check one result against Rust's contract. Returns an error description.
+fn check(is_max: bool, x: f32, y: f32, r: f32) -> Result<(), String> {
+    let (xb, yb, rb) = (x.to_bits(), y.to_bits(), r.to_bits());
+    if x.is_nan() && y.is_nan() {
+        return if r.is_nan() {
+            Ok(())
+        } else {
+            Err(format!("both NaN, got {rb:#010x}"))
+        };
+    }
+    if x.is_nan() || y.is_nan() {
+        let want = if x.is_nan() { yb } else { xb };
+        return if rb == want {
+            Ok(())
+        } else {
+            Err(format!("one NaN, want {want:#010x}, got {rb:#010x}"))
+        };
+    }
+    if is_zero(x) && is_zero(y) {
+        return if is_zero(r) {
+            Ok(())
+        } else {
+            Err(format!("zeros, got non-zero {rb:#010x}"))
+        };
+    }
+    let want = match (is_max, x > y) {
+        (true, true) | (false, false) => xb,
+        _ => yb,
+    };
+    if rb == want {
+        Ok(())
+    } else {
+        Err(format!("want {want:#010x}, got {rb:#010x}"))
+    }
+}
+
+fn main() {
+    println!("=== float_minmax: f32 max/min on the device ===");
+
+    let ctx = CudaContext::new(0).expect("Failed to create CUDA context");
+    let stream = ctx.default_stream();
+
+    let (mut a, mut b) = (Vec::new(), Vec::new());
+    for &x in &VALUES {
+        for &y in &VALUES {
+            a.push(f32::from_bits(x));
+            b.push(f32::from_bits(y));
+        }
+    }
+    let n = a.len();
+
+    let a_dev = DeviceBuffer::from_host(&stream, &a).unwrap();
+    let b_dev = DeviceBuffer::from_host(&stream, &b).unwrap();
+    let module = kernels::load(&ctx).expect("Failed to load embedded CUDA module");
+    let cfg = LaunchConfig::for_num_elems(n as u32);
+
+    macro_rules! run {
+        ($kernel:ident) => {{
+            let mut out = DeviceBuffer::<f32>::zeroed(&stream, n).unwrap();
+            // SAFETY: the launch is 1-D, one thread per element, and the
+            // buffers cover the kernel's accesses.
+            unsafe { module.$kernel(&stream, cfg, &a_dev, &b_dev, &mut out) }
+                .expect(concat!(stringify!($kernel), " launch failed"));
+            out.to_host_vec(&stream).unwrap()
+        }};
+    }
+
+    let mut ok = true;
+    for (name, is_max, out) in [
+        ("std_max", true, run!(std_max)),
+        ("std_min", false, run!(std_min)),
+        ("libm_max", true, run!(libm_max)),
+        ("libm_min", false, run!(libm_min)),
+    ] {
+        let mut bad = 0;
+        for i in 0..n {
+            if let Err(why) = check(is_max, a[i], b[i], out[i]) {
+                if bad < 5 {
+                    println!(
+                        "{name}: x={:#010x} y={:#010x}: {why}",
+                        a[i].to_bits(),
+                        b[i].to_bits()
+                    );
+                }
+                bad += 1;
+            }
+        }
+        println!("{name}: {} of {n} pairs match", n - bad);
+        ok &= bad == 0;
+
+        if name.starts_with("std") {
+            // Pair (x, y) is stored at index xi * VALUES.len() + yi.
+            let at = |xi: usize, yi: usize| out[xi * VALUES.len() + yi].to_bits();
+            println!(
+                "  signed zero: ({name})(-0.0, +0.0) = {:#010x}, (+0.0, -0.0) = {:#010x}",
+                at(3, 2),
+                at(2, 3)
+            );
+        }
+    }
+
+    // The combined kernels: `max + min`. Skip pairs with a NaN; infinities of
+    // opposite sign make the sum NaN on host and device alike.
+    for (name, out) in [
+        ("std_minmax", run!(std_minmax)),
+        ("libm_minmax", run!(libm_minmax)),
+    ] {
+        let mut bad = 0;
+        for i in 0..n {
+            let (x, y) = (a[i], b[i]);
+            if x.is_nan() || y.is_nan() {
+                continue;
+            }
+            let want = x + y;
+            let same = if want.is_nan() {
+                out[i].is_nan()
+            } else {
+                out[i] == want
+            };
+            if !same {
+                bad += 1;
+            }
+        }
+        println!("{name}: {bad} mismatches among the non-NaN pairs");
+        ok &= bad == 0;
+    }
+
+    if ok {
+        println!("SUCCESS: f32 max/min follow Rust's NaN contract");
+    } else {
+        println!("FAIL: device max/min diverge from Rust's contract");
+        std::process::exit(1);
+    }
+}