From 129e92f649cc443434f249d131ac3aa69682cf49 Mon Sep 17 00:00:00 2001 From: Nimish Kapoor <67710754+Nimok15@users.noreply.github.com> Date: Fri, 19 Jun 2026 02:23:03 +0530 Subject: [PATCH 1/6] Update diff_pair_cmirrorbias.py --- .../diffpair_cmirror_bias/diff_pair_cmirrorbias.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py b/src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py index c1a47743..99943290 100644 --- a/src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py +++ b/src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py @@ -80,6 +80,7 @@ def diff_pair_ibias( diffpair_bias: tuple[float, float, int], rmult: int = 1, with_antenna_diode_on_diffinputs: int = 0, + dummies_tied_to_bulk: Optional[bool] = None, ) -> Component: # create and center diffpair diffpair_i_ = Component("temp diffpair and current source") @@ -203,7 +204,10 @@ def diff_pair_ibias( # them tied to VB or magic counts an extra net. ## HACK: Note that this is a hack for magic LVS, and it's likely incorrect ## we probably want to fix it properly - _dummies_tied = (pdk.name.lower() == "sky130") + if dummies_tied_to_bulk is None: + _dummies_tied = (pdk.name.lower() == "sky130") + else: + _dummies_tied = dummies_tied_to_bulk cmirror.info['netlist'] = current_mirror_netlist( pdk, width=diffpair_bias[0], From c1960a75c469ec3d9c60f79de42f532c56e0458e Mon Sep 17 00:00:00 2001 From: Nimish Kapoor <67710754+Nimok15@users.noreply.github.com> Date: Fri, 19 Jun 2026 02:25:33 +0530 Subject: [PATCH 2/6] Update diff_pair_stackedcmirror.py --- .../cells/composite/opamp/diff_pair_stackedcmirror.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py b/src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py index abe009db..6b117473 100644 --- a/src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py +++ b/src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py @@ -24,7 +24,7 @@ @validate_arguments def __add_diff_pair_and_bias(pdk: MappedPDK, toplevel_stacked: Component, half_diffpair_params: tuple[float, float, int], diffpair_bias: tuple[float, float, int], rmult: int, with_antenna_diode_on_diffinputs: int) -> Component: clear_cache() - diffpair_i_ref = diff_pair_ibias(pdk, half_diffpair_params, diffpair_bias, rmult, with_antenna_diode_on_diffinputs) + diffpair_i_ref = diff_pair_ibias(pdk, half_diffpair_params, diffpair_bias, rmult, with_antenna_diode_on_diffinputs, dummies_tied_to_bulk=dummies_tied_to_bulk) toplevel_stacked.add(diffpair_i_ref) toplevel_stacked.add_ports(diffpair_i_ref.get_ports_list(),prefix="diffpair_") @@ -150,12 +150,13 @@ def diff_pair_stackedcmirror( diffpair_bias: tuple[float, float, int], half_common_source_nbias: tuple[float, float, int, int], rmult: int, - with_antenna_diode_on_diffinputs: int + with_antenna_diode_on_diffinputs: int, + dummies_tied_to_bulk: Optional[bool] = None, ) -> Component: # create toplevel_stacked component toplevel_stacked = Component() # place nmos components - diffpair_and_bias = __add_diff_pair_and_bias(pdk, toplevel_stacked, half_diffpair_params, diffpair_bias, rmult, with_antenna_diode_on_diffinputs) + diffpair_and_bias = __add_diff_pair_and_bias(pdk, toplevel_stacked, half_diffpair_params, diffpair_bias, rmult, with_antenna_diode_on_diffinputs, dummies_tied_to_bulk=dummies_tied_to_bulk) # create and position each half of the nmos bias transistor for the common source stage symetrically toplevel_stacked = __add_common_source_nbias_transistors(pdk, toplevel_stacked, half_common_source_nbias, rmult) toplevel_stacked.add_padding(layers=(pdk.get_glayer("pwell"),),default=0) From 6356e7488093da35f50ad30c43dea45c37377a6a Mon Sep 17 00:00:00 2001 From: Nimish Kapoor <67710754+Nimok15@users.noreply.github.com> Date: Fri, 19 Jun 2026 02:27:05 +0530 Subject: [PATCH 3/6] Update opamp_twostage.py --- src/glayout/cells/composite/opamp/opamp_twostage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glayout/cells/composite/opamp/opamp_twostage.py b/src/glayout/cells/composite/opamp/opamp_twostage.py index 5ac43f91..1e3f6fab 100644 --- a/src/glayout/cells/composite/opamp/opamp_twostage.py +++ b/src/glayout/cells/composite/opamp/opamp_twostage.py @@ -225,7 +225,7 @@ def opamp_twostage( raise ValueError("number of antenna diodes should be at least 2 (or 0 to specify no diodes)") if half_common_source_bias[3] < 2: raise ValueError("half_common_source_bias num multiplier must be >= 2") - opamp_top, halfmultn_drain_routeref, halfmultn_gate_routeref, _cref = diff_pair_stackedcmirror(pdk, half_diffpair_params, diffpair_bias, half_common_source_bias, rmult, with_antenna_diode_on_diffinputs) + opamp_top, halfmultn_drain_routeref, halfmultn_gate_routeref, _cref = diff_pair_stackedcmirror(pdk, half_diffpair_params, diffpair_bias, half_common_source_bias, rmult, with_antenna_diode_on_diffinputs, dummies_tied_to_bulk=True,) opamp_top.info['netlist'].circuit_name = "INPUT_STAGE" From e6959f7279dc1f2663b0c7c95cafd1f939aa0973 Mon Sep 17 00:00:00 2001 From: Nimish Kapoor <67710754+Nimok15@users.noreply.github.com> Date: Fri, 19 Jun 2026 02:43:56 +0530 Subject: [PATCH 4/6] Update diff_pair_stackedcmirror.py --- src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py b/src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py index 6b117473..50f2f161 100644 --- a/src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py +++ b/src/glayout/cells/composite/opamp/diff_pair_stackedcmirror.py @@ -22,7 +22,7 @@ @validate_arguments -def __add_diff_pair_and_bias(pdk: MappedPDK, toplevel_stacked: Component, half_diffpair_params: tuple[float, float, int], diffpair_bias: tuple[float, float, int], rmult: int, with_antenna_diode_on_diffinputs: int) -> Component: +def __add_diff_pair_and_bias(pdk: MappedPDK, toplevel_stacked: Component, half_diffpair_params: tuple[float, float, int], diffpair_bias: tuple[float, float, int], rmult: int, with_antenna_diode_on_diffinputs: int, dummies_tied_to_bulk: Optional[bool] = None) -> Component: clear_cache() diffpair_i_ref = diff_pair_ibias(pdk, half_diffpair_params, diffpair_bias, rmult, with_antenna_diode_on_diffinputs, dummies_tied_to_bulk=dummies_tied_to_bulk) toplevel_stacked.add(diffpair_i_ref) From 756ea5ce0624488d3b3fbc47b946cd37c1795a4e Mon Sep 17 00:00:00 2001 From: Nimish Kapoor <67710754+Nimok15@users.noreply.github.com> Date: Fri, 19 Jun 2026 03:10:27 +0530 Subject: [PATCH 5/6] Update opamp_twostage.py --- src/glayout/cells/composite/opamp/opamp_twostage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glayout/cells/composite/opamp/opamp_twostage.py b/src/glayout/cells/composite/opamp/opamp_twostage.py index 1e3f6fab..bf48b5d0 100644 --- a/src/glayout/cells/composite/opamp/opamp_twostage.py +++ b/src/glayout/cells/composite/opamp/opamp_twostage.py @@ -225,7 +225,7 @@ def opamp_twostage( raise ValueError("number of antenna diodes should be at least 2 (or 0 to specify no diodes)") if half_common_source_bias[3] < 2: raise ValueError("half_common_source_bias num multiplier must be >= 2") - opamp_top, halfmultn_drain_routeref, halfmultn_gate_routeref, _cref = diff_pair_stackedcmirror(pdk, half_diffpair_params, diffpair_bias, half_common_source_bias, rmult, with_antenna_diode_on_diffinputs, dummies_tied_to_bulk=True,) + opamp_top, halfmultn_drain_routeref, halfmultn_gate_routeref, _cref = diff_pair_stackedcmirror(pdk, half_diffpair_params, diffpair_bias, half_common_source_bias, rmult, with_antenna_diode_on_diffinputs,) opamp_top.info['netlist'].circuit_name = "INPUT_STAGE" From f4539678ccdf3b3d14278e7906da540d43e183c2 Mon Sep 17 00:00:00 2001 From: Nimish Kapoor <67710754+Nimok15@users.noreply.github.com> Date: Fri, 19 Jun 2026 03:56:15 +0530 Subject: [PATCH 6/6] Update opamp_twostage.py --- .../cells/composite/opamp/opamp_twostage.py | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/glayout/cells/composite/opamp/opamp_twostage.py b/src/glayout/cells/composite/opamp/opamp_twostage.py index bf48b5d0..7d968da4 100644 --- a/src/glayout/cells/composite/opamp/opamp_twostage.py +++ b/src/glayout/cells/composite/opamp/opamp_twostage.py @@ -268,21 +268,20 @@ def opamp_twostage( # as literals — see DIFF_TO_SINGLE's netlist for the same pattern. source_netlist=( ".subckt {circuit_name} {nodes} " - + f"l={_csb_l} w={_csb_w} mr={_csb_f} mo={_csb_f * _csb_m} " - + f"dr={2} do={2 * _csb_m}\n" + + f"l={_csb_l} w={_csb_w} mr={_csb_f} mo={_csb_f * _csb_m}\n" + "XREFL VREF VREF VSS B {model} l={{l}} w={{w}} m={{mr}}\n" + "XREFR VREF VREF VSS B {model} l={{l}} w={{w}} m={{mr}}\n" + "XOUTL VOUT VREF VSS B {model} l={{l}} w={{w}} m={{mo}}\n" + "XOUTR VOUT VREF VSS B {model} l={{l}} w={{w}} m={{mo}}\n" - + "XDREFL B B B B {model} l={{l}} w={{w}} m={{dr}}\n" - + "XDREFR B B B B {model} l={{l}} w={{w}} m={{dr}}\n" - + "XDOUTL B B B B {model} l={{l}} w={{w}} m={{do}}\n" - + "XDOUTR B B B B {model} l={{l}} w={{w}} m={{do}}\n" + + "".join( + f"XDUM{_i+1} B B B B {{model}} l={_csb_l} w={_csb_w}\n" + for _i in range(2 * (2 + 2 * _csb_m)) + ) + ".ends {circuit_name}" ), instance_format=( "X{name} {nodes} {circuit_name} l={length} w={width} " - "mr={mr} mo={mo} dr={dr} do={do}" + "mr={mr} mo={mo}" ), parameters={ 'model': _nfet_model, @@ -290,8 +289,6 @@ def opamp_twostage( 'length': _csb_l, 'mr': _csb_f, 'mo': _csb_f * _csb_m, - 'dr': 2, - 'do': 2 * _csb_m, } )