From 03d6be83e827d72520d1a9af379707f5250d7578 Mon Sep 17 00:00:00 2001
From: Nimish Kapoor <67710754+Nimok15@users.noreply.github.com>
Date: Fri, 26 Jun 2026 02:07:40 +0530
Subject: [PATCH] Update low_voltage_cmirror.spice

---
 .../sim/testbenches/low_voltage_cmirror.spice | 22 +++++++++++--------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/tests/sim/testbenches/low_voltage_cmirror.spice b/tests/sim/testbenches/low_voltage_cmirror.spice
index 75e4f606..e039b920 100644
--- a/tests/sim/testbenches/low_voltage_cmirror.spice
+++ b/tests/sim/testbenches/low_voltage_cmirror.spice
@@ -1,8 +1,8 @@
 * Testbench: low-voltage cascode current mirror
-*   low_voltage_cmirror ports: IBIAS1 IBIAS2 GND IOUT1 IOUT2
-*   IBIAS1 is the reference input node; IBIAS2 is an internally-generated
-*   second-tier bias (left to float to its own operating point); IOUT1/IOUT2
-*   are the two mirrored output branches.
+*   subckt name: Low_voltage_current_mirror (filename stem is low_voltage_cmirror)
+*   ports: IBIAS1 IBIAS2 GND IOUT1 IOUT2
+*   IBIAS1 and IBIAS2 are BOTH reference-current inputs (main + cascode bias);
+*   IOUT1/IOUT2 are the two mirrored output branches.
 *
 * Functional check: push a reference current into IBIAS1 and confirm both
 * output branches sink ~the same current (1:1 mirror) when held at mid-rail.
@@ -13,17 +13,21 @@
 * point is delicate -- calibrate the check bands against a golden ngspice run.
 .param VDD=1.8
 .param IREF=10u
-* Reference current into the IBIAS1 node.
-Iref 0 IBIAS1 DC {IREF}
+* This cell has TWO bias-current inputs: IBIAS1 (main mirror) and IBIAS2
+* (cascode level -- it is the Ib node of the second FVF and gates X4/X5).
+* Both must be driven, or the output cascodes are starved and sink ~0.
+* IBIAS2's value sets the cascode bias and may need a different magnitude
+* than IREF -- calibrate against a golden run.
+Iref  0 IBIAS1 DC {IREF}
+Iref2 0 IBIAS2 DC {IREF}
 * Outputs held near mid-rail through ammeters; i(vmX) is the sunk mirror current.
 Vsup DD 0 DC 0.9
 Vm1 DD IOUT1 DC 0
 Vm2 DD IOUT2 DC 0
 * DUT: IBIAS1 IBIAS2 GND IOUT1 IOUT2
 * GND port tied straight to node 0 (no source -- a 0 V source here both ends
-* on ground reads as a shorted VSRC and aborts the analysis). IBIAS2 left on
-* its own net.
-X1 IBIAS1 net_ibias2 0 IOUT1 IOUT2 low_voltage_cmirror
+* on ground reads as a shorted VSRC and aborts the analysis).
+X1 IBIAS1 IBIAS2 0 IOUT1 IOUT2 Low_voltage_current_mirror
 .dc Iref 2u 20u 1u
 .measure dc iout1_op FIND i(vm1) AT=10u
 .measure dc iout2_op FIND i(vm2) AT=10u