DEVELOPMENT_PLAN §1.3 (signal diagram) + §2.2. Third electronics session. **Scope** - [ ] 4 load cells on the 4 differential channels (PGA=64, ±78 mV) - [ ] Continuous acquisition loop at 1000 Hz + validate actual rate (sample counter) - [ ] Circular buffer + microsecond timestamps - [ ] Battery voltage divider 2× 100 kΩ → GPIO34 (validate ADC vs multimeter) - [ ] (Optional) battery indicator LEDs on GPIOs 21/22/25 **Gate:** 4 stable channels at 1000 Hz (~17–18 effective bits → ~0.075–0.15 N theoretical resolution). **Depends on:** #2 Ref: `docs/DEVELOPMENT_PLAN.md` §1.3, §1.4, §2.2.
DEVELOPMENT_PLAN §1.3 (signal diagram) + §2.2. Third electronics session.
Scope
Gate: 4 stable channels at 1000 Hz (~17–18 effective bits → ~0.075–0.15 N theoretical resolution).
Depends on: #2
Ref:
docs/DEVELOPMENT_PLAN.md§1.3, §1.4, §2.2.