diff --git a/.idea/NanoProcessor-Team-93.iml b/.idea/NanoProcessor-Team-93.iml new file mode 100644 index 0000000..d0876a7 --- /dev/null +++ b/.idea/NanoProcessor-Team-93.iml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/inspectionProfiles/profiles_settings.xml b/.idea/inspectionProfiles/profiles_settings.xml new file mode 100644 index 0000000..105ce2d --- /dev/null +++ b/.idea/inspectionProfiles/profiles_settings.xml @@ -0,0 +1,6 @@ + + + + \ No newline at end of file diff --git a/.idea/misc.xml b/.idea/misc.xml new file mode 100644 index 0000000..a4652f3 --- /dev/null +++ b/.idea/misc.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/.idea/modules.xml b/.idea/modules.xml new file mode 100644 index 0000000..3f6cf4e --- /dev/null +++ b/.idea/modules.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/vcs.xml b/.idea/vcs.xml new file mode 100644 index 0000000..94a25f7 --- /dev/null +++ b/.idea/vcs.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/.idea/workspace.xml b/.idea/workspace.xml new file mode 100644 index 0000000..1809893 --- /dev/null +++ b/.idea/workspace.xml @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + 1686213409510 + + + + \ No newline at end of file diff --git a/Lab9/Lab9.runs/synth_1/.Vivado_Synthesis.queue.rst b/Lab9/Lab9.runs/synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29..0000000 diff --git a/Lab9/Lab9.runs/synth_1/.vivado.begin.rst b/Lab9/Lab9.runs/synth_1/.vivado.begin.rst deleted file mode 100644 index 9030fda..0000000 --- a/Lab9/Lab9.runs/synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Lab9/Lab9.runs/synth_1/.vivado.end.rst b/Lab9/Lab9.runs/synth_1/.vivado.end.rst deleted file mode 100644 index e69de29..0000000 diff --git a/Lab9/Lab9.runs/synth_1/ISEWrap.js b/Lab9/Lab9.runs/synth_1/ISEWrap.js deleted file mode 100644 index 898ddd7..0000000 --- a/Lab9/Lab9.runs/synth_1/ISEWrap.js +++ /dev/null @@ -1,244 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/Lab9/Lab9.runs/synth_1/ISEWrap.sh b/Lab9/Lab9.runs/synth_1/ISEWrap.sh deleted file mode 100644 index e1a8f5d..0000000 --- a/Lab9/Lab9.runs/synth_1/ISEWrap.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/Lab9/Lab9.runs/synth_1/NanoProcessor.dcp b/Lab9/Lab9.runs/synth_1/NanoProcessor.dcp deleted file mode 100644 index df530fc..0000000 Binary files a/Lab9/Lab9.runs/synth_1/NanoProcessor.dcp and /dev/null differ diff --git a/Lab9/Lab9.runs/synth_1/NanoProcessor.tcl b/Lab9/Lab9.runs/synth_1/NanoProcessor.tcl deleted file mode 100644 index 0e9e415..0000000 --- a/Lab9/Lab9.runs/synth_1/NanoProcessor.tcl +++ /dev/null @@ -1,52 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -create_project -in_memory -part xc7a35tcpg236-1 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_property webtalk.parent_dir D:/projects/NanoProcessor-Team-93/Lab9/Lab9.cache/wt [current_project] -set_property parent.project_path D:/projects/NanoProcessor-Team-93/Lab9/Lab9.xpr [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language VHDL [current_project] -set_property board_part digilentinc.com:basys3:part0:1.2 [current_project] -set_property ip_output_repo d:/projects/NanoProcessor-Team-93/Lab9/Lab9.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_vhdl -library xil_defaultlib D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 0 -close [open __synthesis_is_running__ w] - -synth_design -top NanoProcessor -part xc7a35tcpg236-1 - - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef NanoProcessor.dcp -create_report "synth_1_synth_report_utilization_0" "report_utilization -file NanoProcessor_utilization_synth.rpt -pb NanoProcessor_utilization_synth.pb" -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/Lab9/Lab9.runs/synth_1/NanoProcessor.vds b/Lab9/Lab9.runs/synth_1/NanoProcessor.vds deleted file mode 100644 index 730aa99..0000000 --- a/Lab9/Lab9.runs/synth_1/NanoProcessor.vds +++ /dev/null @@ -1,216 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.2 (64-bit) -# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 -# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 -# Start of session at: Sun Jun 4 01:27:26 2023 -# Process ID: 29320 -# Current directory: D:/projects/NanoProcessor-Team-93/Lab9/Lab9.runs/synth_1 -# Command line: vivado.exe -log NanoProcessor.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NanoProcessor.tcl -# Log file: D:/projects/NanoProcessor-Team-93/Lab9/Lab9.runs/synth_1/NanoProcessor.vds -# Journal file: D:/projects/NanoProcessor-Team-93/Lab9/Lab9.runs/synth_1\vivado.jou -#----------------------------------------------------------- -source NanoProcessor.tcl -notrace -Command: synth_design -top NanoProcessor -part xc7a35tcpg236-1 -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 23324 ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 381.465 ; gain = 95.926 ---------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'NanoProcessor' [D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd:38] -INFO: [Synth 8-256] done synthesizing module 'NanoProcessor' (1#1) [D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd:38] -WARNING: [Synth 8-3330] design NanoProcessor has an empty top module ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 437.211 ; gain = 151.672 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 437.211 ; gain = 151.672 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7a35tcpg236-1 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 437.211 ; gain = 151.672 ---------------------------------------------------------------------------------- -INFO: [Device 21-403] Loading part xc7a35tcpg236-1 ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 437.211 ; gain = 151.672 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 90 (col length:60) -BRAMs: 100 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- -No constraint files found. ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -WARNING: [Synth 8-3330] design NanoProcessor has an empty top module ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ -No constraint files found. ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+--------------+------+ -| |Cell |Count | -+------+--------------+------+ -|1 |NanoProcessor | 1| -+------+--------------+------+ - -Report Instance Areas: -+------+---------+-------+------+ -| |Instance |Module |Cells | -+------+---------+-------+------+ -|1 |top | | 0| -+------+---------+-------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 -Synthesis Optimization Complete : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 536.957 ; gain = 251.418 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 654.227 ; gain = 380.789 -WARNING: [Constraints 18-5210] No constraint will be written out. -INFO: [Common 17-1381] The checkpoint 'D:/projects/NanoProcessor-Team-93/Lab9/Lab9.runs/synth_1/NanoProcessor.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file NanoProcessor_utilization_synth.rpt -pb NanoProcessor_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 654.227 ; gain = 0.000 -INFO: [Common 17-206] Exiting Vivado at Sun Jun 4 01:27:44 2023... diff --git a/Lab9/Lab9.runs/synth_1/NanoProcessor_utilization_synth.pb b/Lab9/Lab9.runs/synth_1/NanoProcessor_utilization_synth.pb deleted file mode 100644 index a29faa5..0000000 Binary files a/Lab9/Lab9.runs/synth_1/NanoProcessor_utilization_synth.pb and /dev/null differ diff --git a/Lab9/Lab9.runs/synth_1/NanoProcessor_utilization_synth.rpt b/Lab9/Lab9.runs/synth_1/NanoProcessor_utilization_synth.rpt deleted file mode 100644 index 0dad9f7..0000000 --- a/Lab9/Lab9.runs/synth_1/NanoProcessor_utilization_synth.rpt +++ /dev/null @@ -1,188 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -| Date : Sun Jun 4 01:27:44 2023 -| Host : DESKTOP-33P6OC5 running 64-bit major release (build 9200) -| Command : report_utilization -file NanoProcessor_utilization_synth.rpt -pb NanoProcessor_utilization_synth.pb -| Design : NanoProcessor -| Device : 7a35tcpg236-1 -| Design State : Fully Placed ---------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 0 | 0 | 20800 | 0.00 | -| LUT as Logic | 0 | 0 | 20800 | 0.00 | -| LUT as Memory | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 0 | 0 | 41600 | 0.00 | -| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | -| Register as Latch | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 0 | 0 | 16300 | 0.00 | -| F8 Muxes | 0 | 0 | 8150 | 0.00 | -+-------------------------+------+-------+-----------+-------+ - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 0 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Slice Logic Distribution ---------------------------- - -+--------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+--------------------------+------+-------+-----------+-------+ -| Slice | 0 | 0 | 8150 | 0.00 | -| SLICEL | 0 | 0 | | | -| SLICEM | 0 | 0 | | | -| LUT as Logic | 0 | 0 | 20800 | 0.00 | -| LUT as Memory | 0 | 0 | 9600 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 | -| Unique Control Sets | 0 | | | | -+--------------------------+------+-------+-----------+-------+ -* Note: Review the Control Sets Report for more information regarding control sets. - - -3. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 50 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | -| RAMB18 | 0 | 0 | 100 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -4. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 90 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -5. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 106 | 0.00 | -| Bonded IPADs | 0 | 0 | 10 | 0.00 | -| Bonded OPADs | 0 | 0 | 4 | 0.00 | -| PHY_CONTROL | 0 | 0 | 5 | 0.00 | -| PHASER_REF | 0 | 0 | 5 | 0.00 | -| OUT_FIFO | 0 | 0 | 20 | 0.00 | -| IN_FIFO | 0 | 0 | 20 | 0.00 | -| IDELAYCTRL | 0 | 0 | 5 | 0.00 | -| IBUFDS | 0 | 0 | 104 | 0.00 | -| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | -| ILOGIC | 0 | 0 | 106 | 0.00 | -| OLOGIC | 0 | 0 | 106 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -6. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 20 | 0.00 | -| MMCME2_ADV | 0 | 0 | 5 | 0.00 | -| PLLE2_ADV | 0 | 0 | 5 | 0.00 | -| BUFMRCE | 0 | 0 | 10 | 0.00 | -| BUFHCE | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 20 | 0.00 | -+------------+------+-------+-----------+-------+ - - -7. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -8. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ - - -9. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -10. Instantiated Netlists -------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/Lab9/Lab9.runs/synth_1/__synthesis_is_complete__ b/Lab9/Lab9.runs/synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29..0000000 diff --git a/Lab9/Lab9.runs/synth_1/gen_run.xml b/Lab9/Lab9.runs/synth_1/gen_run.xml deleted file mode 100644 index dacd1a8..0000000 --- a/Lab9/Lab9.runs/synth_1/gen_run.xml +++ /dev/null @@ -1,130 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Lab9/Lab9.runs/synth_1/htr.txt b/Lab9/Lab9.runs/synth_1/htr.txt deleted file mode 100644 index d97f861..0000000 --- a/Lab9/Lab9.runs/synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log NanoProcessor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NanoProcessor.tcl diff --git a/Lab9/Lab9.runs/synth_1/rundef.js b/Lab9/Lab9.runs/synth_1/rundef.js deleted file mode 100644 index a97d6d8..0000000 --- a/Lab9/Lab9.runs/synth_1/rundef.js +++ /dev/null @@ -1,36 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -// - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "D:/SDK/2018.2/bin;D:/Vivado/2018.2/ids_lite/ISE/bin/nt64;D:/Vivado/2018.2/ids_lite/ISE/lib/nt64;D:/Vivado/2018.2/bin;"; -} else { - PathVal = "D:/SDK/2018.2/bin;D:/Vivado/2018.2/ids_lite/ISE/bin/nt64;D:/Vivado/2018.2/ids_lite/ISE/lib/nt64;D:/Vivado/2018.2/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log NanoProcessor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NanoProcessor.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/Lab9/Lab9.runs/synth_1/runme.bat b/Lab9/Lab9.runs/synth_1/runme.bat deleted file mode 100644 index 73c8b46..0000000 --- a/Lab9/Lab9.runs/synth_1/runme.bat +++ /dev/null @@ -1,10 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Lab9/Lab9.runs/synth_1/runme.sh b/Lab9/Lab9.runs/synth_1/runme.sh deleted file mode 100644 index e8dc4ef..0000000 --- a/Lab9/Lab9.runs/synth_1/runme.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -# - -echo "This script was generated under a different operating system." -echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" -exit - -if [ -z "$PATH" ]; then - PATH=D:/SDK/2018.2/bin;D:/Vivado/2018.2/ids_lite/ISE/bin/nt64;D:/Vivado/2018.2/ids_lite/ISE/lib/nt64:D:/Vivado/2018.2/bin -else - PATH=D:/SDK/2018.2/bin;D:/Vivado/2018.2/ids_lite/ISE/bin/nt64;D:/Vivado/2018.2/ids_lite/ISE/lib/nt64:D:/Vivado/2018.2/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='D:/projects/NanoProcessor-Team-93/Lab9/Lab9.runs/synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log NanoProcessor.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source NanoProcessor.tcl diff --git a/Lab9/Lab9.runs/synth_1/vivado.pb b/Lab9/Lab9.runs/synth_1/vivado.pb index aca2328..ef223e2 100644 Binary files a/Lab9/Lab9.runs/synth_1/vivado.pb and b/Lab9/Lab9.runs/synth_1/vivado.pb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit_behav.wdb new file mode 100644 index 0000000..603c600 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit_vhdl.prj b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit_vhdl.prj new file mode 100644 index 0000000..499c6a3 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_3Bit_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../Lab9.srcs/sources_1/new/FA.vhd" \ +"../../../../Lab9.srcs/sources_1/new/HA.vhd" \ +"../../../../Lab9.srcs/sources_1/new/adder_3bit.vhd" \ +"../../../../Lab9.srcs/sim_1/new/TB_Adder_3Bit.vhd" \ + +# Do not sort compile order +nosort diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub_behav.wdb new file mode 100644 index 0000000..4acd750 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub_vhdl.prj b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub_vhdl.prj new file mode 100644 index 0000000..60ec4c3 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Adder_sub_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../Lab9.srcs/sources_1/new/FA.vhd" \ +"../../../../Lab9.srcs/sources_1/new/HA.vhd" \ +"../../../../Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd" \ +"../../../../Lab9.srcs/sim_1/new/TB_Adder_sub.vhd" \ + +# Do not sort compile order +nosort diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_2_way_3_bit_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_2_way_3_bit_behav.wdb index 0ede1f8..c88fc0a 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_2_way_3_bit_behav.wdb and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_2_way_3_bit_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit_behav.wdb new file mode 100644 index 0000000..e556b9d Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit_vhdl.prj b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit_vhdl.prj new file mode 100644 index 0000000..bf4e73b --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_MUX_8_way_4_bit_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../Lab9.srcs/sources_1/new/Decoder_2_to_4.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Decoder_3_to_8.vhd" \ +"../../../../Lab9.srcs/sources_1/new/MUX_8_way_4_bit.vhd" \ +"../../../../Lab9.srcs/sim_1/new/TB_MUX_8_way_4_bit.vhd" \ + +# Do not sort compile order +nosort diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor_behav.wdb new file mode 100644 index 0000000..82d38de Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor_vhdl.prj b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor_vhdl.prj new file mode 100644 index 0000000..a0b4550 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_NanoProcessor_vhdl.prj @@ -0,0 +1,24 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../Lab9.srcs/sources_1/new/Decoder_1_to_2.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Decoder_2_to_4.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Decoder_3_to_8.vhd" \ +"../../../../Lab9.srcs/sources_1/new/FA.vhd" \ +"../../../../Lab9.srcs/sources_1/new/HA.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Instruction_decoder.vhd" \ +"../../../../Lab9.srcs/sources_1/new/LUT_16_7.vhd" \ +"../../../../Lab9.srcs/sources_1/new/MUX_2_way_3_bit.vhd" \ +"../../../../Lab9.srcs/sources_1/new/MUX_2_way_4_bits.vhd" \ +"../../../../Lab9.srcs/sources_1/new/MUX_8_way_4_bit.vhd" \ +"../../../../Lab9.srcs/sources_1/new/NanoProcessor.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Program_Counter.vhd" \ +"../../../../Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd" \ +"../../../../Lab9.srcs/sources_1/new/ROM.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Register_Bank.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Registers.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Slow_Clk.vhd" \ +"../../../../Lab9.srcs/sources_1/new/adder_3bit.vhd" \ +"../../../../Lab9.srcs/sim_1/new/TB_NanoProcessor.vhd" \ + +# Do not sort compile order +nosort diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter_behav.wdb new file mode 100644 index 0000000..2be6c0a Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter_vhdl.prj b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter_vhdl.prj new file mode 100644 index 0000000..36546eb --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Program_Counter_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../Lab9.srcs/sources_1/new/Program_Counter.vhd" \ +"../../../../Lab9.srcs/sim_1/new/TB_Program_Counter.vhd" \ + +# Do not sort compile order +nosort diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor_behav.wdb new file mode 100644 index 0000000..214969c Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor_vhdl.prj b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor_vhdl.prj new file mode 100644 index 0000000..d1cf57b --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_RCA_Adder_subtractor_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../Lab9.srcs/sources_1/new/FA.vhd" \ +"../../../../Lab9.srcs/sources_1/new/HA.vhd" \ +"../../../../Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd" \ +"../../../../Lab9.srcs/sim_1/new/TB_RCA_Adder_subtractor.vhd" \ + +# Do not sort compile order +nosort diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank_behav.wdb new file mode 100644 index 0000000..3669bc4 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank_vhdl.prj b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank_vhdl.prj new file mode 100644 index 0000000..9d6d572 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_Bank_vhdl.prj @@ -0,0 +1,10 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../Lab9.srcs/sources_1/new/Decoder_2_to_4.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Decoder_3_to_8.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Register_Bank.vhd" \ +"../../../../Lab9.srcs/sources_1/new/Registers.vhd" \ +"../../../../Lab9.srcs/sim_1/new/TB_Register_Bank.vhd" \ + +# Do not sort compile order +nosort diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_behav.wdb b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_behav.wdb new file mode 100644 index 0000000..b06f409 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_behav.wdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_vhdl.prj b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_vhdl.prj new file mode 100644 index 0000000..005d584 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/TB_Register_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../Lab9.srcs/sources_1/new/Registers.vhd" \ +"../../../../Lab9.srcs/sim_1/new/TB_Register.vhd" \ + +# Do not sort compile order +nosort diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/compile.bat b/Lab9/Lab9.sim/sim_1/behav/xsim/compile.bat index ecac110..4dc3e6b 100644 --- a/Lab9/Lab9.sim/sim_1/behav/xsim/compile.bat +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/compile.bat @@ -6,7 +6,7 @@ REM Filename : compile.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for compiling the simulation design source files REM -REM Generated by Vivado on Sun Jun 04 02:00:00 +0530 2023 +REM Generated by Vivado on Thu Jun 08 18:05:01 +0530 2023 REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 REM REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. @@ -14,8 +14,8 @@ REM REM usage: compile.bat REM REM **************************************************************************** -echo "xvhdl --incr --relax -prj TB_MUX_2_way_3_bit_vhdl.prj" -call xvhdl --incr --relax -prj TB_MUX_2_way_3_bit_vhdl.prj -log xvhdl.log +echo "xvhdl --incr --relax -prj TB_NanoProcessor_vhdl.prj" +call xvhdl --incr --relax -prj TB_NanoProcessor_vhdl.prj -log xvhdl.log call type xvhdl.log > compile.log if "%errorlevel%"=="1" goto END if "%errorlevel%"=="0" goto SUCCESS diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/elaborate.bat b/Lab9/Lab9.sim/sim_1/behav/xsim/elaborate.bat index 7d5e053..527da39 100644 --- a/Lab9/Lab9.sim/sim_1/behav/xsim/elaborate.bat +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/elaborate.bat @@ -6,7 +6,7 @@ REM Filename : elaborate.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for elaborating the compiled design REM -REM Generated by Vivado on Sun Jun 04 02:00:02 +0530 2023 +REM Generated by Vivado on Thu Jun 08 18:05:03 +0530 2023 REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 REM REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. @@ -14,7 +14,7 @@ REM REM usage: elaborate.bat REM REM **************************************************************************** -call xelab -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_MUX_2_way_3_bit_behav xil_defaultlib.TB_MUX_2_way_3_bit -log elaborate.log +call xelab -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_NanoProcessor_behav xil_defaultlib.TB_NanoProcessor -log elaborate.log if "%errorlevel%"=="0" goto SUCCESS if "%errorlevel%"=="1" goto END :END diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/simulate.bat b/Lab9/Lab9.sim/sim_1/behav/xsim/simulate.bat index 5d4e100..91bd074 100644 --- a/Lab9/Lab9.sim/sim_1/behav/xsim/simulate.bat +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/simulate.bat @@ -6,7 +6,7 @@ REM Filename : simulate.bat REM Simulator : Xilinx Vivado Simulator REM Description : Script for simulating the design by launching the simulator REM -REM Generated by Vivado on Sun Jun 04 02:00:10 +0530 2023 +REM Generated by Vivado on Thu Jun 08 18:05:06 +0530 2023 REM SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 REM REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. @@ -14,7 +14,7 @@ REM REM usage: simulate.bat REM REM **************************************************************************** -call xsim TB_MUX_2_way_3_bit_behav -key {Behavioral:sim_1:Functional:TB_MUX_2_way_3_bit} -tclbatch TB_MUX_2_way_3_bit.tcl -log simulate.log +call xsim TB_NanoProcessor_behav -key {Behavioral:sim_1:Functional:TB_NanoProcessor} -tclbatch TB_NanoProcessor.tcl -log simulate.log if "%errorlevel%"=="0" goto SUCCESS if "%errorlevel%"=="1" goto END :END diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xelab.pb b/Lab9/Lab9.sim/sim_1/behav/xsim/xelab.pb index 910bacb..386b64b 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xelab.pb and b/Lab9/Lab9.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav.wdb/xsimSettings.ini b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav.wdb/xsimSettings.ini new file mode 100644 index 0000000..bd7b01d --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav.wdb/xsimSettings.ini @@ -0,0 +1,35 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=2147483647 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=150 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=90 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=83 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=0 +PROCESS_TYPE_COLUMN_WIDTH=0 +FRAME_INDEX_COLUMN_WIDTH=0 +FRAME_NAME_COLUMN_WIDTH=0 +FRAME_FILE_NAME_COLUMN_WIDTH=0 +FRAME_LINE_NUM_COLUMN_WIDTH=0 +LOCAL_NAME_COLUMN_WIDTH=0 +LOCAL_VALUE_COLUMN_WIDTH=0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/Compile_Options.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/Compile_Options.txt new file mode 100644 index 0000000..458fbfc --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c036f6d3b11b46258ae2394c8cc98222" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Adder_3Bit_behav" "xil_defaultlib.TB_Adder_3Bit" -log "elaborate.log" diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/TempBreakPointFile.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..3198a84 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_1.c b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_1.c new file mode 100644 index 0000000..21a677e --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_1.c @@ -0,0 +1,103 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_37(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[6] = {(funcp)execute_37, (funcp)execute_17, (funcp)execute_18, (funcp)execute_12, (funcp)execute_13, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 6; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Adder_3Bit_behav/xsim.reloc", (void **)funcTab, 6); + iki_vhdl_file_variable_register(dp + 6064); + iki_vhdl_file_variable_register(dp + 6120); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Adder_3Bit_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Adder_3Bit_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Adder_3Bit_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Adder_3Bit_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Adder_3Bit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_1.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..c311555 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/obj/xsim_1.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..c42c492 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1686137820 +1686137908 +11 +1 +c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.wdm b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/usage_statistics_ext_xsim.wdm similarity index 100% rename from Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.wdm rename to Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/usage_statistics_ext_xsim.wdm diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/xsim_webtalk.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..c1b4440 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,42 @@ +webtalk_init -webtalk_dir C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Wed Jun 7 17:37:23 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "e3355ad9-3a98-4321-a981-98669d875211" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "c036f6d3b11b46258ae2394c8cc98222" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "10" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "AMD Ryzen 3 5300U with Radeon Graphics " -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2595 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "7.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key File_Counter -value "8" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "64 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "3 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "19" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "14" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.86_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "53432_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2772093733 -regid "" -xml C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.dbg new file mode 100644 index 0000000..c2f6f00 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.mem new file mode 100644 index 0000000..45f1806 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.reloc b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.reloc new file mode 100644 index 0000000..871b965 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.reloc differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.rlx new file mode 100644 index 0000000..358c26d --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 783272607167326770 , + ccp_crc : 0 , + cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Adder_3Bit_behav xil_defaultlib.TB_Adder_3Bit" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Adder_3Bit_behav/xsimk.exe\" \"xsim.dir/TB_Adder_3Bit_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Adder_3Bit_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.rtti new file mode 100644 index 0000000..5a433b5 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.svtype b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.svtype differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.type new file mode 100644 index 0000000..1af8161 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.xdbg new file mode 100644 index 0000000..ef29512 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsimSettings.ini b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsimSettings.ini new file mode 100644 index 0000000..38f4bee --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsimk.exe b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsimk.exe new file mode 100644 index 0000000..8fc820c Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_3Bit_behav/xsimk.exe differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/Compile_Options.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/Compile_Options.txt new file mode 100644 index 0000000..2835e26 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c036f6d3b11b46258ae2394c8cc98222" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Adder_sub_behav" "xil_defaultlib.TB_Adder_sub" -log "elaborate.log" diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/TempBreakPointFile.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..728b3bb Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_1.c b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_1.c new file mode 100644 index 0000000..0623ddf --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_1.c @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_56(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_53(char*, char *); +extern void execute_54(char*, char *); +extern void execute_55(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_56, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_24, (funcp)execute_25, (funcp)execute_19, (funcp)execute_20, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Adder_sub_behav/xsim.reloc", (void **)funcTab, 15); + iki_vhdl_file_variable_register(dp + 7624); + iki_vhdl_file_variable_register(dp + 7680); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Adder_sub_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Adder_sub_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Adder_sub_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Adder_sub_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Adder_sub_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_1.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..243ef1d Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/obj/xsim_1.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..fbb7007 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1686136053 +1686136194 +5 +1 +c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/usage_statistics_ext_xsim.wdm b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/xsim_webtalk.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..f8d2871 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Wed Jun 7 17:25:55 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "e3355ad9-3a98-4321-a981-98669d875211" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "c036f6d3b11b46258ae2394c8cc98222" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "AMD Ryzen 3 5300U with Radeon Graphics " -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2595 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "7.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "7964_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3610143161 -regid "" -xml C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.dbg new file mode 100644 index 0000000..3e93e71 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.mem new file mode 100644 index 0000000..c4cb367 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.reloc b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.reloc new file mode 100644 index 0000000..ae1e29c Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.reloc differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.rlx new file mode 100644 index 0000000..4ace5e3 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 6678279510378625714 , + ccp_crc : 0 , + cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Adder_sub_behav xil_defaultlib.TB_Adder_sub" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Adder_sub_behav/xsimk.exe\" \"xsim.dir/TB_Adder_sub_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Adder_sub_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.rtti new file mode 100644 index 0000000..3b33d35 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.svtype b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.svtype differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.type new file mode 100644 index 0000000..485ecdb Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.xdbg new file mode 100644 index 0000000..a905ca4 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsimSettings.ini b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsimSettings.ini new file mode 100644 index 0000000..38f4bee --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsimk.exe b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsimk.exe new file mode 100644 index 0000000..c1c7416 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Adder_sub_behav/xsimk.exe differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/obj/xsim_0.win64.obj index 793df23..74a03b2 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/obj/xsim_0.win64.obj and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/.xsim_webtallk.info index 2b9749d..c3f4102 100644 --- a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/.xsim_webtallk.info +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/.xsim_webtallk.info @@ -1,5 +1,5 @@ -1685824205 -0 -2 +1686112131 +1686112673 +4 1 c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.html b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.html index 35e9dbf..72ac81d 100644 --- a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.html +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.html @@ -4,11 +4,11 @@ software_version_and_target_device betaFALSE build_version2258646 - date_generatedSun Jun 4 02:00:05 2023 + date_generatedWed Jun 7 10:07:53 2023 os_platformWIN64 product_versionXSIM v2018.2 (64-bit) project_idc036f6d3b11b46258ae2394c8cc98222 - project_iteration1 + project_iteration3 random_id91ea39e5fcfc55108cea2d38c5723418 registration_id91ea39e5fcfc55108cea2d38c5723418 route_designFALSE @@ -35,27 +35,17 @@ - - - - - - - - +
command_line_options
command=xelabdebug=typicaldpi_used=falsefile_counter=7
gendll=falsehwcosim=falsesdfmodeling=falsevhdl2008=false
command=xsim
- - - - - - - - + + + + +
usage
compiler_memory=53516_KBcompiler_time=0.31_secsimulation_image_code=72 KBsimulation_image_data=2 KB
total_instances=6total_nets=0total_processes=7xilinx_hdl_libraries_used=secureip
iteration=5runtime=1 ussimulation_memory=7132_KBsimulation_time=0.00_sec
trace_waveform=true

diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.xml b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.xml index 787157d..dc27078 100644 --- a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.xml +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/webtalk/usage_statistics_ext_xsim.xml @@ -1,14 +1,14 @@ - +
- + - + @@ -30,24 +30,14 @@
- - - - - - - - +
- - - - - - - - + + + + +
diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.dbg index 53e8a35..9eb828e 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.dbg and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.mem index 69571c2..76356b0 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.mem and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.rlx index 392d472..dab8ef1 100644 --- a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.rlx +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.rlx @@ -1,6 +1,6 @@ { - crc : 5586228104223629120 , + crc : 3717528624420763106 , ccp_crc : 0 , cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_MUX_2_way_3_bit_behav xil_defaultlib.TB_MUX_2_way_3_bit" , buildDate : "Jun 14 2018" , diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.rtti index 5b6e94c..52dd282 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.rtti and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.type index a64bf27..a731282 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.type and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.xdbg index bd1bae7..5e169a5 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.xdbg and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsimSettings.ini b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsimSettings.ini new file mode 100644 index 0000000..38f4bee --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsimk.exe b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsimk.exe index 0cc8d75..c508691 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsimk.exe and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_2_way_3_bit_behav/xsimk.exe differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/Compile_Options.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/Compile_Options.txt new file mode 100644 index 0000000..321702e --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c036f6d3b11b46258ae2394c8cc98222" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_MUX_8_way_4_bit_behav" "xil_defaultlib.TB_MUX_8_way_4_bit" -log "elaborate.log" diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/TempBreakPointFile.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..0412427 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_1.c b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_1.c new file mode 100644 index 0000000..b985ff0 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_1.c @@ -0,0 +1,128 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_39(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void transaction_2(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_3(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_4(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_5(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_6(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_7(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_8(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_9(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[31] = {(funcp)execute_39, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)transaction_2, (funcp)transaction_3, (funcp)transaction_4, (funcp)transaction_5, (funcp)transaction_6, (funcp)transaction_7, (funcp)transaction_8, (funcp)transaction_9, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 31; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.reloc", (void **)funcTab, 31); + iki_vhdl_file_variable_register(dp + 7320); + iki_vhdl_file_variable_register(dp + 7376); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_1.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..0769cfe Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_1.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..968ea27 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1686205944 +1686207030 +5 +1 +c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.html b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..4a52713 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedThu Jun 8 12:20:30 2023os_platformWIN64
product_versionXSIM v2018.2 (64-bit)project_idc036f6d3b11b46258ae2394c8cc98222
project_iteration2random_id91ea39e5fcfc55108cea2d38c5723418
registration_id91ea39e5fcfc55108cea2d38c5723418route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_name11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHzcpu_speed1690 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=6runtime=1 ussimulation_memory=7728_KBsimulation_time=0.01_sec
trace_waveform=true
+

+ + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.wdm b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.xml b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..251f4fe --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/xsim_webtalk.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..042263a --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Jun 8 14:43:42 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "91ea39e5fcfc55108cea2d38c5723418" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "c036f6d3b11b46258ae2394c8cc98222" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "1690 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "7" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "7164_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3880715122 -regid "" -xml D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.dbg new file mode 100644 index 0000000..95c3dfb Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.mem new file mode 100644 index 0000000..f7f0462 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.reloc b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.reloc new file mode 100644 index 0000000..bef4ed4 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.reloc differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.rlx new file mode 100644 index 0000000..e0f9d6d --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 8862478698079749564 , + ccp_crc : 0 , + cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_MUX_8_way_4_bit_behav xil_defaultlib.TB_MUX_8_way_4_bit" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "D:\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_MUX_8_way_4_bit_behav/xsimk.exe\" \"xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_MUX_8_way_4_bit_behav/obj/xsim_1.win64.obj\" \"D:\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"D:\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.rtti new file mode 100644 index 0000000..fb817ef Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.svtype b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.svtype differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.type new file mode 100644 index 0000000..5f7f591 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.xdbg new file mode 100644 index 0000000..6bc178a Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsimSettings.ini b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsimSettings.ini new file mode 100644 index 0000000..38f4bee --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsimk.exe b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsimk.exe new file mode 100644 index 0000000..40858b7 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_MUX_8_way_4_bit_behav/xsimk.exe differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/Compile_Options.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/Compile_Options.txt new file mode 100644 index 0000000..18b2c87 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c036f6d3b11b46258ae2394c8cc98222" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_NanoProcessor_behav" "xil_defaultlib.TB_NanoProcessor" -log "elaborate.log" diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/TempBreakPointFile.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..2573c56 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_1.c b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_1.c new file mode 100644 index 0000000..2b21630 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_1.c @@ -0,0 +1,194 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_250(char*, char *); +extern void execute_248(char*, char *); +extern void execute_249(char*, char *); +extern void execute_17(char*, char *); +extern void execute_19(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void execute_42(char*, char *); +extern void execute_43(char*, char *); +extern void execute_44(char*, char *); +extern void execute_45(char*, char *); +extern void execute_46(char*, char *); +extern void execute_47(char*, char *); +extern void execute_48(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_68(char*, char *); +extern void execute_69(char*, char *); +extern void execute_61(char*, char *); +extern void execute_62(char*, char *); +extern void execute_63(char*, char *); +extern void execute_64(char*, char *); +extern void execute_65(char*, char *); +extern void execute_66(char*, char *); +extern void execute_67(char*, char *); +extern void execute_71(char*, char *); +extern void execute_72(char*, char *); +extern void execute_95(char*, char *); +extern void execute_97(char*, char *); +extern void execute_98(char*, char *); +extern void execute_99(char*, char *); +extern void execute_100(char*, char *); +extern void execute_101(char*, char *); +extern void execute_102(char*, char *); +extern void execute_139(char*, char *); +extern void execute_140(char*, char *); +extern void execute_141(char*, char *); +extern void execute_110(char*, char *); +extern void execute_111(char*, char *); +extern void execute_105(char*, char *); +extern void execute_106(char*, char *); +extern void execute_174(char*, char *); +extern void execute_175(char*, char *); +extern void execute_176(char*, char *); +extern void execute_177(char*, char *); +extern void execute_172(char*, char *); +extern void execute_173(char*, char *); +extern void execute_197(char*, char *); +extern void execute_198(char*, char *); +extern void execute_199(char*, char *); +extern void execute_200(char*, char *); +extern void execute_201(char*, char *); +extern void execute_202(char*, char *); +extern void execute_203(char*, char *); +extern void execute_204(char*, char *); +extern void execute_205(char*, char *); +extern void execute_206(char*, char *); +extern void execute_240(char*, char *); +extern void execute_241(char*, char *); +extern void execute_242(char*, char *); +extern void execute_243(char*, char *); +extern void execute_245(char*, char *); +extern void execute_247(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_8(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_9(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_10(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_11(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_12(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_13(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_14(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_15(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_16(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_17(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_20(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_22(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_25(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_28(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_29(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[97] = {(funcp)execute_250, (funcp)execute_248, (funcp)execute_249, (funcp)execute_17, (funcp)execute_19, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_68, (funcp)execute_69, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_71, (funcp)execute_72, (funcp)execute_95, (funcp)execute_97, (funcp)execute_98, (funcp)execute_99, (funcp)execute_100, (funcp)execute_101, (funcp)execute_102, (funcp)execute_139, (funcp)execute_140, (funcp)execute_141, (funcp)execute_110, (funcp)execute_111, (funcp)execute_105, (funcp)execute_106, (funcp)execute_174, (funcp)execute_175, (funcp)execute_176, (funcp)execute_177, (funcp)execute_172, (funcp)execute_173, (funcp)execute_197, (funcp)execute_198, (funcp)execute_199, (funcp)execute_200, (funcp)execute_201, (funcp)execute_202, (funcp)execute_203, (funcp)execute_204, (funcp)execute_205, (funcp)execute_206, (funcp)execute_240, (funcp)execute_241, (funcp)execute_242, (funcp)execute_243, (funcp)execute_245, (funcp)execute_247, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_8, (funcp)transaction_9, (funcp)transaction_10, (funcp)transaction_11, (funcp)transaction_12, (funcp)transaction_13, (funcp)transaction_14, (funcp)transaction_15, (funcp)transaction_16, (funcp)transaction_17, (funcp)transaction_20, (funcp)transaction_22, (funcp)transaction_25, (funcp)transaction_28, (funcp)transaction_29}; +const int NumRelocateId= 97; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_NanoProcessor_behav/xsim.reloc", (void **)funcTab, 97); + iki_vhdl_file_variable_register(dp + 36240); + iki_vhdl_file_variable_register(dp + 36296); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_NanoProcessor_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_NanoProcessor_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_NanoProcessor_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_NanoProcessor_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_NanoProcessor_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_1.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..3af0c8c Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/obj/xsim_1.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..4d08d33 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1686210014 +1686210151 +36 +1 +c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.html b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..d9c2cdb --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedThu Jun 8 13:12:31 2023os_platformWIN64
product_versionXSIM v2018.2 (64-bit)project_idc036f6d3b11b46258ae2394c8cc98222
project_iteration2random_id91ea39e5fcfc55108cea2d38c5723418
registration_id91ea39e5fcfc55108cea2d38c5723418route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_name11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHzcpu_speed1690 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=1runtime=1 ussimulation_memory=7872_KBsimulation_time=0.00_sec
trace_waveform=true
+

+ + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.wdm b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.xml b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..6fcb699 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/xsim_webtalk.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..a420855 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,42 @@ +webtalk_init -webtalk_dir D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Jun 8 18:05:06 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "91ea39e5fcfc55108cea2d38c5723418" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "c036f6d3b11b46258ae2394c8cc98222" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "35" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "1690 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key File_Counter -value "25" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "126 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "10 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "180" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "58" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.33_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "53508_KB" -context "xsim\\usage" +webtalk_transmit -clientid 499207047 -regid "" -xml D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.dbg new file mode 100644 index 0000000..87e64ba Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.mem new file mode 100644 index 0000000..5bda450 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.reloc b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.reloc new file mode 100644 index 0000000..faca1d8 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.reloc differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.rlx new file mode 100644 index 0000000..540eed1 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 7490033418177953436 , + ccp_crc : 0 , + cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_NanoProcessor_behav xil_defaultlib.TB_NanoProcessor" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "D:\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_NanoProcessor_behav/xsimk.exe\" \"xsim.dir/TB_NanoProcessor_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_NanoProcessor_behav/obj/xsim_1.win64.obj\" \"D:\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"D:\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.rtti new file mode 100644 index 0000000..b686f7f Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.svtype b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.svtype differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.type new file mode 100644 index 0000000..0088a6b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.xdbg new file mode 100644 index 0000000..c76158b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsimSettings.ini b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsimSettings.ini new file mode 100644 index 0000000..38f4bee --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsimk.exe b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsimk.exe new file mode 100644 index 0000000..55e6e32 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_NanoProcessor_behav/xsimk.exe differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/Compile_Options.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/Compile_Options.txt new file mode 100644 index 0000000..bc0cff9 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c036f6d3b11b46258ae2394c8cc98222" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Program_Counter_behav" "xil_defaultlib.TB_Program_Counter" -log "elaborate.log" diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/TempBreakPointFile.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..f9a8549 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_1.c b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_1.c new file mode 100644 index 0000000..266e5b9 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_1.c @@ -0,0 +1,102 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_9(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[5] = {(funcp)execute_10, (funcp)execute_11, (funcp)execute_9, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 5; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Program_Counter_behav/xsim.reloc", (void **)funcTab, 5); + iki_vhdl_file_variable_register(dp + 2648); + iki_vhdl_file_variable_register(dp + 2704); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Program_Counter_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Program_Counter_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Program_Counter_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Program_Counter_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Program_Counter_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_1.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..6062412 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/obj/xsim_1.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..3ef96e8 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1686141265 +0 +2 +1 +c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.dbg new file mode 100644 index 0000000..4587dd0 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.mem new file mode 100644 index 0000000..81445a9 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.reloc b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.reloc new file mode 100644 index 0000000..95230eb Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.reloc differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.rlx new file mode 100644 index 0000000..28277fa --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 6638432506683235456 , + ccp_crc : 0 , + cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Program_Counter_behav xil_defaultlib.TB_Program_Counter" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Program_Counter_behav/xsimk.exe\" \"xsim.dir/TB_Program_Counter_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Program_Counter_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.rtti new file mode 100644 index 0000000..598b627 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.svtype b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.svtype differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.type new file mode 100644 index 0000000..efe9609 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.xdbg new file mode 100644 index 0000000..6eb0112 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsimk.exe b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsimk.exe new file mode 100644 index 0000000..9ba9a2a Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Program_Counter_behav/xsimk.exe differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/Compile_Options.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/Compile_Options.txt new file mode 100644 index 0000000..4331f17 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c036f6d3b11b46258ae2394c8cc98222" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_RCA_Adder_subtractor_behav" "xil_defaultlib.TB_RCA_Adder_subtractor" -log "elaborate.log" diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/TempBreakPointFile.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..a693321 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_1.c b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_1.c new file mode 100644 index 0000000..2b11d01 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_1.c @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_56(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_55(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_56, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_55, (funcp)execute_26, (funcp)execute_27, (funcp)execute_21, (funcp)execute_22, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.reloc", (void **)funcTab, 15); + iki_vhdl_file_variable_register(dp + 7624); + iki_vhdl_file_variable_register(dp + 7680); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_1.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..b9f3315 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_1.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..6b1e857 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1686112172 +1686112358 +5 +1 +c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.html b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..53924f6 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedWed Jun 7 10:02:38 2023os_platformWIN64
product_versionXSIM v2018.2 (64-bit)project_idc036f6d3b11b46258ae2394c8cc98222
project_iteration2random_id91ea39e5fcfc55108cea2d38c5723418
registration_id91ea39e5fcfc55108cea2d38c5723418route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_name11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHzcpu_speed1690 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=3runtime=1 ussimulation_memory=7696_KBsimulation_time=0.00_sec
trace_waveform=true
+

+ + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.wdm b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.xml b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..0ca6ba1 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/xsim_webtalk.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..b571e46 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Wed Jun 7 10:07:52 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "91ea39e5fcfc55108cea2d38c5723418" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "c036f6d3b11b46258ae2394c8cc98222" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "1690 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "9" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "7144_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3987367689 -regid "" -xml D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/projects/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.dbg new file mode 100644 index 0000000..4ae902d Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.mem new file mode 100644 index 0000000..8b5f225 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.reloc b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.reloc new file mode 100644 index 0000000..b11e4aa Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.reloc differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.rlx new file mode 100644 index 0000000..086583e --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 4086819509640164394 , + ccp_crc : 0 , + cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_RCA_Adder_subtractor_behav xil_defaultlib.TB_RCA_Adder_subtractor" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "D:\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_RCA_Adder_subtractor_behav/xsimk.exe\" \"xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_RCA_Adder_subtractor_behav/obj/xsim_1.win64.obj\" \"D:\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"D:\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.rtti new file mode 100644 index 0000000..8100409 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.svtype b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.svtype differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.type new file mode 100644 index 0000000..6f5cc58 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.xdbg new file mode 100644 index 0000000..83f90e7 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsimSettings.ini b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsimSettings.ini new file mode 100644 index 0000000..38f4bee --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsimk.exe b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsimk.exe new file mode 100644 index 0000000..b584362 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_RCA_Adder_subtractor_behav/xsimk.exe differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/Compile_Options.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/Compile_Options.txt new file mode 100644 index 0000000..369a3f5 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c036f6d3b11b46258ae2394c8cc98222" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Register_Bank_behav" "xil_defaultlib.TB_Register_Bank" -log "elaborate.log" diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/TempBreakPointFile.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..107ddda Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_1.c b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_1.c new file mode 100644 index 0000000..f4ca64e --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_1.c @@ -0,0 +1,116 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_52(char*, char *); +extern void execute_53(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[19] = {(funcp)execute_52, (funcp)execute_53, (funcp)execute_29, (funcp)execute_30, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_32, (funcp)execute_33, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 19; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Register_Bank_behav/xsim.reloc", (void **)funcTab, 19); + iki_vhdl_file_variable_register(dp + 8120); + iki_vhdl_file_variable_register(dp + 8176); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Register_Bank_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Register_Bank_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Register_Bank_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Register_Bank_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Register_Bank_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_1.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..d0bb50e Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/obj/xsim_1.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..23d9f12 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1686218889 +1686134473 +14 +1 +c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/usage_statistics_ext_xsim.html b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..2fc6bc6 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,63 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2258646
date_generatedThu Jun 8 15:38:09 2023os_platformWIN64
product_versionXSIM v2018.2 (64-bit)project_idc036f6d3b11b46258ae2394c8cc98222
project_iteration13random_id91ea39e5fcfc55108cea2d38c5723418
registration_id91ea39e5fcfc55108cea2d38c5723418route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_name11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHzcpu_speed1690 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + + + + + + + + +
command_line_options
command=xelabdebug=typicaldpi_used=falsefile_counter=9
gendll=falsehwcosim=falsesdfmodeling=falsevhdl2008=false
+
+ + + + + + + + + + +
usage
compiler_memory=53504_KBcompiler_time=0.31_secsimulation_image_code=69 KBsimulation_image_data=3 KB
total_instances=15total_nets=0total_processes=33xilinx_hdl_libraries_used=secureip
+

+ + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/usage_statistics_ext_xsim.xml b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..75f866e --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,54 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ + + + + + + + +
+
+ + + + + + + + +
+
+
+ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.dbg new file mode 100644 index 0000000..2c806d5 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.mem new file mode 100644 index 0000000..ff7eb63 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.reloc b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.reloc new file mode 100644 index 0000000..9a6d08d Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.reloc differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.rlx new file mode 100644 index 0000000..f49eb6d --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 5585111709275208010 , + ccp_crc : 0 , + cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Register_Bank_behav xil_defaultlib.TB_Register_Bank" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "D:\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Register_Bank_behav/xsimk.exe\" \"xsim.dir/TB_Register_Bank_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Register_Bank_behav/obj/xsim_1.win64.obj\" \"D:\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"D:\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.rtti new file mode 100644 index 0000000..5ec1741 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.svtype b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.svtype new file mode 100644 index 0000000..afe268b Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.svtype differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.type new file mode 100644 index 0000000..c9cb118 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.xdbg new file mode 100644 index 0000000..aa32bc2 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsimSettings.ini b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsimSettings.ini new file mode 100644 index 0000000..38f4bee --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsimSettings.ini @@ -0,0 +1,41 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsimk.exe b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsimk.exe new file mode 100644 index 0000000..5cec725 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_Bank_behav/xsimk.exe differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/Compile_Options.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/Compile_Options.txt new file mode 100644 index 0000000..36c0d09 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c036f6d3b11b46258ae2394c8cc98222" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "TB_Register_behav" "xil_defaultlib.TB_Register" -log "elaborate.log" diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/TempBreakPointFile.txt b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_0.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..2b86362 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_0.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_1.c b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_1.c new file mode 100644 index 0000000..4cfab13 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_1.c @@ -0,0 +1,103 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[6] = {(funcp)execute_11, (funcp)execute_12, (funcp)execute_9, (funcp)execute_10, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 6; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/TB_Register_behav/xsim.reloc", (void **)funcTab, 6); + iki_vhdl_file_variable_register(dp + 2864); + iki_vhdl_file_variable_register(dp + 2920); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/TB_Register_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/TB_Register_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/TB_Register_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/TB_Register_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/TB_Register_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_1.win64.obj b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..6167595 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/obj/xsim_1.win64.obj differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/.xsim_webtallk.info b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..d24baad --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1686141927 +0 +2 +1 +c036f6d3b11b46258ae2394c8cc98222 diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/usage_statistics_ext_xsim.wdm b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/usage_statistics_ext_xsim.wdm new file mode 100644 index 0000000..0410530 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/usage_statistics_ext_xsim.wdm @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/xsim_webtalk.tcl b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..259e150 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,42 @@ +webtalk_init -webtalk_dir C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Wed Jun 7 18:15:27 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "e3355ad9-3a98-4321-a981-98669d875211" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "c036f6d3b11b46258ae2394c8cc98222" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "1" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "AMD Ryzen 3 5300U with Radeon Graphics " -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2595 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "7.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key File_Counter -value "6" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "64 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "2 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "4" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "5" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.39_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "53424_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3004985078 -regid "" -xml C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/SITHUM JEEVANTHA/OneDrive/Documents/GitHub/NanoProcessor-Team-93/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.dbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.dbg new file mode 100644 index 0000000..f403f81 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.dbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.mem b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.mem new file mode 100644 index 0000000..82b3478 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.mem differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.reloc b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.reloc new file mode 100644 index 0000000..71a15e2 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.reloc differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.rlx new file mode 100644 index 0000000..a1a51a7 --- /dev/null +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 827716129127707954 , + ccp_crc : 0 , + cmdline : " -wto c036f6d3b11b46258ae2394c8cc98222 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot TB_Register_behav xil_defaultlib.TB_Register" , + buildDate : "Jun 14 2018" , + buildTime : "20:41:02" , + linkCmd : "C:\\Xilinx\\Vivado\\2018.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/TB_Register_behav/xsimk.exe\" \"xsim.dir/TB_Register_behav/obj/xsim_0.win64.obj\" \"xsim.dir/TB_Register_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2018.2\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.rtti b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.rtti new file mode 100644 index 0000000..b24aa07 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.rtti differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.type b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.type new file mode 100644 index 0000000..88ce6d7 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.type differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.xdbg b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.xdbg new file mode 100644 index 0000000..50ffc21 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsim.xdbg differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/TB_Register_behav/xsimk.exe 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a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_program_counter.vdb b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_program_counter.vdb new file mode 100644 index 0000000..d3c5d2d Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_program_counter.vdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_rca_adder_subtractor.vdb b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_rca_adder_subtractor.vdb new file mode 100644 index 0000000..358a2f8 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_rca_adder_subtractor.vdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_register.vdb b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_register.vdb new file mode 100644 index 0000000..3ba8d21 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_register.vdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_register_bank.vdb b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_register_bank.vdb new file mode 100644 index 0000000..5d799e6 Binary files /dev/null and b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_register_bank.vdb differ diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index 4fe4287..e8a136d 100644 --- a/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/Lab9/Lab9.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -2,9 +2,24 @@ 2018.2 Jun 14 2018 20:41:02 -D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sim_1/new/TB_MUX_2_way_3_bit.vhd,1685824158,vhdl,,,,tb_mux_2_way_3_bit,,,,,,,, -D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sim_1/new/TB_insruction_decoder.vhd,1685821370,vhdl,,,,tb_insruction_decoder,,,,,,,, -D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Decoder_1_to_2.vhd,1685008117,vhdl,,,,decoder_1_to_2,,,,,,,, -D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Decoder_2_to_4.vhd,1684319480,vhdl,,,,decoder_2_to_4,,,,,,,, -D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Instruction_decoder.vhd,1685818096,vhdl,,,,instruction_decoder,,,,,,,, -D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/MUX_2_way_3_bit.vhd,1685822654,vhdl,,,,mux_2_way_3_bit,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sim_1/new/TB_MUX_8_way_4_bit.vhd,1686205932,vhdl,,,,tb_mux_8_way_4_bit,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sim_1/new/TB_NanoProcessor.vhd,1686227687,vhdl,,,,tb_nanoprocessor,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sim_1/new/TB_Register_Bank.vhd,1686218873,vhdl,,,,tb_register_bank,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Decoder_1_to_2.vhd,1686041884,vhdl,,,,decoder_1_to_2,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Decoder_2_to_4.vhd,1686041884,vhdl,,,,decoder_2_to_4,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Decoder_3_to_8.vhd,1686041884,vhdl,,,,decoder_3_to_8,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/FA.vhd,1686145662,vhdl,,,,fa,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/HA.vhd,1686041884,vhdl,,,,ha,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Instruction_decoder.vhd,1686224276,vhdl,,,,instruction_decoder,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/LUT_16_7.vhd,1683267636,vhdl,,,,lut_16_7,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/MUX_2_way_3_bit.vhd,1686044540,vhdl,,,,mux_2_way_3_bit,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/MUX_2_way_4_bits.vhd,1686044540,vhdl,,,,mux_2_way_4_bit,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/MUX_8_way_4_bit.vhd,1686207019,vhdl,,,,mux_8_way_4_bit,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd,1686227570,vhdl,,,,nanoprocessor,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Program_Counter.vhd,1686225444,vhdl,,,,program_counter,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd,1686146804,vhdl,,,,rca_adder_subtractor,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/ROM.vhd,1686209955,vhdl,,,,rom,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Register_Bank.vhd,1686227549,vhdl,,,,register_bank,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Registers.vhd,1686044540,vhdl,,,,registers,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/Slow_Clk.vhd,1686041884,vhdl,,,,slow_clk,,,,,,,, +D:/projects/NanoProcessor-Team-93/Lab9/Lab9.srcs/sources_1/new/adder_3bit.vhd,1686145662,vhdl,,,,adder_3bit,,,,,,,, diff --git a/Lab9/Lab9.sim/sim_1/behav/xsim/xvhdl.pb b/Lab9/Lab9.sim/sim_1/behav/xsim/xvhdl.pb index d6d3a8f..69f367d 100644 Binary files a/Lab9/Lab9.sim/sim_1/behav/xsim/xvhdl.pb and b/Lab9/Lab9.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/Lab9/Lab9.srcs/constrs_1/new/NanoProcessor_constrain.xdc b/Lab9/Lab9.srcs/constrs_1/new/NanoProcessor_constrain.xdc new file mode 100644 index 0000000..08dd900 --- /dev/null +++ b/Lab9/Lab9.srcs/constrs_1/new/NanoProcessor_constrain.xdc @@ -0,0 +1,294 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property PACKAGE_PIN W5 [get_ports clock] + set_property IOSTANDARD LVCMOS33 [get_ports clock] + create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clock] + +## Switches +#set_property PACKAGE_PIN V17 [get_ports {sw[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +#set_property PACKAGE_PIN V16 [get_ports {sw[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +#set_property PACKAGE_PIN W16 [get_ports {sw[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +#set_property PACKAGE_PIN W17 [get_ports {sw[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +#set_property PACKAGE_PIN W15 [get_ports {sw[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +#set_property PACKAGE_PIN V15 [get_ports {sw[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +#set_property PACKAGE_PIN W14 [get_ports {sw[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +#set_property PACKAGE_PIN W13 [get_ports {sw[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +#set_property PACKAGE_PIN V2 [get_ports {sw[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +#set_property PACKAGE_PIN T3 [get_ports {sw[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +#set_property PACKAGE_PIN T2 [get_ports {sw[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +#set_property PACKAGE_PIN R3 [get_ports {sw[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +#set_property PACKAGE_PIN W2 [get_ports {sw[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +#set_property PACKAGE_PIN U1 [get_ports {sw[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +#set_property PACKAGE_PIN T1 [get_ports {sw[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +#set_property PACKAGE_PIN R2 [get_ports {sw[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + +## LEDs +set_property PACKAGE_PIN U16 [get_ports {reg_7_out[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_out[0]}] +set_property PACKAGE_PIN E19 [get_ports {reg_7_out[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_out[1]}] +set_property PACKAGE_PIN U19 [get_ports {reg_7_out[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_out[2]}] +set_property PACKAGE_PIN V19 [get_ports {reg_7_out[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_out[3]}] +#set_property PACKAGE_PIN W18 [get_ports {led[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +#set_property PACKAGE_PIN U15 [get_ports {led[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +#set_property PACKAGE_PIN U14 [get_ports {led[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +#set_property PACKAGE_PIN V14 [get_ports {led[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +#set_property PACKAGE_PIN V13 [get_ports {led[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +#set_property PACKAGE_PIN V3 [get_ports {led[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +#set_property PACKAGE_PIN W3 [get_ports {led[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +#set_property PACKAGE_PIN U3 [get_ports {led[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +#set_property PACKAGE_PIN P3 [get_ports {led[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +#set_property PACKAGE_PIN N3 [get_ports {led[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +set_property PACKAGE_PIN P1 [get_ports {overflow}] + set_property IOSTANDARD LVCMOS33 [get_ports {overflow}] +set_property PACKAGE_PIN L1 [get_ports {Zero}] + set_property IOSTANDARD LVCMOS33 [get_ports {Zero}] + + +##7 segment display +set_property PACKAGE_PIN W7 [get_ports {reg_7_seven_seg[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_seven_seg[0]}] +set_property PACKAGE_PIN W6 [get_ports {reg_7_seven_seg[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_seven_seg[1]}] +set_property PACKAGE_PIN U8 [get_ports {reg_7_seven_seg[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_seven_seg[2]}] +set_property PACKAGE_PIN V8 [get_ports {reg_7_seven_seg[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_seven_seg[3]}] +set_property PACKAGE_PIN U5 [get_ports {reg_7_seven_seg[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_seven_seg[4]}] +set_property PACKAGE_PIN V5 [get_ports {reg_7_seven_seg[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_seven_seg[5]}] +set_property PACKAGE_PIN U7 [get_ports {reg_7_seven_seg[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {reg_7_seven_seg[6]}] + +#set_property PACKAGE_PIN V7 [get_ports dp] + #set_property IOSTANDARD LVCMOS33 [get_ports dp] + +set_property PACKAGE_PIN U2 [get_ports {anode[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode[0]}] +set_property PACKAGE_PIN U4 [get_ports {anode[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode[1]}] +set_property PACKAGE_PIN V4 [get_ports {anode[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode[2]}] +set_property PACKAGE_PIN W4 [get_ports {anode[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {anode[3]}] + + +##Buttons +set_property PACKAGE_PIN U18 [get_ports reset] + set_property IOSTANDARD LVCMOS33 [get_ports reset] +#set_property PACKAGE_PIN T18 [get_ports btnU] + #set_property IOSTANDARD LVCMOS33 [get_ports btnU] +#set_property PACKAGE_PIN W19 [get_ports btnL] + #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +#set_property PACKAGE_PIN T17 [get_ports btnR] + #set_property IOSTANDARD LVCMOS33 [get_ports btnR] +#set_property PACKAGE_PIN U17 [get_ports btnD] + #set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +##Sch name = JA1 +#set_property PACKAGE_PIN J1 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Sch name = JA2 +#set_property PACKAGE_PIN L2 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Sch name = JA3 +#set_property PACKAGE_PIN J2 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Sch name = JA4 +#set_property PACKAGE_PIN G2 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Sch name = JA7 +#set_property PACKAGE_PIN H1 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Sch name = JA8 +#set_property PACKAGE_PIN K2 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Sch name = JA9 +#set_property PACKAGE_PIN H2 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Sch name = JA10 +#set_property PACKAGE_PIN G3 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Sch name = JB1 +#set_property PACKAGE_PIN A14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Sch name = JB2 +#set_property PACKAGE_PIN A16 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Sch name = JB3 +#set_property PACKAGE_PIN B15 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Sch name = JB4 +#set_property PACKAGE_PIN B16 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Sch name = JB7 +#set_property PACKAGE_PIN A15 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Sch name = JB8 +#set_property PACKAGE_PIN A17 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Sch name = JB9 +#set_property PACKAGE_PIN C15 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Sch name = JB10 +#set_property PACKAGE_PIN C16 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Sch name = JC1 +#set_property PACKAGE_PIN K17 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Sch name = JC2 +#set_property PACKAGE_PIN M18 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Sch name = JC3 +#set_property PACKAGE_PIN N17 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Sch name = JC4 +#set_property PACKAGE_PIN P18 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Sch name = JC7 +#set_property PACKAGE_PIN L17 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Sch name = JC8 +#set_property PACKAGE_PIN M19 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Sch name = JC9 +#set_property PACKAGE_PIN P17 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Sch name = JC10 +#set_property PACKAGE_PIN R18 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + +##Pmod Header JXADC +##Sch name = XA1_P +#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +##Sch name = XA2_P +#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +##Sch name = XA3_P +#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +##Sch name = XA4_P +#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +##Sch name = XA1_N +#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +##Sch name = XA2_N +#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +##Sch name = XA3_N +#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +##Sch name = XA4_N +#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] +#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] +#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] +#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] +#set_property PACKAGE_PIN P19 [get_ports Hsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +#set_property PACKAGE_PIN R19 [get_ports Vsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] + + +##USB-RS232 Interface +#set_property PACKAGE_PIN B18 [get_ports RsRx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +#set_property PACKAGE_PIN A18 [get_ports RsTx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] + + +##USB HID (PS/2) +#set_property PACKAGE_PIN C17 [get_ports PS2Clk] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + #set_property PULLUP true [get_ports PS2Clk] +#set_property PACKAGE_PIN B17 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + #set_property PULLUP true [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +#set_property PACKAGE_PIN K19 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_Adder_3Bit.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_Adder_3Bit.vhd new file mode 100644 index 0000000..4159e81 --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_Adder_3Bit.vhd @@ -0,0 +1,74 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/07/2023 04:53:39 PM +-- Design Name: +-- Module Name: TB_Adder_3Bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Adder_3Bit is +-- Port ( ); +end TB_Adder_3Bit; + +architecture Behavioral of TB_Adder_3Bit is +component adder_3bit + Port ( A :in STD_LOGIC_VECTOR(2 downto 0); + B: in STD_LOGIC_VECTOR(2 downto 0); + S : out STD_LOGIC_VECTOR(2 downto 0); + C_in : in STD_LOGIC; + C_out : out STD_LOGIC); +end component; + +signal C_in : STD_LOGIC; +signal C_out: STD_LOGIC; +signal A,B,S: STD_LOGIC_VECTOR(2 downto 0); +begin + UUT: adder_3bit port map( + A=>A,B=>B,C_in=>C_in,S=>S,C_out=>C_out); + +process +begin + C_in<='0'; + A<="101"; + B<="001"; + wait for 100 ns; + + A<="000"; + B<="000"; + wait for 100 ns; + + + A<="111"; + B<="011"; + wait for 100 ns; + + A<="111"; + B<="111"; + wait ; +end process; +end Behavioral; diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_Adder_sub.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_Adder_sub.vhd new file mode 100644 index 0000000..5dcc728 --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_Adder_sub.vhd @@ -0,0 +1,74 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/03/2023 01:24:23 AM +-- Design Name: +-- Module Name: TB_Adder_sub - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Adder_sub is +-- Port ( ); +end TB_Adder_sub; + +architecture Behavioral of TB_Adder_sub is +component RCA_Adder_Subtractor + port ( A,B: in std_logic_vector(3 downto 0); + S: out std_logic_vector(3 downto 0); + subtract: in std_logic; + Zero:out std_logic; + C_out, overflow: out std_logic); +end component; + +signal A,B,S:std_logic_vector(3 downto 0); +signal subtract,Zero,C_out,overflow: std_logic; +begin + UUT :RCA_Adder_Subtractor port map( + A=>A,B=>B,S=>S,subtract=>subtract,Zero=>Zero,C_out=>C_out,overflow=>overflow); +process +begin + wait for 20 ns; + + subtract<='0'; + A<="1010"; + B<="0011"; + wait for 100 ns; + + A<="0000"; + B<="0000"; + wait for 100 ns; + + subtract<='1'; + A<="1110"; + B<="0011"; + wait for 100 ns; + + A<="0000"; + B<="0000"; + wait ; +end process; +end Behavioral; diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_MUX_2_way_4_bit.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_MUX_2_way_4_bit.vhd new file mode 100644 index 0000000..dba6b7f --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_MUX_2_way_4_bit.vhd @@ -0,0 +1,69 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/08/2023 10:31:27 AM +-- Design Name: +-- Module Name: TB_MUX_2_way_4_bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_MUX_2_way_4_bit is +-- Port ( ); +end TB_MUX_2_way_4_bit; + +architecture Behavioral of TB_MUX_2_way_4_bit is +component MUX_2_way_4_bit +Port ( MUX_2_way_4_bit_DATA : in STD_LOGIC_VECTOR (7 downto 0); + MUX_2_way_4_bit_controls : in STD_LOGIC; + MUX_2_way_4_bit_EN : in STD_LOGIC; + MUX_2_way_4_bit_OUT : out STD_LOGIC_VECTOR (3 downto 0)); + +end component; +signal MUX_2_way_4_bit_DATA : STD_LOGIC_VECTOR(7 downto 0); +signal MUX_2_way_4_bit_controls, MUX_2_way_4_bit_EN: STD_LOGIC; +signal MUX_2_way_4_bit_OUT: STD_LOGIC_VECTOR(3 downto 0); +begin +UUT: MUX_2_way_4_bit +PORT MAP( + MUX_2_way_4_bit_DATA =>MUX_2_way_4_bit_DATA, + MUX_2_way_4_bit_controls=> MUX_2_way_4_bit_controls, + MUX_2_way_4_bit_EN => MUX_2_way_4_bit_EN, + MUX_2_way_4_bit_OUT =>MUX_2_way_4_bit_OUT + +); + +process begin +MUX_2_way_4_bit_EN<= '1'; +MUX_2_way_4_bit_DATA <= "01101001"; +MUX_2_way_4_bit_controls<= '1'; +wait for 100ns; +MUX_2_way_4_bit_DATA <= "01101010"; +MUX_2_way_4_bit_controls<= '0'; +wait for 100ns; +MUX_2_way_4_bit_EN <='0'; +end process; +end Behavioral; diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_MUX_8_way_4_bit.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_MUX_8_way_4_bit.vhd new file mode 100644 index 0000000..3764f26 --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_MUX_8_way_4_bit.vhd @@ -0,0 +1,85 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/08/2023 11:27:28 AM +-- Design Name: +-- Module Name: TB_MUX_8_way_4_bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_MUX_8_way_4_bit is +-- Port ( ); +end TB_MUX_8_way_4_bit; + +architecture Behavioral of TB_MUX_8_way_4_bit is +component MUX_8_way_4_bit + Port ( S : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIc; + MUX_data_bit : in STD_LOGIC_VECTOR (31 downto 0); + MUX_output : out STD_LOGIC_VECTOR(3 downto 0)); +end component; +signal S :STD_LOGIC_VECTOR (2 downto 0); +signal EN:STD_LOGIC; +signal MUX_data_bit_0,MUX_data_bit_1,MUX_data_bit_2,MUX_data_bit_3,MUX_data_bit_4,MUX_data_bit_5,MUX_data_bit_6,MUX_data_bit_7:STD_LOGIC_VECTOR (3 downto 0); +signal MUX_output: STD_LOGIC_VECTOR(3 downto 0); + +begin +UUT: MUX_8_way_4_bit port Map +( + S => S, + EN => EN, + MUX_data_bit(3 downto 0) =>MUX_data_bit_0, + MUX_data_bit(7 downto 4) =>MUX_data_bit_1, + MUX_data_bit(11 downto 8) =>MUX_data_bit_2, + MUX_data_bit(15 downto 12) =>MUX_data_bit_3, + MUX_data_bit(19 downto 16) =>MUX_data_bit_4, + MUX_data_bit(23 downto 20) =>MUX_data_bit_5, + MUX_data_bit(27 downto 24) =>MUX_data_bit_6, + MUX_data_bit(31 downto 28)=> MUX_data_bit_7, + MUX_output => MUX_output + +); + +process begin +MUX_data_bit_0 <= "0101" ;--5 +MUX_data_bit_1 <= "0100" ;--4 +MUX_data_bit_2 <= "0111" ; --7 +MUX_data_bit_3 <= "1000" ;--8 +MUX_data_bit_4 <= "1001" ;--9 +MUX_data_bit_5 <= "1011" ;--11-b +MUX_data_bit_6 <= "0001" ; --1 +MUX_data_bit_7<= "0010" ; --2 + +EN <= '1'; +S <= "100";--4 +wait for 100ns; +S<= "001";--1 +wait for 100ns; +S<= "101" ;--5 +wait for 100ns; +end process; +end Behavioral; diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_NanoProcessor.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_NanoProcessor.vhd new file mode 100644 index 0000000..4c6e193 --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_NanoProcessor.vhd @@ -0,0 +1,113 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/08/2023 12:24:20 PM +-- Design Name: +-- Module Name: TB_NanoProcessor - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_NanoProcessor is +-- Port ( ); +end TB_NanoProcessor; + +architecture Behavioral of TB_NanoProcessor is +component NanoProcessor + +Port ( + clock :in STD_LOGIC; + reset: in STD_LOGIC; + overflow: OUT std_logic; + Zero : out std_logic; + reg_7_out:out std_logic_vector(3 downto 0); + reg_7_seven_seg :out std_logic_vector(6 downto 0); + anode: out STD_LOGIC_VECTOR(3 downto 0) + + + --register_0: out STD_LOGIC_VECTOR(3 downto 0); + --register_1: out STD_LOGIC_VECTOR(3 downto 0); + --register_2: out STD_LOGIC_VECTOR(3 downto 0); + --register_3: out STD_LOGIC_VECTOR(3 downto 0); + --register_4: out STD_LOGIC_VECTOR(3 downto 0); + --register_5: out STD_LOGIC_VECTOR(3 downto 0); + --register_6: out STD_LOGIC_VECTOR(3 downto 0); + --register_7: out STD_LOGIC_VECTOR(3 downto 0); + --current_ins : out STD_LOGIC_VECTOR(11 downto 0); + --adder_3_bit_out_sim : out STD_LOGIC_VECTOR(2 downto 0); + --memory_select_out_sim: out STD_LOGIC_VECTOR(2 downto 0); + --test_out :out STD_LOGIC_VECTOR(2 downto 0) + ); +end component; + +signal clock :STD_LOGIC:= '0'; +signal reset, overflow, Zero: STD_LOGIC:='0'; +signal reg_7_out, anode:std_logic_vector(3 downto 0); +signal reg_7_seven_seg :std_logic_vector(6 downto 0); + +--signal register_0,register_1,register_2,register_3,register_4,register_5,register_6,register_7:std_logic_vector(3 downto 0); +--signal current_ins: STD_LOGIC_VECTOR(11 downto 0); +--signal adder_3_bit_out_sim,memory_select_out_sim, test_out: STD_LOGIC_VECTOR(2 downto 0); +begin +UUT: NanoProcessor port map +( + clock => clock, + reset => reset, + overflow => overflow, + Zero => Zero, + reg_7_out => reg_7_out, + reg_7_seven_seg => reg_7_seven_seg, + anode => anode + + --register_0 =>register_0, + --register_1 =>register_1, + --register_2 =>register_2, + --register_3 =>register_3, + --register_4 =>register_4, + --register_5 =>register_5, + --register_6 =>register_6, + --register_7 =>register_7, + --current_ins=> current_ins, + --adder_3_bit_out_sim =>adder_3_bit_out_sim, + --memory_select_out_sim =>memory_select_out_sim, + --test_out => test_out + ) +; + +process begin +clock<=not(clock); +WAIT FOR 2ns; +end process; + + +--reset <= '1'; +--wait for 8ns; +--reset<='0'; + + + + +end Behavioral; diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_Program_Counter.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_Program_Counter.vhd new file mode 100644 index 0000000..1f1643e --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_Program_Counter.vhd @@ -0,0 +1,58 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Program_Counter is +-- Port ( ); +end TB_Program_Counter; + +architecture Behavioral of TB_Program_Counter is +component Program_Counter + Port ( Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + D : in STD_LOGIC_VECTOR (2 downto 0); + Q : out STD_LOGIC_VECTOR (2 downto 0)); +end component; +signal Clk,Reset: std_logic; +signal D,Q: STD_LOGIC_VECTOR (2 downto 0); + + +begin + UUT: Program_Counter port map( + Clk=>Clk, + Reset=>Reset, + Q=>Q, + D=>D); +process +begin + Clk <= '0'; + wait for 10 ns; + Clk <= '1'; + wait for 10 ns; +end process; + +process +begin + Reset <= '1'; + wait for 100ns; + + Reset <= '0'; + D <= "001"; + wait for 100ns; + + Reset <= '0'; + D <= "010"; + wait for 100ns; + + Reset <= '1'; + wait; +end process; +end; \ No newline at end of file diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_ROM.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_ROM.vhd new file mode 100644 index 0000000..0028b6f --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_ROM.vhd @@ -0,0 +1,72 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/08/2023 10:45:37 AM +-- Design Name: +-- Module Name: TB_ROM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_ROM is +-- Port ( ); +end TB_ROM; + +architecture Behavioral of TB_ROM is +component ROM +Port ( address : in STD_LOGIC_VECTOR (2 downto 0); + + ins : out STD_LOGIC_VECTOR (11 downto 0)); + +end component; +signal address: STD_LOGIC_VECTOR( 2 downto 0); +signal ins: STD_LOGIC_VECTOR(11 downto 0); +begin +UUT :ROM port map( + address => address, + ins => ins +); +process begin + +address <= "000"; +wait for 100ns; +address <= "001"; +wait for 100ns; +address <= "010"; +wait for 100ns; +address <= "011"; +wait for 100ns; +address <= "100"; +wait for 100ns; +address <= "101"; +wait for 100ns; +address <= "110"; +wait for 100ns; +address <= "111"; +wait for 100ns; +end process; + +end Behavioral; diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_Register.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_Register.vhd new file mode 100644 index 0000000..e7d792b --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_Register.vhd @@ -0,0 +1,81 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05/31/2023 03:45:42 PM +-- Design Name: +-- Module Name: TB_Register - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Register is +-- Port ( ); +end TB_Register; + +architecture Behavioral of TB_Register is +component Registers + Port ( Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + EN: in STD_LOGIC; + D : in STD_LOGIC_VECTOR (3 downto 0); + Q : out STD_LOGIC_VECTOR (3 downto 0)); +end component; + +signal Clk,Reset,EN: std_logic; +signal D,Q: STD_LOGIC_VECTOR (3 downto 0); + +begin + UUT: Registers port map( + Clk=>Clk,Reset=>Reset,Q=>Q,D=>D,EN=>EN); +process +begin + Clk <= '0'; + wait for 10 ns; + Clk <= '1'; + wait for 10 ns; +end process; + +process +begin + EN <= '1'; + Reset <= '1'; + wait for 100ns; + + EN <= '1'; + Reset <= '0'; + D <= "0011"; + wait for 100ns; + + EN <= '0'; + Reset <= '0'; + D <= "0100"; + wait for 100ns; + + EN <= '1'; + Reset <= '1'; + wait; +end process; +end Behavioral; diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_Register_Bank.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_Register_Bank.vhd new file mode 100644 index 0000000..ded9003 --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_Register_Bank.vhd @@ -0,0 +1,105 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/03/2023 10:20:55 AM +-- Design Name: +-- Module Name: TB_Register_Bank - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_Register_Bank is +-- Port ( ); +end TB_Register_Bank; + +architecture Behavioral of TB_Register_Bank is +component Register_Bank + Port ( Clk : in STD_LOGIC:='0'; + Reset : in STD_LOGIC:= '0'; + Register_enable : in STD_LOGIC_VECTOR(2 downto 0); + Register_input : in STD_LOGIC_VECTOR (3 downto 0); + register0 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register1 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register2 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register3 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register4 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register5 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register6 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register7 : out STD_LOGIC_VECTOR(3 downto 0):="0000"); +end component; + +signal Clk: STD_LOGIC:='0'; +signal Reset: STD_LOGIC; +signal Register_enable:STD_LOGIC_VECTOR (2 downto 0); +signal Register_input,register0,register1,register2,register3,register4,register5,register6,register7:STD_LOGIC_VECTOR(3 downto 0); + +begin + UUT: Register_Bank port map + ( Clk=>Clk, + Reset=>Reset, + Register_input=>Register_input, + Register_enable =>Register_enable, + register0=>register0, + register1=>register1, + register2=>register2, + register3=>register3, + register4=>register4, + register5=>register5, + register6=>register6, + register7=>register7 + ); + +process begin +Clk<=not(Clk); +WAIT FOR 2ns; +end process; + +process +begin + + Reset <= '1'; + wait for 100ns; + Reset <= '0'; + Register_enable <= "001"; + Register_input <= "0101"; + + + wait for 100ns; + + Register_enable <= "001"; + Register_input <= "0100"; + wait for 100ns; + + Register_enable <= "010"; + Register_input <= "0100"; + wait for 100ns; + + + + + +end process; +end Behavioral; diff --git a/Lab9/Lab9.srcs/sim_1/new/TB_adder_3_bit.vhd b/Lab9/Lab9.srcs/sim_1/new/TB_adder_3_bit.vhd new file mode 100644 index 0000000..0aee103 --- /dev/null +++ b/Lab9/Lab9.srcs/sim_1/new/TB_adder_3_bit.vhd @@ -0,0 +1,52 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/08/2023 04:55:13 PM +-- Design Name: +-- Module Name: TB_adder_3_bit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TB_adder_3_bit is +-- Port ( ); +end TB_adder_3_bit; + +architecture Behavioral of TB_adder_3_bit is +component adder_3bit +Port ( A :in STD_LOGIC_VECTOR(2 downto 0); + B: in STD_LOGIC_VECTOR(2 downto 0); + S : out STD_LOGIC_VECTOR(2 downto 0); + C_in : in STD_LOGIC:= '0' ; + C_out : out STD_LOGIC); + end component; + + + +begin + + +end Behavioral; diff --git a/Lab9/Lab9.srcs/sources_1/new/Counter.vhd b/Lab9/Lab9.srcs/sources_1/new/Counter.vhd deleted file mode 100644 index 46d8f59..0000000 --- a/Lab9/Lab9.srcs/sources_1/new/Counter.vhd +++ /dev/null @@ -1,95 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 04/08/2023 02:34:15 PM --- Design Name: --- Module Name: Counter - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx leaf cells in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity Counter is - Port ( Dir : in STD_LOGIC; - Res : in STD_LOGIC; - Clk : in STD_LOGIC; - Q : out STD_LOGIC_VECTOR (2 downto 0)); -end Counter; - -architecture Behavioral of Counter is -component D_FF - port ( -D : in STD_LOGIC; -Res: in STD_LOGIC; -Clk : in STD_LOGIC; -Q : out STD_LOGIC; -Qbar : out STD_LOGIC); -end component; -component Slow_Clk -port ( -Clk_in : in STD_LOGIC; -Clk_out: out STD_LOGIC); -end component; - -signal D0, D1, D2 : std_logic; -- Internal signals -signal Q0, Q1, Q2 : std_logic; -- Internal signals -signal Clk_slow : std_logic; -- Internal clock -begin - - Slow_Clk0 : Slow_Clk - port map ( - Clk_in => Clk, - Clk_out => Clk_slow); - - D0 <= ((not Q2) and (not Dir)) or (Q1 and Dir); - D1 <= ((Q0 and (not Dir)) or (not(Q2) and Dir)); - D2 <= (((not Q0) and Dir ) or (Q1 and (not Dir))); - - D_FF0 : D_FF - port map ( - D => D0, - Res => Res, - Clk => Clk_slow, - Q => Q0); - D_FF1 : D_FF - port map ( - D => D1, - Res => Res, - Clk => Clk_slow, - Q => Q1); --Fill missing details - D_FF2 : D_FF - port map ( - D => D2, - Res => Res, - Clk => Clk_slow, - Q => Q2); --Fill missing details - -Q(0) <= Q0; -Q(1)<=Q1; -Q(2)<=Q2; - - -end Behavioral; - diff --git a/Lab9/Lab9.srcs/sources_1/new/FA.vhd b/Lab9/Lab9.srcs/sources_1/new/FA.vhd index b655ca3..6b2f9a1 100644 --- a/Lab9/Lab9.srcs/sources_1/new/FA.vhd +++ b/Lab9/Lab9.srcs/sources_1/new/FA.vhd @@ -58,10 +58,10 @@ HA_0 : HA C => HA0_C); HA_1 : HA port map ( - A => HA0_S, - B => C_in, - S => HA1_S, - C => HA1_C); + A => HA0_S, + B => C_in, + S => HA1_S, + C => HA1_C); S <= HA1_S; C_out <= HA1_C OR HA0_C; diff --git a/Lab9/Lab9.srcs/sources_1/new/Instruction_decoder.vhd b/Lab9/Lab9.srcs/sources_1/new/Instruction_decoder.vhd index eeb4eba..0145c3a 100644 --- a/Lab9/Lab9.srcs/sources_1/new/Instruction_decoder.vhd +++ b/Lab9/Lab9.srcs/sources_1/new/Instruction_decoder.vhd @@ -35,7 +35,7 @@ entity Instruction_decoder is Port ( Instruction_decoder_in : in STD_LOGIC_VECTOR (11 downto 0); register_check_for_jump: in STD_LOGIC_VECTOR(3 downto 0); add_or_sub_select: out STD_LOGIC := '0'; - register_enable: out STD_LOGIC_VECTOR(2 downto 0):= (others => 'Z'); + register_enable: out STD_LOGIC_VECTOR(2 downto 0):= "000"; register_select : out STD_LOGIC_VECTOR(5 downto 0):= "000000"; immidiate_value: out STD_LOGIC_VECTOR(3 downto 0):= "0000"; load_select: out STD_LOGIC :='0'; @@ -92,13 +92,12 @@ reg_enable_ins<= Instruction_decoder_in(9 downto 7); --to enable a register in t immidiate_value_ins <= Instruction_decoder_in(3 downto 0); -- immidiate vallue decoded from the instruction address_to_jump_ins <= Instruction_decoder_in(2 downto 0);-- adress to jump when jump instruction is enable jump_flag_signal <=NOT( register_check_for_jump(0) OR register_check_for_jump(1) OR register_check_for_jump(2) OR register_check_for_jump(3)); - reg_sel_A(2 downto 0) <=(ins_0_3_bit OR ins_1_3_bit OR ins_3_3_bit) AND (reg_sel_A_ins); reg_sel_B <= ins_0_3_bit AND (reg_sel_B_ins); register_select(5 downto 3) <= reg_sel_A; register_select(2 downto 0) <= reg_sel_B; register_enable <=( ins_0_3_bit OR ins_1_3_bit OR ins_2_3_bit) AND (reg_enable_ins); -add_or_sub_select <= (ins_no(0) OR ins_no(1)); +add_or_sub_select <= ins_no(1); immidiate_value <= (ins_2_4_bit) AND immidiate_value_ins; load_select<= ins_no(0) OR ins_no(1); jump_flag <= ins_no(3) and jump_flag_signal; diff --git a/Lab9/Lab9.srcs/sources_1/new/LUT_16_7.vhd b/Lab9/Lab9.srcs/sources_1/new/LUT_16_7.vhd new file mode 100644 index 0000000..1c2c936 --- /dev/null +++ b/Lab9/Lab9.srcs/sources_1/new/LUT_16_7.vhd @@ -0,0 +1,66 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05/03/2023 09:51:43 AM +-- Design Name: +-- Module Name: LUT_16_7 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity LUT_16_7 is + Port ( address : in STD_LOGIC_VECTOR (3 downto 0); + + data : out STD_LOGIC_VECTOR (6 downto 0)); +end LUT_16_7; + +architecture Behavioral of LUT_16_7 is +type rom_type is array (0 to 15) of std_logic_vector(6 downto 0); + + signal sevenSegment_ROM : rom_type := ( + "1000000", -- 0 + "1111001",--1 + "0100100",--2 + "1100000",--3 + "0011001",--4 + "0010010",--5 + "0000010",--6 + "1111000", --7 + "0000000",--8 + "0010000", --9 + "0001000", -- a + "0000011",--b + "1000110",--c + "0100001",--d + "0000110",--e + "0001110" -- f + ); + +begin +data <= sevenSegment_ROM(to_integer(unsigned(address))); + +end Behavioral; diff --git a/Lab9/Lab9.srcs/sources_1/new/MUX_8_way_4_bit.vhd b/Lab9/Lab9.srcs/sources_1/new/MUX_8_way_4_bit.vhd index f29cc3f..7991c4a 100644 --- a/Lab9/Lab9.srcs/sources_1/new/MUX_8_way_4_bit.vhd +++ b/Lab9/Lab9.srcs/sources_1/new/MUX_8_way_4_bit.vhd @@ -70,13 +70,13 @@ MUX_enable_signal <= ( EN & EN & EN & EN ); MUX_output<=( ((MUX_data_bi_signal(3 downto 0) AND MUX_data_bit(3 downto 0)) OR - (MUX_data_bi_signal(7 downto 4) AND MUX_data_bit(3 downto 0)) OR - (MUX_data_bi_signal(11 downto 8) AND MUX_data_bit(3 downto 0)) OR - (MUX_data_bi_signal(15 downto 12) AND MUX_data_bit(3 downto 0)) OR - (MUX_data_bi_signal(19 downto 16)AND MUX_data_bit(3 downto 0)) OR - (MUX_data_bi_signal(23 downto 20)AND MUX_data_bit(3 downto 0)) OR - (MUX_data_bi_signal(27 downto 24) AND MUX_data_bit(3 downto 0)) OR - (MUX_data_bi_signal(31 downto 28) AND MUX_data_bit(3 downto 0)) ) AND MUX_enable_signal + (MUX_data_bi_signal(7 downto 4) AND MUX_data_bit(7 downto 4)) OR + (MUX_data_bi_signal(11 downto 8) AND MUX_data_bit(11 downto 8)) OR + (MUX_data_bi_signal(15 downto 12) AND MUX_data_bit(15 downto 12)) OR + (MUX_data_bi_signal(19 downto 16)AND MUX_data_bit(19 downto 16)) OR + (MUX_data_bi_signal(23 downto 20)AND MUX_data_bit(23 downto 20)) OR + (MUX_data_bi_signal(27 downto 24) AND MUX_data_bit(27 downto 24)) OR + (MUX_data_bi_signal(31 downto 28) AND MUX_data_bit(31 downto 28)) ) AND MUX_enable_signal ) ; diff --git a/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd b/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd index 7a6d678..6e0e191 100644 --- a/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd +++ b/Lab9/Lab9.srcs/sources_1/new/NanoProcessor.vhd @@ -32,12 +32,268 @@ use IEEE.STD_LOGIC_1164.ALL; --use UNISIM.VComponents.all; entity NanoProcessor is --- Port ( ); + Port ( + clock :in STD_LOGIC; + reset: in STD_LOGIC; + overflow: OUT std_logic; + Zero : out std_logic; + reg_7_out:out std_logic_vector(3 downto 0); + reg_7_seven_seg :out std_logic_vector(6 downto 0); + anode: out STD_LOGIC_VECTOR(3 downto 0) + + --register_0: out STD_LOGIC_VECTOR(3 downto 0); + --register_1: out STD_LOGIC_VECTOR(3 downto 0); + --register_2: out STD_LOGIC_VECTOR(3 downto 0); + --register_3: out STD_LOGIC_VECTOR(3 downto 0); + --register_4: out STD_LOGIC_VECTOR(3 downto 0); + --register_5: out STD_LOGIC_VECTOR(3 downto 0); + --register_6: out STD_LOGIC_VECTOR(3 downto 0); + --register_7: out STD_LOGIC_VECTOR(3 downto 0); + --current_ins : out STD_LOGIC_VECTOR(11 downto 0); + --adder_3_bit_out_sim : out STD_LOGIC_VECTOR(2 downto 0); + --memory_select_out_sim: out STD_LOGIC_VECTOR(2 downto 0); + --test_out : out std_LOGIC_vector(2 downto 0) + ); + end NanoProcessor; architecture Behavioral of NanoProcessor is +component Instruction_decoder + Port ( Instruction_decoder_in : in STD_LOGIC_VECTOR (11 downto 0); + register_check_for_jump: in STD_LOGIC_VECTOR(3 downto 0); + add_or_sub_select: out STD_LOGIC := '0'; + register_enable: out STD_LOGIC_VECTOR(2 downto 0):= (others => 'Z'); + register_select : out STD_LOGIC_VECTOR(5 downto 0):= "000000"; + immidiate_value: out STD_LOGIC_VECTOR(3 downto 0):= "0000"; + load_select: out STD_LOGIC :='0'; + jump_flag: out STD_LOGIC := '0'; + address_to_jump:out STD_LOGIC_VECTOR(2 downto 0):= "000" + + + ); +end component; +component ROM +Port ( address : in STD_LOGIC_VECTOR (2 downto 0); + ins : out STD_LOGIC_VECTOR (11 downto 0)); +end component; +component Register_Bank +Port ( Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + Register_enable : in STD_LOGIC_VECTOR(2 downto 0); + Register_input : in STD_LOGIC_VECTOR (3 downto 0); + register0 : out STD_LOGIC_VECTOR(3 downto 0); + register1 : out STD_LOGIC_VECTOR(3 downto 0); + register2 : out STD_LOGIC_VECTOR(3 downto 0); + register3 : out STD_LOGIC_VECTOR(3 downto 0); + register4 : out STD_LOGIC_VECTOR(3 downto 0); + register5 : out STD_LOGIC_VECTOR(3 downto 0); + register6 : out STD_LOGIC_VECTOR(3 downto 0); + register7 : out STD_LOGIC_VECTOR(3 downto 0)); +end component; + +component RCA_Adder_Subtractor + port ( A,B: in std_logic_vector(3 downto 0); + S: out std_logic_vector(3 downto 0); + subtract: in std_logic; + Zero:out std_logic; + C_out, overflow: out std_logic); +end component; +component adder_3bit + Port ( A :in STD_LOGIC_VECTOR(2 downto 0); + B: in STD_LOGIC_VECTOR(2 downto 0); + S : out STD_LOGIC_VECTOR(2 downto 0); + C_in : in STD_LOGIC; + C_out : out STD_LOGIC); +end component; + +component MUX_2_way_3_bit +Port ( MUX_2_way_3_bit_DATA : in STD_LOGIC_VECTOR (5 downto 0); + MUX_2_way_3_bit_controls:in STD_LOGIC; + MUX_2_way_3_bit_EN : in STD_LOGIC; + MUX_2_way_3_bit_OUT : out STD_LOGIC_VECTOR (2 downto 0)); +end component; + +component MUX_8_way_4_bit +Port ( S : in STD_LOGIC_VECTOR (2 downto 0); + EN : in STD_LOGIc; + MUX_data_bit : in STD_LOGIC_VECTOR (31 downto 0); + MUX_output : out STD_LOGIC_VECTOR(3 downto 0)); +end component; + +component MUX_2_way_4_bit + Port ( MUX_2_way_4_bit_DATA : in STD_LOGIC_VECTOR (7 downto 0); + MUX_2_way_4_bit_controls : in STD_LOGIC; + MUX_2_way_4_bit_EN : in STD_LOGIC; + MUX_2_way_4_bit_OUT : out STD_LOGIC_VECTOR (3 downto 0)); +end component; +component Program_Counter +Port ( Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + D : in STD_LOGIC_VECTOR (2 downto 0); + Q : out STD_LOGIC_VECTOR (2 downto 0)); + +end component; +component Slow_Clk + +Port ( Clk_in : in STD_LOGIC; + Clk_out : out STD_LOGIC); +end component; + +component LUT_16_7 +Port ( address : in STD_LOGIC_VECTOR (3 downto 0); + + data : out STD_LOGIC_VECTOR (6 downto 0)); +end component; + +signal Register_enable_signal : STD_LOGIC_VECTOR(2 downto 0):="000";--instruction decoder , register bank +signal Data_bus_0, Data_bus_1, Data_bus_2,Data_bus_3,Data_bus_4,Data_bus_5,Data_bus_6,Data_bus_7:STD_LOGIC_VECTOR(3 downto 0):="0000"; --register_bank, muxes +signal Register_select_A, Register_select_B :STD_LOGIC_VECTOR(2 downto 0):="000"; --instruction decoder, mux +signal Register_A_out, Register_B_out: STD_LOGIC_VECTOR(3 downto 0):="0000";--muxes, adder_subtractor +signal Adder_out: STD_LOGIC_VECTOR(3 downto 0):= "0000";--adder_subtractor, 2 way4 bit mux +signal Load_select : STD_LOGIC:= '0'; -- ins_decoder, 2 way 4 bit mux +signal Immidiate_value :STD_LOGIC_VECTOR(3 downto 0):= "0000"; --ins_decoder, 2way 4 bit mux +signal Add_sub_select:STD_LOGIC:= '0'; --adder_subtracor, ins decoder +signal Jump_flag_signal: STD_LOGIC:= '0'; -- ins_decoder, 2 way 3 bit mux +signal Address_to_jump: STD_LOGIC_VECTOR(2 downto 0):="000"; -- ins_decoder, 2 way_3bit mux +signal Memory_select: STD_LOGIC_VECTOR(2 downto 0):="000";--ROM, PC , 3 bitadder +signal MUX_2_way_3_bit_OUT : STD_LOGIC_VECTOR(2 downto 0):="000";-- 2 way 3 bit mux, pc +signal Adder_3_bit_out: STD_LOGIC_VECTOR(2 downto 0):="000"; -- 3 bit adder, 2 way 3 bit mux +signal Clock_out :STD_LOGIC:= '0'; +signal Instructions: STD_LOGIC_VECTOR(11 downto 0):="000000000000"; -- ROM, ins decoder +signal MUX_output_register_Bank :STD_LOGIC_VECTOR( 3 downto 0):="0000"; -- Register bank, 2 way 4 bit mux begin +Slow_clk_0: Slow_Clk Port map( + Clk_in => clock, + Clk_out => Clock_out +); +Instruction_decoder_0: Instruction_decoder Port map( + Instruction_decoder_in => Instructions, + register_check_for_jump =>Register_A_out, + add_or_sub_select => Add_sub_select, + register_enable => Register_enable_signal, + register_select(5 downto 3) =>Register_select_A, + register_select(2 downto 0) => Register_select_B, + immidiate_value => Immidiate_value, + load_select => Load_select, + jump_flag => Jump_flag_signal, + address_to_jump => Address_to_jump + +); +Register_Bank_0 : Register_Bank Port map( + Clk =>Clock_out, + Reset => reset, + Register_enable => Register_enable_signal, + Register_input => MUX_output_register_Bank, + register0 => Data_bus_0, + register1 => Data_bus_1, + register2 => Data_bus_2, + register3 => Data_bus_3, + register4 => Data_bus_4, + register5 => Data_bus_5, + register6 => Data_bus_6, + register7 => Data_bus_7 + + +); +ROM_0 :ROM Port map( + address => Memory_select, + ins =>Instructions +); + +RCA_Adder_Subtractor_0 :RCA_Adder_Subtractor port map( + A=> Register_A_out, + B=> Register_B_out, + subtract =>Add_sub_select, + S => Adder_out, + Zero => Zero, + overflow => overflow +); + +adder_3bit_0 : adder_3bit port map( + A=> Memory_select, + B => "001", + S => Adder_3_bit_out, + C_in => '0' + +); + +MUX_2_way_3_bit_0 :MUX_2_way_3_bit port map( + MUX_2_way_3_bit_DATA(5 downto 3) => Address_to_jump, + MUX_2_way_3_bit_DATA(2 downto 0) => Adder_3_bit_out, + MUX_2_way_3_bit_controls => Jump_flag_signal, + MUX_2_way_3_bit_EN => '1', + MUX_2_way_3_bit_OUT => MUX_2_way_3_bit_OUT + +); + +MUX_8_way_4_bit_0 :MUX_8_way_4_bit port map( + S => Register_select_A, + EN =>'1', + MUX_data_bit(3 downto 0) =>Data_bus_0, + MUX_data_bit(7 downto 4) =>Data_bus_1, + MUX_data_bit(11 downto 8) =>Data_bus_2, + MUX_data_bit(15 downto 12) =>Data_bus_3, + MUX_data_bit(19 downto 16) =>Data_bus_4, + MUX_data_bit(23 downto 20) =>Data_bus_5, + MUX_data_bit(27 downto 24) =>Data_bus_6, + MUX_data_bit(31 downto 28) =>Data_bus_7, + MUX_output => Register_A_out + + +); +MUX_8_way_4_bit_1 :MUX_8_way_4_bit port map( + S => Register_select_B, + EN =>'1', + MUX_data_bit(3 downto 0) =>Data_bus_0, + MUX_data_bit(7 downto 4) =>Data_bus_1, + MUX_data_bit(11 downto 8) =>Data_bus_2, + MUX_data_bit(15 downto 12) =>Data_bus_3, + MUX_data_bit(19 downto 16) =>Data_bus_4, + MUX_data_bit(23 downto 20) =>Data_bus_5, + MUX_data_bit(27 downto 24) =>Data_bus_6, + MUX_data_bit(31 downto 28) =>Data_bus_7, + MUX_output => Register_B_out + + +); + +MUX_2_way_4_bit_0 : MUX_2_way_4_bit port map +( + MUX_2_way_4_bit_DATA(7 downto 4) => Adder_out, + MUX_2_way_4_bit_DATA(3 downto 0) =>immidiate_value, + MUX_2_way_4_bit_controls => Load_select, + MUX_2_way_4_bit_EN => '1', + MUX_2_way_4_bit_OUT =>MUX_output_register_Bank +); +Program_Counter_0 : Program_Counter port map +( + Clk => Clock_out, + Reset =>reset , + D => MUX_2_way_3_bit_OUT , + Q => Memory_select +); +LUT_16_7_0 :LUT_16_7 port map +( + address => Data_bus_7, + data => reg_7_seven_seg + +); + +reg_7_out <= Data_bus_7; +anode <= "1110"; +--register_0 <= Data_bus_0; +--register_1 <= Data_bus_1; +--register_2 <= Data_bus_2; +--register_3 <= Data_bus_3; +--register_4 <= Data_bus_4; +--register_5 <= Data_bus_5; +--register_6 <= Data_bus_6; +--register_7 <= Data_bus_7; +--current_ins <= Instructions; +--adder_3_bit_out_sim<= Adder_3_bit_out; +--test_out <= "000"; +--memory_select_out_sim <= Memory_select; end Behavioral; diff --git a/Lab9/Lab9.srcs/sources_1/new/Program_Counter.vhd b/Lab9/Lab9.srcs/sources_1/new/Program_Counter.vhd new file mode 100644 index 0000000..549d998 --- /dev/null +++ b/Lab9/Lab9.srcs/sources_1/new/Program_Counter.vhd @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 06/06/2023 01:54:06 PM +-- Design Name: +-- Module Name: Program_Counter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Program_Counter is +Port ( Clk : in STD_LOGIC:='0'; + Reset : in STD_LOGIC:='0'; + D : in STD_LOGIC_VECTOR (2 downto 0):= "000"; + Q : out STD_LOGIC_VECTOR (2 downto 0):="000"); +end Program_Counter; + +architecture Behavioral of Program_Counter is + + +begin + +process(Clk) begin +if(rising_edge(Clk)) then + if(Reset ='1') then + Q <= "000"; + else + Q <= D; + end if; +end if; + + +end process; + + +end Behavioral; \ No newline at end of file diff --git a/Lab9/Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd b/Lab9/Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd index ef04c61..ffbe8e0 100644 --- a/Lab9/Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd +++ b/Lab9/Lab9.srcs/sources_1/new/RCA_Adder_Subtractor.vhd @@ -53,8 +53,7 @@ begin C(0) <= subtract; C_out <= C(4); -overflow <= C(4) xor C(3); -zero<=NOT(S_temp(0) OR S_temp(1) OR S_temp(2) OR S_temp(3)); + B_temp(0) <= B(0) xor subtract; B_temp(1) <= B(1) xor subtract; @@ -89,5 +88,7 @@ FA_3: FA port map( S=>S_temp(3), C_out=>C(4)); S<=S_temp; - +overflow <= C(4) xor C(3); +zero<=NOT(S_temp(0) OR S_temp(1) OR S_temp(2) OR S_temp(3)); + end Behavioral; \ No newline at end of file diff --git a/Lab9/Lab9.srcs/sources_1/new/ROM.vhd b/Lab9/Lab9.srcs/sources_1/new/ROM.vhd new file mode 100644 index 0000000..92391ad --- /dev/null +++ b/Lab9/Lab9.srcs/sources_1/new/ROM.vhd @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05/03/2023 09:51:43 AM +-- Design Name: +-- Module Name: LUT_16_7 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ROM is + Port ( address : in STD_LOGIC_VECTOR (2 downto 0); + + ins : out STD_LOGIC_VECTOR (11 downto 0)); +end ROM; + +architecture Behavioral of ROM is +type rom_type is array (0 to 7) of std_logic_vector(11 downto 0); + + signal sevenSegment_ROM : rom_type := ( + "101110000001",-- 0 + "100010000010",--1 + "001110010000",--2 + "100010000011",--3 + "001110010000",--4 + "110000000000",--5 + "000000000000",--6 + "000000000000" --7 + + ); + +begin +ins <= sevenSegment_ROM(to_integer(unsigned(address))); + +end Behavioral; diff --git a/Lab9/Lab9.srcs/sources_1/new/Register_Bank.vhd b/Lab9/Lab9.srcs/sources_1/new/Register_Bank.vhd index 6d65149..e66bc26 100644 --- a/Lab9/Lab9.srcs/sources_1/new/Register_Bank.vhd +++ b/Lab9/Lab9.srcs/sources_1/new/Register_Bank.vhd @@ -34,18 +34,16 @@ use IEEE.STD_LOGIC_1164.ALL; entity Register_Bank is Port ( Clk : in STD_LOGIC; Reset : in STD_LOGIC; - EN : in STD_LOGIC; - MuxInput: in STD_LOGIC_VECTOR (2 downto 0); + Register_enable : in STD_LOGIC_VECTOR(2 downto 0); Register_input : in STD_LOGIC_VECTOR (3 downto 0); - MuxOutput : out STD_LOGIC_VECTOR(7 downto 0); - register0 : out STD_LOGIC_VECTOR(3 downto 0); - register1 : out STD_LOGIC_VECTOR(3 downto 0); - register2 : out STD_LOGIC_VECTOR(3 downto 0); - register3 : out STD_LOGIC_VECTOR(3 downto 0); - register4 : out STD_LOGIC_VECTOR(3 downto 0); - register5 : out STD_LOGIC_VECTOR(3 downto 0); - register6 : out STD_LOGIC_VECTOR(3 downto 0); - register7 : out STD_LOGIC_VECTOR(3 downto 0)); + register0 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register1 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register2 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register3 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register4 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register5 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register6 : out STD_LOGIC_VECTOR(3 downto 0):="0000"; + register7 : out STD_LOGIC_VECTOR(3 downto 0):="0000"); end Register_Bank; @@ -68,6 +66,14 @@ signal Y : STD_LOGIC_VECTOR(7 downto 0); signal MuxSignal:STD_LOGIC_VECTOR(7 downto 0); begin + Decoder : Decoder_3_to_8 + port map( + I => Register_enable, + EN => '1', + Y => Y + ); + + MuxSignal<=Y; register0<="0000"; Reg1 : Registers @@ -100,7 +106,7 @@ begin Reg4 : Registers port map( D => Register_input, - EN => MuxSignal(4), + EN => MuxSignal(4) , Clk => Clk, Reset => Reset, Q => register4 @@ -109,7 +115,7 @@ begin Reg5 :Registers port map( D => Register_input, - EN => MuxSignal(5), + EN => MuxSignal(5) , Clk => Clk, Reset => Reset, Q => register5 @@ -118,7 +124,7 @@ begin Reg6 : Registers port map( D => Register_input, - EN => MuxSignal(6), + EN => MuxSignal(6) , Clk => Clk, Reset => Reset, Q =>register6 @@ -127,20 +133,13 @@ begin Reg7 : Registers port map( D => Register_input, - EN => MuxSignal(7), + EN => MuxSignal(7) , Clk => Clk, Reset => Reset, Q =>register7 ); - Decoder : Decoder_3_to_8 - port map( - I => MuxInput, - EN => '1', - Y => Y - ); - MuxSignal<=Y; - MuxOutput<=MuxSignal; + end Behavioral; diff --git a/Lab9/Lab9.srcs/sources_1/new/adder_3bit.vhd b/Lab9/Lab9.srcs/sources_1/new/adder_3bit.vhd index afa4c03..8493fc2 100644 --- a/Lab9/Lab9.srcs/sources_1/new/adder_3bit.vhd +++ b/Lab9/Lab9.srcs/sources_1/new/adder_3bit.vhd @@ -36,7 +36,7 @@ entity adder_3bit is Port ( A :in STD_LOGIC_VECTOR(2 downto 0); B: in STD_LOGIC_VECTOR(2 downto 0); S : out STD_LOGIC_VECTOR(2 downto 0); - C_in : in STD_LOGIC; + C_in : in STD_LOGIC:= '0' ; C_out : out STD_LOGIC); end adder_3bit; diff --git a/Lab9/Lab9.xpr b/Lab9/Lab9.xpr index cea481a..2347459 100644 --- a/Lab9/Lab9.xpr +++ b/Lab9/Lab9.xpr @@ -33,7 +33,7 @@