From 733575855457b20cbd17bf1653b3f23e4a96762d Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Wed, 8 Sep 2021 15:38:05 -0300 Subject: [PATCH 01/11] target/ppc: Move vsel to decodetree --- target/ppc/insn32.decode | 2 ++ target/ppc/translate/vmx-impl.c.inc | 12 ++++++++++++ 2 files changed, 14 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e135b8aba417..96835accd0f8 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -408,6 +408,8 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN +VSEL 000100 ..... ..... ..... ..... 101010 @VA + # VSX Load/Store Instructions LXV 111101 ..... ..... ............ . 001 @DQ_TSX diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index b361f73a67a9..95d9b1a1dfbd 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1566,6 +1566,18 @@ static void gen_vpermr(DisasContext *ctx) tcg_temp_free_ptr(rd); } +static bool trans_VSEL(DisasContext *ctx, arg_VA *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + REQUIRE_VSX(ctx); + + tcg_gen_gvec_bitsel(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->rc), + avr_full_offset(a->vrb), avr_full_offset(a->vra), + 16, 16); + + return true; +} + GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) From cd4040c202ed6e888a258dd52131629e6742bf6f Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Wed, 8 Sep 2021 17:11:32 -0300 Subject: [PATCH 02/11] target/ppc: move vperm/vpermr to decodetree --- target/ppc/helper.h | 5 +-- target/ppc/insn32.decode | 3 ++ target/ppc/int_helper.c | 13 +------ target/ppc/translate/vmx-impl.c.inc | 57 +++++++++++++++++++++-------- target/ppc/translate/vmx-ops.c.inc | 2 - 5 files changed, 48 insertions(+), 32 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 67c639ada741..f2baed819405 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -247,9 +247,8 @@ DEF_HELPER_2(vupklsh, void, avr, avr) DEF_HELPER_2(vupklsw, void, avr, avr) DEF_HELPER_5(vmsumubm, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsummbm, void, env, avr, avr, avr, avr) -DEF_HELPER_5(vsel, void, env, avr, avr, avr, avr) -DEF_HELPER_5(vperm, void, env, avr, avr, avr, avr) -DEF_HELPER_5(vpermr, void, env, avr, avr, avr, avr) +DEF_HELPER_4(VPERM, void, avr, avr, avr, avr) +DEF_HELPER_4(VPERMR, void, avr, avr, avr, avr) DEF_HELPER_4(vpkshss, void, env, avr, avr, avr) DEF_HELPER_4(vpkshus, void, env, avr, avr, avr) DEF_HELPER_4(vpkswss, void, env, avr, avr, avr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 96835accd0f8..9edec2c2cd26 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -408,6 +408,9 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN +VPERM 000100 ..... ..... ..... ..... 101011 @VA +VPERMR 000100 ..... ..... ..... ..... 111011 @VA + VSEL 000100 ..... ..... ..... ..... 101010 @VA # VSX Load/Store Instructions diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 4f56e83d46c7..d181f729e9bf 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1253,8 +1253,7 @@ void helper_vmulhud(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) mulu64(&discard, &r->u64[1], a->u64[1], b->u64[1]); } -void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, - ppc_avr_t *c) +void helper_VPERM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) { ppc_avr_t result; int i; @@ -1272,8 +1271,7 @@ void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, *r = result; } -void helper_vpermr(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, - ppc_avr_t *c) +void helper_VPERMR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) { ppc_avr_t result; int i; @@ -1541,13 +1539,6 @@ VRLMI(vrlwmi, 32, u32, 1); VRLMI(vrldnm, 64, u64, 0); VRLMI(vrlwnm, 32, u32, 0); -void helper_vsel(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, - ppc_avr_t *c) -{ - r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]); - r->u64[1] = (a->u64[1] & ~c->u64[1]) | (b->u64[1] & c->u64[1]); -} - void helper_vexptefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) { int i; diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 95d9b1a1dfbd..db08526c394c 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1548,22 +1548,48 @@ static void gen_vmladduhm(DisasContext *ctx) tcg_temp_free_ptr(rd); } -static void gen_vpermr(DisasContext *ctx) +static bool trans_VPERM(DisasContext *ctx, arg_VA *a) { - TCGv_ptr ra, rb, rc, rd; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - ra = gen_avr_ptr(rA(ctx->opcode)); - rb = gen_avr_ptr(rB(ctx->opcode)); - rc = gen_avr_ptr(rC(ctx->opcode)); - rd = gen_avr_ptr(rD(ctx->opcode)); - gen_helper_vpermr(cpu_env, rd, ra, rb, rc); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rb); - tcg_temp_free_ptr(rc); - tcg_temp_free_ptr(rd); + TCGv_ptr vrt, vra, vrb, vrc; + + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + REQUIRE_VSX(ctx); + + vrt = gen_avr_ptr(a->vrt); + vra = gen_avr_ptr(a->vra); + vrb = gen_avr_ptr(a->vrb); + vrc = gen_avr_ptr(a->rc); + + gen_helper_VPERM(vrt, vra, vrb, vrc); + + tcg_temp_free_ptr(vrt); + tcg_temp_free_ptr(vra); + tcg_temp_free_ptr(vrb); + tcg_temp_free_ptr(vrc); + + return true; +} + +static bool trans_VPERMR(DisasContext *ctx, arg_VA *a) +{ + TCGv_ptr vrt, vra, vrb, vrc; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VSX(ctx); + + vrt = gen_avr_ptr(a->vrt); + vra = gen_avr_ptr(a->vra); + vrb = gen_avr_ptr(a->vrb); + vrc = gen_avr_ptr(a->rc); + + gen_helper_VPERMR(vrt, vra, vrb, vrc); + + tcg_temp_free_ptr(vrt); + tcg_temp_free_ptr(vra); + tcg_temp_free_ptr(vrb); + tcg_temp_free_ptr(vrc); + + return true; } static bool trans_VSEL(DisasContext *ctx, arg_VA *a) @@ -1581,7 +1607,6 @@ static bool trans_VSEL(DisasContext *ctx, arg_VA *a) GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) -GEN_VAFORM_PAIRED(vsel, vperm, 21) GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) GEN_VXFORM_NOA(vclzb, 1, 28) diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc index 25ee715b4326..cf8a109114ce 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -241,7 +241,6 @@ GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E), GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F), GEN_VXFORM_300_EO(vclzlsbb, 0x01, 0x18, 0x0), GEN_VXFORM_300_EO(vctzlsbb, 0x01, 0x18, 0x1), -GEN_VXFORM_300(vpermr, 0x1D, 0xFF), #define GEN_VXFORM_NOA(name, opc2, opc3) \ GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) @@ -276,7 +275,6 @@ GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), -GEN_VAFORM_PAIRED(vsel, vperm, 21), GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), From 60f567b9d2ad4714d5e61ee496a48c9e2a47a566 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Tue, 14 Sep 2021 15:40:23 -0300 Subject: [PATCH 03/11] target/ppc: Move xxsel to decodetree --- target/ppc/insn32.decode | 13 +++++++-- target/ppc/insn64.decode | 22 +++++++-------- target/ppc/translate/vsx-impl.c.inc | 20 ++++++-------- target/ppc/translate/vsx-ops.c.inc | 43 ----------------------------- 4 files changed, 29 insertions(+), 69 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 9edec2c2cd26..c5d20c6155fe 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -123,10 +123,15 @@ &X_vrt_frbp vrt frbp @X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp +%xx_xt 0:1 21:5 +%xx_xb 1:1 11:5 +%xx_xa 2:1 16:5 +%xx_xc 3:1 6:5 &XX2 xt xb uim:uint8_t -%xx2_xt 0:1 21:5 -%xx2_xb 1:1 11:5 -@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb +@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb + +&XX4 xt xa xb xc +@XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt xa=%xx_xa xb=%xx_xb xc=%xx_xc &Z22_bf_fra bf fra dm @Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra @@ -429,6 +434,8 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8 XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2 +XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4 + ## VSX Vector Load Special Value Instruction LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5 diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index c1965dca1786..0d4db2df1af4 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -45,14 +45,14 @@ &8RR_D si=%8rr_si xt=%8rr_xt # Format XX4 -&XX4 xt xa xb xc -%xx4_xt 0:1 21:5 -%xx4_xa 2:1 16:5 -%xx4_xb 1:1 11:5 -%xx4_xc 3:1 6:5 -@XX4 ........ ........ ........ ........ \ +%8rr_xx_xt 0:1 21:5 +%8rr_xx_xa 2:1 16:5 +%8rr_xx_xb 1:1 11:5 +%8rr_xx_xc 3:1 6:5 +&8RR_XX4 xt xa xb xc +@8RR_XX4 ........ ........ ........ ........ \ ...... ..... ..... ..... ..... .. .... \ - &XX4 xt=%xx4_xt xa=%xx4_xa xb=%xx4_xb xc=%xx4_xc + &8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc ### Fixed-Point Load Instructions @@ -187,10 +187,10 @@ XXSPLTI32DX 000001 01 0000 -- -- ................ \ 100000 ..... 000 .. ................ @8RR_D_IX XXBLENDVD 000001 01 0000 -- ------------------ \ - 100001 ..... ..... ..... ..... 11 .... @XX4 + 100001 ..... ..... ..... ..... 11 .... @8RR_XX4 XXBLENDVW 000001 01 0000 -- ------------------ \ - 100001 ..... ..... ..... ..... 10 .... @XX4 + 100001 ..... ..... ..... ..... 10 .... @8RR_XX4 XXBLENDVH 000001 01 0000 -- ------------------ \ - 100001 ..... ..... ..... ..... 01 .... @XX4 + 100001 ..... ..... ..... ..... 01 .... @8RR_XX4 XXBLENDVB 000001 01 0000 -- ------------------ \ - 100001 ..... ..... ..... ..... 00 .... @XX4 + 100001 ..... ..... ..... ..... 00 .... @8RR_XX4 diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index badf70cb01a8..e350b760788f 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1446,19 +1446,15 @@ static void glue(gen_, name)(DisasContext *ctx) \ VSX_XXMRG(xxmrghw, 1) VSX_XXMRG(xxmrglw, 0) -static void gen_xxsel(DisasContext *ctx) +static bool trans_XXSEL(DisasContext *ctx, arg_XX4 *a) { - int rt = xT(ctx->opcode); - int ra = xA(ctx->opcode); - int rb = xB(ctx->opcode); - int rc = xC(ctx->opcode); + REQUIRE_INSNS_FLAGS2(ctx, VSX); + REQUIRE_VSX(ctx); - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc), - vsr_full_offset(rb), vsr_full_offset(ra), 16, 16); + tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(a->xt), vsr_full_offset(a->xc), + vsr_full_offset(a->xb), vsr_full_offset(a->xa), 16, 16); + + return true; } static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a) @@ -2189,7 +2185,7 @@ static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b, tcg_temp_free_vec(tmp); } -static bool do_xxblendv(DisasContext *ctx, arg_XX4 *a, unsigned vece) +static bool do_xxblendv(DisasContext *ctx, arg_8RR_XX4 *a, unsigned vece) { static const TCGOpcode vecop_list[] = { INDEX_op_sari_vec, 0 diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc index 152d1e5c3bfb..35dd89b44509 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -352,47 +352,4 @@ GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300), GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300), -#define GEN_XXSEL_ROW(opc3) \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \ -GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \ - -GEN_XXSEL_ROW(0x00) -GEN_XXSEL_ROW(0x01) -GEN_XXSEL_ROW(0x02) -GEN_XXSEL_ROW(0x03) -GEN_XXSEL_ROW(0x04) -GEN_XXSEL_ROW(0x05) -GEN_XXSEL_ROW(0x06) -GEN_XXSEL_ROW(0x07) -GEN_XXSEL_ROW(0x08) -GEN_XXSEL_ROW(0x09) -GEN_XXSEL_ROW(0x0A) -GEN_XXSEL_ROW(0x0B) -GEN_XXSEL_ROW(0x0C) -GEN_XXSEL_ROW(0x0D) -GEN_XXSEL_ROW(0x0E) -GEN_XXSEL_ROW(0x0F) -GEN_XXSEL_ROW(0x10) -GEN_XXSEL_ROW(0x11) -GEN_XXSEL_ROW(0x12) -GEN_XXSEL_ROW(0x13) -GEN_XXSEL_ROW(0x14) -GEN_XXSEL_ROW(0x15) -GEN_XXSEL_ROW(0x16) -GEN_XXSEL_ROW(0x17) -GEN_XXSEL_ROW(0x18) -GEN_XXSEL_ROW(0x19) -GEN_XXSEL_ROW(0x1A) -GEN_XXSEL_ROW(0x1B) -GEN_XXSEL_ROW(0x1C) -GEN_XXSEL_ROW(0x1D) -GEN_XXSEL_ROW(0x1E) -GEN_XXSEL_ROW(0x1F) - GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), From a9a93b26b45989902f2e31e34f2f4e3845c156f5 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 10 Sep 2021 09:19:09 -0300 Subject: [PATCH 04/11] target/ppc: move xxperm/xxpermr to decodetree --- target/ppc/fpu_helper.c | 21 --------------- target/ppc/helper.h | 2 -- target/ppc/insn32.decode | 8 ++++++ target/ppc/translate/vsx-impl.c.inc | 42 +++++++++++++++++++++++++++-- target/ppc/translate/vsx-ops.c.inc | 2 -- 5 files changed, 48 insertions(+), 27 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c4896cecc80c..697147c0c0b0 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2987,27 +2987,6 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) return xt; } -#define VSX_XXPERM(op, indexed) \ -void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ - ppc_vsr_t *xa, ppc_vsr_t *pcv) \ -{ \ - ppc_vsr_t t = *xt; \ - int i, idx; \ - \ - for (i = 0; i < 16; i++) { \ - idx = pcv->VsrB(i) & 0x1F; \ - if (indexed) { \ - idx = 31 - idx; \ - } \ - t.VsrB(i) = (idx <= 15) ? xa->VsrB(idx) \ - : xt->VsrB(idx - 16); \ - } \ - *xt = t; \ -} - -VSX_XXPERM(xxperm, 0) -VSX_XXPERM(xxpermr, 1) - void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) { ppc_vsr_t t = { }; diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f2baed819405..3b33dd71621a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -516,8 +516,6 @@ DEF_HELPER_3(xvrspic, void, env, vsr, vsr) DEF_HELPER_3(xvrspim, void, env, vsr, vsr) DEF_HELPER_3(xvrspip, void, env, vsr, vsr) DEF_HELPER_3(xvrspiz, void, env, vsr, vsr) -DEF_HELPER_4(xxperm, void, env, vsr, vsr, vsr) -DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr) DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32) DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32) DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index c5d20c6155fe..190b4a2c21bd 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -130,6 +130,9 @@ &XX2 xt xb uim:uint8_t @XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb +&XX3 xt xa xb +@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb + &XX4 xt xa xb xc @XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt xa=%xx_xa xb=%xx_xb xc=%xx_xc @@ -434,6 +437,11 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8 XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2 +## VSX Permute Instructions + +XXPERM 111100 ..... ..... ..... 00011010 ... @XX3 +XXPERMR 111100 ..... ..... ..... 00111010 ... @XX3 + XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4 ## VSX Vector Load Special Value Instruction diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index e350b760788f..e3bc5fdab56c 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1217,8 +1217,46 @@ GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) + +static bool trans_XXPERM(DisasContext *ctx, arg_XX3 *a) +{ + TCGv_ptr xt, xa, xb; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VSX(ctx); + + xt = gen_vsr_ptr(a->xt); + xa = gen_vsr_ptr(a->xa); + xb = gen_vsr_ptr(a->xb); + + gen_helper_VPERM(xt, xa, xt, xb); + + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xa); + tcg_temp_free_ptr(xb); + + return true; +} + +static bool trans_XXPERMR(DisasContext *ctx, arg_XX3 *a) +{ + TCGv_ptr xt, xa, xb; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VSX(ctx); + + xt = gen_vsr_ptr(a->xt); + xa = gen_vsr_ptr(a->xa); + xb = gen_vsr_ptr(a->xb); + + gen_helper_VPERMR(xt, xa, xt, xb); + + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xa); + tcg_temp_free_ptr(xb); + + return true; +} #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ static void gen_##name(DisasContext *ctx) \ diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc index 35dd89b44509..9a6378d840a3 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -346,8 +346,6 @@ VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207), VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207), GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), -GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300), -GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300), GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300), GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300), From a652a4912d978bff2f52e0c226b3f936d8bd5662 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 10 Sep 2021 13:59:07 -0300 Subject: [PATCH 05/11] target/ppc: Move xxpermdi to decodetree --- target/ppc/insn32.decode | 4 ++ target/ppc/translate/vsx-impl.c.inc | 95 +++++++++++++++-------------- target/ppc/translate/vsx-ops.c.inc | 2 - 3 files changed, 52 insertions(+), 49 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 190b4a2c21bd..7ebfd53fbe06 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -133,6 +133,9 @@ &XX3 xt xa xb @XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb +&XX3_dm xt xa xb dm +@XX3_dm ...... ..... ..... ..... . dm:2 ..... ... &XX3_dm xt=%xx_xt xa=%xx_xa xb=%xx_xb + &XX4 xt xa xb xc @XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt xa=%xx_xa xb=%xx_xb xc=%xx_xc @@ -441,6 +444,7 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2 XXPERM 111100 ..... ..... ..... 00011010 ... @XX3 XXPERMR 111100 ..... ..... ..... 00111010 ... @XX3 +XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ... @XX3_dm XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4 diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index e3bc5fdab56c..59fc45496848 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -675,53 +675,6 @@ static void gen_mtvsrws(DisasContext *ctx) #endif -static void gen_xxpermdi(DisasContext *ctx) -{ - TCGv_i64 xh, xl; - - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - - xh = tcg_temp_new_i64(); - xl = tcg_temp_new_i64(); - - if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) || - (xT(ctx->opcode) == xB(ctx->opcode)))) { - if ((DM(ctx->opcode) & 2) == 0) { - get_cpu_vsrh(xh, xA(ctx->opcode)); - } else { - get_cpu_vsrl(xh, xA(ctx->opcode)); - } - if ((DM(ctx->opcode) & 1) == 0) { - get_cpu_vsrh(xl, xB(ctx->opcode)); - } else { - get_cpu_vsrl(xl, xB(ctx->opcode)); - } - - set_cpu_vsrh(xT(ctx->opcode), xh); - set_cpu_vsrl(xT(ctx->opcode), xl); - } else { - if ((DM(ctx->opcode) & 2) == 0) { - get_cpu_vsrh(xh, xA(ctx->opcode)); - set_cpu_vsrh(xT(ctx->opcode), xh); - } else { - get_cpu_vsrl(xh, xA(ctx->opcode)); - set_cpu_vsrh(xT(ctx->opcode), xh); - } - if ((DM(ctx->opcode) & 1) == 0) { - get_cpu_vsrh(xl, xB(ctx->opcode)); - set_cpu_vsrl(xT(ctx->opcode), xl); - } else { - get_cpu_vsrl(xl, xB(ctx->opcode)); - set_cpu_vsrl(xT(ctx->opcode), xl); - } - } - tcg_temp_free_i64(xh); - tcg_temp_free_i64(xl); -} - #define OP_ABS 1 #define OP_NABS 2 #define OP_NEG 3 @@ -1258,6 +1211,54 @@ static bool trans_XXPERMR(DisasContext *ctx, arg_XX3 *a) return true; } +static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3_dm *a) +{ + TCGv_i64 t0, t1; + + REQUIRE_INSNS_FLAGS2(ctx, VSX); + REQUIRE_VSX(ctx); + + t0 = tcg_temp_new_i64(); + + if (unlikely(a->xt == a->xa || a->xt == a->xb)) { + t1 = tcg_temp_new_i64(); + + if ((a->dm & 2) == 0) { + get_cpu_vsrh(t0, a->xa); + } else { + get_cpu_vsrl(t0, a->xa); + } + if ((a->dm & 1) == 0) { + get_cpu_vsrh(t1, a->xb); + } else { + get_cpu_vsrl(t1, a->xb); + } + + set_cpu_vsrh(a->xt, t0); + set_cpu_vsrl(a->xt, t1); + + tcg_temp_free_i64(t1); + } else { + if ((a->dm & 2) == 0) { + get_cpu_vsrh(t0, a->xa); + } else { + get_cpu_vsrl(t0, a->xa); + } + set_cpu_vsrh(a->xt, t0); + + if ((a->dm & 1) == 0) { + get_cpu_vsrh(t0, a->xb); + } else { + get_cpu_vsrl(t0, a->xb); + } + set_cpu_vsrl(a->xt, t0); + } + + tcg_temp_free_i64(t0); + + return true; +} + #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc index 9a6378d840a3..1f1f5ba2eb52 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -349,5 +349,3 @@ GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300), GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300), - -GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), From 6e84abef986dca70a7df8749066db9331d5a708a Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Wed, 8 Sep 2021 11:21:44 -0300 Subject: [PATCH 06/11] target/ppc: Implement xxpermx instruction --- target/ppc/helper.h | 1 + target/ppc/insn64.decode | 8 ++++++++ target/ppc/int_helper.c | 20 ++++++++++++++++++++ target/ppc/translate/vsx-impl.c.inc | 22 ++++++++++++++++++++++ 4 files changed, 51 insertions(+) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 3b33dd71621a..b5619e5b98d0 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -517,6 +517,7 @@ DEF_HELPER_3(xvrspim, void, env, vsr, vsr) DEF_HELPER_3(xvrspip, void, env, vsr, vsr) DEF_HELPER_3(xvrspiz, void, env, vsr, vsr) DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32) +DEF_HELPER_5(XXPERMX, void, vsr, vsr, vsr, vsr, tl) DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32) DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr) DEF_HELPER_5(XXBLENDVB, void, vsr, vsr, vsr, vsr, i32) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 0d4db2df1af4..12b938191563 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -54,6 +54,11 @@ ...... ..... ..... ..... ..... .. .... \ &8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc +&XX4_uim3 xt xa xb xc uim3 +@XX4_uim3 ...... .. .... -- ............... uim3:3 \ + ...... ..... ..... ..... ..... .. .... \ + &XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc + ### Fixed-Point Load Instructions PLBZ 000001 10 0--.-- .................. \ @@ -194,3 +199,6 @@ XXBLENDVH 000001 01 0000 -- ------------------ \ 100001 ..... ..... ..... ..... 01 .... @8RR_XX4 XXBLENDVB 000001 01 0000 -- ------------------ \ 100001 ..... ..... ..... ..... 00 .... @8RR_XX4 + +XXPERMX 000001 01 0000 -- --------------- ... \ + 100010 ..... ..... ..... ..... 00 .... @XX4_uim3 diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index d181f729e9bf..f46f2d3ee172 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1253,6 +1253,26 @@ void helper_vmulhud(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) mulu64(&discard, &r->u64[1], a->u64[1], b->u64[1]); } +void helper_XXPERMX(ppc_vsr_t *t, ppc_vsr_t *s0, ppc_vsr_t *s1, ppc_vsr_t *pcv, + target_ulong uim) +{ + int i, idx; + ppc_vsr_t tmp = { .u64 = {0, 0} }; + + for (i = 0; i < ARRAY_SIZE(t->u8); i++) { + if ((pcv->VsrB(i) >> 5) == uim) { + idx = pcv->VsrB(i) & 0x1f; + if (idx < ARRAY_SIZE(t->u8)) { + tmp.VsrB(i) = s0->VsrB(idx); + } else { + tmp.VsrB(i) = s1->VsrB(idx - ARRAY_SIZE(t->u8)); + } + } + } + + *t = tmp; +} + void helper_VPERM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) { ppc_avr_t result; diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 59fc45496848..7562589ddba3 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1259,6 +1259,28 @@ static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3_dm *a) return true; } +static bool trans_XXPERMX(DisasContext *ctx, arg_XX4_uim3 *a) +{ + TCGv_ptr xt, xa, xb, xc; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VSX(ctx); + + xt = gen_vsr_ptr(a->xt); + xa = gen_vsr_ptr(a->xa); + xb = gen_vsr_ptr(a->xb); + xc = gen_vsr_ptr(a->xc); + + gen_helper_XXPERMX(xt, xa, xb, xc, tcg_constant_tl(a->uim3)); + + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xa); + tcg_temp_free_ptr(xb); + tcg_temp_free_ptr(xc); + + return true; +} + #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ From be72a1f1f912d3753ce588bfb8f126a475bf95b4 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 24 Sep 2021 10:51:23 -0300 Subject: [PATCH 07/11] fixup! target/ppc: move vperm/vpermr to decodetree --- target/ppc/translate/vmx-impl.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index db08526c394c..fe5cf75f0131 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1553,7 +1553,7 @@ static bool trans_VPERM(DisasContext *ctx, arg_VA *a) TCGv_ptr vrt, vra, vrb, vrc; REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); - REQUIRE_VSX(ctx); + REQUIRE_VECTOR(ctx); vrt = gen_avr_ptr(a->vrt); vra = gen_avr_ptr(a->vra); @@ -1575,7 +1575,7 @@ static bool trans_VPERMR(DisasContext *ctx, arg_VA *a) TCGv_ptr vrt, vra, vrb, vrc; REQUIRE_INSNS_FLAGS2(ctx, ISA300); - REQUIRE_VSX(ctx); + REQUIRE_VECTOR(ctx); vrt = gen_avr_ptr(a->vrt); vra = gen_avr_ptr(a->vra); From cffb5ee8bf83eebdc682ae1c0a6dbab145b97819 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 24 Sep 2021 10:53:55 -0300 Subject: [PATCH 08/11] fixup! target/ppc: Move vsel to decodetree --- target/ppc/translate/vmx-impl.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index fe5cf75f0131..eb0c41a7c354 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1595,7 +1595,7 @@ static bool trans_VPERMR(DisasContext *ctx, arg_VA *a) static bool trans_VSEL(DisasContext *ctx, arg_VA *a) { REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); - REQUIRE_VSX(ctx); + REQUIRE_VECTOR(ctx); tcg_gen_gvec_bitsel(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->rc), avr_full_offset(a->vrb), avr_full_offset(a->vra), From fcaa75196117ddc27df4a256930ce18c072edeef Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 15 Oct 2021 10:51:40 -0300 Subject: [PATCH 09/11] fixup! target/ppc: Implement xxpermx instruction --- target/ppc/insn64.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 12b938191563..57dc579b7e40 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -55,7 +55,7 @@ &8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc &XX4_uim3 xt xa xb xc uim3 -@XX4_uim3 ...... .. .... -- ............... uim3:3 \ +@XX4_uim3 ...... .. .... .. ............... uim3:3 \ ...... ..... ..... ..... ..... .. .... \ &XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc From a4a8160daee613eafc0cab1cea728e843ad94036 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 15 Oct 2021 10:55:03 -0300 Subject: [PATCH 10/11] fixup! target/ppc: Implement xxpermx instruction --- target/ppc/insn64.decode | 8 ++++---- target/ppc/translate/vsx-impl.c.inc | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 57dc579b7e40..0cb500a5571c 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -54,10 +54,10 @@ ...... ..... ..... ..... ..... .. .... \ &8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc -&XX4_uim3 xt xa xb xc uim3 -@XX4_uim3 ...... .. .... .. ............... uim3:3 \ +&8RR_XX4_uim3 xt xa xb xc uim3 +@8RR_XX4_uim3 ...... .. .... .. ............... uim3:3 \ ...... ..... ..... ..... ..... .. .... \ - &XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc + &8RR_XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc ### Fixed-Point Load Instructions @@ -201,4 +201,4 @@ XXBLENDVB 000001 01 0000 -- ------------------ \ 100001 ..... ..... ..... ..... 00 .... @8RR_XX4 XXPERMX 000001 01 0000 -- --------------- ... \ - 100010 ..... ..... ..... ..... 00 .... @XX4_uim3 + 100010 ..... ..... ..... ..... 00 .... @8RR_XX4_uim3 diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 7562589ddba3..1afbc6e0e3e0 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1259,7 +1259,7 @@ static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3_dm *a) return true; } -static bool trans_XXPERMX(DisasContext *ctx, arg_XX4_uim3 *a) +static bool trans_XXPERMX(DisasContext *ctx, arg_8RR_XX4_uim3 *a) { TCGv_ptr xt, xa, xb, xc; From 5af7d23a8d276713f2c6074f8416a04478ea340a Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Tue, 4 Jan 2022 14:35:50 -0300 Subject: [PATCH 11/11] fixup! target/ppc: Move xxsel to decodetree --- target/ppc/insn64.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 0cb500a5571c..3061864ac7a2 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -44,7 +44,7 @@ ...... ..... .... . ................ \ &8RR_D si=%8rr_si xt=%8rr_xt -# Format XX4 +# Format 8RR:XX4 %8rr_xx_xt 0:1 21:5 %8rr_xx_xa 2:1 16:5 %8rr_xx_xb 1:1 11:5