From 3f40cb23936305256ff8b0e4bffae12bbc1a7dfe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Mon, 7 Mar 2022 15:01:40 -0300 Subject: [PATCH 1/6] target/ppc: Fix FPSCR.FI flag for VSX_CVT_INT_TO_FP helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 122 ++++++++++++++++++++++++++++++++++------ 1 file changed, 105 insertions(+), 17 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 7e8be99cc0c89..3624cc1900ad8 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -212,6 +212,24 @@ static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr) } } +/* TODO: this is not a 'finish' anymore, find a better name */ +static void finish_invalid_op_excp2(CPUPPCState *env, int op) +{ + /* Update the floating-point invalid operation summary */ + env->fpscr |= FP_VX; + /* Update the floating-point exception summary */ + env->fpscr |= FP_FX; + if (fpscr_ve != 0) { + /* Update the floating-point enabled exception summary */ + env->fpscr |= FP_FEX; + + CPUState *cs = env_cpu(env); + cs->exception_index = POWERPC_EXCP_PROGRAM; + env->error_code = POWERPC_EXCP_FP | op; + /* Exception is deferred */ + } +} + static void finish_invalid_op_arith(CPUPPCState *env, int op, bool set_fpcc, uintptr_t retaddr) { @@ -232,6 +250,13 @@ static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr) finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr); } +/* TODO: Rename this to float_invalid_op_vxsnan when conversion is over */ +static void float_invalid_op_vxsnan2(CPUPPCState *env) +{ + env->fpscr |= FP_VXSNAN; + finish_invalid_op_excp2(env, POWERPC_EXCP_FP_VXSNAN); +} + /* Magnitude subtraction of infinities */ static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc, uintptr_t retaddr) @@ -383,6 +408,22 @@ static inline void float_inexact_excp(CPUPPCState *env) } } +static inline void float_inexact_excp2(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + + env->fpscr |= FP_XX; + /* Update the floating-point exception summary */ + env->fpscr |= FP_FX; + if (fpscr_xe != 0) { + /* Update the floating-point enabled exception summary */ + env->fpscr |= FP_FEX; + /* We must update the target FPR before raising the exception */ + cs->exception_index = POWERPC_EXCP_PROGRAM; + env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; + } +} + void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) { uint32_t mask = 1u << bit; @@ -462,6 +503,45 @@ void helper_fpscr_check_status(CPUPPCState *env) } } +static void finish_fp_operation(CPUPPCState *env, int mask, uintptr_t raddr) +{ + CPUState *cs = env_cpu(env); + int flags = get_float_exception_flags(&env->fp_status); + + if (flags & float_flag_invalid) { + if ((mask & FP_VXSNAN) && (flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan2(env); + } + + /* TODO: Add other invalid exceptions */ + } + + if ((mask & FP_OX) && (flags & float_flag_overflow)) { + float_overflow_excp(env); + } + if ((mask & FP_UX) && (flags & float_flag_underflow)) { + float_underflow_excp(env); + } + if (mask & FP_FI) { + if (flags & float_flag_inexact) { + env->fpscr |= FP_FI; + } else { + env->fpscr &= ~FP_FI; + } + } + if ((mask & FP_XX) && (flags & float_flag_inexact)) { + float_inexact_excp2(env); + } + + if (cs->exception_index == POWERPC_EXCP_PROGRAM && + (env->error_code & POWERPC_EXCP_FP)) { + if (fp_exceptions_enabled(env)) { + raise_exception_err_ra(env, cs->exception_index, + env->error_code, raddr); + } + } +} + static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) { CPUState *cs = env_cpu(env); @@ -3006,10 +3086,8 @@ VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL) * ttp - target type (float32 or float64) * sfld - source vsr_t field * tfld - target vsr_t field - * jdef - definition of the j index (i or 2*i) - * sfprf - set FPRF */ -#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \ +#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, r2sp, fpscr_mask) \ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ ppc_vsr_t t = { }; \ @@ -3020,25 +3098,35 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ if (r2sp) { \ t.tfld = do_frsp(env, t.tfld, GETPC()); \ } \ - if (sfprf) { \ + if (fpscr_mask & FP_FPRF) { \ helper_compute_fprf_float64(env, t.tfld); \ } \ } \ \ *xt = t; \ - do_float_check_status(env, GETPC()); \ -} - -VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0) -VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0) -VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1) -VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1) -VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0) -VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0) -VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0) -VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0) -VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0) -VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0) + finish_fp_operation(env, fpscr_mask, GETPC()); \ +} + +VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 0, \ + (FP_FPRF | FP_FI | FP_XX)) +VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 0, \ + (FP_FPRF | FP_FI | FP_XX)) +VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, \ + (FP_FPRF | FP_FI | FP_XX)) +VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, \ + (FP_FPRF | FP_FI | FP_XX)) +VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, \ + FP_XX) +VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, \ + FP_XX) +VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, \ + FP_XX) +VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, \ + FP_XX) +VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, \ + FP_XX) +VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, \ + FP_XX) #define VSX_CVT_INT_TO_FP2(op, stp, ttp) \ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ From 6dd0995f6e19c38fbf4fd4407c4121fccd3603cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Mon, 7 Mar 2022 16:59:34 -0300 Subject: [PATCH 2/6] target/ppc: Fix FPSCR.FI flag for VSX_MADD helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Víctor Colombo --- target/ppc/fpu_helper.c | 102 ++++++++++++++++++++++++++++------------ 1 file changed, 73 insertions(+), 29 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 3624cc1900ad8..0c00be15e9d9c 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -243,6 +243,19 @@ static void finish_invalid_op_arith(CPUPPCState *env, int op, finish_invalid_op_excp(env, op, retaddr); } +/* TODO: this is not a 'finish' anymore, find a better name */ +static void finish_invalid_op_arith2(CPUPPCState *env, int op, bool set_fpcc) +{ + env->fpscr &= ~(FP_FR | FP_FI); + if (fpscr_ve == 0) { + if (set_fpcc) { + env->fpscr &= ~FP_FPCC; + env->fpscr |= (FP_C | FP_FU); + } + } + finish_invalid_op_excp2(env, op); +} + /* Signalling NaN */ static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr) { @@ -265,6 +278,13 @@ static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc, finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr); } +/* TODO: Rename this to float_invalid_op_vxisi when conversion is over */ +static void float_invalid_op_vxisi2(CPUPPCState *env, bool set_fpcc) +{ + env->fpscr |= FP_VXISI; + finish_invalid_op_arith2(env, POWERPC_EXCP_FP_VXISI, set_fpcc); +} + /* Division of infinity by infinity */ static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc, uintptr_t retaddr) @@ -289,6 +309,13 @@ static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc, finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr); } +/* TODO: Rename this to float_invalid_op_vximz when conversion is over */ +static void float_invalid_op_vximz2(CPUPPCState *env, bool set_fpcc) +{ + env->fpscr |= FP_VXIMZ; + finish_invalid_op_arith2(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc); +} + /* Square root of a negative number */ static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc, uintptr_t retaddr) @@ -509,6 +536,12 @@ static void finish_fp_operation(CPUPPCState *env, int mask, uintptr_t raddr) int flags = get_float_exception_flags(&env->fp_status); if (flags & float_flag_invalid) { + if ((mask & FP_VXIMZ) && (flags & float_flag_invalid_imz)) { + float_invalid_op_vximz2(env, mask & FP_FPRF); + } + if ((mask & FP_VXISI) && (flags & float_flag_invalid_isi)) { + float_invalid_op_vxisi2(env, mask & FP_FPRF); + } if ((mask & FP_VXSNAN) && (flags & float_flag_invalid_snan)) { float_invalid_op_vxsnan2(env); } @@ -2235,9 +2268,8 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23) * fld - vsr_t field (VsrD(*) or VsrW(*)) * maddflgs - flags for the float*muladd routine that control the * various forms (madd, msub, nmadd, nmsub) - * sfprf - set FPRF */ -#define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf) \ +#define VSX_MADD(op, nels, tp, fld, maddflgs, fpscr_mask) \ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ ppc_vsr_t *s1, ppc_vsr_t *s2, ppc_vsr_t *s3) \ { \ @@ -2252,37 +2284,49 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ t.fld = tp##_muladd(s1->fld, s3->fld, s2->fld, maddflgs, &tstat); \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ - if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - float_invalid_op_madd(env, tstat.float_exception_flags, \ - sfprf, GETPC()); \ - } \ - \ - if (sfprf) { \ + if (fpscr_mask & FP_FPRF) { \ helper_compute_fprf_float64(env, t.fld); \ } \ } \ + \ *xt = t; \ - do_float_check_status(env, GETPC()); \ -} - -VSX_MADD(XSMADDDP, 1, float64, VsrD(0), MADD_FLGS, 1) -VSX_MADD(XSMSUBDP, 1, float64, VsrD(0), MSUB_FLGS, 1) -VSX_MADD(XSNMADDDP, 1, float64, VsrD(0), NMADD_FLGS, 1) -VSX_MADD(XSNMSUBDP, 1, float64, VsrD(0), NMSUB_FLGS, 1) -VSX_MADD(XSMADDSP, 1, float64r32, VsrD(0), MADD_FLGS, 1) -VSX_MADD(XSMSUBSP, 1, float64r32, VsrD(0), MSUB_FLGS, 1) -VSX_MADD(XSNMADDSP, 1, float64r32, VsrD(0), NMADD_FLGS, 1) -VSX_MADD(XSNMSUBSP, 1, float64r32, VsrD(0), NMSUB_FLGS, 1) - -VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0) -VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0) -VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0) -VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0) - -VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0) -VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0) -VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0) -VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0) + finish_fp_operation(env, fpscr_mask, GETPC()); \ +} + +VSX_MADD(XSMADDDP, 1, float64, VsrD(0), MADD_FLGS, \ + (FP_FPRF | FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_FI | FP_XX | FP_UX | FP_OX)) +VSX_MADD(XSMSUBDP, 1, float64, VsrD(0), MSUB_FLGS, \ + (FP_FPRF | FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_FI | FP_XX | FP_UX | FP_OX)) +VSX_MADD(XSNMADDDP, 1, float64, VsrD(0), NMADD_FLGS, \ + (FP_FPRF | FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_FI | FP_XX | FP_UX | FP_OX)) +VSX_MADD(XSNMSUBDP, 1, float64, VsrD(0), NMSUB_FLGS, \ + (FP_FPRF | FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_FI | FP_XX | FP_UX | FP_OX)) +VSX_MADD(XSMADDSP, 1, float64r32, VsrD(0), MADD_FLGS, \ + (FP_FPRF | FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_FI | FP_XX | FP_UX | FP_OX)) +VSX_MADD(XSMSUBSP, 1, float64r32, VsrD(0), MSUB_FLGS, \ + (FP_FPRF | FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_FI | FP_XX | FP_UX | FP_OX)) +VSX_MADD(XSNMADDSP, 1, float64r32, VsrD(0), NMADD_FLGS, \ + (FP_FPRF | FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_FI | FP_XX | FP_UX | FP_OX)) +VSX_MADD(XSNMSUBSP, 1, float64r32, VsrD(0), NMSUB_FLGS, \ + (FP_FPRF | FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_FI | FP_XX | FP_UX | FP_OX)) + +VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, \ + (FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_XX | FP_UX | FP_OX)) +VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, \ + (FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_XX | FP_UX | FP_OX)) +VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, \ + (FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_XX | FP_UX | FP_OX)) +VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, \ + (FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_XX | FP_UX | FP_OX)) + +VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, \ + (FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_XX | FP_UX | FP_OX)) +VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, \ + (FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_XX | FP_UX | FP_OX)) +VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, \ + (FP_VXSNAN | FP_VXISI | FP_VXIMZ | FP_XX | FP_UX | FP_OX)) +VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, \ + (FP_VXSNAN | FP_XX | FP_UX | FP_OX)) /* * VSX_MADDQ - VSX floating point quad-precision muliply/add From b276447e4d8f3be3fd0f802df76d7da98e1bf7d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Wed, 23 Mar 2022 08:23:55 -0300 Subject: [PATCH 3/6] fixup! target/ppc: Fix FPSCR.FI flag for VSX_CVT_INT_TO_FP helper --- target/ppc/fpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 0c00be15e9d9c..b95c846c590f8 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -219,7 +219,7 @@ static void finish_invalid_op_excp2(CPUPPCState *env, int op) env->fpscr |= FP_VX; /* Update the floating-point exception summary */ env->fpscr |= FP_FX; - if (fpscr_ve != 0) { + if (env->fpscr & FP_VE) { /* Update the floating-point enabled exception summary */ env->fpscr |= FP_FEX; @@ -442,7 +442,7 @@ static inline void float_inexact_excp2(CPUPPCState *env) env->fpscr |= FP_XX; /* Update the floating-point exception summary */ env->fpscr |= FP_FX; - if (fpscr_xe != 0) { + if (env->fpscr & FP_XE) { /* Update the floating-point enabled exception summary */ env->fpscr |= FP_FEX; /* We must update the target FPR before raising the exception */ From 8c6e2a6205fef166efbffbd69965493b5a047999 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Wed, 23 Mar 2022 09:53:38 -0300 Subject: [PATCH 4/6] fixup! target/ppc: Fix FPSCR.FI flag for VSX_MADD helper --- target/ppc/fpu_helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index b95c846c590f8..d4dae67656268 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -246,7 +246,6 @@ static void finish_invalid_op_arith(CPUPPCState *env, int op, /* TODO: this is not a 'finish' anymore, find a better name */ static void finish_invalid_op_arith2(CPUPPCState *env, int op, bool set_fpcc) { - env->fpscr &= ~(FP_FR | FP_FI); if (fpscr_ve == 0) { if (set_fpcc) { env->fpscr &= ~FP_FPCC; From 470df3f5a6edc1e76ccdd55420f044a3060e38f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Thu, 24 Mar 2022 13:39:28 -0300 Subject: [PATCH 5/6] fixup! target/ppc: Fix FPSCR.FI flag for VSX_CVT_INT_TO_FP helper --- target/ppc/fpu_helper.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index d4dae67656268..79cde43a22b40 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -400,6 +400,23 @@ static inline void float_overflow_excp(CPUPPCState *env) } } +static inline void float_overflow_excp2(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + + env->fpscr |= FP_OX; + /* Update the floating-point exception summary */ + env->fpscr |= FP_FX; + if (env->fpscr && FP_OE) { + /* XXX: should adjust the result */ + /* Update the floating-point enabled exception summary */ + env->fpscr |= FP_FEX; + /* We must update the target FPR before raising the exception */ + cs->exception_index = POWERPC_EXCP_PROGRAM; + env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; + } +} + static inline void float_underflow_excp(CPUPPCState *env) { CPUState *cs = env_cpu(env); @@ -549,7 +566,7 @@ static void finish_fp_operation(CPUPPCState *env, int mask, uintptr_t raddr) } if ((mask & FP_OX) && (flags & float_flag_overflow)) { - float_overflow_excp(env); + float_overflow_excp2(env); } if ((mask & FP_UX) && (flags & float_flag_underflow)) { float_underflow_excp(env); From 70ca4894dd7662c0897708673c784e329fdaba94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Tue, 29 Mar 2022 12:35:07 -0300 Subject: [PATCH 6/6] fixup! fixup! target/ppc: Fix FPSCR.FI flag for VSX_MADD helper --- target/ppc/fpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 79cde43a22b40..7826e1c552a38 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -246,7 +246,7 @@ static void finish_invalid_op_arith(CPUPPCState *env, int op, /* TODO: this is not a 'finish' anymore, find a better name */ static void finish_invalid_op_arith2(CPUPPCState *env, int op, bool set_fpcc) { - if (fpscr_ve == 0) { + if (env->fpscr & FP_VE) { if (set_fpcc) { env->fpscr &= ~FP_FPCC; env->fpscr |= (FP_C | FP_FU);