From b8e86c9685e92726dd44ba22b6d27da678597687 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Mon, 2 May 2022 16:41:06 -0300 Subject: [PATCH 1/2] tests/tcg/ppc64: Add mffsce test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add mffsce test to check both the return value and the new fpscr stored in the cpu. Signed-off-by: Víctor Colombo --- tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/ppc64le/Makefile.target | 1 + tests/tcg/ppc64le/mffsce.c | 38 +++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+) create mode 100644 tests/tcg/ppc64le/mffsce.c diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target index babd209573d2c..331fae628e2f7 100644 --- a/tests/tcg/ppc64/Makefile.target +++ b/tests/tcg/ppc64/Makefile.target @@ -11,6 +11,7 @@ endif $(PPC64_TESTS): CFLAGS += -mpower8-vector PPC64_TESTS += mtfsf +PPC64_TESTS += mffsce ifneq ($(CROSS_CC_HAS_POWER10),) PPC64_TESTS += byte_reverse sha512-vector diff --git a/tests/tcg/ppc64le/Makefile.target b/tests/tcg/ppc64le/Makefile.target index 5b0eb5e8703d7..6ca3003f026be 100644 --- a/tests/tcg/ppc64le/Makefile.target +++ b/tests/tcg/ppc64le/Makefile.target @@ -24,6 +24,7 @@ run-sha512-vector: QEMU_OPTS+=-cpu POWER10 run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10 PPC64LE_TESTS += mtfsf +PPC64LE_TESTS += mffsce PPC64LE_TESTS += signal_save_restore_xer PPC64LE_TESTS += xxspltw diff --git a/tests/tcg/ppc64le/mffsce.c b/tests/tcg/ppc64le/mffsce.c new file mode 100644 index 0000000000000..4123407d7418c --- /dev/null +++ b/tests/tcg/ppc64le/mffsce.c @@ -0,0 +1,38 @@ +#include +#include +#include + +#define MTFSF(FLM, FRB) asm volatile ("mtfsf %0, %1" :: "i" (FLM), "f" (FRB)) +#define MFFS(FRT) asm("mffs %0" : "=f" (FRT)) +#define MFFSCE(FRT) asm("mffsce %0" : "=f" (FRT)) + +#define PPC_BIT_NR(nr) (63 - (nr)) + +#define FP_VE (1ull << PPC_BIT_NR(56)) +#define FP_OE (1ull << PPC_BIT_NR(57)) +#define FP_UE (1ull << PPC_BIT_NR(58)) +#define FP_ZE (1ull << PPC_BIT_NR(59)) +#define FP_XE (1ull << PPC_BIT_NR(60)) +#define FP_NI (1ull << PPC_BIT_NR(61)) +#define FP_RN0 (1ull << PPC_BIT_NR(62)) +#define FP_RN1 (1ull << PPC_BIT_NR(63)) + +int main(void) +{ + uint64_t frt, fpscr; + uint64_t last_8_bits = FP_VE | FP_UE | FP_ZE | + FP_XE | FP_NI | FP_RN1; + MTFSF(0b11111111, last_8_bits); // set test value to cpu fpscr + MFFSCE(frt); + MFFS(fpscr); + + // in the returned value + // should be as the cpu fpscr was before + assert((frt & 0xff) == last_8_bits); + + // in the cpu fpscr + // last 3 bits should be unchanged and enable bits should be unset + assert((fpscr & 0xff) == (last_8_bits & 0x7)); + + return 0; +} From ec9f075631beec792cf6d65024136c64e408281c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Tue, 10 May 2022 14:58:00 -0300 Subject: [PATCH 2/2] fixup! tests/tcg/ppc64: Add mffsce test --- tests/tcg/ppc64le/mffsce.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/tests/tcg/ppc64le/mffsce.c b/tests/tcg/ppc64le/mffsce.c index 4123407d7418c..1763a9da61ce7 100644 --- a/tests/tcg/ppc64le/mffsce.c +++ b/tests/tcg/ppc64le/mffsce.c @@ -8,12 +8,12 @@ #define PPC_BIT_NR(nr) (63 - (nr)) -#define FP_VE (1ull << PPC_BIT_NR(56)) -#define FP_OE (1ull << PPC_BIT_NR(57)) -#define FP_UE (1ull << PPC_BIT_NR(58)) -#define FP_ZE (1ull << PPC_BIT_NR(59)) -#define FP_XE (1ull << PPC_BIT_NR(60)) -#define FP_NI (1ull << PPC_BIT_NR(61)) +#define FP_VE (1ull << PPC_BIT_NR(56)) +#define FP_OE (1ull << PPC_BIT_NR(57)) +#define FP_UE (1ull << PPC_BIT_NR(58)) +#define FP_ZE (1ull << PPC_BIT_NR(59)) +#define FP_XE (1ull << PPC_BIT_NR(60)) +#define FP_NI (1ull << PPC_BIT_NR(61)) #define FP_RN0 (1ull << PPC_BIT_NR(62)) #define FP_RN1 (1ull << PPC_BIT_NR(63)) @@ -22,16 +22,17 @@ int main(void) uint64_t frt, fpscr; uint64_t last_8_bits = FP_VE | FP_UE | FP_ZE | FP_XE | FP_NI | FP_RN1; - MTFSF(0b11111111, last_8_bits); // set test value to cpu fpscr + MTFSF(0b11111111, last_8_bits); /* set test value to cpu fpscr */ MFFSCE(frt); MFFS(fpscr); - // in the returned value - // should be as the cpu fpscr was before + /* the returned value should be as the cpu fpscr was before */ assert((frt & 0xff) == last_8_bits); - // in the cpu fpscr - // last 3 bits should be unchanged and enable bits should be unset + /* + * the cpu fpscr last 3 bits should be unchanged + * and enable bits should be unset + */ assert((fpscr & 0xff) == (last_8_bits & 0x7)); return 0;