diff --git a/boards/alinx_ax4010/board_specific_top.sv b/boards/alinx_ax4010/board_specific_top.sv index 472ae6ef..b5165a61 100644 --- a/boards/alinx_ax4010/board_specific_top.sv +++ b/boards/alinx_ax4010/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define USE_DIGILENT_PMOD_MIC3 @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), @@ -154,7 +154,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index 064bb4c6..ee443b8d 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define INMP441_MIC @@ -84,23 +84,23 @@ module board_specific_top //------------------------------------------------------------------------ wire [ 3:0] KEY = { BTN_3, BTN_2, BTN_1, BTN_0 }; - wire [ w_sw - 1:0] top_sw = SW [w_sw - 1:0]; + wire [ w_sw - 1:0] lab_sw = SW [w_sw - 1:0]; localparam w_tm_key = 8, w_tm_led = 8, w_tm_digit = 8; - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif @@ -108,41 +108,41 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, KEY }; + assign lab_key = { tm_key, KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { KEY, tm_key }; + assign lab_key = { KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -155,28 +155,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), + .w_key ( w_lab_key ), .w_sw ( w_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( JC [1] ), .hsync ( JC [0] ), diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index d1977a1d..6100a5f3 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define INMP441_MIC @@ -84,23 +84,23 @@ module board_specific_top //------------------------------------------------------------------------ wire [ 3:0] KEY = { BTN_3, BTN_2, BTN_1, BTN_0 }; - wire [ w_sw - 1:0] top_sw = SW [w_sw - 1:0]; + wire [ w_sw - 1:0] lab_sw = SW [w_sw - 1:0]; localparam w_tm_key = 8, w_tm_led = 8, w_tm_digit = 8; - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif @@ -108,41 +108,41 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, KEY }; + assign lab_key = { tm_key, KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { KEY, tm_key }; + assign lab_key = { KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -155,28 +155,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), + .w_key ( w_lab_key ), .w_sw ( w_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( JC [1] ), .hsync ( JC [0] ), diff --git a/boards/basys3/board_specific_top.sv b/boards/basys3/board_specific_top.sv index 9a8575ed..e7f4e322 100644 --- a/boards/basys3/board_specific_top.sv +++ b/boards/basys3/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -42,10 +42,10 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire rst = sw [w_sw - 1]; - wire [w_top_sw - 1:0] top_sw = sw [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = sw [w_lab_sw - 1:0]; // FIXME: Should be assigned to some GPIO! wire UART_RX = '1; @@ -72,16 +72,16 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index 4f0763c4..454545ed 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD @@ -33,17 +33,17 @@ module board_specific_top inout [w_gpio - 1:0] GPIO ); - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -62,25 +62,25 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -103,7 +103,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // The last 4 LEDR are used like a 7SEG dp + assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // The last 4 LEDR are used like a 7SEG dp //------------------------------------------------------------------------ @@ -121,7 +121,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display @@ -192,7 +192,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index 53d7bde3..4ddfe638 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD @@ -33,17 +33,17 @@ module board_specific_top inout [w_gpio - 1:0] GPIO ); - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -64,25 +64,25 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -103,7 +103,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // The last 4 LEDR are used like a 7SEG dp + assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // The last 4 LEDR are used like a 7SEG dp logic [ 3:0] reg_vga_r, reg_vga_g, reg_vga_b; logic reg_vga_vs, reg_vga_hs; @@ -192,7 +192,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index 9950f975..1940ccf3 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD @@ -33,17 +33,17 @@ module board_specific_top inout [w_gpio - 1:0] GPIO ); - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -57,24 +57,24 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -95,7 +95,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // The last 4 LEDR are used like a 7SEG dp + assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // The last 4 LEDR are used like a 7SEG dp logic [ 3:0] reg_vga_r, reg_vga_g, reg_vga_b; logic reg_vga_vs, reg_vga_hs; @@ -184,7 +184,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/cmod_a7/board_specific_top.sv b/boards/cmod_a7/board_specific_top.sv index 0384c0c8..72578f64 100644 --- a/boards/cmod_a7/board_specific_top.sv +++ b/boards/cmod_a7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index 48ca6181..d69f2632 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -38,13 +38,13 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ BUTTON; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ BUTTON; //------------------------------------------------------------------------ @@ -67,23 +67,23 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO_0[7:2] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), .led ( LEDG ), @@ -121,7 +121,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display @@ -184,7 +184,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index 8e7bf401..66ac3433 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -1,14 +1,19 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( - parameter clk_mhz = 50, + parameter clk_mhz = 50, + pixel_mhz = 25, w_key = 4, w_sw = 10, w_led = 10, w_digit = 6, - w_gpio = 72 // GPIO_0[5:0] reserved for mic + w_gpio = 72, // GPIO_0[5:0] reserved for mic + screen_width = 640, + screen_height = 480, + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input CLOCK_50, @@ -24,7 +29,6 @@ module board_specific_top output logic [ 6:0] HEX3, output logic [ 6:0] HEX4, output logic [ 6:0] HEX5, - output VGA_HS, output VGA_VS, output [ 3:0] VGA_R, @@ -36,15 +40,16 @@ module board_specific_top ); //------------------------------------------------------------------------ - + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; wire clk = CLOCK_50; wire rst = ~ RESET_N; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [w_led - w_digit - 1:0] top_led; + wire [w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -64,7 +69,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -73,22 +78,25 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( SW ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + + + + .x ( x ), + .y ( y ), .red ( VGA_R ), .green ( VGA_G ), @@ -105,7 +113,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LEDR [w_led - w_digit - 1:0] = top_led; // The last 6 LEDR are used like a 7SEG dp + assign LEDR [w_led - w_digit - 1:0] = lab_led; // The last 6 LEDR are used like a 7SEG dp //------------------------------------------------------------------------ @@ -120,10 +128,34 @@ module board_specific_top assign hgfedcba [i] = abcdefgh [$left (abcdefgh) - i]; end endgenerate + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( ) + ); + + + `endif //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display @@ -202,7 +234,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index 7bd35637..e3ab8f37 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD @@ -27,13 +27,13 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -57,17 +57,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -76,40 +76,40 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -122,28 +122,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), @@ -289,7 +289,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 2c5d64e7..c37880a1 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD @@ -27,13 +27,13 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -57,17 +57,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -76,66 +76,66 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), @@ -281,7 +281,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 3c36d43e..5b651a9d 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD @@ -27,12 +27,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -56,17 +56,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -75,40 +75,40 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -121,28 +121,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), @@ -292,7 +292,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 5d34e960..598a7623 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD @@ -27,12 +27,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -56,17 +56,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -75,40 +75,40 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -121,28 +121,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), @@ -292,7 +292,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index 60210d3e..8efe95e9 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -1,60 +1,87 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( - parameter clk_mhz = 50, - w_key = 4, - w_sw = 10, // One onboard SW is used as a reset - w_led = 18, - w_digit = 4, - w_gpio = 72 // GPIO_1[5:0] reserved for mic + parameter clk_mhz = 50, + pixel_mhz = 25, + + w_key = 4, + w_sw = 10, // One onboard SW is used as a reset + w_led = 8, + w_digit = 4, + w_gpio = 72, // GPIO_1[5:0] reserved for mic + + // gpio 0..5 are reserved for INMP 441 I2S microphone. + // Odd gpio .. are reserved I2S audio. + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( - input CLOCK_50, + input CLOCK_50, - input [w_key - 1:0] KEY, - input [w_sw - 1:0] SW, + input [w_key - 1:0] KEY, + input [w_sw - 1:0] SW, + output logic [ 9:0] LEDR, + output logic [ 7:0] LEDG, - input UART_RXD, - output UART_TXD, + output logic [ 6:0] HEX0, // HEX[7] aka dp are not connected to FPGA at DE1 board + output logic [ 6:0] HEX1, + output logic [ 6:0] HEX2, + output logic [ 6:0] HEX3, - output [ 9:0] LEDR, // The last 4 LEDR are used like a 7SEG dp - output [ 7:0] LEDG, + output VGA_HS, + output VGA_VS, + output [w_red - 1:0] VGA_R, + output [w_green - 1:0] VGA_G, + output [w_blue - 1:0] VGA_B, - output logic [ 6:0] HEX0, // HEX[7] aka dp doesn't connected to FPGA at "DE1" board - output logic [ 6:0] HEX1, - output logic [ 6:0] HEX2, - output logic [ 6:0] HEX3, + input UART_RXD, + output UART_TXD, - output VGA_HS, - output VGA_VS, - output [ 3:0] VGA_R, - output [ 3:0] VGA_G, - output [ 3:0] VGA_B, - - inout [ 35:0] GPIO_0, - inout [ 35:0] GPIO_1 + inout [w_gpio / 2 - 1:0] GPIO_0, + inout [w_gpio / 2 - 1:0] GPIO_1 ); //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset + + //------------------------------------------------------------------------ - wire clk = CLOCK_50; + wire clk = CLOCK_50; + wire rst = SW [w_lab_sw]; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + // Keys, switches, LEDs - //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; - wire [ 7:0] abcdefgh; - wire [ w_digit - 1:0] digit; + // A dynamic seven-segment display - wire [ 23:0] mic; - wire [ 15:0] sound; + wire [ 7:0] abcdefgh; + wire [ w_digit - 1:0] digit; + + // Graphics + + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; + + wire [ w_red - 1:0] red; + wire [ w_green - 1:0] green; + wire [ w_blue - 1:0] blue; + + // Microphone, sound output and UART + + wire [ 23:0] mic; + wire [ 15:0] sound; //------------------------------------------------------------------------ @@ -65,53 +92,55 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_top_sw ), - .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) - i_top + i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( ~ KEY ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( LEDG ), - .abcdefgh ( abcdefgh ), - .digit ( digit ), + .abcdefgh ( abcdefgh ), + .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + .x ( x ), + .y ( y ), - .red ( VGA_R ), - .green ( VGA_G ), - .blue ( VGA_B ), + .red ( VGA_R ), + .green ( VGA_G ), + .blue ( VGA_B ), - .uart_rx ( UART_RXD ), - .uart_tx ( UART_TXD ), + .mic ( mic ), + .sound ( sound ), - .mic ( mic ), - .sound ( sound ), + .uart_rx ( UART_RXD ), + .uart_tx ( UART_TXD ), - .gpio ( { GPIO_0, GPIO_1 } ) + .gpio ( { GPIO_0, GPIO_1 } ) ); //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // The last 4 LEDR are used like a 7SEG dp - - //------------------------------------------------------------------------ - - wire [$left (abcdefgh):0] hgfedcba; - logic [$left (digit):0] dp; + wire [$left (abcdefgh):0] hgfedcba; generate genvar i; @@ -124,7 +153,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display @@ -143,18 +172,23 @@ module board_specific_top // positive logic - assign LEDR [$left(LEDR) - w_digit + 1] = digit [0] ? hgfedcba [$left (HEX0) + 1] : '0; - assign LEDR [$left(LEDR) - w_digit + 2] = digit [1] ? hgfedcba [$left (HEX1) + 1] : '0; - assign LEDR [$left(LEDR) - w_digit + 3] = digit [2] ? hgfedcba [$left (HEX2) + 1] : '0; - assign LEDR [$left(LEDR) - w_digit + 4] = digit [3] ? hgfedcba [$left (HEX3) + 1] : '0; + always_comb + begin + LEDR = '0; + + for (int i = 0; i < w_digit; i ++) + LEDR [$bits (LEDR) - w_digit + i] + = digit [i] ? hgfedcba [$left (HEX0) + 1] : '0; + end `else always_ff @ (posedge clk or posedge rst) + begin if (rst) begin { HEX0, HEX1, HEX2, HEX3 } <= '1; - dp <= '0; + LEDR <= '0; end else begin @@ -163,47 +197,81 @@ module board_specific_top if (digit [2]) HEX2 <= ~ hgfedcba [$left (HEX2):0]; if (digit [3]) HEX3 <= ~ hgfedcba [$left (HEX3):0]; - if (digit [0]) dp[0] <= hgfedcba [$left (HEX0) + 1]; - if (digit [1]) dp[1] <= hgfedcba [$left (HEX1) + 1]; - if (digit [2]) dp[2] <= hgfedcba [$left (HEX2) + 1]; - if (digit [3]) dp[3] <= hgfedcba [$left (HEX3) + 1]; + for (int i = 0; i < w_digit; i ++) + if (digit [i]) + LEDR [$bits (LEDR) - w_digit + i] <= hgfedcba [$left (HEX0) + 1]; end + end - assign LEDR [$left(LEDR):$left(LEDR) - w_digit + 1] = dp; // The last 4 LEDR are used like a 7SEG dp + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( ) + ); `endif //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( GPIO_1 [0] ), // JP2 pin 1 - .ws ( GPIO_1 [2] ), // JP2 pin 3 - .sck ( GPIO_1 [4] ), // JP2 pin 5 - .sd ( GPIO_1 [5] ), // JP2 pin 6 - .value ( mic ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE + + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( GPIO_1 [0] ), + .ws ( GPIO_1 [2] ), + .sck ( GPIO_1 [4] ), + .sd ( GPIO_1 [5] ), + .value ( mic ) + ); - assign GPIO_1 [1] = 1'b0; // GND - JP2 pin 2 - assign GPIO_1 [3] = 1'b1; // VCC - JP2 pin 4 + assign GPIO_1 [1] = 1'b0; // GND + assign GPIO_1 [3] = 1'b1; // VCC + + `endif + //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - o_audio - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), - .mclk ( GPIO_1 [29] ), // JP2 pin 38 - .bclk ( GPIO_1 [27] ), // JP2 pin 36 - .lrclk ( GPIO_1 [23] ), // JP2 pin 32 - .sdata ( GPIO_1 [25] ) // JP2 pin 34 - ); // JP2 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( GPIO_1 [33] ), + .bclk ( GPIO_1 [31] ), + .lrclk ( GPIO_1 [27] ), + .sdata ( GPIO_1 [29] ) + ); + + + `endif endmodule diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index de2d75d1..3c1aca87 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -1,14 +1,26 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( parameter clk_mhz = 50, + pixel_mhz = 50, w_key = 2, w_sw = 10, w_led = 10, w_digit = 6, - w_gpio = 36 // GPIO[5:0] reserved for mic + w_gpio = 36, // GPIO[5:0] reserved for mic + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) + ) ( input MAX10_CLK1_50, @@ -24,30 +36,43 @@ module board_specific_top output logic [7:0] HEX4, output logic [7:0] HEX5, - output VGA_HS, - output VGA_VS, - output [ 3:0] VGA_R, - output [ 3:0] VGA_G, - output [ 3:0] VGA_B, + + output VGA_HS, + output VGA_VS, + output [w_red - 1:0] VGA_R, + output [w_green - 1:0] VGA_G, + output [w_blue - 1:0] VGA_B, + output VGA_BLANK_N, + output VGA_SYNC_N, inout [w_gpio - 1:0] GPIO ); //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = MAX10_CLK1_50; wire rst = SW [w_sw - 1]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; + // Graphics + + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; + + wire [ w_red - 1:0] red; + wire [ w_green - 1:0] green; + wire [ w_blue - 1:0] blue; + + wire [ 23:0] mic; wire [ 15:0] sound; @@ -64,31 +89,42 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), - .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic + .w_gpio ( w_gpio ), // GPIO[5:0] reserved for mic + + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) + + ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), .led ( LEDR ), .abcdefgh ( abcdefgh ), .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + .x ( x ), + .y ( y ), + .red ( VGA_R ), .green ( VGA_G ), @@ -118,7 +154,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display @@ -152,6 +188,33 @@ module board_specific_top if (digit [5]) HEX5 <= ~ hgfedcba; end + `endif + + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( VGA_CLK ) + ); + + assign VGA_BLANK_N = 1'b1; + assign VGA_SYNC_N = 1'b0; + `endif //------------------------------------------------------------------------ @@ -176,7 +239,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), @@ -187,4 +250,5 @@ module board_specific_top .sdata ( GPIO [29] ) // JP1 pin 34 ); // JP1 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + endmodule diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 8dd044f8..074f831d 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -39,12 +39,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = MAX10_CLK1_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; assign ARDUINO_RESET_N = ~ rst; @@ -68,17 +68,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -87,41 +87,41 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LEDR } = top_led; - assign { tm_digit , digit } = top_digit; + assign { tm_led , LEDR } = lab_led; + assign { tm_digit , digit } = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; - assign { LEDR , tm_led } = top_led; - assign { digit , tm_digit } = top_digit; + assign { LEDR , tm_led } = lab_led; + assign { digit , tm_digit } = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LEDR = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LEDR = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign digit = top_digit [w_digit - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign digit = lab_digit [w_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -134,31 +134,31 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_arduino + w_gpio ) // top gpio includes both ARDUINO and GPIO pins // GPIO [31], [33], [35] reserved for tm1638, GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), @@ -191,7 +191,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display @@ -268,7 +268,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index 0663fd0b..bf254d73 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD @@ -28,17 +28,17 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; `ifdef MISTER_IO_BOARD - wire rst = SW [w_top_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; + wire rst = SW [w_lab_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; `else - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; `endif - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -62,17 +62,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -81,67 +81,67 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), @@ -315,7 +315,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index f5332358..704d184b 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD @@ -28,17 +28,17 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; `ifdef MISTER_IO_BOARD - wire rst = SW [w_top_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; + wire rst = SW [w_lab_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; `else - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; `endif - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -62,17 +62,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -81,40 +81,40 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -127,28 +127,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), @@ -321,7 +321,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index cbd97cb1..f72b0c77 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD @@ -28,17 +28,17 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; `ifdef MISTER_IO_BOARD - wire rst = SW [w_top_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; + wire rst = SW [w_lab_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; `else - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; `endif - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -62,17 +62,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -81,67 +81,67 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; - assign tm_digit = top_digit; + assign { tm_led , LED } = lab_led; + assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; - assign tm_digit = top_digit; + assign { LED , tm_led } = lab_led; + assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), @@ -314,7 +314,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index a5f67c54..22562745 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -40,16 +40,16 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [w_led - w_digit - 1:0] top_led; + wire [w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -71,25 +71,25 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 6 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -109,7 +109,7 @@ module board_specific_top ); //------------------------------------------------------------------------ - assign LEDR [w_led - w_digit - 1:0] = top_led; // The last 6 LEDR are used like a 7SEG dp + assign LEDR [w_led - w_digit - 1:0] = lab_led; // The last 6 LEDR are used like a 7SEG dp assign VGA_R = { vga_red_4b, 4'd0 }; assign VGA_G = { vga_green_4b, 4'd0 }; @@ -166,7 +166,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index 978224d4..397e76d5 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -1,27 +1,37 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( - parameter clk_mhz = 50, - w_key = 4, + parameter clk_mhz = 50, + pixel_mhz = 25, + + w_key = 4, w_sw = 18, // One onboard SW is used as a reset w_led = 26, w_digit = 8, w_gpio = 72, // GPIO[5:0] reserved for mic - vga_clock = 25 // Pixel clock of VGA in MHz, recommend be equal with VGA_CLOCK from labs/common/vga.sv -) -( - input CLOCK_50, + vga_clock = 25, // Pixel clock of VGA in MHz, recommend be equal with VGA_CLOCK from labs/common/vga.sv + // gpio 0..5 are reserved for INMP 441 I2S microphone. + // Odd gpio .. are reserved I2S audio. - input [w_key - 1:0] KEY, - input [w_sw - 1:0] SW, + screen_width = 640, + screen_height = 480, - input UART_RXD, - output UART_TXD, + w_red = 4, + w_green = 4, + w_blue = 4, - output [ 17:0] LEDR, // The last 8 LEDR are used like a 7SEG dp - output [ 7:0] LEDG, + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) +) +( + input CLOCK_50, + + input [w_key - 1:0] KEY, + input [w_sw - 1:0] SW, + output logic [ 17:0] LEDR, // The last 8 LEDR are used like a 7SEG dp + output logic [ 7:0] LEDG, output logic [ 6:0] HEX0, // HEX[7] aka dp doesn't connected to FPGA at DE2 board output logic [ 6:0] HEX1, @@ -32,39 +42,53 @@ module board_specific_top output logic [ 6:0] HEX6, output logic [ 6:0] HEX7, - output VGA_CLK, // VGA DAC input triggers CLK - output VGA_HS, - output VGA_VS, - output [ 9:0] VGA_R, - output [ 9:0] VGA_G, - output [ 9:0] VGA_B, - output VGA_BLANK, - output VGA_SYNC, - - inout [ 35:0] GPIO_0, - inout [ 35:0] GPIO_1 + output VGA_CLK, + output VGA_HS, + output VGA_VS, + output VGA_BLANK, + output VGA_SYNC, + output [w_red - 1:0] VGA_R, + output [w_green - 1:0] VGA_G, + output [w_blue - 1:0] VGA_B, + + input UART_RXD, + output UART_TXD, + + inout [w_gpio / 2 - 1:0] GPIO_0, + inout [w_gpio / 2 - 1:0] GPIO_1 ); //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_led = w_led - w_digit; - wire clk = CLOCK_50; + //------------------------------------------------------------------------ - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire clk = CLOCK_50; + wire rst = SW [w_lab_sw]; - //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + // Keys, switches, LEDs + + wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + // wire [ w_lab_led - 1:0] lab_led; // FIX? + // wire [ w_led - w_digit - 1:0] lab_led; + + // A dynamic seven-segment display + + wire [ 7:0] abcdefgh; + wire [ w_digit - 1:0] digit; - wire [ 7:0] abcdefgh; - wire [ w_digit - 1:0] digit; + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; - wire [ 3:0] vga_red_4b,vga_green_4b,vga_blue_4b; + wire [ w_red - 1:0] vga_red_4b; + wire [ w_green - 1:0] vga_green_4b; + wire [ w_blue - 1:0] vga_blue_4b; - wire [ 23:0] mic; - wire [ 15:0] sound; + // Microphone, sound output and UART + wire [ 23:0] mic; + wire [ 15:0] sound; //------------------------------------------------------------------------ @@ -75,48 +99,56 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_top_sw ), - .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp + .w_digit ( w_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) - i_top + i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( ~ KEY ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( LEDG ), - .abcdefgh ( abcdefgh ), - .digit ( digit ), + .abcdefgh ( abcdefgh ), + .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + .x ( x ), + .y ( y ), - .red ( vga_red_4b ), - .green ( vga_green_4b ), - .blue ( vga_blue_4b ), + .red ( vga_red_4b ), + .green ( vga_green_4b ), + .blue ( vga_blue_4b ), - .uart_rx ( UART_RXD ), - .uart_tx ( UART_TXD ), + .mic ( mic ), + .sound ( sound ), - .mic ( mic ), - .sound ( sound ), + .uart_rx ( UART_RXD ), + .uart_tx ( UART_TXD ), - .gpio ( { GPIO_0, GPIO_1 } ) + .gpio ( { GPIO_0, GPIO_1 } ) ); //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // Last 8 LEDR are used like a 7SEG dp + //assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = w_led; // Last 8 LEDR are used like a 7SEG dp HACK? + // assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = w_lab_led; // Last 8 LEDR are used like a 7SEG dp HACK? assign VGA_R = { vga_red_4b, 4'd0 }; assign VGA_G = { vga_green_4b, 4'd0 }; @@ -156,8 +188,7 @@ module board_specific_top assign VGA_CLK = clk_en; //------------------------------------------------------------------------ - - wire [$left (abcdefgh):0] hgfedcba; + wire [$left (abcdefgh):0] hgfedcba; logic [$left (digit):0] dp; generate @@ -171,7 +202,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display @@ -183,18 +214,18 @@ module board_specific_top // inverted logic - assign HEX0 = digit [0] ? ~ hgfedcba [$left (HEX0):0] : '1; - assign HEX1 = digit [1] ? ~ hgfedcba [$left (HEX1):0] : '1; - assign HEX2 = digit [2] ? ~ hgfedcba [$left (HEX2):0] : '1; - assign HEX3 = digit [3] ? ~ hgfedcba [$left (HEX3):0] : '1; - assign HEX4 = digit [4] ? ~ hgfedcba [$left (HEX4):0] : '1; - assign HEX5 = digit [5] ? ~ hgfedcba [$left (HEX5):0] : '1; - assign HEX6 = digit [6] ? ~ hgfedcba [$left (HEX6):0] : '1; - assign HEX7 = digit [7] ? ~ hgfedcba [$left (HEX7):0] : '1; + assign HEX0 = digit [0] ? ~ hgfedcba [$left (HEX0):0] : '1; + assign HEX1 = digit [1] ? ~ hgfedcba [$left (HEX1):0] : '1; + assign HEX2 = digit [2] ? ~ hgfedcba [$left (HEX2):0] : '1; + assign HEX3 = digit [3] ? ~ hgfedcba [$left (HEX3):0] : '1; + assign HEX4 = digit [4] ? ~ hgfedcba [$left (HEX4):0] : '1; + assign HEX5 = digit [5] ? ~ hgfedcba [$left (HEX5):0] : '1; + assign HEX6 = digit [6] ? ~ hgfedcba [$left (HEX6):0] : '1; + assign HEX7 = digit [7] ? ~ hgfedcba [$left (HEX7):0] : '1; // positive logic - assign LEDR [ w_led - w_digit] = digit [0] ? hgfedcba [$left (HEX0) + 1] : '0; + assign LEDR [w_led - w_digit ] = digit [0] ? hgfedcba [$left (HEX0) + 1] : '0; assign LEDR [w_led - w_digit + 1] = digit [1] ? hgfedcba [$left (HEX1) + 1] : '0; assign LEDR [w_led - w_digit + 2] = digit [2] ? hgfedcba [$left (HEX2) + 1] : '0; assign LEDR [w_led - w_digit + 3] = digit [3] ? hgfedcba [$left (HEX3) + 1] : '0; @@ -206,11 +237,10 @@ module board_specific_top `else always_ff @ (posedge clk or posedge rst) - begin if (rst) begin { HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 } <= '1; - dp <= '0; + LEDR <= '0; end else begin @@ -231,44 +261,82 @@ module board_specific_top if (digit [5]) dp[5] <= hgfedcba [$left (HEX5) + 1]; if (digit [6]) dp[6] <= hgfedcba [$left (HEX6) + 1]; if (digit [7]) dp[7] <= hgfedcba [$left (HEX7) + 1]; + + + for (int i = 0; i < w_digit; i ++) + if (digit [i]) + LEDR [$bits (LEDR) - w_digit + i] <= hgfedcba [$left (HEX0) + 1]; end - end - assign LEDR [$left(LEDR):$left(LEDR) - w_digit + 1] = dp; // The last 4 LEDR are used like a 7SEG dp + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( ) + ); `endif //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( GPIO_1 [0] ), // JP2 pin 1 - .ws ( GPIO_1 [2] ), // JP2 pin 3 - .sck ( GPIO_1 [4] ), // JP2 pin 5 - .sd ( GPIO_1 [5] ), // JP2 pin 6 - .value ( mic ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE - assign GPIO_1 [1] = 1'b0; // GND - JP2 pin 2 - assign GPIO_1 [3] = 1'b1; // VCC - JP2 pin 4 + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( GPIO_1 [0] ), // JP2 pin 1 + .ws ( GPIO_1 [2] ), // JP2 pin 3 + .sck ( GPIO_1 [4] ), // JP2 pin 5 + .sd ( GPIO_1 [5] ), // JP2 pin 6 + .value ( mic ) + ); + + assign GPIO_1 [1] = 1'b0; // GND- JP2 pin 2 + assign GPIO_1 [3] = 1'b1; // VCC- JP2 pin 4 + + `endif + //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - o_audio - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), - .mclk ( GPIO_1 [29] ), // JP2 pin 38 - .bclk ( GPIO_1 [27] ), // JP2 pin 36 - .lrclk ( GPIO_1 [23] ), // JP2 pin 32 - .sdata ( GPIO_1 [25] ) // JP2 pin 34 - ); // JP2 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( GPIO_1 [29] ), // JP2 pin 38 + .bclk ( GPIO_1 [27] ), // JP2 pin 36 + .lrclk ( GPIO_1 [23] ), // JP2 pin 32 + .sdata ( GPIO_1 [25] ) // JP2 pin 34 + ); // JP2 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + + + `endif endmodule diff --git a/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference b/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference new file mode 100644 index 00000000..338beb92 --- /dev/null +++ b/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference @@ -0,0 +1,1189 @@ +#============================================================ +# Build by Terasic System Builder V1.0.0 +#============================================================ + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY DE2_115_GOLDEN_TOP +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 +set_global_assignment -name LAST_QUARTUS_VERSION 12.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:02:28 JANUARY 27,2010" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name SDC_FILE DE2_115_GOLDEN_TOP.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 + + +#============================================================ +# Sma +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] + +#============================================================ +# LCD +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON + +#============================================================ +# RS232 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS + +#============================================================ +# PS2 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 + +#============================================================ +# SDCARD +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] + +#============================================================ +# Audio +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK + +#============================================================ +# I2C for EEPROM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT + +#============================================================ +# I2C for Audioand Tv-Decode 1 and 2 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT + +#============================================================ +# Ethernet 0 +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO + +#============================================================ +# Ethernet 1 +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO + + +#============================================================ +# TV Decoder +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] + +#============================================================ +# USB +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N + +#============================================================ +# IR Receiver +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] + +#============================================================ +# SRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N + +#============================================================ +# Flash +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] + +#============================================================ +# HSMC, HSMC connect to HSMC Default +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 + +#============================================================ +# HSMC, HSMC connect to HSMC Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name SOPC_BUILDER_SIGNATURE_ID 002618860F9B000001268748D130 -qip DE2_115_SOPC.qip +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name MISC_FILE "D:/svn/DE2_115_GOLDEN_TOP/DE2_115_GOLDEN_TOP.dpf" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name MISC_FILE "D:/Document/de2c4/DE2_115_GOLDEN_TOP/DE2_115_GOLDEN_TOP.dpf" + +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_C19 -to ENET0_RST_N +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D22 -to ENET1_RST_N +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_Y15 -to IRDA_RXD +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_location_assignment PIN_F7 -to TD_DATA[7] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_G6 -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_location_assignment PIN_G14 -to UART_RTS +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_D12 -to VGA_B[7] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0 +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name MISC_FILE "D:/Projects/DE2C4/trunk/test/DE2_115_GOLDEN_TOP/DE2_115_GOLDEN_TOP.dpf" +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] + +set_location_assignment PIN_J10 -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_location_assignment PIN_E10 -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_D5 -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_location_assignment PIN_A14 -to ENETCLK_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0] +set_location_assignment PIN_F14 -to EX_IO[4] +set_location_assignment PIN_J13 -to UART_CTS +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_H12 -to VGA_G[3] +set_global_assignment -name MISC_FILE "D:/Document/de2c4/de2_115_golden_top/DE2_115_GOLDEN_TOP.dpf" + +set_global_assignment -name MISC_FILE "E:/SVN/DE2_115/trunk/test/de2_115_golden_top/DE2_115_GOLDEN_TOP.dpf" +set_global_assignment -name MISC_FILE "\\\\wuhan-file1\\R3\\RD\\cd_rom\\DE2_115_v1.0.5_CDROM\\DE2_115_demonstrations\\DE2_115_golden_top\\DE2_115_GOLDEN_TOP.dpf" +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name MISC_FILE "C:/Users/Administrator/Desktop/USB/de2_115_qsys/de2_115_qsys/DE2_115_golden_top/DE2_115_GOLDEN_TOP.dpf" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/boards/de2_115/board_specific.qsf b/boards/de2_115/board_specific.qsf index e9c6a82e..8999dc7b 100644 --- a/boards/de2_115/board_specific.qsf +++ b/boards/de2_115/board_specific.qsf @@ -1,207 +1,220 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" + set_global_assignment -name DEVICE EP4CE115F29C7 + set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" #----------------------------------------------------------------------------- -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD -set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY* -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW* -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR* - -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0* -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1* -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7* - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* + + set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY* + set_instance_assignment -name IO_STANDARD "2.5 V" -to SW* + set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR* + set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG* + + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0* + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1* + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7* + + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO* #----------------------------------------------------------------------------- -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" - -#set_location_assignment PIN_AG14 -to CLOCK2_50 -#set_location_assignment PIN_AG15 -to CLOCK3_50 -set_location_assignment PIN_Y2 -to CLOCK_50 - -#set_location_assignment PIN_G9 -to UART_TXD -set_location_assignment PIN_G12 -to UART_RXD - -set_location_assignment PIN_M23 -to KEY[0] -set_location_assignment PIN_M21 -to KEY[1] -set_location_assignment PIN_N21 -to KEY[2] -set_location_assignment PIN_R24 -to KEY[3] - -set_location_assignment PIN_AB28 -to SW[0] -set_location_assignment PIN_AC28 -to SW[1] -set_location_assignment PIN_AC27 -to SW[2] -set_location_assignment PIN_AD27 -to SW[3] -set_location_assignment PIN_AB27 -to SW[4] -set_location_assignment PIN_AC26 -to SW[5] -set_location_assignment PIN_AD26 -to SW[6] -set_location_assignment PIN_AB26 -to SW[7] -set_location_assignment PIN_AC25 -to SW[8] -set_location_assignment PIN_AB25 -to SW[9] -set_location_assignment PIN_AC24 -to SW[10] -set_location_assignment PIN_AB24 -to SW[11] -set_location_assignment PIN_AB23 -to SW[12] -set_location_assignment PIN_AA24 -to SW[13] -set_location_assignment PIN_AA23 -to SW[14] -set_location_assignment PIN_AA22 -to SW[15] -set_location_assignment PIN_Y24 -to SW[16] -set_location_assignment PIN_Y23 -to SW[17] - -set_location_assignment PIN_G19 -to LEDR[0] -set_location_assignment PIN_F19 -to LEDR[1] -set_location_assignment PIN_E19 -to LEDR[2] -set_location_assignment PIN_F21 -to LEDR[3] -set_location_assignment PIN_F18 -to LEDR[4] -set_location_assignment PIN_E18 -to LEDR[5] -set_location_assignment PIN_J19 -to LEDR[6] -set_location_assignment PIN_H19 -to LEDR[7] -set_location_assignment PIN_J17 -to LEDR[8] -set_location_assignment PIN_G17 -to LEDR[9] -set_location_assignment PIN_J15 -to LEDR[10] -set_location_assignment PIN_H16 -to LEDR[11] -set_location_assignment PIN_J16 -to LEDR[12] -set_location_assignment PIN_H17 -to LEDR[13] -set_location_assignment PIN_F15 -to LEDR[14] -set_location_assignment PIN_G15 -to LEDR[15] -set_location_assignment PIN_G16 -to LEDR[16] -set_location_assignment PIN_H15 -to LEDR[17] - -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] - -set_location_assignment PIN_A12 -to VGA_CLK -set_location_assignment PIN_F11 -to VGA_BLANK_N -set_location_assignment PIN_C10 -to VGA_SYNC_N -set_location_assignment PIN_G13 -to VGA_HS -set_location_assignment PIN_C13 -to VGA_VS -set_location_assignment PIN_E12 -to VGA_R[0] -set_location_assignment PIN_E11 -to VGA_R[1] -set_location_assignment PIN_D10 -to VGA_R[2] -set_location_assignment PIN_F12 -to VGA_R[3] -set_location_assignment PIN_G10 -to VGA_R[4] -set_location_assignment PIN_J12 -to VGA_R[5] -set_location_assignment PIN_H8 -to VGA_R[6] -set_location_assignment PIN_H10 -to VGA_R[7] -set_location_assignment PIN_G8 -to VGA_G[0] -set_location_assignment PIN_G11 -to VGA_G[1] -set_location_assignment PIN_F8 -to VGA_G[2] -set_location_assignment PIN_H12 -to VGA_G[3] -set_location_assignment PIN_C8 -to VGA_G[4] -set_location_assignment PIN_B8 -to VGA_G[5] -set_location_assignment PIN_F10 -to VGA_G[6] -set_location_assignment PIN_C9 -to VGA_G[7] -set_location_assignment PIN_B10 -to VGA_B[0] -set_location_assignment PIN_A10 -to VGA_B[1] -set_location_assignment PIN_C11 -to VGA_B[2] -set_location_assignment PIN_B11 -to VGA_B[3] -set_location_assignment PIN_A11 -to VGA_B[4] -set_location_assignment PIN_C12 -to VGA_B[5] -set_location_assignment PIN_D11 -to VGA_B[6] -set_location_assignment PIN_D12 -to VGA_B[7] - -set_location_assignment PIN_AB22 -to GPIO[0] -set_location_assignment PIN_AC15 -to GPIO[1] -set_location_assignment PIN_AB21 -to GPIO[2] -set_location_assignment PIN_Y17 -to GPIO[3] -set_location_assignment PIN_AC21 -to GPIO[4] -set_location_assignment PIN_Y16 -to GPIO[5] -set_location_assignment PIN_AD21 -to GPIO[6] -set_location_assignment PIN_AE16 -to GPIO[7] -set_location_assignment PIN_AD15 -to GPIO[8] -set_location_assignment PIN_AE15 -to GPIO[9] -set_location_assignment PIN_AC19 -to GPIO[10] -set_location_assignment PIN_AF16 -to GPIO[11] -set_location_assignment PIN_AD19 -to GPIO[12] -set_location_assignment PIN_AF15 -to GPIO[13] -set_location_assignment PIN_AF24 -to GPIO[14] -set_location_assignment PIN_AE21 -to GPIO[15] -set_location_assignment PIN_AF25 -to GPIO[16] -set_location_assignment PIN_AC22 -to GPIO[17] -set_location_assignment PIN_AE22 -to GPIO[18] -set_location_assignment PIN_AF21 -to GPIO[19] -set_location_assignment PIN_AF22 -to GPIO[20] -set_location_assignment PIN_AD22 -to GPIO[21] -set_location_assignment PIN_AG25 -to GPIO[22] -set_location_assignment PIN_AD25 -to GPIO[23] -set_location_assignment PIN_AH25 -to GPIO[24] -set_location_assignment PIN_AE25 -to GPIO[25] -set_location_assignment PIN_AG22 -to GPIO[26] -set_location_assignment PIN_AE24 -to GPIO[27] -set_location_assignment PIN_AH22 -to GPIO[28] -set_location_assignment PIN_AF26 -to GPIO[29] -set_location_assignment PIN_AE20 -to GPIO[30] -set_location_assignment PIN_AG23 -to GPIO[31] -set_location_assignment PIN_AF20 -to GPIO[32] -set_location_assignment PIN_AH26 -to GPIO[33] -set_location_assignment PIN_AH23 -to GPIO[34] -set_location_assignment PIN_AG26 -to GPIO[35] + set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# set_location_assignment PIN_AG14 -to CLOCK2_50 +# set_location_assignment PIN_AG15 -to CLOCK3_50 + set_location_assignment PIN_Y2 -to CLOCK_50 + + set_location_assignment PIN_M23 -to KEY[0] + set_location_assignment PIN_M21 -to KEY[1] + set_location_assignment PIN_N21 -to KEY[2] + set_location_assignment PIN_R24 -to KEY[3] + + set_location_assignment PIN_AB28 -to SW[0] + set_location_assignment PIN_AC28 -to SW[1] + set_location_assignment PIN_AC27 -to SW[2] + set_location_assignment PIN_AD27 -to SW[3] + set_location_assignment PIN_AB27 -to SW[4] + set_location_assignment PIN_AC26 -to SW[5] + set_location_assignment PIN_AD26 -to SW[6] + set_location_assignment PIN_AB26 -to SW[7] + set_location_assignment PIN_AC25 -to SW[8] + set_location_assignment PIN_AB25 -to SW[9] + set_location_assignment PIN_AC24 -to SW[10] + set_location_assignment PIN_AB24 -to SW[11] + set_location_assignment PIN_AB23 -to SW[12] + set_location_assignment PIN_AA24 -to SW[13] + set_location_assignment PIN_AA23 -to SW[14] + set_location_assignment PIN_AA22 -to SW[15] + set_location_assignment PIN_Y24 -to SW[16] + set_location_assignment PIN_Y23 -to SW[17] + + set_location_assignment PIN_G19 -to LEDR[0] + set_location_assignment PIN_F19 -to LEDR[1] + set_location_assignment PIN_E19 -to LEDR[2] + set_location_assignment PIN_F21 -to LEDR[3] + set_location_assignment PIN_F18 -to LEDR[4] + set_location_assignment PIN_E18 -to LEDR[5] + set_location_assignment PIN_J19 -to LEDR[6] + set_location_assignment PIN_H19 -to LEDR[7] + set_location_assignment PIN_J17 -to LEDR[8] + set_location_assignment PIN_G17 -to LEDR[9] + set_location_assignment PIN_J15 -to LEDR[10] + set_location_assignment PIN_H16 -to LEDR[11] + set_location_assignment PIN_J16 -to LEDR[12] + set_location_assignment PIN_H17 -to LEDR[13] + set_location_assignment PIN_F15 -to LEDR[14] + set_location_assignment PIN_G15 -to LEDR[15] + set_location_assignment PIN_G16 -to LEDR[16] + set_location_assignment PIN_H15 -to LEDR[17] + + set_location_assignment PIN_E21 -to LEDG[0] + set_location_assignment PIN_E22 -to LEDG[1] + set_location_assignment PIN_E25 -to LEDG[2] + set_location_assignment PIN_E24 -to LEDG[3] + set_location_assignment PIN_H21 -to LEDG[4] + set_location_assignment PIN_G20 -to LEDG[5] + set_location_assignment PIN_G22 -to LEDG[6] + set_location_assignment PIN_G21 -to LEDG[7] + set_location_assignment PIN_F17 -to LEDG[8] + + set_location_assignment PIN_G18 -to HEX0[0] + set_location_assignment PIN_F22 -to HEX0[1] + set_location_assignment PIN_E17 -to HEX0[2] + set_location_assignment PIN_L26 -to HEX0[3] + set_location_assignment PIN_L25 -to HEX0[4] + set_location_assignment PIN_J22 -to HEX0[5] + set_location_assignment PIN_H22 -to HEX0[6] + set_location_assignment PIN_M24 -to HEX1[0] + set_location_assignment PIN_Y22 -to HEX1[1] + set_location_assignment PIN_W21 -to HEX1[2] + set_location_assignment PIN_W22 -to HEX1[3] + set_location_assignment PIN_W25 -to HEX1[4] + set_location_assignment PIN_U23 -to HEX1[5] + set_location_assignment PIN_U24 -to HEX1[6] + set_location_assignment PIN_AA25 -to HEX2[0] + set_location_assignment PIN_AA26 -to HEX2[1] + set_location_assignment PIN_Y25 -to HEX2[2] + set_location_assignment PIN_W26 -to HEX2[3] + set_location_assignment PIN_Y26 -to HEX2[4] + set_location_assignment PIN_W27 -to HEX2[5] + set_location_assignment PIN_W28 -to HEX2[6] + set_location_assignment PIN_V21 -to HEX3[0] + set_location_assignment PIN_U21 -to HEX3[1] + set_location_assignment PIN_AB20 -to HEX3[2] + set_location_assignment PIN_AA21 -to HEX3[3] + set_location_assignment PIN_AD24 -to HEX3[4] + set_location_assignment PIN_AF23 -to HEX3[5] + set_location_assignment PIN_Y19 -to HEX3[6] + set_location_assignment PIN_AB19 -to HEX4[0] + set_location_assignment PIN_AA19 -to HEX4[1] + set_location_assignment PIN_AG21 -to HEX4[2] + set_location_assignment PIN_AH21 -to HEX4[3] + set_location_assignment PIN_AE19 -to HEX4[4] + set_location_assignment PIN_AF19 -to HEX4[5] + set_location_assignment PIN_AE18 -to HEX4[6] + set_location_assignment PIN_AD18 -to HEX5[0] + set_location_assignment PIN_AC18 -to HEX5[1] + set_location_assignment PIN_AB18 -to HEX5[2] + set_location_assignment PIN_AH19 -to HEX5[3] + set_location_assignment PIN_AG19 -to HEX5[4] + set_location_assignment PIN_AF18 -to HEX5[5] + set_location_assignment PIN_AH18 -to HEX5[6] + set_location_assignment PIN_AA17 -to HEX6[0] + set_location_assignment PIN_AB16 -to HEX6[1] + set_location_assignment PIN_AA16 -to HEX6[2] + set_location_assignment PIN_AB17 -to HEX6[3] + set_location_assignment PIN_AB15 -to HEX6[4] + set_location_assignment PIN_AA15 -to HEX6[5] + set_location_assignment PIN_AC17 -to HEX6[6] + set_location_assignment PIN_AD17 -to HEX7[0] + set_location_assignment PIN_AE17 -to HEX7[1] + set_location_assignment PIN_AG17 -to HEX7[2] + set_location_assignment PIN_AH17 -to HEX7[3] + set_location_assignment PIN_AF17 -to HEX7[4] + set_location_assignment PIN_AG18 -to HEX7[5] + set_location_assignment PIN_AA14 -to HEX7[6] + + set_location_assignment PIN_A12 -to VGA_CLK + set_location_assignment PIN_F11 -to VGA_BLANK_N + set_location_assignment PIN_C10 -to VGA_SYNC_N + set_location_assignment PIN_G13 -to VGA_HS + set_location_assignment PIN_C13 -to VGA_VS + set_location_assignment PIN_E12 -to VGA_R[0] + set_location_assignment PIN_E11 -to VGA_R[1] + set_location_assignment PIN_D10 -to VGA_R[2] + set_location_assignment PIN_F12 -to VGA_R[3] + set_location_assignment PIN_G10 -to VGA_R[4] + set_location_assignment PIN_J12 -to VGA_R[5] + set_location_assignment PIN_H8 -to VGA_R[6] + set_location_assignment PIN_H10 -to VGA_R[7] + set_location_assignment PIN_G8 -to VGA_G[0] + set_location_assignment PIN_G11 -to VGA_G[1] + set_location_assignment PIN_F8 -to VGA_G[2] + set_location_assignment PIN_H12 -to VGA_G[3] + set_location_assignment PIN_C8 -to VGA_G[4] + set_location_assignment PIN_B8 -to VGA_G[5] + set_location_assignment PIN_F10 -to VGA_G[6] + set_location_assignment PIN_C9 -to VGA_G[7] + set_location_assignment PIN_B10 -to VGA_B[0] + set_location_assignment PIN_A10 -to VGA_B[1] + set_location_assignment PIN_C11 -to VGA_B[2] + set_location_assignment PIN_B11 -to VGA_B[3] + set_location_assignment PIN_A11 -to VGA_B[4] + set_location_assignment PIN_C12 -to VGA_B[5] + set_location_assignment PIN_D11 -to VGA_B[6] + set_location_assignment PIN_D12 -to VGA_B[7] + + set_location_assignment PIN_G14 -to UART_RTS + set_location_assignment PIN_J13 -to UART_CTS + set_location_assignment PIN_G12 -to UART_RXD + set_location_assignment PIN_G9 -to UART_TXD + + set_location_assignment PIN_AB22 -to GPIO[0] + set_location_assignment PIN_AC15 -to GPIO[1] + set_location_assignment PIN_AB21 -to GPIO[2] + set_location_assignment PIN_Y17 -to GPIO[3] + set_location_assignment PIN_AC21 -to GPIO[4] + set_location_assignment PIN_Y16 -to GPIO[5] + set_location_assignment PIN_AD21 -to GPIO[6] + set_location_assignment PIN_AE16 -to GPIO[7] + set_location_assignment PIN_AD15 -to GPIO[8] + set_location_assignment PIN_AE15 -to GPIO[9] + set_location_assignment PIN_AC19 -to GPIO[10] + set_location_assignment PIN_AF16 -to GPIO[11] + set_location_assignment PIN_AD19 -to GPIO[12] + set_location_assignment PIN_AF15 -to GPIO[13] + set_location_assignment PIN_AF24 -to GPIO[14] + set_location_assignment PIN_AE21 -to GPIO[15] + set_location_assignment PIN_AF25 -to GPIO[16] + set_location_assignment PIN_AC22 -to GPIO[17] + set_location_assignment PIN_AE22 -to GPIO[18] + set_location_assignment PIN_AF21 -to GPIO[19] + set_location_assignment PIN_AF22 -to GPIO[20] + set_location_assignment PIN_AD22 -to GPIO[21] + set_location_assignment PIN_AG25 -to GPIO[22] + set_location_assignment PIN_AD25 -to GPIO[23] + set_location_assignment PIN_AH25 -to GPIO[24] + set_location_assignment PIN_AE25 -to GPIO[25] + set_location_assignment PIN_AG22 -to GPIO[26] + set_location_assignment PIN_AE24 -to GPIO[27] + set_location_assignment PIN_AH22 -to GPIO[28] + set_location_assignment PIN_AF26 -to GPIO[29] + set_location_assignment PIN_AE20 -to GPIO[30] + set_location_assignment PIN_AG23 -to GPIO[31] + set_location_assignment PIN_AF20 -to GPIO[32] + set_location_assignment PIN_AH26 -to GPIO[33] + set_location_assignment PIN_AH23 -to GPIO[34] + set_location_assignment PIN_AG26 -to GPIO[35] diff --git a/boards/de2_115/board_specific.sdc b/boards/de2_115/board_specific.sdc index 80c97317..4ca2cee9 100644 --- a/boards/de2_115/board_specific.sdc +++ b/boards/de2_115/board_specific.sdc @@ -1,23 +1,17 @@ create_clock -period "50.0 MHz" [get_ports CLOCK_50] -# for calculating divide_by value see vga_clock parameter in boards/de2_115/board_specific_top.sv - -create_generated_clock -name vga_clk -divide_by 2 -source [get_ports { CLOCK_50 }] [get_registers { clk_en }] -create_generated_clock -name vga_clk_out -source [get_registers { clk_en }] [get_ports { VGA_CLK }] - derive_clock_uncertainty set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] -set_false_path -from UART_RXD -to [all_clocks] set_false_path -from [get_ports {SW[*]}] -to [all_clocks] +set_false_path -from UART_RTS -to [all_clocks] +set_false_path -from UART_RXD -to [all_clocks] set_false_path -from [get_ports {GPIO[*]}] -to [all_clocks] -# set_false_path -from * -to UART_TXD - set_false_path -from * -to [get_ports {LEDR[*]}] - +set_false_path -from * -to [get_ports {LEDG[*]}] set_false_path -from * -to [get_ports {HEX*}] - set_false_path -from * -to [get_ports {VGA_*}] - +set_false_path -from * -to UART_CTS +set_false_path -from * -to UART_TXD set_false_path -from * -to [get_ports {GPIO[*]}] diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index f6dfdcf6..b2f6266b 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -1,24 +1,39 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( - parameter clk_mhz = 50, - w_key = 4, - w_sw = 18, - w_led = 18, - w_digit = 8, - w_gpio = 36, // GPIO[5:0] reserved for mic - vga_clock = 25 // Pixel clock of VGA in MHz, recommend be equal with VGA_CLOCK from labs/common/vga.sv + parameter clk_mhz = 50, + pixel_mhz = 25, + + w_key = 4, + w_sw = 18, + w_led = 8, + w_digit = 8, + w_gpio = 36, + + // gpio 0..5 are reserved for INMP 441 I2S microphone. + // Odd gpio .. are reserved I2S audio. + + screen_width = 640, + screen_height = 480, + + w_red = 8, + w_green = 8, + w_blue = 8, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input CLOCK_50, input [w_key - 1:0] KEY, input [w_sw - 1:0] SW, - output [w_led - 1:0] LEDR, // The last 8 LEDR are used like a 7SEG dp + output logic [ 17:0] LEDR, + output logic [ 8:0] LEDG, - output logic [ 6:0] HEX0, // HEX[7] aka dp doesn't connected to FPGA at DE2-115 + output logic [ 6:0] HEX0, // HEX[7] aka dp are not connected to FPGA at DE2-115 output logic [ 6:0] HEX1, output logic [ 6:0] HEX2, output logic [ 6:0] HEX3, @@ -27,42 +42,56 @@ module board_specific_top output logic [ 6:0] HEX6, output logic [ 6:0] HEX7, - output VGA_CLK, // VGA DAC input triggers CLK + output VGA_CLK, output VGA_HS, output VGA_VS, - output [ 7:0] VGA_R, - output [ 7:0] VGA_G, - output [ 7:0] VGA_B, + output [w_red - 1:0] VGA_R, + output [w_green - 1:0] VGA_G, + output [w_blue - 1:0] VGA_B, output VGA_BLANK_N, output VGA_SYNC_N, + input UART_RTS, + input UART_RXD, + + output UART_CTS, + output UART_TXD, + inout [w_gpio - 1:0] GPIO ); //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One sw is used as a reset - - wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset //------------------------------------------------------------------------ - wire [w_led - w_digit - 1:0] top_led; + wire clk = CLOCK_50; + wire rst = SW [w_lab_sw]; + + // Keys, switches, LEDs + + wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [ w_led - 1:0] lab_led; + + // A dynamic seven-segment display + + wire [ 7:0] abcdefgh; + wire [ w_digit - 1:0] digit; - wire [ 7:0] abcdefgh; - wire [ w_digit - 1:0] digit; + // Graphics - wire [ 3:0] vga_red_4b,vga_green_4b,vga_blue_4b; + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; - wire [ 23:0] mic; - wire [ 15:0] sound; + wire [ w_red - 1:0] red; + wire [ w_green - 1:0] green; + wire [ w_blue - 1:0] blue; - // FIXME: Should be assigned to some GPIO! - wire UART_TX; - wire UART_RX = '1; + // Microphone, sound output and UART + + wire [ 23:0] mic; + wire [ 15:0] sound; //------------------------------------------------------------------------ @@ -73,90 +102,59 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_top_sw ), - .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) - i_top + i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( ~ KEY ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), - .abcdefgh ( abcdefgh ), - .digit ( digit ), + .abcdefgh ( abcdefgh ), + .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + .x ( x ), + .y ( y ), - .red ( vga_red_4b ), - .green ( vga_green_4b ), - .blue ( vga_blue_4b ), + .red ( VGA_R ), + .green ( VGA_G ), + .blue ( VGA_B ), - .uart_rx ( UART_RX ), - .uart_tx ( UART_TX ), + .mic ( mic ), + .sound ( sound ), - .mic ( mic ), - .sound ( sound ), + .uart_rx ( UART_RXD ), + .uart_tx ( UART_TXD ), - .gpio ( GPIO ) + .gpio ( GPIO ) ); //------------------------------------------------------------------------ - assign LEDR [w_led - w_digit - 1:0] = top_led; // The last 8 LEDR are used like a 7SEG dp - - assign VGA_R = { vga_red_4b, 4'd0 }; - assign VGA_G = { vga_green_4b, 4'd0 }; - assign VGA_B = { vga_blue_4b, 4'd0 }; - - assign VGA_BLANK_N = 1'b1; - assign VGA_SYNC_N = 0; - - // Divide VGA DAC clock from clk_mhz to vga_clock - localparam CLK_DIV = $clog2 (clk_mhz / vga_clock) - 1; - - logic [CLK_DIV:0] clk_en_cnt; - logic clk_en; - - always_ff @ (posedge clk or posedge rst) - begin - if (rst) - begin - clk_en_cnt <= 'b0; - clk_en <= 'b0; - end - else - begin - if (clk_en_cnt == (clk_mhz / vga_clock) - 1) - begin - clk_en_cnt <= 'b0; - clk_en <= 'b1; - end - else - begin - clk_en_cnt <= clk_en_cnt + 1; - clk_en <= 'b0; - end - end - end - - assign VGA_CLK = clk_en; + assign LEDG = { { $bits (LEDG) - w_led { 1'b0 } }, lab_led }; //------------------------------------------------------------------------ - wire [$left (abcdefgh):0] hgfedcba; - logic [$left (digit):0] dp; + wire [$left (abcdefgh):0] hgfedcba; generate genvar i; @@ -169,7 +167,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display @@ -192,14 +190,14 @@ module board_specific_top // positive logic - assign LEDR [ w_led - w_digit] = digit [0] ? hgfedcba [$left (HEX0) + 1] : '0; - assign LEDR [w_led - w_digit + 1] = digit [1] ? hgfedcba [$left (HEX1) + 1] : '0; - assign LEDR [w_led - w_digit + 2] = digit [2] ? hgfedcba [$left (HEX2) + 1] : '0; - assign LEDR [w_led - w_digit + 3] = digit [3] ? hgfedcba [$left (HEX3) + 1] : '0; - assign LEDR [w_led - w_digit + 4] = digit [4] ? hgfedcba [$left (HEX4) + 1] : '0; - assign LEDR [w_led - w_digit + 5] = digit [5] ? hgfedcba [$left (HEX5) + 1] : '0; - assign LEDR [w_led - w_digit + 6] = digit [6] ? hgfedcba [$left (HEX6) + 1] : '0; - assign LEDR [w_led - w_digit + 7] = digit [7] ? hgfedcba [$left (HEX7) + 1] : '0; + always_comb + begin + LEDR = '0; + + for (int i = 0; i < w_digit; i ++) + LEDR [$bits (LEDR) - w_digit + i] + = digit [i] ? hgfedcba [$left (HEX0) + 1] : '0; + end `else @@ -208,7 +206,7 @@ module board_specific_top if (rst) begin { HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 } <= '1; - dp <= '0; + LEDR <= '0; end else begin @@ -221,52 +219,84 @@ module board_specific_top if (digit [6]) HEX6 <= ~ hgfedcba [$left (HEX6):0]; if (digit [7]) HEX7 <= ~ hgfedcba [$left (HEX7):0]; - if (digit [0]) dp[0] <= hgfedcba [$left (HEX0) + 1]; - if (digit [1]) dp[1] <= hgfedcba [$left (HEX1) + 1]; - if (digit [2]) dp[2] <= hgfedcba [$left (HEX2) + 1]; - if (digit [3]) dp[3] <= hgfedcba [$left (HEX3) + 1]; - if (digit [4]) dp[4] <= hgfedcba [$left (HEX4) + 1]; - if (digit [5]) dp[5] <= hgfedcba [$left (HEX5) + 1]; - if (digit [6]) dp[6] <= hgfedcba [$left (HEX6) + 1]; - if (digit [7]) dp[7] <= hgfedcba [$left (HEX7) + 1]; + for (int i = 0; i < w_digit; i ++) + if (digit [i]) + LEDR [$bits (LEDR) - w_digit + i] <= hgfedcba [$left (HEX0) + 1]; end end - assign LEDR [w_led - 1:w_led - w_digit] = dp; // The last 8 LEDR are used like a 7SEG dp + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( VGA_CLK ) + ); + + assign VGA_BLANK_N = 1'b1; + assign VGA_SYNC_N = 1'b0; `endif //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( GPIO [0] ), // JP5 pin 1 - .ws ( GPIO [2] ), // JP5 pin 3 - .sck ( GPIO [4] ), // JP5 pin 5 - .sd ( GPIO [5] ), // JP5 pin 6 - .value ( mic ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE - assign GPIO [1] = 1'b0; // GND - JP5 pin 2 - assign GPIO [3] = 1'b1; // VCC - JP5 pin 4 + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( GPIO [0] ), + .ws ( GPIO [2] ), + .sck ( GPIO [4] ), + .sd ( GPIO [5] ), + .value ( mic ) + ); + + assign GPIO [1] = 1'b0; // GND + assign GPIO [3] = 1'b1; // VCC + + `endif //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - o_audio - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), // TODO - check all comments with pins - .mclk ( GPIO [33] ), // JP5 pin 38 - .bclk ( GPIO [31] ), // JP5 pin 36 - .lrclk ( GPIO [27] ), // JP5 pin 32 - .sdata ( GPIO [29] ) // JP5 pin 34 - ); // JP5 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( GPIO [33] ), + .bclk ( GPIO [31] ), + .lrclk ( GPIO [27] ), + .sdata ( GPIO [29] ) + ); + + // VCC and GND for i2s_audio_out are on dedicated pins + + `endif endmodule diff --git a/boards/dk_dev_3c120n/board_specific_top.sv b/boards/dk_dev_3c120n/board_specific_top.sv index 434e387b..70201849 100644 --- a/boards/dk_dev_3c120n/board_specific_top.sv +++ b/boards/dk_dev_3c120n/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -81,7 +81,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -90,7 +90,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/emooc_cc/board_specific_top.sv b/boards/emooc_cc/board_specific_top.sv index f0f3a6fd..8dd553c8 100644 --- a/boards/emooc_cc/board_specific_top.sv +++ b/boards/emooc_cc/board_specific_top.sv @@ -6,7 +6,7 @@ // for more details. `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -48,12 +48,12 @@ module board_specific_top // locally useful numeric constants localparam w_gpio = w_gpio_j7 + w_gpio_p1 + w_gpio_p2, - w_top_sw = w_sw - 1; + w_lab_sw = w_sw - 1; // one switch is used as reset, others - as input signals; - // for convenience, declare set of wires "top_sw" + // for convenience, declare set of wires "lab_sw" wire rst = SW [w_sw - 1]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; // need explicit wire to be able to invert wire [ 7:0] abcdefgh; @@ -76,24 +76,24 @@ module board_specific_top //------------------------------------------------------------------------ // "top" module is a parametrized type, here are numeric parameters - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), // only non-reset switches used as inputs + .w_sw ( w_lab_sw ), // only non-reset switches used as inputs .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - // i_top is an instance, passing signal mappings - ?.. - i_top + // i_lab_top is an instance, passing signal mappings - ?.. + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), .key ( ~ KEY_N ), // invert keys, bringing to standard - .sw ( top_sw ), + .sw ( lab_sw ), .led ( LED ), diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 59a89c26..3cb28150 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -41,19 +41,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -63,9 +63,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -73,20 +73,20 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -102,28 +102,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), @@ -136,7 +136,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -158,7 +158,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index 68813be2..6b3ab269 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `undef ENABLE_INMP441 module board_specific_top @@ -44,19 +44,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -66,9 +66,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -76,21 +76,21 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; - assign LED = top_led; + assign LED = lab_led; `else // TM1638 module is not connected assign rst = KEY [w_key - 1]; - assign top_key = KEY [w_key - 1:0]; + assign lab_key = KEY [w_key - 1:0]; - assign LED = top_led; + assign LED = lab_led; `endif @@ -106,28 +106,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), @@ -140,7 +140,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -162,7 +162,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/nexys4/board_specific_top.sv b/boards/nexys4/board_specific_top.sv index 73166078..7f6a179a 100644 --- a/boards/nexys4/board_specific_top.sv +++ b/boards/nexys4/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -102,7 +102,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -111,7 +111,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/nexys4_ddr/board_specific_top.sv b/boards/nexys4_ddr/board_specific_top.sv index ffb9946d..36eabd4a 100644 --- a/boards/nexys4_ddr/board_specific_top.sv +++ b/boards/nexys4_ddr/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -107,7 +107,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -116,7 +116,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/nexys_a7/board_specific_top.sv b/boards/nexys_a7/board_specific_top.sv index ffb9946d..36eabd4a 100644 --- a/boards/nexys_a7/board_specific_top.sv +++ b/boards/nexys_a7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -107,7 +107,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -116,7 +116,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/omdazz/board_specific_top.sv b/boards/omdazz/board_specific_top.sv index dfe19f43..0d7ada34 100644 --- a/boards/omdazz/board_specific_top.sv +++ b/boards/omdazz/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define USE_DIGILENT_PMOD_MIC3 @@ -59,12 +59,12 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; - wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_sw - 1:0] lab_sw = ~ KEY [w_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [w_led - 1:0] top_led; + wire [w_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -96,16 +96,16 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -132,7 +132,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LED = ~ top_led; + assign LED = ~ lab_led; assign SEG = ~ abcdefgh; assign DIG = ~ digit; @@ -189,7 +189,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/omdazz_pmod_mic3/board_specific_top.sv b/boards/omdazz_pmod_mic3/board_specific_top.sv index 3b12c476..bec1a506 100644 --- a/boards/omdazz_pmod_mic3/board_specific_top.sv +++ b/boards/omdazz_pmod_mic3/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_DIGILENT_PMOD_MIC3 @@ -59,12 +59,12 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; - wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_sw - 1:0] lab_sw = ~ KEY [w_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [w_led - 1:0] top_led; + wire [w_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -96,16 +96,16 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -132,7 +132,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LED = ~ top_led; + assign LED = ~ lab_led; assign SEG = ~ abcdefgh; assign DIG = ~ digit; @@ -189,7 +189,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index 69c5ecc0..6a250edd 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `undef ENABLE_INMP441 module board_specific_top @@ -44,19 +44,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -66,9 +66,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -76,20 +76,20 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -105,28 +105,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), @@ -139,7 +139,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -161,7 +161,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/piswords6/board_specific_top.sv b/boards/piswords6/board_specific_top.sv index 1ad6cd8e..a60d6c83 100644 --- a/boards/piswords6/board_specific_top.sv +++ b/boards/piswords6/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -33,10 +33,10 @@ module board_specific_top wire clk = CLK; - localparam w_top_key = w_key - 1; // One key is used as a reset + localparam w_lab_key = w_key - 1; // One key is used as a reset - wire rst = ~ KEY [w_top_key]; - wire [w_top_key - 1:0] top_key = ~ KEY [w_top_key - 1:0]; + wire rst = ~ KEY [w_lab_key]; + wire [w_lab_key - 1:0] lab_key = ~ KEY [w_lab_key - 1:0]; //------------------------------------------------------------------------ @@ -60,22 +60,22 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), + .w_key ( w_lab_key ), .w_sw ( w_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ~ SW ), .led ( led ), diff --git a/boards/qmtech_c4_starter/board_specific_top.sv b/boards/qmtech_c4_starter/board_specific_top.sv index d01ca001..10c88dde 100644 --- a/boards/qmtech_c4_starter/board_specific_top.sv +++ b/boards/qmtech_c4_starter/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -63,7 +63,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( 1 ), // There are no keys @@ -72,7 +72,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/qmtech_kintex_7/board_specific_top.sv b/boards/qmtech_kintex_7/board_specific_top.sv index 1905732a..0a3b947f 100644 --- a/boards/qmtech_kintex_7/board_specific_top.sv +++ b/boards/qmtech_kintex_7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -78,7 +78,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( 5 ), @@ -87,7 +87,7 @@ module board_specific_top .w_digit ( 4 ), .w_gpio ( 0 ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), @@ -110,7 +110,7 @@ module board_specific_top .blue ( ), .mic ( '0 ), - .gpio ( ) + .gpio ( ) ); endmodule diff --git a/boards/runber/board_specific_top.sv b/boards/runber/board_specific_top.sv index 594cd50e..2b3be335 100644 --- a/boards/runber/board_specific_top.sv +++ b/boards/runber/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -39,7 +39,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), @@ -55,7 +55,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/rzrd/board_specific_top.sv b/boards/rzrd/board_specific_top.sv index dfe19f43..0d7ada34 100644 --- a/boards/rzrd/board_specific_top.sv +++ b/boards/rzrd/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define USE_DIGILENT_PMOD_MIC3 @@ -59,12 +59,12 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; - wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_sw - 1:0] lab_sw = ~ KEY [w_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [w_led - 1:0] top_led; + wire [w_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -96,16 +96,16 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -132,7 +132,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LED = ~ top_led; + assign LED = ~ lab_led; assign SEG = ~ abcdefgh; assign DIG = ~ digit; @@ -189,7 +189,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/rzrd_pmod_mic3/board_specific_top.sv b/boards/rzrd_pmod_mic3/board_specific_top.sv index 3b12c476..bec1a506 100644 --- a/boards/rzrd_pmod_mic3/board_specific_top.sv +++ b/boards/rzrd_pmod_mic3/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_DIGILENT_PMOD_MIC3 @@ -59,12 +59,12 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; - wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_sw - 1:0] lab_sw = ~ KEY [w_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [w_led - 1:0] top_led; + wire [w_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -96,16 +96,16 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -132,7 +132,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LED = ~ top_led; + assign LED = ~ lab_led; assign SEG = ~ abcdefgh; assign DIG = ~ digit; @@ -189,7 +189,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/saylinx/board_specific_top.sv b/boards/saylinx/board_specific_top.sv index 472ae6ef..b5165a61 100644 --- a/boards/saylinx/board_specific_top.sv +++ b/boards/saylinx/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define USE_DIGILENT_PMOD_MIC3 @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), @@ -154,7 +154,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/saylinx_pmod_mic3/board_specific_top.sv b/boards/saylinx_pmod_mic3/board_specific_top.sv index b8d7b4d2..67ccba09 100644 --- a/boards/saylinx_pmod_mic3/board_specific_top.sv +++ b/boards/saylinx_pmod_mic3/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_DIGILENT_PMOD_MIC3 @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), @@ -154,7 +154,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/step_max10/board_specific_top.sv b/boards/step_max10/board_specific_top.sv index feb938b0..b80245ef 100644 --- a/boards/step_max10/board_specific_top.sv +++ b/boards/step_max10/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -24,13 +24,13 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = clk_in; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ BTN; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [w_key - 1:0] lab_key = ~ BTN; //------------------------------------------------------------------------ @@ -41,23 +41,23 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), .led ( WAT_LED ), diff --git a/boards/tang_nano_1k/board_specific.cst b/boards/tang_nano_1k/board_specific.cst index 50027764..24e1f252 100644 --- a/boards/tang_nano_1k/board_specific.cst +++ b/boards/tang_nano_1k/board_specific.cst @@ -12,12 +12,12 @@ IO_PORT "key[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_LOC "key[0]" 13; IO_PORT "key[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP; -IO_LOC "led[2]" 11; -IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "led[1]" 10; -IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "led[0]" 9; -IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[2]" 11; +IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[1]" 10; +IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[0]" 9; +IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; IO_LOC "gpio[0]" 16 ; IO_PORT "gpio[0]" IO_TYPE=LVCMOS33; IO_LOC "gpio[1]" 17 ; IO_PORT "gpio[1]" IO_TYPE=LVCMOS33; diff --git a/boards/tang_nano_1k/board_specific_top.sv b/boards/tang_nano_1k/board_specific_top.sv index 04103aab..40360834 100644 --- a/boards/tang_nano_1k/board_specific_top.sv +++ b/boards/tang_nano_1k/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -48,10 +48,10 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .pixel_mhz ( pixel_mhz ), + .pixel_mhz ( pixel_mhz ), .w_key ( w_tm_key ), .w_sw ( w_tm_led ), @@ -64,7 +64,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), @@ -89,7 +89,7 @@ module board_specific_top .uart_tx ( ), .mic ( ), - .gpio ( gpio ) + .gpio ( gpio ) ); //------------------------------------------------------------------------ diff --git a/boards/tang_nano_1k_min/board_specific.cst b/boards/tang_nano_1k_min/board_specific.cst index b0f63764..677a531c 100644 --- a/boards/tang_nano_1k_min/board_specific.cst +++ b/boards/tang_nano_1k_min/board_specific.cst @@ -12,9 +12,9 @@ IO_PORT "key[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_LOC "key[0]" 13; IO_PORT "key[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP; -IO_LOC "led[2]" 11; -IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "led[1]" 10; -IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "led[0]" 9; -IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[2]" 11; +IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[1]" 10; +IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[0]" 9; +IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; diff --git a/boards/tang_nano_1k_min/board_specific_top.sv b/boards/tang_nano_1k_min/board_specific_top.sv index 4f1f696f..05524b62 100644 --- a/boards/tang_nano_1k_min/board_specific_top.sv +++ b/boards/tang_nano_1k_min/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -33,7 +33,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), @@ -49,7 +49,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index aa5e82bd..e5120411 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -35,19 +35,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -57,9 +57,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -74,20 +74,20 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -100,28 +100,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index d7b43729..77fc2b8a 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -41,19 +41,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -63,9 +63,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -73,20 +73,20 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -99,28 +99,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index ab8d2bbc..bb39c77b 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `undef ENABLE_INMP441 module board_specific_top @@ -44,19 +44,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -66,9 +66,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -76,20 +76,20 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -102,28 +102,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), @@ -136,7 +136,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -158,7 +158,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index 8bea48a9..093a4ca3 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -1,8 +1,8 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_HDMI -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( @@ -44,24 +44,24 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif //------------------------------------------------------------------------ - + wire clk_hdl; wire clk_hd; wire clk_px; @@ -81,9 +81,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -103,17 +103,17 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `ifdef USE_HDMI assign rst = ~ ( ~tm_key[w_tm_key - 1] & pll_lock ); `else assign rst = tm_key [w_tm_key - 1]; `endif - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -122,9 +122,9 @@ module board_specific_top `else assign rst = ~KEY[w_key - 1]; `endif - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -138,17 +138,17 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( `ifdef USE_HDMI .clk_mhz ( vid_clk_mhz ), `else .clk_mhz ( clk_mhz ), `endif - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) `ifdef USE_HDMI , @@ -157,7 +157,7 @@ module board_specific_top .w_blue ( 8 ) `endif ) - i_top + i_lab_top ( `ifdef USE_HDMI .clk ( clk_hd ), @@ -167,13 +167,13 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vsync ), .hsync ( hsync ), @@ -228,7 +228,7 @@ module board_specific_top //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver + inmp441_mic_i2s_receiver # ( .clk_mhz ( clk_mhz ) ) diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index d825358c..3441c07d 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -1,22 +1,28 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" -// `undef ENABLE_TM1638 +// `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( - parameter clk_mhz = 27, - pixel_mhz = 9, - - w_key = 2, // The last key is used for a reset - w_sw = 0, - w_led = 6, - w_digit = 0, - w_gpio = 10, - - w_red = 5, - w_green = 6, - w_blue = 5 + parameter clk_mhz = 27, + pixel_mhz = 9, + + w_key = 2, // The last key is used for a reset + w_sw = 0, + w_led = 6, + w_digit = 0, + w_gpio = 10, + + screen_width = 480, + screen_height = 272, + + w_red = 5, + w_green = 6, + w_blue = 5, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input CLK, @@ -83,19 +89,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -105,34 +111,38 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; + + wire [w_x - 1:0] x; + wire [w_y - 1:0] y; + wire [ 23:0] mic; wire [ 15:0] sound; //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; - assign LED = w_led' (~ top_led); + assign LED = w_led' (~ lab_led); `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -145,58 +155,55 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( - .clk_mhz ( clk_mhz ), - .pixel_mhz ( pixel_mhz ), - - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_key ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), - .w_gpio ( w_gpio ), - - .w_red ( w_red ), - .w_green ( w_green ), - .w_blue ( w_blue ) + .clk_mhz ( clk_mhz ), + + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_key ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) - i_top + i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), - - .key ( top_key ), - .sw ( top_key ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .led ( top_led ), + .key ( lab_key ), + .sw ( lab_key ), - .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .led ( lab_led ), - .vsync ( LARGE_LCD_VS ), - .hsync ( LARGE_LCD_HS ), + .abcdefgh ( abcdefgh ), + .digit ( lab_digit ), - .red ( LARGE_LCD_R ), - .green ( LARGE_LCD_G ), - .blue ( LARGE_LCD_B ), + .x ( x ), + .y ( y ), - .display_on ( LARGE_LCD_DE ), - .pixel_clk ( LARGE_LCD_CK ), + .red ( LARGE_LCD_R ), + .green ( LARGE_LCD_G ), + .blue ( LARGE_LCD_B ), - .uart_rx ( UART_RX ), - .uart_tx ( UART_TX ), + .uart_rx ( UART_RX ), + .uart_tx ( UART_TX ), - .mic ( mic ), - .sound ( sound ), - .gpio ( gpio ) + .mic ( mic ), + .sound ( sound ), + .gpio ( gpio ) ); - assign LARGE_LCD_INIT = 1'b0; - //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE wire [$left (abcdefgh):0] hgfedcba; @@ -213,7 +220,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( @@ -237,33 +244,69 @@ module board_specific_top //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( TF_CS ), - .ws ( TF_MOSI ), - .sck ( TF_SCLK ), - .sd ( TF_MISO ), - .value ( mic ) - ); + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( LARGE_LCD_HS ), + .vsync ( LARGE_LCD_VS ), + .display_on ( LARGE_LCD_DE ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( LARGE_LCD_CK ) + ); + + assign LARGE_LCD_INIT = 1'b0; + assign LARGE_LCD_BL = 1'b0; + `endif //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - o_audio - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), - .mclk ( SMALL_LCD_DATA ), - .bclk ( SMALL_LCD_CLK ), - .lrclk ( SMALL_LCD_RS ), - .sdata ( SMALL_LCD_CS ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE + + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( TF_CS ), + .ws ( TF_MOSI ), + .sck ( TF_SCLK ), + .sd ( TF_MISO ), + .value ( mic ) + ); + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( SMALL_LCD_DATA ), + .bclk ( SMALL_LCD_CLK ), + .lrclk ( SMALL_LCD_RS ), + .sdata ( SMALL_LCD_CS ) + ); + + `endif endmodule diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.cst b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.cst new file mode 100644 index 00000000..a3feafaa --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.cst @@ -0,0 +1,95 @@ +# The pin assignments +# All I/O pins here are 3.3V compatible unless specified otherwise + +IO_LOC "CLK" 52; + +IO_LOC "KEY[0]" 4; +IO_LOC "KEY[1]" 3; + +IO_LOC "LED[0]" 10; +IO_LOC "LED[1]" 11; +IO_LOC "LED[2]" 13; +IO_LOC "LED[3]" 14; +IO_LOC "LED[4]" 15; +IO_LOC "LED[5]" 16; + +IO_LOC "LARGE_LCD_DE" 33; +IO_LOC "LARGE_LCD_VS" 34; +IO_LOC "LARGE_LCD_HS" 40; +IO_LOC "LARGE_LCD_CK" 35; +IO_LOC "LARGE_LCD_INIT" 63; +IO_LOC "LARGE_LCD_BL" 86; + +IO_LOC "LARGE_LCD_R[3]" 75; +IO_LOC "LARGE_LCD_R[4]" 74; +IO_LOC "LARGE_LCD_R[5]" 73; +IO_LOC "LARGE_LCD_R[6]" 72; +IO_LOC "LARGE_LCD_R[7]" 71; + +IO_LOC "LARGE_LCD_G[2]" 70; +IO_LOC "LARGE_LCD_G[3]" 69; +IO_LOC "LARGE_LCD_G[4]" 68; +IO_LOC "LARGE_LCD_G[5]" 57; +IO_LOC "LARGE_LCD_G[6]" 56; +IO_LOC "LARGE_LCD_G[7]" 55; + +IO_LOC "LARGE_LCD_B[3]" 54; +IO_LOC "LARGE_LCD_B[4]" 53; +IO_LOC "LARGE_LCD_B[5]" 51; +IO_LOC "LARGE_LCD_B[6]" 42; +IO_LOC "LARGE_LCD_B[7]" 41; + +IO_LOC "UART_RX" 18; +IO_LOC "UART_TX" 17; + +# The following 4 pins (TF_CS, TF_MOSI, TF_SCLK, TF_MISO) +# are used for INMP441 microphone +# in basics-graphics-music labs + +IO_LOC "TF_CS" 38; # inmp441: lr +IO_LOC "TF_MOSI" 37; # inmp441: ws +IO_LOC "TF_SCLK" 36; # inmp441: sck +IO_LOC "TF_MISO" 39; # inmp441: sd + +# The first 3 GPIO pins are used for TM1638 I/O module +# which carries 8 LEDs, 8-digit 7-segment display and 8 keys + +IO_LOC "GPIO[0]" 25; # tm1638: sio_data +IO_LOC "GPIO[1]" 26; # tm1638: sio_clk +IO_LOC "GPIO[2]" 27; # tm1638: sio_stb +IO_LOC "GPIO[3]" 28; +IO_LOC "GPIO[4]" 29; +IO_LOC "GPIO[5]" 30; + +# The 4 pins SMALL_LCD_CLK, _CS, _RS and _DATA +# are used for the I2S audio output module PCM5102 +# in basics-graphics-music labs + +IO_LOC "SMALL_LCD_DATA" 77; # pcm5102: sck i2s_audio_out: mclk +IO_LOC "SMALL_LCD_CLK" 76; # pcm5102: bck i2s_audio_out: bclk +IO_LOC "SMALL_LCD_RESETN" 47; +IO_LOC "SMALL_LCD_CS" 48; # pcm5102: din i2s_audio_out: sdata +IO_LOC "SMALL_LCD_RS" 49; # pcm5102: lrck i2s_audio_out: lrclk + +# TMDS pins will be used later + +# IO_LOC "TMDS_CLK_P" 69,68; +# IO_LOC "TMDS_D_P[0]" 71,70; +# IO_LOC "TMDS_D_P[1]" 73,72; +# IO_LOC "TMDS_D_P[2]" 75,74; + +IO_LOC "FLASH_CLK" 59; +IO_LOC "FLASH_CSB" 60; +IO_LOC "FLASH_MOSI" 61; +IO_LOC "FLASH_MISO" 62; + +# The following pins are not used for the lab examples +# because they are 1.8V compatible + +# IO_LOC "GPIO_1_8_V_UNUSED[0]" 85; +# IO_LOC "GPIO_1_8_V_UNUSED[1]" 84; +# IO_LOC "GPIO_1_8_V_UNUSED[2]" 83; +# IO_LOC "GPIO_1_8_V_UNUSED[3]" 82; +# IO_LOC "GPIO_1_8_V_UNUSED[4]" 81; +# IO_LOC "GPIO_1_8_V_UNUSED[5]" 80; +# IO_LOC "GPIO_1_8_V_UNUSED[6]" 79; diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.sdc b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.sdc new file mode 100644 index 00000000..bf0aab16 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.sdc @@ -0,0 +1,4 @@ +# The timing constraints + +create_clock -name CLK -period 37.037 -waveform {0 18.518} [get_ports {CLK}] +create_clock -name LARGE_LCD_CK -period 111.11 -waveform {0 55.555} [get_ports {LARGE_LCD_CK}] diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.tcl b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.tcl new file mode 100644 index 00000000..794089f1 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.tcl @@ -0,0 +1,11 @@ +# Synthesis and Place & Route settings + +set_device GW1NR-LV9QN88PC6/I5 -name GW1NR-9 -device_version C + +set_option -synthesis_tool gowinsynthesis +set_option -output_base_name fpga_project +set_option -top_module board_specific_top +set_option -verilog_std sysv2017 + +set_option -use_mspi_as_gpio 1 +set_option -use_sspi_as_gpio 1 diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific_top.sv new file mode 100644 index 00000000..1a425fca --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific_top.sv @@ -0,0 +1,2 @@ +`define FORCE_NO_INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +`include "../tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv" diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_01.gprj b/boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_01.gprj new file mode 100644 index 00000000..79b1311f --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_01.gprj @@ -0,0 +1,7 @@ + + + + + 5 + gw1nr9c-004 + diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_02.gprj b/boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_02.gprj new file mode 100644 index 00000000..8c6b9904 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_02.gprj @@ -0,0 +1,2 @@ + + diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.ipc b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.ipc new file mode 100644 index 00000000..bf8c92d9 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.ipc @@ -0,0 +1,24 @@ +[General] +ipc_version=4 +file=gowin_rpll +module=Gowin_rPLL +target_device=gw1nr9c-004 +type=clock_rpll +version=1.0 + +[Config] +CKLOUTD3=false +CLKFB_SOURCE=0 +CLKIN_FREQ=27 +CLKOUTD=false +CLKOUTP=false +CLKOUT_BYPASS=false +CLKOUT_DIVIDE_DYN=true +CLKOUT_FREQ=9 +CLKOUT_TOLERANCE=0 +DYNAMIC=true +LANG=0 +LOCK_EN=false +MODE_GENERAL=true +PLL_PWD=false +RESET_PLL=false diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.mod b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.mod new file mode 100644 index 00000000..39dc975c --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.mod @@ -0,0 +1,32 @@ +-series GW1NR +-device GW1NR-9C +-package QFN88P +-part_number GW1NR-LV9QN88PC6/I5 + + +-mod_name Gowin_rPLL +-file_name gowin_rpll +-path Y:/4.3inch_screen/lcd_led/src/gowin_rpll/ +-type PLL +-rPll true +-file_type vlg +-dev_type GW1NR-9C +-dyn_idiv_sel false +-idiv_sel 3 +-dyn_fbdiv_sel false +-fbdiv_sel 1 +-dyn_odiv_sel false +-odiv_sel 48 +-dyn_da_en true +-rst_sig false +-rst_sig_p false +-fclkin 27 +-clkfb_sel 0 +-en_lock false +-clkout_bypass false +-clkout_ft_dir 1 +-en_clkoutp false +-clkoutp_bypass false +-en_clkoutd false +-clkoutd_bypass false +-en_clkoutd3 false \ No newline at end of file diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.v b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.v new file mode 100644 index 00000000..95f15287 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.v @@ -0,0 +1,63 @@ +//Copyright (C)2014-2022 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: IP file +//GOWIN Version: V1.9.8.09 +//Part Number: GW1NR-LV9QN88PC6/I5 +//Device: GW1NR-9C +//Created Time: Tue Mar 21 12:46:45 2023 + +module Gowin_rPLL (clkout, clkin); + +output clkout; +input clkin; + +wire lock_o; +wire clkoutp_o; +wire clkoutd_o; +wire clkoutd3_o; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +rPLL rpll_inst ( + .CLKOUT(clkout), + .LOCK(lock_o), + .CLKOUTP(clkoutp_o), + .CLKOUTD(clkoutd_o), + .CLKOUTD3(clkoutd3_o), + .RESET(gw_gnd), + .RESET_P(gw_gnd), + .CLKIN(clkin), + .CLKFB(gw_gnd), + .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) +); + +defparam rpll_inst.FCLKIN = "27"; +defparam rpll_inst.DYN_IDIV_SEL = "false"; +defparam rpll_inst.IDIV_SEL = 2; +defparam rpll_inst.DYN_FBDIV_SEL = "false"; +defparam rpll_inst.FBDIV_SEL = 0; +defparam rpll_inst.DYN_ODIV_SEL = "false"; +defparam rpll_inst.ODIV_SEL = 48; +defparam rpll_inst.PSDA_SEL = "0000"; +defparam rpll_inst.DYN_DA_EN = "true"; +defparam rpll_inst.DUTYDA_SEL = "1000"; +defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUT_DLY_STEP = 0; +defparam rpll_inst.CLKOUTP_DLY_STEP = 0; +defparam rpll_inst.CLKFB_SEL = "internal"; +defparam rpll_inst.CLKOUT_BYPASS = "false"; +defparam rpll_inst.CLKOUTP_BYPASS = "false"; +defparam rpll_inst.CLKOUTD_BYPASS = "false"; +defparam rpll_inst.DYN_SDIV_SEL = 2; +defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; +defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; +defparam rpll_inst.DEVICE = "GW1NR-9C"; + +endmodule //Gowin_rPLL diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_01.json b/boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_01.json new file mode 100644 index 00000000..8b6c52aa --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_01.json @@ -0,0 +1,32 @@ +{ + "Allow_Duplicate_Modules" : false, + "Annotated_Properties_for_Analyst" : true, + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CRC_CHECK" : true, + "Clock_Conversion" : true, + "Clock_Route_Order" : 0, + "Correct_Hold_Violation" : true, + "DONE" : true, + "DOWNLOAD_SPEED" : "default", + "Default_Enum_Encoding" : "default", + "Disable_Insert_Pad" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "FORMAT" : "binary", + "FSM Compiler" : true, + "Fanout_Guide" : 10000, + "Frequency" : "Auto", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "Implicit_Initial_Value_Support" : false, + "IncludePath" : [ diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_02.json b/boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_02.json new file mode 100644 index 00000000..a861fbcd --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_02.json @@ -0,0 +1,53 @@ + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "Multiple_File_Compilation_Unit" : true, + "Number_of_Critical_Paths" : "", + "Number_of_Start/End_Points" : "", + "OUTPUT_BASE_NAME" : "fpga_project", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "Pipelining" : true, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "Push_Tristates" : true, + "READY" : true, + "RECONFIG_N" : false, + "Ram_RW_Check" : true, + "Report_Auto-Placed_Io_Information" : false, + "Resolve_Mixed_Drivers" : false, + "Resource_Sharing" : true, + "Retiming" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SPI_FLASH_ADDR" : "00000000", + "SSPI" : true, + "Show_All_Warnings" : false, + "Synthesis On/Off Implemented as Translate On/Off" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "board_specific_top", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "Update_Compile_Point_Timing_Data" : false, + "Use_Clock_Period_for_Unconstrainted IO" : false, + "VCCAUX" : 3.3, + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_Sysv2017", + "WAKE_UP" : "0", + "Write_Vendor_Constraint_File" : true, + "dsp_balance" : false, + "show_all_warnings" : false, + "turn_off_bg" : false +} diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.cst b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.cst new file mode 100644 index 00000000..a3feafaa --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.cst @@ -0,0 +1,95 @@ +# The pin assignments +# All I/O pins here are 3.3V compatible unless specified otherwise + +IO_LOC "CLK" 52; + +IO_LOC "KEY[0]" 4; +IO_LOC "KEY[1]" 3; + +IO_LOC "LED[0]" 10; +IO_LOC "LED[1]" 11; +IO_LOC "LED[2]" 13; +IO_LOC "LED[3]" 14; +IO_LOC "LED[4]" 15; +IO_LOC "LED[5]" 16; + +IO_LOC "LARGE_LCD_DE" 33; +IO_LOC "LARGE_LCD_VS" 34; +IO_LOC "LARGE_LCD_HS" 40; +IO_LOC "LARGE_LCD_CK" 35; +IO_LOC "LARGE_LCD_INIT" 63; +IO_LOC "LARGE_LCD_BL" 86; + +IO_LOC "LARGE_LCD_R[3]" 75; +IO_LOC "LARGE_LCD_R[4]" 74; +IO_LOC "LARGE_LCD_R[5]" 73; +IO_LOC "LARGE_LCD_R[6]" 72; +IO_LOC "LARGE_LCD_R[7]" 71; + +IO_LOC "LARGE_LCD_G[2]" 70; +IO_LOC "LARGE_LCD_G[3]" 69; +IO_LOC "LARGE_LCD_G[4]" 68; +IO_LOC "LARGE_LCD_G[5]" 57; +IO_LOC "LARGE_LCD_G[6]" 56; +IO_LOC "LARGE_LCD_G[7]" 55; + +IO_LOC "LARGE_LCD_B[3]" 54; +IO_LOC "LARGE_LCD_B[4]" 53; +IO_LOC "LARGE_LCD_B[5]" 51; +IO_LOC "LARGE_LCD_B[6]" 42; +IO_LOC "LARGE_LCD_B[7]" 41; + +IO_LOC "UART_RX" 18; +IO_LOC "UART_TX" 17; + +# The following 4 pins (TF_CS, TF_MOSI, TF_SCLK, TF_MISO) +# are used for INMP441 microphone +# in basics-graphics-music labs + +IO_LOC "TF_CS" 38; # inmp441: lr +IO_LOC "TF_MOSI" 37; # inmp441: ws +IO_LOC "TF_SCLK" 36; # inmp441: sck +IO_LOC "TF_MISO" 39; # inmp441: sd + +# The first 3 GPIO pins are used for TM1638 I/O module +# which carries 8 LEDs, 8-digit 7-segment display and 8 keys + +IO_LOC "GPIO[0]" 25; # tm1638: sio_data +IO_LOC "GPIO[1]" 26; # tm1638: sio_clk +IO_LOC "GPIO[2]" 27; # tm1638: sio_stb +IO_LOC "GPIO[3]" 28; +IO_LOC "GPIO[4]" 29; +IO_LOC "GPIO[5]" 30; + +# The 4 pins SMALL_LCD_CLK, _CS, _RS and _DATA +# are used for the I2S audio output module PCM5102 +# in basics-graphics-music labs + +IO_LOC "SMALL_LCD_DATA" 77; # pcm5102: sck i2s_audio_out: mclk +IO_LOC "SMALL_LCD_CLK" 76; # pcm5102: bck i2s_audio_out: bclk +IO_LOC "SMALL_LCD_RESETN" 47; +IO_LOC "SMALL_LCD_CS" 48; # pcm5102: din i2s_audio_out: sdata +IO_LOC "SMALL_LCD_RS" 49; # pcm5102: lrck i2s_audio_out: lrclk + +# TMDS pins will be used later + +# IO_LOC "TMDS_CLK_P" 69,68; +# IO_LOC "TMDS_D_P[0]" 71,70; +# IO_LOC "TMDS_D_P[1]" 73,72; +# IO_LOC "TMDS_D_P[2]" 75,74; + +IO_LOC "FLASH_CLK" 59; +IO_LOC "FLASH_CSB" 60; +IO_LOC "FLASH_MOSI" 61; +IO_LOC "FLASH_MISO" 62; + +# The following pins are not used for the lab examples +# because they are 1.8V compatible + +# IO_LOC "GPIO_1_8_V_UNUSED[0]" 85; +# IO_LOC "GPIO_1_8_V_UNUSED[1]" 84; +# IO_LOC "GPIO_1_8_V_UNUSED[2]" 83; +# IO_LOC "GPIO_1_8_V_UNUSED[3]" 82; +# IO_LOC "GPIO_1_8_V_UNUSED[4]" 81; +# IO_LOC "GPIO_1_8_V_UNUSED[5]" 80; +# IO_LOC "GPIO_1_8_V_UNUSED[6]" 79; diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.sdc b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.sdc new file mode 100644 index 00000000..bf0aab16 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.sdc @@ -0,0 +1,4 @@ +# The timing constraints + +create_clock -name CLK -period 37.037 -waveform {0 18.518} [get_ports {CLK}] +create_clock -name LARGE_LCD_CK -period 111.11 -waveform {0 55.555} [get_ports {LARGE_LCD_CK}] diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.tcl b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.tcl new file mode 100644 index 00000000..794089f1 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.tcl @@ -0,0 +1,11 @@ +# Synthesis and Place & Route settings + +set_device GW1NR-LV9QN88PC6/I5 -name GW1NR-9 -device_version C + +set_option -synthesis_tool gowinsynthesis +set_option -output_base_name fpga_project +set_option -top_module board_specific_top +set_option -verilog_std sysv2017 + +set_option -use_mspi_as_gpio 1 +set_option -use_sspi_as_gpio 1 diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv new file mode 100644 index 00000000..65451d7c --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv @@ -0,0 +1,317 @@ +`include "config.svh" +`include "lab_specific_board_config.svh" + +`ifdef FORCE_NO_INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +`endif + +module board_specific_top +# ( + parameter clk_mhz = 27, + pixel_mhz = 9, + + w_key = 2, // The last key is used for a reset + w_sw = 0, + w_led = 6, + w_digit = 0, + w_gpio = 10, + + screen_width = 480, + screen_height = 272, + + w_red = 5, + w_green = 6, + w_blue = 5, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) +) +( + input CLK, + + input [w_key - 1:0] KEY, + + output [w_led - 1:0] LED, + + output LARGE_LCD_DE, + output LARGE_LCD_VS, + output LARGE_LCD_HS, + output LARGE_LCD_CK, + output LARGE_LCD_INIT, + output LARGE_LCD_BL, + + output [7:7 + 1 - w_red ] LARGE_LCD_R, + output [7:7 + 1 - w_green ] LARGE_LCD_G, + output [7:7 + 1 - w_blue ] LARGE_LCD_B, + + input UART_RX, + output UART_TX, + + // The following 4 pins (TF_CS, TF_MOSI, TF_SCLK, TF_MISO) + // are used for INMP441 microphone + // in basics-graphics-music labs + + inout TF_CS, + inout TF_MOSI, + inout TF_SCLK, + inout TF_MISO, + + inout [w_gpio - 1:0] GPIO, + + // The 4 pins SMALL_LCD_CLK, _CS, _RS and _DATA + // are used for the I2S audio output + // in basics-graphics-music labs + + inout SMALL_LCD_CLK, + inout SMALL_LCD_RESETN, + inout SMALL_LCD_CS, + inout SMALL_LCD_RS, + inout SMALL_LCD_DATA, + + // TMDS pins will be used later + + // output TMDS_CLK_N, + // output TMDS_CLK_P, + // output [ 2:0] TMDS_D_N, + // output [ 2:0] TMDS_D_P, + + output FLASH_CLK, + output FLASH_CSB, + output FLASH_MOSI, + input FLASH_MISO +); + + wire clk = CLK; + + //------------------------------------------------------------------------ + + localparam w_tm_key = 8, + w_tm_led = 8, + w_tm_digit = 8; + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; + + `else // TM1638 module is not connected + + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; + + `endif + + //------------------------------------------------------------------------ + + wire [w_tm_key - 1:0] tm_key; + wire [w_tm_led - 1:0] tm_led; + wire [w_tm_digit - 1:0] tm_digit; + + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; + + wire rst; + wire [ 7:0] abcdefgh; + + wire [w_x - 1:0] x; + wire [w_y - 1:0] y; + + wire [ 23:0] mic; + wire [ 15:0] sound; + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + assign rst = tm_key [w_tm_key - 1]; + assign lab_key = tm_key [w_tm_key - 1:0]; + + assign tm_led = lab_led; + assign tm_digit = lab_digit; + + assign LED = w_led' (~ lab_led); + + `else // TM1638 module is not connected + + assign rst = ~ KEY [w_key - 1]; + assign lab_key = ~ KEY [w_key - 1:0]; + + assign LED = ~ lab_led; + + `endif + + //------------------------------------------------------------------------ + + wire slow_clk; + + slow_clk_gen # (.fast_clk_mhz (clk_mhz), .slow_clk_hz (1)) + i_slow_clk_gen (.slow_clk (slow_clk), .*); + + //------------------------------------------------------------------------ + + wire [w_x - 1:0] mirrored_x = w_x' (screen_width - 1 - x); + wire [w_y - 1:0] mirrored_y = w_y' (screen_height - 1 - y); + + //------------------------------------------------------------------------ + + lab_top + # ( + .clk_mhz ( clk_mhz ), + + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_key ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) + ) + i_lab_top + ( + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), + + .key ( lab_key ), + .sw ( lab_key ), + + .led ( lab_led ), + + .abcdefgh ( abcdefgh ), + .digit ( lab_digit ), + + .x ( mirrored_x ), + .y ( mirrored_y ), + + .red ( LARGE_LCD_R ), + .green ( LARGE_LCD_G ), + .blue ( LARGE_LCD_B ), + + .uart_rx ( UART_RX ), + .uart_tx ( UART_TX ), + + .mic ( mic ), + .sound ( sound ), + .gpio ( gpio ) + ); + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + wire [$left (abcdefgh):0] hgfedcba; + + generate + genvar i; + + for (i = 0; i < $bits (abcdefgh); i ++) + begin : abc + assign hgfedcba [i] = abcdefgh [$left (abcdefgh) - i]; + end + endgenerate + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + tm1638_board_controller + # ( + .clk_mhz ( clk_mhz ), + .w_digit ( w_tm_digit ) + ) + i_tm1638 + ( + .clk ( clk ), + .rst ( rst ), + .hgfedcba ( hgfedcba ), + .digit ( tm_digit ), + .ledr ( tm_led ), + .keys ( tm_key ), + .sio_data ( GPIO [0] ), + .sio_clk ( GPIO [1] ), + .sio_stb ( GPIO [2] ) + ); + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + Gowin_rPLL i_Gowin_rPLL + ( + .clkout ( LARGE_LCD_CK ), // 9 MHz + .clkin ( clk ) // 27 MHz + ); + + lcd_480_272 + ( + .PixelClk ( LARGE_LCD_CK ), + .nRST ( ~ rst ), + + .LCD_DE ( LARGE_LCD_DE ), + .LCD_HSYNC ( LARGE_LCD_HS ), + .LCD_VSYNC ( LARGE_LCD_VS ), + + .x ( x ), + .y ( y ) + ); + + assign LARGE_LCD_INIT = 1'b0; + assign LARGE_LCD_BL = 1'b0; + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE + + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( TF_CS ), + .ws ( TF_MOSI ), + .sck ( TF_SCLK ), + .sd ( TF_MISO ), + .value ( mic ) + ); + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( SMALL_LCD_DATA ), + .bclk ( SMALL_LCD_CLK ), + .lrclk ( SMALL_LCD_RS ), + .sdata ( SMALL_LCD_CS ) + ); + + `endif + +endmodule diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_01.gprj b/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_01.gprj new file mode 100644 index 00000000..79b1311f --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_01.gprj @@ -0,0 +1,7 @@ + + + + + 5 + gw1nr9c-004 + diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_02.gprj b/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_02.gprj new file mode 100644 index 00000000..8c6b9904 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_02.gprj @@ -0,0 +1,2 @@ + + diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.ipc b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.ipc new file mode 100644 index 00000000..bf8c92d9 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.ipc @@ -0,0 +1,24 @@ +[General] +ipc_version=4 +file=gowin_rpll +module=Gowin_rPLL +target_device=gw1nr9c-004 +type=clock_rpll +version=1.0 + +[Config] +CKLOUTD3=false +CLKFB_SOURCE=0 +CLKIN_FREQ=27 +CLKOUTD=false +CLKOUTP=false +CLKOUT_BYPASS=false +CLKOUT_DIVIDE_DYN=true +CLKOUT_FREQ=9 +CLKOUT_TOLERANCE=0 +DYNAMIC=true +LANG=0 +LOCK_EN=false +MODE_GENERAL=true +PLL_PWD=false +RESET_PLL=false diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.mod b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.mod new file mode 100644 index 00000000..39dc975c --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.mod @@ -0,0 +1,32 @@ +-series GW1NR +-device GW1NR-9C +-package QFN88P +-part_number GW1NR-LV9QN88PC6/I5 + + +-mod_name Gowin_rPLL +-file_name gowin_rpll +-path Y:/4.3inch_screen/lcd_led/src/gowin_rpll/ +-type PLL +-rPll true +-file_type vlg +-dev_type GW1NR-9C +-dyn_idiv_sel false +-idiv_sel 3 +-dyn_fbdiv_sel false +-fbdiv_sel 1 +-dyn_odiv_sel false +-odiv_sel 48 +-dyn_da_en true +-rst_sig false +-rst_sig_p false +-fclkin 27 +-clkfb_sel 0 +-en_lock false +-clkout_bypass false +-clkout_ft_dir 1 +-en_clkoutp false +-clkoutp_bypass false +-en_clkoutd false +-clkoutd_bypass false +-en_clkoutd3 false \ No newline at end of file diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.v b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.v new file mode 100644 index 00000000..95f15287 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.v @@ -0,0 +1,63 @@ +//Copyright (C)2014-2022 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: IP file +//GOWIN Version: V1.9.8.09 +//Part Number: GW1NR-LV9QN88PC6/I5 +//Device: GW1NR-9C +//Created Time: Tue Mar 21 12:46:45 2023 + +module Gowin_rPLL (clkout, clkin); + +output clkout; +input clkin; + +wire lock_o; +wire clkoutp_o; +wire clkoutd_o; +wire clkoutd3_o; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +rPLL rpll_inst ( + .CLKOUT(clkout), + .LOCK(lock_o), + .CLKOUTP(clkoutp_o), + .CLKOUTD(clkoutd_o), + .CLKOUTD3(clkoutd3_o), + .RESET(gw_gnd), + .RESET_P(gw_gnd), + .CLKIN(clkin), + .CLKFB(gw_gnd), + .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) +); + +defparam rpll_inst.FCLKIN = "27"; +defparam rpll_inst.DYN_IDIV_SEL = "false"; +defparam rpll_inst.IDIV_SEL = 2; +defparam rpll_inst.DYN_FBDIV_SEL = "false"; +defparam rpll_inst.FBDIV_SEL = 0; +defparam rpll_inst.DYN_ODIV_SEL = "false"; +defparam rpll_inst.ODIV_SEL = 48; +defparam rpll_inst.PSDA_SEL = "0000"; +defparam rpll_inst.DYN_DA_EN = "true"; +defparam rpll_inst.DUTYDA_SEL = "1000"; +defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUT_DLY_STEP = 0; +defparam rpll_inst.CLKOUTP_DLY_STEP = 0; +defparam rpll_inst.CLKFB_SEL = "internal"; +defparam rpll_inst.CLKOUT_BYPASS = "false"; +defparam rpll_inst.CLKOUTP_BYPASS = "false"; +defparam rpll_inst.CLKOUTD_BYPASS = "false"; +defparam rpll_inst.DYN_SDIV_SEL = 2; +defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; +defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; +defparam rpll_inst.DEVICE = "GW1NR-9C"; + +endmodule //Gowin_rPLL diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_01.json b/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_01.json new file mode 100644 index 00000000..8b6c52aa --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_01.json @@ -0,0 +1,32 @@ +{ + "Allow_Duplicate_Modules" : false, + "Annotated_Properties_for_Analyst" : true, + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CRC_CHECK" : true, + "Clock_Conversion" : true, + "Clock_Route_Order" : 0, + "Correct_Hold_Violation" : true, + "DONE" : true, + "DOWNLOAD_SPEED" : "default", + "Default_Enum_Encoding" : "default", + "Disable_Insert_Pad" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "FORMAT" : "binary", + "FSM Compiler" : true, + "Fanout_Guide" : 10000, + "Frequency" : "Auto", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "Implicit_Initial_Value_Support" : false, + "IncludePath" : [ diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_02.json b/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_02.json new file mode 100644 index 00000000..a861fbcd --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_02.json @@ -0,0 +1,53 @@ + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "Multiple_File_Compilation_Unit" : true, + "Number_of_Critical_Paths" : "", + "Number_of_Start/End_Points" : "", + "OUTPUT_BASE_NAME" : "fpga_project", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "Pipelining" : true, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "Push_Tristates" : true, + "READY" : true, + "RECONFIG_N" : false, + "Ram_RW_Check" : true, + "Report_Auto-Placed_Io_Information" : false, + "Resolve_Mixed_Drivers" : false, + "Resource_Sharing" : true, + "Retiming" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SPI_FLASH_ADDR" : "00000000", + "SSPI" : true, + "Show_All_Warnings" : false, + "Synthesis On/Off Implemented as Translate On/Off" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "board_specific_top", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "Update_Compile_Point_Timing_Data" : false, + "Use_Clock_Period_for_Unconstrainted IO" : false, + "VCCAUX" : 3.3, + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_Sysv2017", + "WAKE_UP" : "0", + "Write_Vendor_Constraint_File" : true, + "dsp_balance" : false, + "show_all_warnings" : false, + "turn_off_bg" : false +} diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index fce17aba..86993a1c 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -37,19 +37,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -59,10 +59,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + logic [w_lab_sw - 1:0] lab_sw; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -77,22 +77,22 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_key = tm_key [w_tm_key - 1:0]; + assign lab_sw = ~ SW; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_key = ~ KEY [w_key - 1:0]; + assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -105,28 +105,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_primer_20k_dock_alt/board_specific.cst b/boards/tang_primer_20k_dock_alt/board_specific.cst index 5eeb82cb..472cbfd0 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific.cst +++ b/boards/tang_primer_20k_dock_alt/board_specific.cst @@ -137,8 +137,8 @@ IO_PORT "GPIO_0[1]" IO_TYPE=LVCMOS33; IO_LOC "GPIO_0[0]" T6; IO_PORT "GPIO_0[0]" IO_TYPE=LVCMOS33; -// HDMI Output -IO_LOC "tmds_d_p[0]" H14,H16; -IO_LOC "tmds_d_p[1]" J15,K16; -IO_LOC "tmds_d_p[2]" K14,K15; -IO_LOC "tmds_clk_p" G16,H15; +// HDMI Output +IO_LOC "tmds_d_p[0]" H14,H16; +IO_LOC "tmds_d_p[1]" J15,K16; +IO_LOC "tmds_d_p[2]" K14,K15; +IO_LOC "tmds_clk_p" G16,H15; diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index cea05441..b2c22996 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -1,12 +1,12 @@ `include "config.svh" -`include "lab_specific_config.svh" - -// `define ENABLE_VGA16 -// `define ENABLE_VGA666 - `undef ENABLE_VGA16 - `define ENABLE_HDMI - -`undef ENABLE_TM1638 +`include "lab_specific_board_config.svh" + +// `define ENABLE_VGA16 +// `define ENABLE_VGA666 + `undef ENABLE_VGA16 + `define ENABLE_HDMI + +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( @@ -29,16 +29,16 @@ module board_specific_top output [w_led - 1:0] LED, inout [w_gpio / 4 - 1:0] GPIO_0, - inout [w_gpio / 4 - 1:0] GPIO_1, + inout [w_gpio / 4 - 1:0] GPIO_1, inout [w_gpio / 4 - 1:0] GPIO_2, - inout [w_gpio / 4 - 1:0] GPIO_3 - + inout [w_gpio / 4 - 1:0] GPIO_3 + `ifdef ENABLE_HDMI - , output tmds_clk_n - , output tmds_clk_p - , output [ 2:0] tmds_d_n - , output [ 2:0] tmds_d_p -`endif + , output tmds_clk_n + , output tmds_clk_p + , output [ 2:0] tmds_d_n + , output [ 2:0] tmds_d_p +`endif ); wire clk = CLK; @@ -51,115 +51,115 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif //------------------------------------------------------------------------ - `ifdef ENABLE_VGA16 - localparam w_top_red = 5, - w_top_green = 6, - w_top_blue = 5; - `elsif ENABLE_VGA666 - localparam w_top_red = 6, - w_top_green = 6, - w_top_blue = 6; - `elsif ENABLE_HDMI - localparam vid_clk_mhz = 125, - w_top_red = 8, - w_top_green = 8, - w_top_blue = 8; - `else - localparam w_top_red = 4, - w_top_green = 4, - w_top_blue = 4; - `endif - - //------------------------------------------------------------------------ - + `ifdef ENABLE_VGA16 + localparam w_lab_red = 5, + w_lab_green = 6, + w_lab_blue = 5; + `elsif ENABLE_VGA666 + localparam w_lab_red = 6, + w_lab_green = 6, + w_lab_blue = 6; + `elsif ENABLE_HDMI + localparam vid_clk_mhz = 125, + w_lab_red = 8, + w_lab_green = 8, + w_lab_blue = 8; + `else + localparam w_lab_red = 4, + w_lab_green = 4, + w_lab_blue = 4; + `endif + + //------------------------------------------------------------------------ + wire [w_tm_key - 1:0] tm_key; wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + logic [w_lab_sw - 1:0] lab_sw; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; wire [ 23:0] mic; - //------------------------------------------------------------------------ - - wire clk_hdl; - wire clk_hd; - wire clk_px; - wire pll_lock; - wire sys_resetn; - wire display_on; - + //------------------------------------------------------------------------ + + wire clk_hdl; + wire clk_hd; + wire clk_px; + wire pll_lock; + wire sys_resetn; + wire display_on; + wire VGA_HS; wire VGA_VS; - logic [ w_top_red - 1:0] VGA_R; - logic [ w_top_green - 1:0] VGA_G; - logic [ w_top_blue - 1:0] VGA_B; + logic [ w_lab_red - 1:0] VGA_R; + logic [ w_lab_green - 1:0] VGA_G; + logic [ w_lab_blue - 1:0] VGA_B; //------------------------------------------------------------------------ - - `ifdef ENABLE_HDMI - BUFG clHD(.I(clk_hdl), .O(clk_hd)); - - Gowin_rPLL hdPLL( - .clkout( clk_hdl ), //output clkout - .clkin ( clk ), //input clkin - .lock ( pll_lock ) - ); - `endif - //------------------------------------------------------------------------ - - `ifdef ENABLE_TM1638 // TM1638 module is connected - - `ifdef ENABLE_HDMI - assign rst = ~ ( ~tm_key[w_tm_key - 1] & pll_lock ); - `else - assign rst = tm_key [w_tm_key - 1]; - `endif - assign top_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; - - assign tm_led = top_led; - assign tm_digit = top_digit; + + `ifdef ENABLE_HDMI + BUFG clHD(.I(clk_hdl), .O(clk_hd)); + + Gowin_rPLL hdPLL( + .clkout( clk_hdl ), //output clkout + .clkin ( clk ), //input clkin + .lock ( pll_lock ) + ); + `endif + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + `ifdef ENABLE_HDMI + assign rst = ~ ( ~tm_key[w_tm_key - 1] & pll_lock ); + `else + assign rst = tm_key [w_tm_key - 1]; + `endif + assign lab_key = tm_key [w_tm_key - 1:0]; + assign lab_sw = ~ SW; + + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected - `ifdef ENABLE_HDMI - assign rst = ~ ( KEY[w_key - 1] & pll_lock ); - `else - assign rst = ~KEY[w_key - 1]; - `endif - assign top_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + `ifdef ENABLE_HDMI + assign rst = ~ ( KEY[w_key - 1] & pll_lock ); + `else + assign rst = ~KEY[w_key - 1]; + `endif + assign lab_key = ~ KEY [w_key - 1:0]; + assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif - //------------------------------------------------------------------------ + //------------------------------------------------------------------------ wire slow_clk; @@ -168,47 +168,47 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( -`ifdef ENABLE_HDMI - .clk_mhz ( vid_clk_mhz ), -`else - .clk_mhz ( clk_mhz ), -`endif - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), - .w_gpio ( w_gpio ), - .w_red ( w_top_red ), - .w_green ( w_top_green ), - .w_blue ( w_top_blue ) +`ifdef ENABLE_HDMI + .clk_mhz ( vid_clk_mhz ), +`else + .clk_mhz ( clk_mhz ), +`endif + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), + .w_gpio ( w_gpio ), + .w_red ( w_lab_red ), + .w_green ( w_lab_green ), + .w_blue ( w_lab_blue ) ) - i_top - ( -`ifdef ENABLE_HDMI - .clk ( clk_hd ), + i_lab_top + ( +`ifdef ENABLE_HDMI + .clk ( clk_hd ), `else - .clk ( clk ), + .clk ( clk ), `endif .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), .red ( VGA_R ), .green ( VGA_G ), - .blue ( VGA_B ), - .display_on( display_on ), + .blue ( VGA_B ), + .display_on( display_on ), .pixel_clk ( clk_px ), .uart_rx ( UART_RX ), @@ -268,40 +268,40 @@ module board_specific_top // assign GPIO_3 = {VGA_B, VGA_R}; // assign GPIO_2 = {VGA_HS, VGA_VS, 2'bz, VGA_G}; - `ifdef ENABLE_VGA16 - - assign GPIO_3 = {2'bz, VGA_R[3], VGA_R[1], 2'bz, VGA_R[4], VGA_R[2]}; - assign GPIO_2 = {VGA_G[5], VGA_G[3], VGA_G[1], VGA_B[4], VGA_R[0], VGA_G[4], VGA_G[2], VGA_G[0]}; - assign GPIO_1 = {VGA_B[2], VGA_B[0], VGA_HS, 1'bz, VGA_B[3], VGA_B[1], VGA_VS, 1'bz}; - - `elsif ENABLE_VGA666 - - assign GPIO_3 = { VGA_G[4], VGA_G[5], VGA_R[2], VGA_B[4], VGA_VS, VGA_HS, VGA_B[0], VGA_R[1] }; - assign GPIO_2 = { VGA_B[3], VGA_G[2], VGA_R[0], VGA_R[4], VGA_G[0], VGA_B[5], VGA_G[1], VGA_B[1] }; - assign GPIO_1 = { VGA_R[5], 3'bz, VGA_B[2], VGA_G[3], VGA_R[3], 1'bz }; - - `elsif ENABLE_HDMI - DVI_TX_Top myDVI( - .I_rst_n ( ~rst ), //input I_rst_n - .I_serial_clk ( clk_hd ), //input I_serial_clk - .I_rgb_clk ( clk_px ), //input I_rgb_clk - .I_rgb_vs ( ~VGA_VS ), //input I_rgb_vs - .I_rgb_hs ( ~VGA_HS ), //input I_rgb_hs - .I_rgb_de ( display_on ), //input I_rgb_de - .I_rgb_r ( VGA_R ), //input [7:0] I_rgb_r - .I_rgb_g ( VGA_G ), //input [7:0] I_rgb_g - .I_rgb_b ( VGA_B ), //input [7:0] I_rgb_b - .O_tmds_clk_p ( tmds_clk_p ), //output O_tmds_clk_p - .O_tmds_clk_n ( tmds_clk_n ), //output O_tmds_clk_n - .O_tmds_data_p( tmds_d_p ), //output [2:0] O_tmds_data_p - .O_tmds_data_n( tmds_d_n ) //output [2:0] O_tmds_data_n - ); - - `else - - assign GPIO_2 = { VGA_B, VGA_R }; - assign GPIO_3 = { 2'bz, VGA_VS, VGA_HS, VGA_G }; - - `endif + `ifdef ENABLE_VGA16 + + assign GPIO_3 = {2'bz, VGA_R[3], VGA_R[1], 2'bz, VGA_R[4], VGA_R[2]}; + assign GPIO_2 = {VGA_G[5], VGA_G[3], VGA_G[1], VGA_B[4], VGA_R[0], VGA_G[4], VGA_G[2], VGA_G[0]}; + assign GPIO_1 = {VGA_B[2], VGA_B[0], VGA_HS, 1'bz, VGA_B[3], VGA_B[1], VGA_VS, 1'bz}; + + `elsif ENABLE_VGA666 + + assign GPIO_3 = { VGA_G[4], VGA_G[5], VGA_R[2], VGA_B[4], VGA_VS, VGA_HS, VGA_B[0], VGA_R[1] }; + assign GPIO_2 = { VGA_B[3], VGA_G[2], VGA_R[0], VGA_R[4], VGA_G[0], VGA_B[5], VGA_G[1], VGA_B[1] }; + assign GPIO_1 = { VGA_R[5], 3'bz, VGA_B[2], VGA_G[3], VGA_R[3], 1'bz }; + + `elsif ENABLE_HDMI + DVI_TX_Top myDVI( + .I_rst_n ( ~rst ), //input I_rst_n + .I_serial_clk ( clk_hd ), //input I_serial_clk + .I_rgb_clk ( clk_px ), //input I_rgb_clk + .I_rgb_vs ( ~VGA_VS ), //input I_rgb_vs + .I_rgb_hs ( ~VGA_HS ), //input I_rgb_hs + .I_rgb_de ( display_on ), //input I_rgb_de + .I_rgb_r ( VGA_R ), //input [7:0] I_rgb_r + .I_rgb_g ( VGA_G ), //input [7:0] I_rgb_g + .I_rgb_b ( VGA_B ), //input [7:0] I_rgb_b + .O_tmds_clk_p ( tmds_clk_p ), //output O_tmds_clk_p + .O_tmds_clk_n ( tmds_clk_n ), //output O_tmds_clk_n + .O_tmds_data_p( tmds_d_p ), //output [2:0] O_tmds_data_p + .O_tmds_data_n( tmds_d_n ) //output [2:0] O_tmds_data_n + ); + + `else + + assign GPIO_2 = { VGA_B, VGA_R }; + assign GPIO_3 = { 2'bz, VGA_VS, VGA_HS, VGA_G }; + + `endif endmodule diff --git a/boards/tang_primer_20k_dock_alt/dvi_tx.ipc b/boards/tang_primer_20k_dock_alt/dvi_tx.ipc index 49ace32f..64143584 100644 --- a/boards/tang_primer_20k_dock_alt/dvi_tx.ipc +++ b/boards/tang_primer_20k_dock_alt/dvi_tx.ipc @@ -1,16 +1,16 @@ -[General] -ipc_version=4 -file=dvi_tx -module=DVI_TX_Top -target_device=gw2a18c-011 -type=dvi_tx -version=1.0 - -[Config] -DISABLE_IO_INSERTION=true -ELVDS=true -LANG=0 -RX_CLOCK_IN_FREQUENCY=40 -Synthesis_tool=GowinSynthesis -TLVDS=false -USING_EXTERNAL_CLOCK=true +[General] +ipc_version=4 +file=dvi_tx +module=DVI_TX_Top +target_device=gw2a18c-011 +type=dvi_tx +version=1.0 + +[Config] +DISABLE_IO_INSERTION=true +ELVDS=true +LANG=0 +RX_CLOCK_IN_FREQUENCY=40 +Synthesis_tool=GowinSynthesis +TLVDS=false +USING_EXTERNAL_CLOCK=true diff --git a/boards/tang_primer_20k_dock_alt/dvi_tx.v b/boards/tang_primer_20k_dock_alt/dvi_tx.v index 27647424..309f3a61 100644 --- a/boards/tang_primer_20k_dock_alt/dvi_tx.v +++ b/boards/tang_primer_20k_dock_alt/dvi_tx.v @@ -1,1125 +1,1125 @@ -// -//Written by GowinSynthesis -//Tool Version "V1.9.9.03 (64-bit)" -//Sun Jun 2 18:05:56 2024 - -//Source file index table: -//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/DVI_TX/data/dvi_tx_top.v" -//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/DVI_TX/data/rgb2dvi.v" -`timescale 100 ps/100 ps -`pragma protect begin_protected -`pragma protect version="2.3" -`pragma protect author="default" -`pragma protect author_info="default" -`pragma protect encrypt_agent="GOWIN" -`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3" - -`pragma protect encoding=(enctype="base64", line_length=76, bytes=256) -`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa" -`pragma protect key_block -al6vro4MZ1BEEUNKHyex8TrSQas6QVBVJhpXhBzRnuZuJ7JEmoYoEOcD8cbwqnxILAMligQh8clz -2kiaBde0ZVKCbjqACyNEd4iWaSBHjcT71leNC8k2hdxWGqdY4iaMTueebLuGJ5M+Viob6yxFbSy9 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O_tmds_clk_n, - O_tmds_data_p, - O_tmds_data_n -) -; -input I_rst_n; -input I_serial_clk; -input I_rgb_clk; -input I_rgb_vs; -input I_rgb_hs; -input I_rgb_de; -input [7:0] I_rgb_r; -input [7:0] I_rgb_g; -input [7:0] I_rgb_b; -output O_tmds_clk_p; -output O_tmds_clk_n; -output [2:0] O_tmds_data_p; -output [2:0] O_tmds_data_n; -wire VCC; -wire GND; - \~rgb2dvi.DVI_TX_Top rgb2dvi_inst ( - .I_rgb_clk(I_rgb_clk), - .I_serial_clk(I_serial_clk), - .I_rst_n(I_rst_n), - .I_rgb_de(I_rgb_de), - .I_rgb_vs(I_rgb_vs), - .I_rgb_hs(I_rgb_hs), - .I_rgb_r(I_rgb_r[7:0]), - .I_rgb_g(I_rgb_g[7:0]), - .I_rgb_b(I_rgb_b[7:0]), - .O_tmds_clk_p(O_tmds_clk_p), - .O_tmds_clk_n(O_tmds_clk_n), - .O_tmds_data_p(O_tmds_data_p[2:0]), - .O_tmds_data_n(O_tmds_data_n[2:0]) -); - VCC VCC_cZ ( - .V(VCC) -); - GND GND_cZ ( - .G(GND) -); - GSR GSR ( - .GSRI(VCC) -); -endmodule /* DVI_TX_Top */ +// +//Written by GowinSynthesis +//Tool Version "V1.9.9.03 (64-bit)" +//Sun Jun 2 18:05:56 2024 + +//Source file index table: +//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/DVI_TX/data/dvi_tx_top.v" +//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/DVI_TX/data/rgb2dvi.v" +`timescale 100 ps/100 ps +`pragma protect begin_protected +`pragma protect version="2.3" +`pragma protect author="default" +`pragma protect author_info="default" +`pragma protect encrypt_agent="GOWIN" +`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3" + +`pragma protect encoding=(enctype="base64", line_length=76, bytes=256) +`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa" +`pragma protect key_block +al6vro4MZ1BEEUNKHyex8TrSQas6QVBVJhpXhBzRnuZuJ7JEmoYoEOcD8cbwqnxILAMligQh8clz +2kiaBde0ZVKCbjqACyNEd4iWaSBHjcT71leNC8k2hdxWGqdY4iaMTueebLuGJ5M+Viob6yxFbSy9 +KGCeEveTSZKM1/Gb9ek+8QKTcMAKRtcMBKMPQHjVqo/yjDY9NpcOXHSfI31n+TDaXM6hydDiqGAJ +W97xt0kpzA2DkVaMBPMUgPLfN4gKjQg9N1bbKmErZlJb4whyOHJ54/yQ73zzPg0eIh4+AKMVsJPJ +sWLq4+YqxepTedSeZ970LDAZOjW6eBcboG6lrQ== + +`pragma protect encoding=(enctype="base64", line_length=76, bytes=59136) +`pragma protect data_keyowner="default-ip-vendor" +`pragma protect data_keyname="default-ip-key" +`pragma protect data_method="aes128-cfb" +`pragma protect data_block +7mTxKdQOH2ImYodBh4aGPvmLSPzEmKXRBXSYQ9zPW6+7Z2k2FXkL+shomy8FZ7P+pc2JOHqB9uWz +AcQ3dC0ecQBG62bHoiZNBGta1FYuLUprDVdvx0TfDkMmOmGQbSYH97knQTkP1SIf9mnplrAaA3Q7 +qEDggvlp4CgAxLc3ggXlcgykaKEWcSNJDtIlU8OQVbuzkFN5pVUmTtyLrjJAI5FVglcLoZb3iZuw +/So1tdvJBe2id2j+7zozWMr+j7PFFPrgVMQELSvE2RAzWosz3RFZ21p/D9fyiux2+YpykSeaEG+C +fkSsx7jvN7PV9aOWYNotDszh9b9VbRovfEZ4jGyRQA/6yVnGzZF/SEmiwnzEeiyzGdCalIeVw6S1 +zDaM4U2mPvfRdBMI+tB0GtvwBKcHKbL5NXg0Z6NIDnUaHv1jxY9zMGH2Tly9Fp3sczrLmezbPlNw +wWutlIbbaPxFR6/Cc6//2SSgJ7EBNp0TWoTsMKPX+fHJV368kV9qCMLZuCtkwIn9gQhNLKhw3Fnf +A9TQgcD7ZevV5PL27J4uiDoyF3OoczHx0aaIHCeoTWPx19eBqsv8TkeLh3a8+p630YFcJ+65Pvi0 +exAExkq2NiQQg3ZpkvvDJv6wKTx5y2nF5cJ2KFI7tGgA9qSJFiOqC1LqBSzmhMyMFIokhFoykfKR +tVCmaatxqCc+FgA3HECIW9m0biw5H03JnmIH+/Cy6zGnX6I9iGnI1ojfhTUHd01t3KneYLqKsHiB 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+EZEBNnPBGXIStBRcDzfU6l+XSVIK1c3T6kQXd8PveY4tBwE8eZpRi7cK5uUXSdMz14qpMYwx4mV6 +58miGzBSk2a7wwEbYbL2ExVJAE1Ss5N0IkWIsxxp4dy+uePWlU0g4Uas+RMtD88QRL6KWYaCrJ9L +sW3hMuzCotooRSMs5vGx1ix7HkVb2koJ8hHXY1I6WzYZA6lp1K2PafQMupyRYlhvcgm6hKIK3TCx +H9f/hp5QaP+CaBLudEEQx52aet/8C6fyrbMHynKiuXCiLi1riO4QibEhPbcACpCGJxV8xIHkvXAy +Cn8Y+lQ4s7LSoKkOwOioqHt+/Pp2l34Ns5jxc/My3wEYHAmlaNiHcFiRjp260N7bnLmF1O4ZpwzE +YEYGSfsGBcFPF2Yjfmwa4Xy2LHAtCQFA0P0AsuFvFbxXqHdzu23efWGKs3n3FRXABTDwudGn3+Is +WvOxnqnh8i9rukrMDDZ3L+Fs9sKlL4tx0kQEZ9QIoAZipJlemjLjNzjtdEcCmf1GmgXSoEnqNx++ +NrCri52I5cnHYFJqSNibbjT9rnNVzlZqVxGh +`pragma protect end_protected +module DVI_TX_Top ( + I_rst_n, + I_serial_clk, + I_rgb_clk, + I_rgb_vs, + I_rgb_hs, + I_rgb_de, + I_rgb_r, + I_rgb_g, + I_rgb_b, + O_tmds_clk_p, + O_tmds_clk_n, + O_tmds_data_p, + O_tmds_data_n +) +; +input I_rst_n; +input I_serial_clk; +input I_rgb_clk; +input I_rgb_vs; +input I_rgb_hs; +input I_rgb_de; +input [7:0] I_rgb_r; +input [7:0] I_rgb_g; +input [7:0] I_rgb_b; +output O_tmds_clk_p; +output O_tmds_clk_n; +output [2:0] O_tmds_data_p; +output [2:0] O_tmds_data_n; +wire VCC; +wire GND; + \~rgb2dvi.DVI_TX_Top rgb2dvi_inst ( + .I_rgb_clk(I_rgb_clk), + .I_serial_clk(I_serial_clk), + .I_rst_n(I_rst_n), + .I_rgb_de(I_rgb_de), + .I_rgb_vs(I_rgb_vs), + .I_rgb_hs(I_rgb_hs), + .I_rgb_r(I_rgb_r[7:0]), + .I_rgb_g(I_rgb_g[7:0]), + .I_rgb_b(I_rgb_b[7:0]), + .O_tmds_clk_p(O_tmds_clk_p), + .O_tmds_clk_n(O_tmds_clk_n), + .O_tmds_data_p(O_tmds_data_p[2:0]), + .O_tmds_data_n(O_tmds_data_n[2:0]) +); + VCC VCC_cZ ( + .V(VCC) +); + GND GND_cZ ( + .G(GND) +); + GSR GSR ( + .GSRI(VCC) +); +endmodule /* DVI_TX_Top */ diff --git a/boards/tang_primer_20k_dock_alt/dvi_tx.vo b/boards/tang_primer_20k_dock_alt/dvi_tx.vo index 94258cc1..0fded162 100644 --- a/boards/tang_primer_20k_dock_alt/dvi_tx.vo +++ b/boards/tang_primer_20k_dock_alt/dvi_tx.vo @@ -1,3369 +1,3369 @@ -//Copyright (C)2014-2024 Gowin Semiconductor Corporation. -//All rights reserved. -//File Title: Post-PnR Simulation Model file -//Tool Version: V1.9.9.03 (64-bit) -//Created Time: Sun Jun 2 18:05:57 2024 - -`timescale 100 ps/100 ps -module DVI_TX_Top( - I_rst_n, - I_serial_clk, - I_rgb_clk, - I_rgb_vs, - I_rgb_hs, - I_rgb_de, - I_rgb_r, - I_rgb_g, - I_rgb_b, - O_tmds_clk_p, - O_tmds_clk_n, - O_tmds_data_p, - O_tmds_data_n -); -input I_rst_n; -input I_serial_clk; -input I_rgb_clk; -input I_rgb_vs; -input I_rgb_hs; -input I_rgb_de; -input [7:0] I_rgb_r; -input [7:0] I_rgb_g; -input [7:0] I_rgb_b; -output O_tmds_clk_p; -output O_tmds_clk_n; -output [2:0] O_tmds_data_p; -output [2:0] O_tmds_data_n; -wire GND; -wire [7:0] I_rgb_b; -wire I_rgb_clk; -wire I_rgb_de; -wire [7:0] I_rgb_g; -wire I_rgb_hs; -wire [7:0] I_rgb_r; -wire I_rgb_vs; -wire I_rst_n; -wire I_serial_clk; -wire O_tmds_clk_n; -wire O_tmds_clk_p; -wire [2:0] O_tmds_data_n; -wire [2:0] O_tmds_data_p; -wire VCC; -wire \rgb2dvi_inst/sdataout_r ; -wire \rgb2dvi_inst/sdataout_g ; -wire \rgb2dvi_inst/sdataout_b ; -wire \rgb2dvi_inst/sdataout_clk ; -wire \rgb2dvi_inst/n36_6 ; -wire \rgb2dvi_inst/de_d ; -wire \rgb2dvi_inst/c1_d ; -wire [9:0] \rgb2dvi_inst/q_out_r ; -wire [9:0] \rgb2dvi_inst/q_out_g ; -wire [9:0] \rgb2dvi_inst/q_out_b ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n132_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_1_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n364_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n236_5_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ; -wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit ; -wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_r/din_d ; -wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_r/cnt ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n132_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_1_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n364_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n236_5_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ; -wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit ; -wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_g/din_d ; -wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_g/cnt ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n132_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_1_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n364_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n236_5_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ; -wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit ; -wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_b/din_d ; -wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_b/cnt ; -VCC VCC_cZ ( - .V(VCC) -); -GND GND_cZ ( - .G(GND) -); -GSR GSR ( - .GSRI(VCC) -); -ELVDS_OBUF \rgb2dvi_inst/u_LVDS_r ( - .I(\rgb2dvi_inst/sdataout_r ), - .O(O_tmds_data_p[2]), - .OB(O_tmds_data_n[2]) -); -ELVDS_OBUF \rgb2dvi_inst/u_LVDS_g ( - .I(\rgb2dvi_inst/sdataout_g ), - .O(O_tmds_data_p[1]), - .OB(O_tmds_data_n[1]) -); -ELVDS_OBUF \rgb2dvi_inst/u_LVDS_b ( - .I(\rgb2dvi_inst/sdataout_b ), - .O(O_tmds_data_p[0]), - .OB(O_tmds_data_n[0]) -); -ELVDS_OBUF \rgb2dvi_inst/u_LVDS_clk ( - .I(\rgb2dvi_inst/sdataout_clk ), - .O(O_tmds_clk_p), - .OB(O_tmds_clk_n) -); -OSER10 \rgb2dvi_inst/u_OSER10_r ( - .D0(\rgb2dvi_inst/q_out_r [0]), - .D1(\rgb2dvi_inst/q_out_r [1]), - .D2(\rgb2dvi_inst/q_out_r [2]), - .D3(\rgb2dvi_inst/q_out_r [3]), - .D4(\rgb2dvi_inst/q_out_r [4]), - .D5(\rgb2dvi_inst/q_out_r [5]), - .D6(\rgb2dvi_inst/q_out_r [6]), - .D7(\rgb2dvi_inst/q_out_r [7]), - .D8(\rgb2dvi_inst/q_out_r [8]), - .D9(\rgb2dvi_inst/q_out_r [9]), - .PCLK(I_rgb_clk), - .FCLK(I_serial_clk), - .RESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/sdataout_r ) -); -defparam \rgb2dvi_inst/u_OSER10_r .GSREN="false"; -defparam \rgb2dvi_inst/u_OSER10_r .LSREN="true"; -OSER10 \rgb2dvi_inst/u_OSER10_g ( - .D0(\rgb2dvi_inst/q_out_g [0]), - .D1(\rgb2dvi_inst/q_out_g [1]), - .D2(\rgb2dvi_inst/q_out_g [2]), - .D3(\rgb2dvi_inst/q_out_g [3]), - .D4(\rgb2dvi_inst/q_out_g [4]), - .D5(\rgb2dvi_inst/q_out_g [5]), - .D6(\rgb2dvi_inst/q_out_g [6]), - .D7(\rgb2dvi_inst/q_out_g [7]), - .D8(\rgb2dvi_inst/q_out_g [8]), - .D9(\rgb2dvi_inst/q_out_g [9]), - .PCLK(I_rgb_clk), - .FCLK(I_serial_clk), - .RESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/sdataout_g ) -); -defparam \rgb2dvi_inst/u_OSER10_g .GSREN="false"; -defparam \rgb2dvi_inst/u_OSER10_g .LSREN="true"; -OSER10 \rgb2dvi_inst/u_OSER10_b ( - .D0(\rgb2dvi_inst/q_out_b [0]), - .D1(\rgb2dvi_inst/q_out_b [1]), - .D2(\rgb2dvi_inst/q_out_b [2]), - .D3(\rgb2dvi_inst/q_out_b [3]), - .D4(\rgb2dvi_inst/q_out_b [4]), - .D5(\rgb2dvi_inst/q_out_b [5]), - .D6(\rgb2dvi_inst/q_out_b [6]), - .D7(\rgb2dvi_inst/q_out_b [7]), - .D8(\rgb2dvi_inst/q_out_b [8]), - .D9(\rgb2dvi_inst/q_out_b [9]), - .PCLK(I_rgb_clk), - .FCLK(I_serial_clk), - .RESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/sdataout_b ) -); -defparam \rgb2dvi_inst/u_OSER10_b .GSREN="false"; -defparam \rgb2dvi_inst/u_OSER10_b .LSREN="true"; -OSER10 \rgb2dvi_inst/u_OSER10_clk ( - .D0(GND), - .D1(GND), - .D2(GND), - .D3(GND), - .D4(GND), - .D5(VCC), - .D6(VCC), - .D7(VCC), - .D8(VCC), - .D9(VCC), - .PCLK(I_rgb_clk), - .FCLK(I_serial_clk), - .RESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/sdataout_clk ) -); -defparam \rgb2dvi_inst/u_OSER10_clk .GSREN="false"; -defparam \rgb2dvi_inst/u_OSER10_clk .LSREN="true"; -INV \rgb2dvi_inst/n36_s2 ( - .I(I_rst_n), - .O(\rgb2dvi_inst/n36_6 ) -); -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n274_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n274_s0 .INIT=8'h3A; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0 .INIT=8'hCA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0 ( - .I0(I_rgb_r[0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0 .INIT=16'hFCC4; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0 .INIT=16'h4F44; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0 .INIT=16'hF004; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n681_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n681_s1 .INIT=8'h35; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s0 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ), - .I1(\rgb2dvi_inst/c1_d ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15 .INIT=16'h71BE; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1 .INIT=16'hCA00; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1 .INIT=16'h3500; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1 .INIT=16'h3A00; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n403_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n403_s4 .INIT=4'h9; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n402_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n402_s4 .INIT=8'hE1; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1 .INIT=16'hE8FE; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2 ( - .I0(I_rgb_r[0]), - .I1(I_rgb_r[1]), - .I2(I_rgb_r[2]), - .I3(I_rgb_r[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2 .INIT=16'h8000; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3 ( - .I0(I_rgb_r[7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3 .INIT=8'hDB; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1 .INIT=16'h96D7; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2 .INIT=8'h01; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1 .INIT=16'h8E00; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1 .INIT=8'h14; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s2 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3 .INIT=8'h07; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s15 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15 .INIT=16'h6FF9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16 .INIT=16'h96AA; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16 .INIT=8'h0B; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s2 .INIT=16'hAAC3; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3 .INIT=16'hAA3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s4 ( - .I0(I_rgb_r[0]), - .I1(I_rgb_r[1]), - .I2(I_rgb_r[2]), - .I3(I_rgb_r[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s4 .INIT=16'h7EE8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s5 ( - .I0(I_rgb_r[3]), - .I1(I_rgb_r[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s5 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6 ( - .I0(I_rgb_r[6]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ), - .I2(I_rgb_r[3]), - .I3(I_rgb_r[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6 .INIT=16'h8EE8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8 ( - .I0(I_rgb_r[3]), - .I1(I_rgb_r[5]), - .I2(I_rgb_r[6]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s4 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5 .INIT=8'h96; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s3 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19 .INIT=16'h5A3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20 .INIT=16'hDD4B; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17 .INIT=16'h0002; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9 ( - .I0(I_rgb_r[0]), - .I1(I_rgb_r[1]), - .I2(I_rgb_r[2]), - .I3(I_rgb_r[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s22 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s22 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s16 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ), - .I1(I_rgb_r[3]), - .I2(I_rgb_r[5]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10 .INIT=16'h6A95; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6 .INIT=16'hEA15; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s4 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n401_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n401_s4 .INIT=16'hAAA9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s6 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s3 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s3 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s2 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s12 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s12 .INIT=16'h1001; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s23 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s23 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n680_s3 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n680_s3 .INIT=16'hFFD5; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2 .INIT=16'hA088; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s7 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s7 .INIT=16'h9669; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s4 .INIT=16'h6900; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_6_s0 ( - .D(I_rgb_r[6]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_5_s0 ( - .D(I_rgb_r[5]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_4_s0 ( - .D(I_rgb_r[4]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 ( - .D(I_rgb_r[3]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 ( - .D(I_rgb_r[2]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0 ( - .D(I_rgb_r[1]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 ( - .D(I_rgb_r[0]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/de_d_s0 ( - .D(I_rgb_de), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/de_d ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/de_d_s0 .INIT=1'b0; -DFFP \rgb2dvi_inst/TMDS8b10b_inst_r/c1_d_s0 ( - .D(GND), - .CLK(I_rgb_clk), - .PRESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/c1_d ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/c1_d_s0 .INIT=1'b1; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_9_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [9]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_9_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_8_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [8]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_8_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_7_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_7_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_5_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_7_s0 ( - .D(I_rgb_r[7]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_7_s0 .INIT=1'b0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n135_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n135_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n134_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n134_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n133_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n133_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n132_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n132_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s1 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_1_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n364_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n364_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s2 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n239_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n239_s6 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_5_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(VCC), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s3 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3 .ALU_MODE=1; -MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ), - .S0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .O(\rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ) -); -INV \rgb2dvi_inst/TMDS8b10b_inst_r/n404_s5 ( - .I(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .O(\rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ) -); -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n274_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n274_s0 .INIT=8'h3A; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0 .INIT=8'hCA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0 .INIT=8'hB2; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s0 .INIT=16'h1F11; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0 .INIT=16'hF004; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n681_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/c1_d ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n681_s1 .INIT=8'h53; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ), - .I1(\rgb2dvi_inst/c1_d ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0 .INIT=8'hAC; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s13 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s13 .INIT=8'h96; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s11 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s11 .INIT=8'h01; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1 .INIT=16'hCA00; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1 .INIT=16'h3500; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1 .INIT=16'h3A00; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n403_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n403_s4 .INIT=4'h9; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n402_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n402_s4 .INIT=8'hE1; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1 ( - .I0(I_rgb_g[0]), - .I1(I_rgb_g[1]), - .I2(I_rgb_g[2]), - .I3(I_rgb_g[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1 .INIT=16'h8000; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2 ( - .I0(I_rgb_g[7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ), - .I3(I_rgb_g[0]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2 .INIT=16'h8100; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3 .INIT=16'hFDD4; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1 .INIT=16'hCFF5; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2 .INIT=16'h30A0; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s3 .INIT=8'h01; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1 .INIT=8'h14; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s2 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3 .INIT=8'h07; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s1 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15 .INIT=16'hF96F; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12 .INIT=16'hDD0F; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2 .INIT=16'hAAC3; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3 .INIT=16'hAA3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s4 ( - .I0(I_rgb_g[3]), - .I1(I_rgb_g[5]), - .I2(I_rgb_g[6]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s4 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6 ( - .I0(I_rgb_g[6]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ), - .I2(I_rgb_g[3]), - .I3(I_rgb_g[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6 .INIT=16'h7117; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s7 ( - .I0(I_rgb_g[0]), - .I1(I_rgb_g[1]), - .I2(I_rgb_g[2]), - .I3(I_rgb_g[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s7 .INIT=16'h7EE8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8 ( - .I0(I_rgb_g[3]), - .I1(I_rgb_g[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8 .INIT=4'h8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ), - .I1(I_rgb_g[7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s4 .INIT=16'hACCA; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s6 .INIT=8'h96; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s3 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s15 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17 .INIT=16'h5A3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18 .INIT=16'hDD4B; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10 ( - .I0(I_rgb_g[0]), - .I1(I_rgb_g[1]), - .I2(I_rgb_g[2]), - .I3(I_rgb_g[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s5 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s16 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s11 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ), - .I2(I_rgb_g[3]), - .I3(I_rgb_g[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s11 .INIT=16'h6999; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6 .INIT=16'hEA15; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s4 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n401_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n401_s4 .INIT=16'hAAA9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s3 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16 .INIT=16'h5554; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s7 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s7 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n680_s3 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n680_s3 .INIT=16'hFFD5; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2 .INIT=16'hA088; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7 .INIT=16'h9669; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_6_s0 ( - .D(I_rgb_g[6]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_5_s0 ( - .D(I_rgb_g[5]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_4_s0 ( - .D(I_rgb_g[4]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 ( - .D(I_rgb_g[3]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 ( - .D(I_rgb_g[2]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 ( - .D(I_rgb_g[1]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 ( - .D(I_rgb_g[0]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_9_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [9]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_9_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_8_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [8]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_8_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0 ( - .D(I_rgb_g[7]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0 .INIT=1'b0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n135_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n135_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n134_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n134_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n133_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n133_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n132_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n132_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s1 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_1_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n364_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n364_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s2 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n239_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n239_s6 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_5_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I3(GND), - .CIN(VCC), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s3 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3 .ALU_MODE=1; -MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ), - .S0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .O(\rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ) -); -INV \rgb2dvi_inst/TMDS8b10b_inst_g/n404_s5 ( - .I(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .O(\rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ) -); -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n274_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n274_s0 .INIT=8'h3A; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0 .INIT=8'hCA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0 .INIT=8'hB2; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0 .INIT=16'h4F44; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0 .INIT=16'hFFE0; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0 .INIT=16'h55C3; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n681_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n681_s1 .INIT=8'h35; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0 .INIT=8'hCA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15 .INIT=16'hDC2B; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1 .INIT=16'hCA00; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1 .INIT=16'h3500; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1 .INIT=16'h3A00; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n403_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n403_s4 .INIT=4'h9; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n402_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n402_s4 .INIT=8'hE1; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1 ( - .I0(I_rgb_b[0]), - .I1(I_rgb_b[1]), - .I2(I_rgb_b[2]), - .I3(I_rgb_b[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1 .INIT=16'h8000; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2 ( - .I0(I_rgb_b[7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ), - .I3(I_rgb_b[0]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2 .INIT=16'h8100; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3 .INIT=16'hFDD4; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1 .INIT=16'h7EBD; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s2 .INIT=8'h01; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s1 .INIT=16'h000D; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s2 .INIT=8'h20; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1 .INIT=8'h07; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1 .INIT=8'h14; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s14 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s14 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s15 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16 .INIT=16'h6FF9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16 .INIT=16'hD728; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s18 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s18 .INIT=16'hC3AA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s3 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2 .INIT=16'hAAC3; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3 .INIT=16'hAA3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s4 ( - .I0(I_rgb_b[3]), - .I1(I_rgb_b[5]), - .I2(I_rgb_b[6]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s4 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6 ( - .I0(I_rgb_b[6]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ), - .I2(I_rgb_b[3]), - .I3(I_rgb_b[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6 .INIT=16'h7117; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s7 ( - .I0(I_rgb_b[0]), - .I1(I_rgb_b[1]), - .I2(I_rgb_b[2]), - .I3(I_rgb_b[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s7 .INIT=16'h7EE8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8 ( - .I0(I_rgb_b[3]), - .I1(I_rgb_b[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8 .INIT=4'h8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ), - .I1(I_rgb_b[7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s3 .INIT=16'h4DD4; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4 .INIT=8'h96; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17 .INIT=16'h0096; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18 .INIT=16'h5A3C; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s19 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s19 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s20 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s20 .INIT=8'hC5; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10 ( - .I0(I_rgb_b[0]), - .I1(I_rgb_b[1]), - .I2(I_rgb_b[2]), - .I3(I_rgb_b[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_3_s12 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_3_s12 .INIT=16'h4004; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s11 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ), - .I2(I_rgb_b[3]), - .I3(I_rgb_b[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s11 .INIT=16'h6999; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6 .INIT=16'hEA15; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s4 .INIT=8'h96; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s16 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n401_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n401_s4 .INIT=16'hAAA9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s3 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s3 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s2 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2 .INIT=16'hA088; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7 .INIT=16'h9669; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_6_s0 ( - .D(I_rgb_b[6]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_5_s0 ( - .D(I_rgb_b[5]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_4_s0 ( - .D(I_rgb_b[4]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 ( - .D(I_rgb_b[3]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 ( - .D(I_rgb_b[2]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0 ( - .D(I_rgb_b[1]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 ( - .D(I_rgb_b[0]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 .INIT=1'b0; -DFFP \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 ( - .D(I_rgb_vs), - .CLK(I_rgb_clk), - .PRESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 .INIT=1'b1; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [9]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [8]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0 ( - .D(I_rgb_b[7]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0 .INIT=1'b0; -DFFP \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0 ( - .D(I_rgb_hs), - .CLK(I_rgb_clk), - .PRESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0 .INIT=1'b1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n135_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n135_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n134_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n134_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n133_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n133_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n132_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n132_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s1 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_1_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n364_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n364_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s2 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n239_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n239_s6 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_5_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(VCC), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s3 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s3 .ALU_MODE=1; -MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ), - .S0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .O(\rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ) -); -INV \rgb2dvi_inst/TMDS8b10b_inst_b/n404_s5 ( - .I(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .O(\rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ) -); -endmodule +//Copyright (C)2014-2024 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: Post-PnR Simulation Model file +//Tool Version: V1.9.9.03 (64-bit) +//Created Time: Sun Jun 2 18:05:57 2024 + +`timescale 100 ps/100 ps +module DVI_TX_Top( + I_rst_n, + I_serial_clk, + I_rgb_clk, + I_rgb_vs, + I_rgb_hs, + I_rgb_de, + I_rgb_r, + I_rgb_g, + I_rgb_b, + O_tmds_clk_p, + O_tmds_clk_n, + O_tmds_data_p, + O_tmds_data_n +); +input I_rst_n; +input I_serial_clk; +input I_rgb_clk; +input I_rgb_vs; +input I_rgb_hs; +input I_rgb_de; +input [7:0] I_rgb_r; +input [7:0] I_rgb_g; +input [7:0] I_rgb_b; +output O_tmds_clk_p; +output O_tmds_clk_n; +output [2:0] O_tmds_data_p; +output [2:0] O_tmds_data_n; +wire GND; +wire [7:0] I_rgb_b; +wire I_rgb_clk; +wire I_rgb_de; +wire [7:0] I_rgb_g; +wire I_rgb_hs; +wire [7:0] I_rgb_r; +wire I_rgb_vs; +wire I_rst_n; +wire I_serial_clk; +wire O_tmds_clk_n; +wire O_tmds_clk_p; +wire [2:0] O_tmds_data_n; +wire [2:0] O_tmds_data_p; +wire VCC; +wire \rgb2dvi_inst/sdataout_r ; +wire \rgb2dvi_inst/sdataout_g ; +wire \rgb2dvi_inst/sdataout_b ; +wire \rgb2dvi_inst/sdataout_clk ; +wire \rgb2dvi_inst/n36_6 ; +wire \rgb2dvi_inst/de_d ; +wire \rgb2dvi_inst/c1_d ; +wire [9:0] \rgb2dvi_inst/q_out_r ; +wire [9:0] \rgb2dvi_inst/q_out_g ; +wire [9:0] \rgb2dvi_inst/q_out_b ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n132_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_1_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n364_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n236_5_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ; +wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit ; +wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_r/din_d ; +wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_r/cnt ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n132_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_1_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n364_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n236_5_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ; +wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit ; +wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_g/din_d ; +wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_g/cnt ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n132_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_1_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n364_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n236_5_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ; +wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit ; +wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_b/din_d ; +wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_b/cnt ; +VCC VCC_cZ ( + .V(VCC) +); +GND GND_cZ ( + .G(GND) +); +GSR GSR ( + .GSRI(VCC) +); +ELVDS_OBUF \rgb2dvi_inst/u_LVDS_r ( + .I(\rgb2dvi_inst/sdataout_r ), + .O(O_tmds_data_p[2]), + .OB(O_tmds_data_n[2]) +); +ELVDS_OBUF \rgb2dvi_inst/u_LVDS_g ( + .I(\rgb2dvi_inst/sdataout_g ), + .O(O_tmds_data_p[1]), + .OB(O_tmds_data_n[1]) +); +ELVDS_OBUF \rgb2dvi_inst/u_LVDS_b ( + .I(\rgb2dvi_inst/sdataout_b ), + .O(O_tmds_data_p[0]), + .OB(O_tmds_data_n[0]) +); +ELVDS_OBUF \rgb2dvi_inst/u_LVDS_clk ( + .I(\rgb2dvi_inst/sdataout_clk ), + .O(O_tmds_clk_p), + .OB(O_tmds_clk_n) +); +OSER10 \rgb2dvi_inst/u_OSER10_r ( + .D0(\rgb2dvi_inst/q_out_r [0]), + .D1(\rgb2dvi_inst/q_out_r [1]), + .D2(\rgb2dvi_inst/q_out_r [2]), + .D3(\rgb2dvi_inst/q_out_r [3]), + .D4(\rgb2dvi_inst/q_out_r [4]), + .D5(\rgb2dvi_inst/q_out_r [5]), + .D6(\rgb2dvi_inst/q_out_r [6]), + .D7(\rgb2dvi_inst/q_out_r [7]), + .D8(\rgb2dvi_inst/q_out_r [8]), + .D9(\rgb2dvi_inst/q_out_r [9]), + .PCLK(I_rgb_clk), + .FCLK(I_serial_clk), + .RESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/sdataout_r ) +); +defparam \rgb2dvi_inst/u_OSER10_r .GSREN="false"; +defparam \rgb2dvi_inst/u_OSER10_r .LSREN="true"; +OSER10 \rgb2dvi_inst/u_OSER10_g ( + .D0(\rgb2dvi_inst/q_out_g [0]), + .D1(\rgb2dvi_inst/q_out_g [1]), + .D2(\rgb2dvi_inst/q_out_g [2]), + .D3(\rgb2dvi_inst/q_out_g [3]), + .D4(\rgb2dvi_inst/q_out_g [4]), + .D5(\rgb2dvi_inst/q_out_g [5]), + .D6(\rgb2dvi_inst/q_out_g [6]), + .D7(\rgb2dvi_inst/q_out_g [7]), + .D8(\rgb2dvi_inst/q_out_g [8]), + .D9(\rgb2dvi_inst/q_out_g [9]), + .PCLK(I_rgb_clk), + .FCLK(I_serial_clk), + .RESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/sdataout_g ) +); +defparam \rgb2dvi_inst/u_OSER10_g .GSREN="false"; +defparam \rgb2dvi_inst/u_OSER10_g .LSREN="true"; +OSER10 \rgb2dvi_inst/u_OSER10_b ( + .D0(\rgb2dvi_inst/q_out_b [0]), + .D1(\rgb2dvi_inst/q_out_b [1]), + .D2(\rgb2dvi_inst/q_out_b [2]), + .D3(\rgb2dvi_inst/q_out_b [3]), + .D4(\rgb2dvi_inst/q_out_b [4]), + .D5(\rgb2dvi_inst/q_out_b [5]), + .D6(\rgb2dvi_inst/q_out_b [6]), + .D7(\rgb2dvi_inst/q_out_b [7]), + .D8(\rgb2dvi_inst/q_out_b [8]), + .D9(\rgb2dvi_inst/q_out_b [9]), + .PCLK(I_rgb_clk), + .FCLK(I_serial_clk), + .RESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/sdataout_b ) +); +defparam \rgb2dvi_inst/u_OSER10_b .GSREN="false"; +defparam \rgb2dvi_inst/u_OSER10_b .LSREN="true"; +OSER10 \rgb2dvi_inst/u_OSER10_clk ( + .D0(GND), + .D1(GND), + .D2(GND), + .D3(GND), + .D4(GND), + .D5(VCC), + .D6(VCC), + .D7(VCC), + .D8(VCC), + .D9(VCC), + .PCLK(I_rgb_clk), + .FCLK(I_serial_clk), + .RESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/sdataout_clk ) +); +defparam \rgb2dvi_inst/u_OSER10_clk .GSREN="false"; +defparam \rgb2dvi_inst/u_OSER10_clk .LSREN="true"; +INV \rgb2dvi_inst/n36_s2 ( + .I(I_rst_n), + .O(\rgb2dvi_inst/n36_6 ) +); +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n274_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n274_s0 .INIT=8'h3A; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0 .INIT=8'hCA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0 ( + .I0(I_rgb_r[0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0 .INIT=16'hFCC4; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0 .INIT=16'h4F44; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0 .INIT=16'hF004; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n681_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n681_s1 .INIT=8'h35; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s0 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ), + .I1(\rgb2dvi_inst/c1_d ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15 .INIT=16'h71BE; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1 .INIT=16'hCA00; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1 .INIT=16'h3500; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1 .INIT=16'h3A00; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n403_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n403_s4 .INIT=4'h9; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n402_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n402_s4 .INIT=8'hE1; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1 .INIT=16'hE8FE; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2 ( + .I0(I_rgb_r[0]), + .I1(I_rgb_r[1]), + .I2(I_rgb_r[2]), + .I3(I_rgb_r[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2 .INIT=16'h8000; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3 ( + .I0(I_rgb_r[7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3 .INIT=8'hDB; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1 .INIT=16'h96D7; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2 .INIT=8'h01; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1 .INIT=16'h8E00; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1 .INIT=8'h14; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s2 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3 .INIT=8'h07; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s15 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15 .INIT=16'h6FF9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16 .INIT=16'h96AA; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16 .INIT=8'h0B; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s2 .INIT=16'hAAC3; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3 .INIT=16'hAA3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s4 ( + .I0(I_rgb_r[0]), + .I1(I_rgb_r[1]), + .I2(I_rgb_r[2]), + .I3(I_rgb_r[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s4 .INIT=16'h7EE8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s5 ( + .I0(I_rgb_r[3]), + .I1(I_rgb_r[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s5 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6 ( + .I0(I_rgb_r[6]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ), + .I2(I_rgb_r[3]), + .I3(I_rgb_r[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6 .INIT=16'h8EE8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8 ( + .I0(I_rgb_r[3]), + .I1(I_rgb_r[5]), + .I2(I_rgb_r[6]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s4 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5 .INIT=8'h96; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s3 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19 .INIT=16'h5A3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20 .INIT=16'hDD4B; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17 .INIT=16'h0002; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9 ( + .I0(I_rgb_r[0]), + .I1(I_rgb_r[1]), + .I2(I_rgb_r[2]), + .I3(I_rgb_r[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s22 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s22 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s16 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ), + .I1(I_rgb_r[3]), + .I2(I_rgb_r[5]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10 .INIT=16'h6A95; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6 .INIT=16'hEA15; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s4 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n401_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n401_s4 .INIT=16'hAAA9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s6 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s3 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s3 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s2 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s12 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s12 .INIT=16'h1001; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s23 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s23 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n680_s3 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n680_s3 .INIT=16'hFFD5; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2 .INIT=16'hA088; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s7 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s7 .INIT=16'h9669; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s4 .INIT=16'h6900; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_6_s0 ( + .D(I_rgb_r[6]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_5_s0 ( + .D(I_rgb_r[5]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_4_s0 ( + .D(I_rgb_r[4]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 ( + .D(I_rgb_r[3]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 ( + .D(I_rgb_r[2]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0 ( + .D(I_rgb_r[1]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 ( + .D(I_rgb_r[0]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/de_d_s0 ( + .D(I_rgb_de), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/de_d ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/de_d_s0 .INIT=1'b0; +DFFP \rgb2dvi_inst/TMDS8b10b_inst_r/c1_d_s0 ( + .D(GND), + .CLK(I_rgb_clk), + .PRESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/c1_d ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/c1_d_s0 .INIT=1'b1; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_9_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [9]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_9_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_8_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [8]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_8_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_7_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_7_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_5_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_7_s0 ( + .D(I_rgb_r[7]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_7_s0 .INIT=1'b0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n135_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n135_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n134_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n134_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n133_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n133_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n132_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n132_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s1 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_1_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n364_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n364_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s2 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n239_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n239_s6 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_5_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(VCC), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s3 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3 .ALU_MODE=1; +MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ), + .S0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .O(\rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ) +); +INV \rgb2dvi_inst/TMDS8b10b_inst_r/n404_s5 ( + .I(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .O(\rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ) +); +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n274_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n274_s0 .INIT=8'h3A; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0 .INIT=8'hCA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0 .INIT=8'hB2; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s0 .INIT=16'h1F11; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0 .INIT=16'hF004; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n681_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/c1_d ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n681_s1 .INIT=8'h53; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ), + .I1(\rgb2dvi_inst/c1_d ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0 .INIT=8'hAC; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s13 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s13 .INIT=8'h96; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s11 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s11 .INIT=8'h01; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1 .INIT=16'hCA00; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1 .INIT=16'h3500; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1 .INIT=16'h3A00; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n403_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n403_s4 .INIT=4'h9; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n402_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n402_s4 .INIT=8'hE1; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1 ( + .I0(I_rgb_g[0]), + .I1(I_rgb_g[1]), + .I2(I_rgb_g[2]), + .I3(I_rgb_g[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1 .INIT=16'h8000; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2 ( + .I0(I_rgb_g[7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ), + .I3(I_rgb_g[0]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2 .INIT=16'h8100; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3 .INIT=16'hFDD4; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1 .INIT=16'hCFF5; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2 .INIT=16'h30A0; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s3 .INIT=8'h01; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1 .INIT=8'h14; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s2 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3 .INIT=8'h07; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s1 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15 .INIT=16'hF96F; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12 .INIT=16'hDD0F; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2 .INIT=16'hAAC3; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3 .INIT=16'hAA3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s4 ( + .I0(I_rgb_g[3]), + .I1(I_rgb_g[5]), + .I2(I_rgb_g[6]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s4 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6 ( + .I0(I_rgb_g[6]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ), + .I2(I_rgb_g[3]), + .I3(I_rgb_g[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6 .INIT=16'h7117; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s7 ( + .I0(I_rgb_g[0]), + .I1(I_rgb_g[1]), + .I2(I_rgb_g[2]), + .I3(I_rgb_g[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s7 .INIT=16'h7EE8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8 ( + .I0(I_rgb_g[3]), + .I1(I_rgb_g[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8 .INIT=4'h8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ), + .I1(I_rgb_g[7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s4 .INIT=16'hACCA; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s6 .INIT=8'h96; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s3 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s15 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17 .INIT=16'h5A3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18 .INIT=16'hDD4B; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10 ( + .I0(I_rgb_g[0]), + .I1(I_rgb_g[1]), + .I2(I_rgb_g[2]), + .I3(I_rgb_g[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s5 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s16 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s11 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ), + .I2(I_rgb_g[3]), + .I3(I_rgb_g[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s11 .INIT=16'h6999; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6 .INIT=16'hEA15; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s4 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n401_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n401_s4 .INIT=16'hAAA9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s3 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16 .INIT=16'h5554; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s7 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s7 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n680_s3 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n680_s3 .INIT=16'hFFD5; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2 .INIT=16'hA088; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7 .INIT=16'h9669; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_6_s0 ( + .D(I_rgb_g[6]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_5_s0 ( + .D(I_rgb_g[5]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_4_s0 ( + .D(I_rgb_g[4]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 ( + .D(I_rgb_g[3]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 ( + .D(I_rgb_g[2]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 ( + .D(I_rgb_g[1]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 ( + .D(I_rgb_g[0]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_9_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [9]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_9_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_8_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [8]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_8_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0 ( + .D(I_rgb_g[7]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0 .INIT=1'b0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n135_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n135_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n134_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n134_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n133_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n133_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n132_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n132_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s1 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_1_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n364_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n364_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s2 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n239_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n239_s6 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_5_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I3(GND), + .CIN(VCC), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s3 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3 .ALU_MODE=1; +MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ), + .S0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .O(\rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ) +); +INV \rgb2dvi_inst/TMDS8b10b_inst_g/n404_s5 ( + .I(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .O(\rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ) +); +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n274_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n274_s0 .INIT=8'h3A; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0 .INIT=8'hCA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0 .INIT=8'hB2; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0 .INIT=16'h4F44; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0 .INIT=16'hFFE0; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0 .INIT=16'h55C3; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n681_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n681_s1 .INIT=8'h35; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0 .INIT=8'hCA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15 .INIT=16'hDC2B; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1 .INIT=16'hCA00; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1 .INIT=16'h3500; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1 .INIT=16'h3A00; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n403_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n403_s4 .INIT=4'h9; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n402_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n402_s4 .INIT=8'hE1; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1 ( + .I0(I_rgb_b[0]), + .I1(I_rgb_b[1]), + .I2(I_rgb_b[2]), + .I3(I_rgb_b[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1 .INIT=16'h8000; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2 ( + .I0(I_rgb_b[7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ), + .I3(I_rgb_b[0]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2 .INIT=16'h8100; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3 .INIT=16'hFDD4; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1 .INIT=16'h7EBD; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s2 .INIT=8'h01; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s1 .INIT=16'h000D; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s2 .INIT=8'h20; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1 .INIT=8'h07; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1 .INIT=8'h14; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s14 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s14 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s15 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16 .INIT=16'h6FF9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16 .INIT=16'hD728; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s18 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s18 .INIT=16'hC3AA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s3 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2 .INIT=16'hAAC3; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3 .INIT=16'hAA3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s4 ( + .I0(I_rgb_b[3]), + .I1(I_rgb_b[5]), + .I2(I_rgb_b[6]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s4 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6 ( + .I0(I_rgb_b[6]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ), + .I2(I_rgb_b[3]), + .I3(I_rgb_b[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6 .INIT=16'h7117; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s7 ( + .I0(I_rgb_b[0]), + .I1(I_rgb_b[1]), + .I2(I_rgb_b[2]), + .I3(I_rgb_b[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s7 .INIT=16'h7EE8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8 ( + .I0(I_rgb_b[3]), + .I1(I_rgb_b[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8 .INIT=4'h8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ), + .I1(I_rgb_b[7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s3 .INIT=16'h4DD4; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4 .INIT=8'h96; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17 .INIT=16'h0096; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18 .INIT=16'h5A3C; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s19 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s19 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s20 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s20 .INIT=8'hC5; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10 ( + .I0(I_rgb_b[0]), + .I1(I_rgb_b[1]), + .I2(I_rgb_b[2]), + .I3(I_rgb_b[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_3_s12 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_3_s12 .INIT=16'h4004; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s11 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ), + .I2(I_rgb_b[3]), + .I3(I_rgb_b[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s11 .INIT=16'h6999; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6 .INIT=16'hEA15; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s4 .INIT=8'h96; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s16 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n401_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n401_s4 .INIT=16'hAAA9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s3 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s3 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s2 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2 .INIT=16'hA088; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7 .INIT=16'h9669; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_6_s0 ( + .D(I_rgb_b[6]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_5_s0 ( + .D(I_rgb_b[5]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_4_s0 ( + .D(I_rgb_b[4]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 ( + .D(I_rgb_b[3]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 ( + .D(I_rgb_b[2]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0 ( + .D(I_rgb_b[1]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 ( + .D(I_rgb_b[0]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 .INIT=1'b0; +DFFP \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 ( + .D(I_rgb_vs), + .CLK(I_rgb_clk), + .PRESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 .INIT=1'b1; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [9]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [8]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0 ( + .D(I_rgb_b[7]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0 .INIT=1'b0; +DFFP \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0 ( + .D(I_rgb_hs), + .CLK(I_rgb_clk), + .PRESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0 .INIT=1'b1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n135_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n135_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n134_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n134_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n133_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n133_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n132_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n132_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s1 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_1_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n364_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n364_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s2 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n239_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n239_s6 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_5_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(VCC), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s3 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s3 .ALU_MODE=1; +MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ), + .S0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .O(\rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ) +); +INV \rgb2dvi_inst/TMDS8b10b_inst_b/n404_s5 ( + .I(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .O(\rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ) +); +endmodule diff --git a/boards/tang_primer_20k_dock_alt/gowin_rpll.ipc b/boards/tang_primer_20k_dock_alt/gowin_rpll.ipc index 9cda9a9b..81b9b468 100644 --- a/boards/tang_primer_20k_dock_alt/gowin_rpll.ipc +++ b/boards/tang_primer_20k_dock_alt/gowin_rpll.ipc @@ -1,24 +1,24 @@ -[General] -ipc_version=4 -file=gowin_rpll -module=Gowin_rPLL -target_device=gw2a18c-011 -type=clock_rpll -version=1.0 - -[Config] -CKLOUTD3=false -CLKFB_SOURCE=0 -CLKIN_FREQ=27 -CLKOUTD=false -CLKOUTP=false -CLKOUT_BYPASS=false -CLKOUT_DIVIDE_DYN=true -CLKOUT_FREQ=125 -CLKOUT_TOLERANCE=1 -DYNAMIC=false -LANG=0 -LOCK_EN=true -MODE_GENERAL=true -PLL_PWD=false -RESET_PLL=false +[General] +ipc_version=4 +file=gowin_rpll +module=Gowin_rPLL +target_device=gw2a18c-011 +type=clock_rpll +version=1.0 + +[Config] +CKLOUTD3=false +CLKFB_SOURCE=0 +CLKIN_FREQ=27 +CLKOUTD=false +CLKOUTP=false +CLKOUT_BYPASS=false +CLKOUT_DIVIDE_DYN=true +CLKOUT_FREQ=125 +CLKOUT_TOLERANCE=1 +DYNAMIC=false +LANG=0 +LOCK_EN=true +MODE_GENERAL=true +PLL_PWD=false +RESET_PLL=false diff --git a/boards/tang_primer_20k_dock_alt/gowin_rpll.mod b/boards/tang_primer_20k_dock_alt/gowin_rpll.mod index bb9adb5e..9978d778 100644 --- a/boards/tang_primer_20k_dock_alt/gowin_rpll.mod +++ b/boards/tang_primer_20k_dock_alt/gowin_rpll.mod @@ -1,32 +1,32 @@ --series GW2A --device GW2A-18 --device_version C --package PBGA256 --part_number GW2A-LV18PG256C8/I7 - - --mod_name Gowin_rPLL --file_name gowin_rpll --path E:/gw/basics-graphics-music/labs/06_vga/run/src/gowin_rpll/ --type PLL --rPll true --file_type vlg --dev_type GW2A-18C --dyn_idiv_sel false --idiv_sel 8 --dyn_fbdiv_sel false --fbdiv_sel 37 --dyn_odiv_sel false --odiv_sel 8 --dyn_da_en false --rst_sig false --rst_sig_p false --fclkin 27 --clkfb_sel 0 --en_lock true --clkout_bypass false --en_clkoutp false --clkoutp_bypass false --en_clkoutd false --clkoutd_bypass false +-series GW2A +-device GW2A-18 +-device_version C +-package PBGA256 +-part_number GW2A-LV18PG256C8/I7 + + +-mod_name Gowin_rPLL +-file_name gowin_rpll +-path E:/gw/basics-graphics-music/labs/06_vga/run/src/gowin_rpll/ +-type PLL +-rPll true +-file_type vlg +-dev_type GW2A-18C +-dyn_idiv_sel false +-idiv_sel 8 +-dyn_fbdiv_sel false +-fbdiv_sel 37 +-dyn_odiv_sel false +-odiv_sel 8 +-dyn_da_en false +-rst_sig false +-rst_sig_p false +-fclkin 27 +-clkfb_sel 0 +-en_lock true +-clkout_bypass false +-en_clkoutp false +-clkoutp_bypass false +-en_clkoutd false +-clkoutd_bypass false -en_clkoutd3 false \ No newline at end of file diff --git a/boards/tang_primer_20k_dock_alt/gowin_rpll.v b/boards/tang_primer_20k_dock_alt/gowin_rpll.v index 8ca521ec..15b4cae3 100644 --- a/boards/tang_primer_20k_dock_alt/gowin_rpll.v +++ b/boards/tang_primer_20k_dock_alt/gowin_rpll.v @@ -1,64 +1,64 @@ -//Copyright (C)2014-2024 Gowin Semiconductor Corporation. -//All rights reserved. -//File Title: IP file -//Tool Version: V1.9.9.03 (64-bit) -//Part Number: GW2A-LV18PG256C8/I7 -//Device: GW2A-18 -//Device Version: C -//Created Time: Sun Jun 2 18:04:20 2024 - -module Gowin_rPLL (clkout, lock, clkin); - -output clkout; -output lock; -input clkin; - -wire clkoutp_o; -wire clkoutd_o; -wire clkoutd3_o; -wire gw_gnd; - -assign gw_gnd = 1'b0; - -rPLL rpll_inst ( - .CLKOUT(clkout), - .LOCK(lock), - .CLKOUTP(clkoutp_o), - .CLKOUTD(clkoutd_o), - .CLKOUTD3(clkoutd3_o), - .RESET(gw_gnd), - .RESET_P(gw_gnd), - .CLKIN(clkin), - .CLKFB(gw_gnd), - .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) -); - -defparam rpll_inst.FCLKIN = "27"; -defparam rpll_inst.DYN_IDIV_SEL = "false"; -defparam rpll_inst.IDIV_SEL = 7; -defparam rpll_inst.DYN_FBDIV_SEL = "false"; -defparam rpll_inst.FBDIV_SEL = 36; -defparam rpll_inst.DYN_ODIV_SEL = "false"; -defparam rpll_inst.ODIV_SEL = 8; -defparam rpll_inst.PSDA_SEL = "0000"; -defparam rpll_inst.DYN_DA_EN = "false"; -defparam rpll_inst.DUTYDA_SEL = "1000"; -defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; -defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; -defparam rpll_inst.CLKOUT_DLY_STEP = 0; -defparam rpll_inst.CLKOUTP_DLY_STEP = 0; -defparam rpll_inst.CLKFB_SEL = "internal"; -defparam rpll_inst.CLKOUT_BYPASS = "false"; -defparam rpll_inst.CLKOUTP_BYPASS = "false"; -defparam rpll_inst.CLKOUTD_BYPASS = "false"; -defparam rpll_inst.DYN_SDIV_SEL = 2; -defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; -defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; -defparam rpll_inst.DEVICE = "GW2A-18C"; - -endmodule //Gowin_rPLL +//Copyright (C)2014-2024 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: IP file +//Tool Version: V1.9.9.03 (64-bit) +//Part Number: GW2A-LV18PG256C8/I7 +//Device: GW2A-18 +//Device Version: C +//Created Time: Sun Jun 2 18:04:20 2024 + +module Gowin_rPLL (clkout, lock, clkin); + +output clkout; +output lock; +input clkin; + +wire clkoutp_o; +wire clkoutd_o; +wire clkoutd3_o; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +rPLL rpll_inst ( + .CLKOUT(clkout), + .LOCK(lock), + .CLKOUTP(clkoutp_o), + .CLKOUTD(clkoutd_o), + .CLKOUTD3(clkoutd3_o), + .RESET(gw_gnd), + .RESET_P(gw_gnd), + .CLKIN(clkin), + .CLKFB(gw_gnd), + .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) +); + +defparam rpll_inst.FCLKIN = "27"; +defparam rpll_inst.DYN_IDIV_SEL = "false"; +defparam rpll_inst.IDIV_SEL = 7; +defparam rpll_inst.DYN_FBDIV_SEL = "false"; +defparam rpll_inst.FBDIV_SEL = 36; +defparam rpll_inst.DYN_ODIV_SEL = "false"; +defparam rpll_inst.ODIV_SEL = 8; +defparam rpll_inst.PSDA_SEL = "0000"; +defparam rpll_inst.DYN_DA_EN = "false"; +defparam rpll_inst.DUTYDA_SEL = "1000"; +defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUT_DLY_STEP = 0; +defparam rpll_inst.CLKOUTP_DLY_STEP = 0; +defparam rpll_inst.CLKFB_SEL = "internal"; +defparam rpll_inst.CLKOUT_BYPASS = "false"; +defparam rpll_inst.CLKOUTP_BYPASS = "false"; +defparam rpll_inst.CLKOUTD_BYPASS = "false"; +defparam rpll_inst.DYN_SDIV_SEL = 2; +defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; +defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; +defparam rpll_inst.DEVICE = "GW2A-18C"; + +endmodule //Gowin_rPLL diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index 55bbb3f7..4fc05a6f 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `undef ENABLE_INMP441 module board_specific_top @@ -40,19 +40,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -62,10 +62,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + logic [w_lab_sw - 1:0] lab_sw; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -80,22 +80,22 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_key = tm_key [w_tm_key - 1:0]; + assign lab_sw = ~ SW; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_key = ~ KEY [w_key - 1:0]; + assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -108,28 +108,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), @@ -142,7 +142,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -164,7 +164,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 94f29072..459f3a0a 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( @@ -39,19 +39,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -61,10 +61,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + logic [w_lab_sw - 1:0] lab_sw; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -79,22 +79,22 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_key = tm_key [w_tm_key - 1:0]; + assign lab_sw = ~ SW; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_key = ~ KEY [w_key - 1:0]; + assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -107,28 +107,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index ddb35492..a9a7776c 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( @@ -39,19 +39,19 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -61,10 +61,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] lab_key; + logic [w_lab_sw - 1:0] lab_sw; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -79,22 +79,22 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_key = tm_key [w_tm_key - 1:0]; + assign lab_sw = ~ SW; - assign tm_led = top_led; - assign tm_digit = top_digit; + assign tm_led = lab_led; + assign tm_digit = lab_digit; `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_key = ~ KEY [w_key - 1:0]; + assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -107,28 +107,28 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), @@ -197,5 +197,5 @@ module board_specific_top assign GPIO_0 = { VGA_R, VGA_B }; assign GPIO_1 = { VGA_G, 2'b00, VGA_VS, VGA_HS }; - + endmodule diff --git a/boards/tang_primer_25k_dock/board_specific_top.sv b/boards/tang_primer_25k_dock/board_specific_top.sv index cdc4e7d6..8a976576 100644 --- a/boards/tang_primer_25k_dock/board_specific_top.sv +++ b/boards/tang_primer_25k_dock/board_specific_top.sv @@ -3,12 +3,13 @@ // Create a variant of 25K with 7-segment, leds and buttons on pmod. `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( parameter clk_mhz = 50, pixel_mhz = 25, + w_key = 2, w_sw = 0, w_led = 0, @@ -82,7 +83,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), @@ -98,7 +99,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), @@ -163,7 +164,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - i_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv index 9645a1de..fdb6e7fd 100644 --- a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv +++ b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv @@ -3,7 +3,7 @@ // Create a variant of 25K with 7-segment, leds and buttons on pmod. `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define ENABLE_DVI @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), @@ -103,7 +103,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), @@ -170,7 +170,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - i_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/trion_t20/board_specific_top.sv b/boards/trion_t20/board_specific_top.sv index ac38a1a3..3e048aaa 100755 --- a/boards/trion_t20/board_specific_top.sv +++ b/boards/trion_t20/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -14,29 +14,29 @@ module board_specific_top //------------------------------------------------------------------------- // PLL interface - //------------------------------------------------------------------------- + //------------------------------------------------------------------------- input clk, // input pll_locked, // output pll_reset_n, //------------------------------------------------------------------------- - // button - //------------------------------------------------------------------------- + // button + //------------------------------------------------------------------------- input rst_button, - + input [w_key - 1: 0] keys, input [w_sw - 1: 0] sw, //------------------------------------------------------------------------- - // LED + // LED //------------------------------------------------------------------------- output [w_led - 1: 0] led_n, - + //------------------------------------------------------------------------- - // UART + // UART //------------------------------------------------------------------------- input RXD, @@ -60,7 +60,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -69,7 +69,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/zeowaa/board_specific_top.sv b/boards/zeowaa/board_specific_top.sv index c3fb516e..6a33230c 100644 --- a/boards/zeowaa/board_specific_top.sv +++ b/boards/zeowaa/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -31,11 +31,11 @@ module board_specific_top inout [w_gpio - 1:0] GPIO ); - localparam w_top_key = w_key - 1; // One onboard key is used as a reset + localparam w_lab_key = w_key - 1; // One onboard key is used as a reset wire clk = CLK; wire rst = ~ KEY_N [w_key - 1]; - wire [w_top_key - 1:0] top_key = ~ KEY_N [w_top_key - 1:0]; + wire [w_lab_key - 1:0] lab_key = ~ KEY_N [w_lab_key - 1:0]; //------------------------------------------------------------------------ @@ -63,22 +63,22 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), + .w_key ( w_lab_key ), .w_sw ( w_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ~ SW_N ), .led ( led ), @@ -133,7 +133,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/zeowaa_wo_dig_0/board_specific_top.sv b/boards/zeowaa_wo_dig_0/board_specific_top.sv index 44b80919..b34ec188 100644 --- a/boards/zeowaa_wo_dig_0/board_specific_top.sv +++ b/boards/zeowaa_wo_dig_0/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -55,10 +55,10 @@ module board_specific_top // This logic is necessary to compensate the defective board - localparam w_top_digit = w_digit - 1; // The right digit is not working on this board - wire [w_top_digit - 1:0] top_digit; + localparam w_lab_digit = w_digit - 1; // The right digit is not working on this board + wire [w_lab_digit - 1:0] lab_digit; - assign digit = { top_digit, 1'b0 }; + assign digit = { lab_digit, 1'b0 }; //------------------------------------------------------------------------ @@ -69,16 +69,16 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), .w_sw ( w_sw ), .w_led ( w_led ), - .w_digit ( w_top_digit ), // Note top_digit, not digit + .w_digit ( w_lab_digit ), // Note lab_digit, not digit .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), @@ -90,7 +90,7 @@ module board_specific_top .led ( led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), // Note top_digit, not digit + .digit ( lab_digit ), // Note lab_digit, not digit .vsync ( VGA_VSYNC ), .hsync ( VGA_HSYNC ), @@ -139,7 +139,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/zybo_z7/board_specific_top.sv b/boards/zybo_z7/board_specific_top.sv index aa59093a..20a05ef3 100644 --- a/boards/zybo_z7/board_specific_top.sv +++ b/boards/zybo_z7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( @@ -45,7 +45,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_key_top = w_key_tm > w_key ? w_key_tm : w_key, w_led_top = w_led_tm > w_led ? w_led_tm : w_led, w_digit_top = w_digit_tm > w_digit ? w_digit_tm : w_digit; @@ -67,17 +67,17 @@ module board_specific_top //------------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign key_top = {key_tm, key}; assign {led_tm, led} = led_top; assign {digit_tm, digit} = digit_top; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign key_top = {key, key_tm}; assign {led, led_tm} = led_top; assign {digit, digit_tm} = digit_top; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin key_top = '0; @@ -100,7 +100,7 @@ module board_specific_top //------------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz (clk_mhz), .w_key (w_key_top), @@ -109,7 +109,7 @@ module board_specific_top .w_digit (w_digit_top), .w_gpio (w_gpio) ) - i_top + i_lab_top ( .clk (clk), .slow_clk (slow_clk), diff --git a/labs/05_7seven_segment_letter/lab_specific_config.svh b/labs/05_7seven_segment_letter/lab_specific_config.svh deleted file mode 100644 index 20899864..00000000 --- a/labs/05_7seven_segment_letter/lab_specific_config.svh +++ /dev/null @@ -1,16 +0,0 @@ -`ifndef LAB_SPECIFIC_CONFIG_SVH -`define LAB_SPECIFIC_CONFIG_SVH - -// The following setting is needed for Gowin boards - `define ENABLE_TM1638 - -// HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 - - `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS - - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM -// `define CONCAT_TM_SIGNALS_AND_REGULAR - -`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/06_vga/tb.sv b/labs/06_vga/tb.sv deleted file mode 100644 index f8c334f3..00000000 --- a/labs/06_vga/tb.sv +++ /dev/null @@ -1,57 +0,0 @@ -`include "config.svh" - -module tb; - - localparam clk_mhz = 1, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100; - - //------------------------------------------------------------------------ - - logic clk; - logic rst; - logic [3:0] key; - logic [7:0] sw; - - //------------------------------------------------------------------------ - - top - # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_sw ), - .w_led ( w_led ), - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) - ) - i_top - ( - .clk ( clk ), - .slow_clk ( clk ), - .rst ( rst ), - .key ( key ), - .sw ( sw ) - ); - - //------------------------------------------------------------------------ - - initial - begin - `ifdef __ICARUS__ - $dumpvars; - `endif - - repeat (8) - begin - # 10 - key <= $urandom (); - sw <= $urandom (); - end - - $finish; - end - -endmodule diff --git a/labs/09_7segment_word/lab_specific_config.svh b/labs/09_7segment_word/lab_specific_config.svh deleted file mode 100644 index 20899864..00000000 --- a/labs/09_7segment_word/lab_specific_config.svh +++ /dev/null @@ -1,16 +0,0 @@ -`ifndef LAB_SPECIFIC_CONFIG_SVH -`define LAB_SPECIFIC_CONFIG_SVH - -// The following setting is needed for Gowin boards - `define ENABLE_TM1638 - -// HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 - - `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS - - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM -// `define CONCAT_TM_SIGNALS_AND_REGULAR - -`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/15_uart/to_integrate/xx_gtkwave_extra.tcl b/labs/15_uart/to_integrate/xx_gtkwave_extra.tcl deleted file mode 100644 index 9dbe0b34..00000000 --- a/labs/15_uart/to_integrate/xx_gtkwave_extra.tcl +++ /dev/null @@ -1 +0,0 @@ -lappend all_signals tb.i_top.rx diff --git a/labs/16_round_robin_arbiter/gtkwave.tcl b/labs/16_round_robin_arbiter/gtkwave.tcl deleted file mode 100644 index 7e659726..00000000 --- a/labs/16_round_robin_arbiter/gtkwave.tcl +++ /dev/null @@ -1,15 +0,0 @@ -# gtkwave::loadFile "dump.vcd" - -set all_signals [list] - -lappend all_signals tb.clk -lappend all_signals tb.rst -lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit - -set num_added [ gtkwave::addSignalsFromList $all_signals ] - -gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/16_round_robin_arbiter/lab_specific_config.svh b/labs/16_round_robin_arbiter/lab_specific_config.svh deleted file mode 100644 index 20899864..00000000 --- a/labs/16_round_robin_arbiter/lab_specific_config.svh +++ /dev/null @@ -1,16 +0,0 @@ -`ifndef LAB_SPECIFIC_CONFIG_SVH -`define LAB_SPECIFIC_CONFIG_SVH - -// The following setting is needed for Gowin boards - `define ENABLE_TM1638 - -// HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 - - `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS - - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM -// `define CONCAT_TM_SIGNALS_AND_REGULAR - -`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/17_geiger_muller_radiation_counter/gtkwave.tcl b/labs/17_geiger_muller_radiation_counter/gtkwave.tcl deleted file mode 100644 index 7e659726..00000000 --- a/labs/17_geiger_muller_radiation_counter/gtkwave.tcl +++ /dev/null @@ -1,15 +0,0 @@ -# gtkwave::loadFile "dump.vcd" - -set all_signals [list] - -lappend all_signals tb.clk -lappend all_signals tb.rst -lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit - -set num_added [ gtkwave::addSignalsFromList $all_signals ] - -gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_config.svh deleted file mode 100644 index ad213b90..00000000 --- a/labs/17_geiger_muller_radiation_counter/lab_specific_config.svh +++ /dev/null @@ -1,16 +0,0 @@ -`ifndef LAB_SPECIFIC_CONFIG_SVH -`define LAB_SPECIFIC_CONFIG_SVH - -// The following setting is needed for Gowin boards - `define ENABLE_TM1638 - -// HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 - -// `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS - -// `define DUPLICATE_TM_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM - `define CONCAT_TM_SIGNALS_AND_REGULAR - -`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/17_geiger_muller_radiation_counter/tb.sv b/labs/17_geiger_muller_radiation_counter/tb.sv deleted file mode 100644 index 878384bd..00000000 --- a/labs/17_geiger_muller_radiation_counter/tb.sv +++ /dev/null @@ -1,94 +0,0 @@ -`include "config.svh" - -module tb; - - localparam clk_mhz = 1, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100; - - //------------------------------------------------------------------------ - - logic clk; - logic rst; - logic [3:0] key; - logic [7:0] sw; - - //------------------------------------------------------------------------ - - top - # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_sw ), - .w_led ( w_led ), - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) - ) - i_top - ( - .clk ( clk ), - .slow_clk ( clk ), - .rst ( rst ), - .key ( key ), - .sw ( sw ) - ); - - //------------------------------------------------------------------------ - - initial - begin - clk = 1'b0; - - forever - # 5 clk = ~ clk; - end - - //------------------------------------------------------------------------ - - initial - begin - rst <= 1'bx; - repeat (2) @ (posedge clk); - rst <= 1'b1; - repeat (2) @ (posedge clk); - rst <= 1'b0; - end - - //------------------------------------------------------------------------ - - initial - begin - `ifdef __ICARUS__ - $dumpvars; - `endif - - key <= '0; - sw <= '0; - - @ (negedge rst); - - repeat (50) - begin - @ (posedge clk); - - key <= $urandom (); - sw <= $urandom (); - end - - // To change only one key - - key <= '0; - - repeat (50) - begin - @ (posedge clk); - key [0] <= $urandom (); - end - - $finish; - end - -endmodule diff --git a/labs/01_and_or_not_xor_de_morgan/01_clean.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/01_clean.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/01_clean.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/01_clean.bash diff --git a/labs/01_and_or_not_xor_de_morgan/02_simulate_rtl.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/02_simulate_rtl.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/02_simulate_rtl.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/02_simulate_rtl.bash diff --git a/labs/01_and_or_not_xor_de_morgan/03_synthesize_for_fpga.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/03_synthesize_for_fpga.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/03_synthesize_for_fpga.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/03_synthesize_for_fpga.bash diff --git a/labs/01_and_or_not_xor_de_morgan/04_configure_fpga.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/04_configure_fpga.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/04_configure_fpga.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/04_configure_fpga.bash diff --git a/labs/01_and_or_not_xor_de_morgan/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/01_and_or_not_xor_de_morgan/06_choose_another_fpga_board.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/06_choose_another_fpga_board.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/06_choose_another_fpga_board.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/06_choose_another_fpga_board.bash diff --git a/labs/01_and_or_not_xor_de_morgan/07_synthesize_for_asic.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/07_synthesize_for_asic.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/07_synthesize_for_asic.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/07_synthesize_for_asic.bash diff --git a/labs/01_and_or_not_xor_de_morgan/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/01_and_or_not_xor_de_morgan/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_01_and_or_not_xor_de_morgan/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/01_and_or_not_xor_de_morgan/top.sv b/labs/1_basics/1_01_and_or_not_xor_de_morgan/lab_top.sv similarity index 78% rename from labs/01_and_or_not_xor_de_morgan/top.sv rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/lab_top.sv index 3c26ba54..8f7df9c7 100644 --- a/labs/01_and_or_not_xor_de_morgan/top.sv +++ b/labs/1_basics/1_01_and_or_not_xor_de_morgan/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/01_and_or_not_xor_de_morgan/tb.sv b/labs/1_basics/1_01_and_or_not_xor_de_morgan/tb.sv similarity index 97% rename from labs/01_and_or_not_xor_de_morgan/tb.sv rename to labs/1_basics/1_01_and_or_not_xor_de_morgan/tb.sv index f8c334f3..4c88f3b5 100644 --- a/labs/01_and_or_not_xor_de_morgan/tb.sv +++ b/labs/1_basics/1_01_and_or_not_xor_de_morgan/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/02_mux/01_clean.bash b/labs/1_basics/1_02_mux/01_clean.bash similarity index 100% rename from labs/02_mux/01_clean.bash rename to labs/1_basics/1_02_mux/01_clean.bash diff --git a/labs/02_mux/02_simulate_rtl.bash b/labs/1_basics/1_02_mux/02_simulate_rtl.bash similarity index 100% rename from labs/02_mux/02_simulate_rtl.bash rename to labs/1_basics/1_02_mux/02_simulate_rtl.bash diff --git a/labs/02_mux/03_synthesize_for_fpga.bash b/labs/1_basics/1_02_mux/03_synthesize_for_fpga.bash similarity index 100% rename from labs/02_mux/03_synthesize_for_fpga.bash rename to labs/1_basics/1_02_mux/03_synthesize_for_fpga.bash diff --git a/labs/02_mux/04_configure_fpga.bash b/labs/1_basics/1_02_mux/04_configure_fpga.bash similarity index 100% rename from labs/02_mux/04_configure_fpga.bash rename to labs/1_basics/1_02_mux/04_configure_fpga.bash diff --git a/labs/02_mux/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_02_mux/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/02_mux/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_02_mux/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/02_mux/06_choose_another_fpga_board.bash b/labs/1_basics/1_02_mux/06_choose_another_fpga_board.bash similarity index 100% rename from labs/02_mux/06_choose_another_fpga_board.bash rename to labs/1_basics/1_02_mux/06_choose_another_fpga_board.bash diff --git a/labs/02_mux/07_synthesize_for_asic.bash b/labs/1_basics/1_02_mux/07_synthesize_for_asic.bash similarity index 100% rename from labs/02_mux/07_synthesize_for_asic.bash rename to labs/1_basics/1_02_mux/07_synthesize_for_asic.bash diff --git a/labs/02_mux/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_02_mux/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/02_mux/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_02_mux/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/02_mux/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_02_mux/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/02_mux/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_02_mux/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/02_mux/gtkwave.tcl b/labs/1_basics/1_02_mux/gtkwave.tcl similarity index 87% rename from labs/02_mux/gtkwave.tcl rename to labs/1_basics/1_02_mux/gtkwave.tcl index 7a319bb3..de52ed19 100644 --- a/labs/02_mux/gtkwave.tcl +++ b/labs/1_basics/1_02_mux/gtkwave.tcl @@ -8,7 +8,7 @@ lappend all_signals tb.b lappend all_signals tb.key lappend all_signals tb.led lappend all_signals {tb.led[0]} -lappend all_signals tb.i_top.all_muxes +lappend all_signals tb.i_lab_top.all_muxes set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/02_mux/top.sv b/labs/1_basics/1_02_mux/lab_top.sv similarity index 91% rename from labs/02_mux/top.sv rename to labs/1_basics/1_02_mux/lab_top.sv index a057b074..3c5a6dac 100644 --- a/labs/02_mux/top.sv +++ b/labs/1_basics/1_02_mux/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; @@ -93,7 +96,7 @@ module top //------------------------------------------------------------------------ wire [1:0] ab = { a, b }; - assign mux1 = ab [sel]; + wire mux1 = ab [sel]; //------------------------------------------------------------------------ diff --git a/labs/02_mux/tb.sv b/labs/1_basics/1_02_mux/tb.sv similarity index 93% rename from labs/02_mux/tb.sv rename to labs/1_basics/1_02_mux/tb.sv index 77ea60ff..4417e6c6 100644 --- a/labs/02_mux/tb.sv +++ b/labs/1_basics/1_02_mux/tb.sv @@ -19,7 +19,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -28,7 +28,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), @@ -57,8 +57,8 @@ module tb; //-------------------------------------------------------------------- // Checking multiple bits - if ($bits (i_top.all_muxes) < $bits (led)) - n_muxes_to_check = $bits (i_top.all_muxes); + if ($bits (i_lab_top.all_muxes) < $bits (led)) + n_muxes_to_check = $bits (i_lab_top.all_muxes); else n_muxes_to_check = $bits (led); @@ -74,9 +74,9 @@ module tb; //-------------------------------------------------------------------- // White-box testing - checking XMR (external module reference) - for (int i = 0; i < $bits (i_top.all_muxes); i ++) + for (int i = 0; i < $bits (i_lab_top.all_muxes); i ++) begin - result = i_top.all_muxes [i]; + result = i_lab_top.all_muxes [i]; if (result !== expected) $display ("Mismatch in mux %0d: %b ? %b : %b. expected: %b actual: %b", diff --git a/labs/03_decoder/01_clean.bash b/labs/1_basics/1_03_decoder/01_clean.bash similarity index 100% rename from labs/03_decoder/01_clean.bash rename to labs/1_basics/1_03_decoder/01_clean.bash diff --git a/labs/03_decoder/02_simulate_rtl.bash b/labs/1_basics/1_03_decoder/02_simulate_rtl.bash similarity index 100% rename from labs/03_decoder/02_simulate_rtl.bash rename to labs/1_basics/1_03_decoder/02_simulate_rtl.bash diff --git a/labs/03_decoder/03_synthesize_for_fpga.bash b/labs/1_basics/1_03_decoder/03_synthesize_for_fpga.bash similarity index 100% rename from labs/03_decoder/03_synthesize_for_fpga.bash rename to labs/1_basics/1_03_decoder/03_synthesize_for_fpga.bash diff --git a/labs/03_decoder/04_configure_fpga.bash b/labs/1_basics/1_03_decoder/04_configure_fpga.bash similarity index 100% rename from labs/03_decoder/04_configure_fpga.bash rename to labs/1_basics/1_03_decoder/04_configure_fpga.bash diff --git a/labs/03_decoder/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_03_decoder/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/03_decoder/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_03_decoder/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/03_decoder/06_choose_another_fpga_board.bash b/labs/1_basics/1_03_decoder/06_choose_another_fpga_board.bash similarity index 100% rename from labs/03_decoder/06_choose_another_fpga_board.bash rename to labs/1_basics/1_03_decoder/06_choose_another_fpga_board.bash diff --git a/labs/03_decoder/07_synthesize_for_asic.bash b/labs/1_basics/1_03_decoder/07_synthesize_for_asic.bash similarity index 100% rename from labs/03_decoder/07_synthesize_for_asic.bash rename to labs/1_basics/1_03_decoder/07_synthesize_for_asic.bash diff --git a/labs/03_decoder/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_03_decoder/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/03_decoder/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_03_decoder/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/03_decoder/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_03_decoder/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/03_decoder/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_03_decoder/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/03_decoder/top.sv b/labs/1_basics/1_03_decoder/lab_top.sv similarity index 76% rename from labs/03_decoder/top.sv rename to labs/1_basics/1_03_decoder/lab_top.sv index f9275241..f9e8f378 100644 --- a/labs/03_decoder/top.sv +++ b/labs/1_basics/1_03_decoder/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/03_decoder/tb.sv b/labs/1_basics/1_03_decoder/tb.sv similarity index 97% rename from labs/03_decoder/tb.sv rename to labs/1_basics/1_03_decoder/tb.sv index f8c334f3..4c88f3b5 100644 --- a/labs/03_decoder/tb.sv +++ b/labs/1_basics/1_03_decoder/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/04_priority_encoder/01_clean.bash b/labs/1_basics/1_04_priority_encoder/01_clean.bash similarity index 100% rename from labs/04_priority_encoder/01_clean.bash rename to labs/1_basics/1_04_priority_encoder/01_clean.bash diff --git a/labs/04_priority_encoder/02_simulate_rtl.bash b/labs/1_basics/1_04_priority_encoder/02_simulate_rtl.bash similarity index 100% rename from labs/04_priority_encoder/02_simulate_rtl.bash rename to labs/1_basics/1_04_priority_encoder/02_simulate_rtl.bash diff --git a/labs/04_priority_encoder/03_synthesize_for_fpga.bash b/labs/1_basics/1_04_priority_encoder/03_synthesize_for_fpga.bash similarity index 100% rename from labs/04_priority_encoder/03_synthesize_for_fpga.bash rename to labs/1_basics/1_04_priority_encoder/03_synthesize_for_fpga.bash diff --git a/labs/04_priority_encoder/04_configure_fpga.bash b/labs/1_basics/1_04_priority_encoder/04_configure_fpga.bash similarity index 100% rename from labs/04_priority_encoder/04_configure_fpga.bash rename to labs/1_basics/1_04_priority_encoder/04_configure_fpga.bash diff --git a/labs/04_priority_encoder/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_04_priority_encoder/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/04_priority_encoder/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_04_priority_encoder/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/04_priority_encoder/06_choose_another_fpga_board.bash b/labs/1_basics/1_04_priority_encoder/06_choose_another_fpga_board.bash similarity index 100% rename from labs/04_priority_encoder/06_choose_another_fpga_board.bash rename to labs/1_basics/1_04_priority_encoder/06_choose_another_fpga_board.bash diff --git a/labs/04_priority_encoder/07_synthesize_for_asic.bash b/labs/1_basics/1_04_priority_encoder/07_synthesize_for_asic.bash similarity index 100% rename from labs/04_priority_encoder/07_synthesize_for_asic.bash rename to labs/1_basics/1_04_priority_encoder/07_synthesize_for_asic.bash diff --git a/labs/04_priority_encoder/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_04_priority_encoder/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/04_priority_encoder/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_04_priority_encoder/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/04_priority_encoder/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_04_priority_encoder/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/04_priority_encoder/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_04_priority_encoder/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/04_priority_encoder/top.sv b/labs/1_basics/1_04_priority_encoder/lab_top.sv similarity index 87% rename from labs/04_priority_encoder/top.sv rename to labs/1_basics/1_04_priority_encoder/lab_top.sv index 33a0566c..f42a1c00 100644 --- a/labs/04_priority_encoder/top.sv +++ b/labs/1_basics/1_04_priority_encoder/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/04_priority_encoder/tb.sv b/labs/1_basics/1_04_priority_encoder/tb.sv similarity index 97% rename from labs/04_priority_encoder/tb.sv rename to labs/1_basics/1_04_priority_encoder/tb.sv index f8c334f3..4c88f3b5 100644 --- a/labs/04_priority_encoder/tb.sv +++ b/labs/1_basics/1_04_priority_encoder/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/05_7seven_segment_letter/01_clean.bash b/labs/1_basics/1_05_7seven_segment_letter/01_clean.bash similarity index 100% rename from labs/05_7seven_segment_letter/01_clean.bash rename to labs/1_basics/1_05_7seven_segment_letter/01_clean.bash diff --git a/labs/05_7seven_segment_letter/02_simulate_rtl.bash b/labs/1_basics/1_05_7seven_segment_letter/02_simulate_rtl.bash similarity index 100% rename from labs/05_7seven_segment_letter/02_simulate_rtl.bash rename to labs/1_basics/1_05_7seven_segment_letter/02_simulate_rtl.bash diff --git a/labs/05_7seven_segment_letter/03_synthesize_for_fpga.bash b/labs/1_basics/1_05_7seven_segment_letter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/05_7seven_segment_letter/03_synthesize_for_fpga.bash rename to labs/1_basics/1_05_7seven_segment_letter/03_synthesize_for_fpga.bash diff --git a/labs/05_7seven_segment_letter/04_configure_fpga.bash b/labs/1_basics/1_05_7seven_segment_letter/04_configure_fpga.bash similarity index 100% rename from labs/05_7seven_segment_letter/04_configure_fpga.bash rename to labs/1_basics/1_05_7seven_segment_letter/04_configure_fpga.bash diff --git a/labs/05_7seven_segment_letter/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_05_7seven_segment_letter/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/05_7seven_segment_letter/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_05_7seven_segment_letter/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/05_7seven_segment_letter/06_choose_another_fpga_board.bash b/labs/1_basics/1_05_7seven_segment_letter/06_choose_another_fpga_board.bash similarity index 100% rename from labs/05_7seven_segment_letter/06_choose_another_fpga_board.bash rename to labs/1_basics/1_05_7seven_segment_letter/06_choose_another_fpga_board.bash diff --git a/labs/05_7seven_segment_letter/07_synthesize_for_asic.bash b/labs/1_basics/1_05_7seven_segment_letter/07_synthesize_for_asic.bash similarity index 100% rename from labs/05_7seven_segment_letter/07_synthesize_for_asic.bash rename to labs/1_basics/1_05_7seven_segment_letter/07_synthesize_for_asic.bash diff --git a/labs/05_7seven_segment_letter/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_05_7seven_segment_letter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/05_7seven_segment_letter/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_05_7seven_segment_letter/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/05_7seven_segment_letter/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_05_7seven_segment_letter/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/05_7seven_segment_letter/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_05_7seven_segment_letter/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/1_basics/1_05_7seven_segment_letter/lab_specific_board_config.svh b/labs/1_basics/1_05_7seven_segment_letter/lab_specific_board_config.svh new file mode 100644 index 00000000..752d2929 --- /dev/null +++ b/labs/1_basics/1_05_7seven_segment_letter/lab_specific_board_config.svh @@ -0,0 +1,17 @@ +`ifndef LAB_SPECIFIC_CONFIG_SVH +`define LAB_SPECIFIC_CONFIG_SVH + + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE + + `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 +// `define CONCAT_TM1638_SIGNALS_AND_REGULAR + + `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + +`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/05_7seven_segment_letter/top.sv b/labs/1_basics/1_05_7seven_segment_letter/lab_top.sv similarity index 77% rename from labs/05_7seven_segment_letter/top.sv rename to labs/1_basics/1_05_7seven_segment_letter/lab_top.sv index e9dd667d..19f4d02a 100644 --- a/labs/05_7seven_segment_letter/top.sv +++ b/labs/1_basics/1_05_7seven_segment_letter/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/05_7seven_segment_letter/seven_segment_alphabet.jpg b/labs/1_basics/1_05_7seven_segment_letter/seven_segment_alphabet.jpg similarity index 100% rename from labs/05_7seven_segment_letter/seven_segment_alphabet.jpg rename to labs/1_basics/1_05_7seven_segment_letter/seven_segment_alphabet.jpg diff --git a/labs/05_7seven_segment_letter/seven_segment_font_editor.jpg b/labs/1_basics/1_05_7seven_segment_letter/seven_segment_font_editor.jpg similarity index 100% rename from labs/05_7seven_segment_letter/seven_segment_font_editor.jpg rename to labs/1_basics/1_05_7seven_segment_letter/seven_segment_font_editor.jpg diff --git a/labs/05_7seven_segment_letter/tb.sv b/labs/1_basics/1_05_7seven_segment_letter/tb.sv similarity index 97% rename from labs/05_7seven_segment_letter/tb.sv rename to labs/1_basics/1_05_7seven_segment_letter/tb.sv index f8c334f3..4c88f3b5 100644 --- a/labs/05_7seven_segment_letter/tb.sv +++ b/labs/1_basics/1_05_7seven_segment_letter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/06_vga/01_clean.bash b/labs/1_basics/1_06_binary_counter/01_clean.bash similarity index 100% rename from labs/06_vga/01_clean.bash rename to labs/1_basics/1_06_binary_counter/01_clean.bash diff --git a/labs/06_vga/02_simulate_rtl.bash b/labs/1_basics/1_06_binary_counter/02_simulate_rtl.bash similarity index 100% rename from labs/06_vga/02_simulate_rtl.bash rename to labs/1_basics/1_06_binary_counter/02_simulate_rtl.bash diff --git a/labs/06_vga/03_synthesize_for_fpga.bash b/labs/1_basics/1_06_binary_counter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/06_vga/03_synthesize_for_fpga.bash rename to labs/1_basics/1_06_binary_counter/03_synthesize_for_fpga.bash diff --git a/labs/06_vga/04_configure_fpga.bash b/labs/1_basics/1_06_binary_counter/04_configure_fpga.bash similarity index 100% rename from labs/06_vga/04_configure_fpga.bash rename to labs/1_basics/1_06_binary_counter/04_configure_fpga.bash diff --git a/labs/06_vga/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_06_binary_counter/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/06_vga/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_06_binary_counter/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/06_vga/06_choose_another_fpga_board.bash b/labs/1_basics/1_06_binary_counter/06_choose_another_fpga_board.bash similarity index 100% rename from labs/06_vga/06_choose_another_fpga_board.bash rename to labs/1_basics/1_06_binary_counter/06_choose_another_fpga_board.bash diff --git a/labs/06_vga/07_synthesize_for_asic.bash b/labs/1_basics/1_06_binary_counter/07_synthesize_for_asic.bash similarity index 100% rename from labs/06_vga/07_synthesize_for_asic.bash rename to labs/1_basics/1_06_binary_counter/07_synthesize_for_asic.bash diff --git a/labs/06_vga/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_06_binary_counter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/06_vga/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_06_binary_counter/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/06_vga/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_06_binary_counter/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/06_vga/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_06_binary_counter/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/09_7segment_word/gtkwave.tcl b/labs/1_basics/1_06_binary_counter/gtkwave.tcl similarity index 59% rename from labs/09_7segment_word/gtkwave.tcl rename to labs/1_basics/1_06_binary_counter/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/09_7segment_word/gtkwave.tcl +++ b/labs/1_basics/1_06_binary_counter/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/07_binary_counter/top.sv b/labs/1_basics/1_06_binary_counter/lab_top.sv similarity index 79% rename from labs/07_binary_counter/top.sv rename to labs/1_basics/1_06_binary_counter/lab_top.sv index 2a2c44ca..aec29cec 100644 --- a/labs/07_binary_counter/top.sv +++ b/labs/1_basics/1_06_binary_counter/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/07_binary_counter/tb.sv b/labs/1_basics/1_06_binary_counter/tb.sv similarity index 98% rename from labs/07_binary_counter/tb.sv rename to labs/1_basics/1_06_binary_counter/tb.sv index 878384bd..643cf7b7 100644 --- a/labs/07_binary_counter/tb.sv +++ b/labs/1_basics/1_06_binary_counter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/07_binary_counter/01_clean.bash b/labs/1_basics/1_07_shift_register/01_clean.bash similarity index 100% rename from labs/07_binary_counter/01_clean.bash rename to labs/1_basics/1_07_shift_register/01_clean.bash diff --git a/labs/07_binary_counter/02_simulate_rtl.bash b/labs/1_basics/1_07_shift_register/02_simulate_rtl.bash similarity index 100% rename from labs/07_binary_counter/02_simulate_rtl.bash rename to labs/1_basics/1_07_shift_register/02_simulate_rtl.bash diff --git a/labs/07_binary_counter/03_synthesize_for_fpga.bash b/labs/1_basics/1_07_shift_register/03_synthesize_for_fpga.bash similarity index 100% rename from labs/07_binary_counter/03_synthesize_for_fpga.bash rename to labs/1_basics/1_07_shift_register/03_synthesize_for_fpga.bash diff --git a/labs/07_binary_counter/04_configure_fpga.bash b/labs/1_basics/1_07_shift_register/04_configure_fpga.bash similarity index 100% rename from labs/07_binary_counter/04_configure_fpga.bash rename to labs/1_basics/1_07_shift_register/04_configure_fpga.bash diff --git a/labs/07_binary_counter/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_07_shift_register/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/07_binary_counter/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_07_shift_register/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/07_binary_counter/06_choose_another_fpga_board.bash b/labs/1_basics/1_07_shift_register/06_choose_another_fpga_board.bash similarity index 100% rename from labs/07_binary_counter/06_choose_another_fpga_board.bash rename to labs/1_basics/1_07_shift_register/06_choose_another_fpga_board.bash diff --git a/labs/07_binary_counter/07_synthesize_for_asic.bash b/labs/1_basics/1_07_shift_register/07_synthesize_for_asic.bash similarity index 100% rename from labs/07_binary_counter/07_synthesize_for_asic.bash rename to labs/1_basics/1_07_shift_register/07_synthesize_for_asic.bash diff --git a/labs/07_binary_counter/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_07_shift_register/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/07_binary_counter/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_07_shift_register/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/07_binary_counter/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_07_shift_register/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/07_binary_counter/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_07_shift_register/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/07_binary_counter/gtkwave.tcl b/labs/1_basics/1_07_shift_register/gtkwave.tcl similarity index 59% rename from labs/07_binary_counter/gtkwave.tcl rename to labs/1_basics/1_07_shift_register/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/07_binary_counter/gtkwave.tcl +++ b/labs/1_basics/1_07_shift_register/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/08_shift_register/top.sv b/labs/1_basics/1_07_shift_register/lab_top.sv similarity index 76% rename from labs/08_shift_register/top.sv rename to labs/1_basics/1_07_shift_register/lab_top.sv index 549d790f..af332d93 100644 --- a/labs/08_shift_register/top.sv +++ b/labs/1_basics/1_07_shift_register/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/08_shift_register/tb.sv b/labs/1_basics/1_07_shift_register/tb.sv similarity index 93% rename from labs/08_shift_register/tb.sv rename to labs/1_basics/1_07_shift_register/tb.sv index 715355d9..a8b16f8d 100644 --- a/labs/08_shift_register/tb.sv +++ b/labs/1_basics/1_07_shift_register/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), @@ -75,9 +75,9 @@ module tb; // Enable override if (i == 20) - force i_top.enable = 1'b1; + force i_lab_top.enable = 1'b1; else if (i == 40) - release i_top.enable; + release i_lab_top.enable; @ (posedge clk); diff --git a/labs/08_shift_register/01_clean.bash b/labs/1_basics/1_08_7segment_word/01_clean.bash similarity index 100% rename from labs/08_shift_register/01_clean.bash rename to labs/1_basics/1_08_7segment_word/01_clean.bash diff --git a/labs/08_shift_register/02_simulate_rtl.bash b/labs/1_basics/1_08_7segment_word/02_simulate_rtl.bash similarity index 100% rename from labs/08_shift_register/02_simulate_rtl.bash rename to labs/1_basics/1_08_7segment_word/02_simulate_rtl.bash diff --git a/labs/08_shift_register/03_synthesize_for_fpga.bash b/labs/1_basics/1_08_7segment_word/03_synthesize_for_fpga.bash similarity index 100% rename from labs/08_shift_register/03_synthesize_for_fpga.bash rename to labs/1_basics/1_08_7segment_word/03_synthesize_for_fpga.bash diff --git a/labs/08_shift_register/04_configure_fpga.bash b/labs/1_basics/1_08_7segment_word/04_configure_fpga.bash similarity index 100% rename from labs/08_shift_register/04_configure_fpga.bash rename to labs/1_basics/1_08_7segment_word/04_configure_fpga.bash diff --git a/labs/08_shift_register/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_08_7segment_word/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/08_shift_register/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_08_7segment_word/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/08_shift_register/06_choose_another_fpga_board.bash b/labs/1_basics/1_08_7segment_word/06_choose_another_fpga_board.bash similarity index 100% rename from labs/08_shift_register/06_choose_another_fpga_board.bash rename to labs/1_basics/1_08_7segment_word/06_choose_another_fpga_board.bash diff --git a/labs/08_shift_register/07_synthesize_for_asic.bash b/labs/1_basics/1_08_7segment_word/07_synthesize_for_asic.bash similarity index 100% rename from labs/08_shift_register/07_synthesize_for_asic.bash rename to labs/1_basics/1_08_7segment_word/07_synthesize_for_asic.bash diff --git a/labs/08_shift_register/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_08_7segment_word/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/08_shift_register/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_08_7segment_word/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/08_shift_register/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_08_7segment_word/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/08_shift_register/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_08_7segment_word/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/10_hex_counter/gtkwave.tcl b/labs/1_basics/1_08_7segment_word/gtkwave.tcl similarity index 59% rename from labs/10_hex_counter/gtkwave.tcl rename to labs/1_basics/1_08_7segment_word/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/10_hex_counter/gtkwave.tcl +++ b/labs/1_basics/1_08_7segment_word/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/1_basics/1_08_7segment_word/lab_specific_board_config.svh b/labs/1_basics/1_08_7segment_word/lab_specific_board_config.svh new file mode 100644 index 00000000..752d2929 --- /dev/null +++ b/labs/1_basics/1_08_7segment_word/lab_specific_board_config.svh @@ -0,0 +1,17 @@ +`ifndef LAB_SPECIFIC_CONFIG_SVH +`define LAB_SPECIFIC_CONFIG_SVH + + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE + + `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 +// `define CONCAT_TM1638_SIGNALS_AND_REGULAR + + `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + +`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/09_7segment_word/top.sv b/labs/1_basics/1_08_7segment_word/lab_top.sv similarity index 81% rename from labs/09_7segment_word/top.sv rename to labs/1_basics/1_08_7segment_word/lab_top.sv index c4fb41a7..3b9edea4 100644 --- a/labs/09_7segment_word/top.sv +++ b/labs/1_basics/1_08_7segment_word/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/09_7segment_word/seven_segment_alphabet.jpg b/labs/1_basics/1_08_7segment_word/seven_segment_alphabet.jpg similarity index 100% rename from labs/09_7segment_word/seven_segment_alphabet.jpg rename to labs/1_basics/1_08_7segment_word/seven_segment_alphabet.jpg diff --git a/labs/09_7segment_word/seven_segment_font_editor.jpg b/labs/1_basics/1_08_7segment_word/seven_segment_font_editor.jpg similarity index 100% rename from labs/09_7segment_word/seven_segment_font_editor.jpg rename to labs/1_basics/1_08_7segment_word/seven_segment_font_editor.jpg diff --git a/labs/09_7segment_word/tb.sv b/labs/1_basics/1_08_7segment_word/tb.sv similarity index 93% rename from labs/09_7segment_word/tb.sv rename to labs/1_basics/1_08_7segment_word/tb.sv index 715355d9..a8b16f8d 100644 --- a/labs/09_7segment_word/tb.sv +++ b/labs/1_basics/1_08_7segment_word/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), @@ -75,9 +75,9 @@ module tb; // Enable override if (i == 20) - force i_top.enable = 1'b1; + force i_lab_top.enable = 1'b1; else if (i == 40) - release i_top.enable; + release i_lab_top.enable; @ (posedge clk); diff --git a/labs/09_7segment_word/01_clean.bash b/labs/1_basics/1_09_hex_counter/01_clean.bash similarity index 100% rename from labs/09_7segment_word/01_clean.bash rename to labs/1_basics/1_09_hex_counter/01_clean.bash diff --git a/labs/09_7segment_word/02_simulate_rtl.bash b/labs/1_basics/1_09_hex_counter/02_simulate_rtl.bash similarity index 100% rename from labs/09_7segment_word/02_simulate_rtl.bash rename to labs/1_basics/1_09_hex_counter/02_simulate_rtl.bash diff --git a/labs/09_7segment_word/03_synthesize_for_fpga.bash b/labs/1_basics/1_09_hex_counter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/09_7segment_word/03_synthesize_for_fpga.bash rename to labs/1_basics/1_09_hex_counter/03_synthesize_for_fpga.bash diff --git a/labs/09_7segment_word/04_configure_fpga.bash b/labs/1_basics/1_09_hex_counter/04_configure_fpga.bash similarity index 100% rename from labs/09_7segment_word/04_configure_fpga.bash rename to labs/1_basics/1_09_hex_counter/04_configure_fpga.bash diff --git a/labs/09_7segment_word/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_09_hex_counter/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/09_7segment_word/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_09_hex_counter/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/09_7segment_word/06_choose_another_fpga_board.bash b/labs/1_basics/1_09_hex_counter/06_choose_another_fpga_board.bash similarity index 100% rename from labs/09_7segment_word/06_choose_another_fpga_board.bash rename to labs/1_basics/1_09_hex_counter/06_choose_another_fpga_board.bash diff --git a/labs/09_7segment_word/07_synthesize_for_asic.bash b/labs/1_basics/1_09_hex_counter/07_synthesize_for_asic.bash similarity index 100% rename from labs/09_7segment_word/07_synthesize_for_asic.bash rename to labs/1_basics/1_09_hex_counter/07_synthesize_for_asic.bash diff --git a/labs/09_7segment_word/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_09_hex_counter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/09_7segment_word/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_09_hex_counter/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/09_7segment_word/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_09_hex_counter/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/09_7segment_word/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_09_hex_counter/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/08_shift_register/gtkwave.tcl b/labs/1_basics/1_09_hex_counter/gtkwave.tcl similarity index 59% rename from labs/08_shift_register/gtkwave.tcl rename to labs/1_basics/1_09_hex_counter/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/08_shift_register/gtkwave.tcl +++ b/labs/1_basics/1_09_hex_counter/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/10_hex_counter/top.sv b/labs/1_basics/1_09_hex_counter/lab_top.sv similarity index 83% rename from labs/10_hex_counter/top.sv rename to labs/1_basics/1_09_hex_counter/lab_top.sv index 5f09e9ed..c4c97265 100644 --- a/labs/10_hex_counter/top.sv +++ b/labs/1_basics/1_09_hex_counter/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/12_snail_fsm/tb.sv b/labs/1_basics/1_09_hex_counter/tb.sv similarity index 98% rename from labs/12_snail_fsm/tb.sv rename to labs/1_basics/1_09_hex_counter/tb.sv index 878384bd..643cf7b7 100644 --- a/labs/12_snail_fsm/tb.sv +++ b/labs/1_basics/1_09_hex_counter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/10_hex_counter/01_clean.bash b/labs/1_basics/1_10_snail_fsm/01_clean.bash similarity index 100% rename from labs/10_hex_counter/01_clean.bash rename to labs/1_basics/1_10_snail_fsm/01_clean.bash diff --git a/labs/10_hex_counter/02_simulate_rtl.bash b/labs/1_basics/1_10_snail_fsm/02_simulate_rtl.bash similarity index 100% rename from labs/10_hex_counter/02_simulate_rtl.bash rename to labs/1_basics/1_10_snail_fsm/02_simulate_rtl.bash diff --git a/labs/10_hex_counter/03_synthesize_for_fpga.bash b/labs/1_basics/1_10_snail_fsm/03_synthesize_for_fpga.bash similarity index 100% rename from labs/10_hex_counter/03_synthesize_for_fpga.bash rename to labs/1_basics/1_10_snail_fsm/03_synthesize_for_fpga.bash diff --git a/labs/10_hex_counter/04_configure_fpga.bash b/labs/1_basics/1_10_snail_fsm/04_configure_fpga.bash similarity index 100% rename from labs/10_hex_counter/04_configure_fpga.bash rename to labs/1_basics/1_10_snail_fsm/04_configure_fpga.bash diff --git a/labs/10_hex_counter/05_run_gui_for_fpga_synthesis.bash b/labs/1_basics/1_10_snail_fsm/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/10_hex_counter/05_run_gui_for_fpga_synthesis.bash rename to labs/1_basics/1_10_snail_fsm/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/10_hex_counter/06_choose_another_fpga_board.bash b/labs/1_basics/1_10_snail_fsm/06_choose_another_fpga_board.bash similarity index 100% rename from labs/10_hex_counter/06_choose_another_fpga_board.bash rename to labs/1_basics/1_10_snail_fsm/06_choose_another_fpga_board.bash diff --git a/labs/10_hex_counter/07_synthesize_for_asic.bash b/labs/1_basics/1_10_snail_fsm/07_synthesize_for_asic.bash similarity index 100% rename from labs/10_hex_counter/07_synthesize_for_asic.bash rename to labs/1_basics/1_10_snail_fsm/07_synthesize_for_asic.bash diff --git a/labs/10_hex_counter/08_visualize_asic_synthesis_results_1.bash b/labs/1_basics/1_10_snail_fsm/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/10_hex_counter/08_visualize_asic_synthesis_results_1.bash rename to labs/1_basics/1_10_snail_fsm/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/10_hex_counter/09_visualize_asic_synthesis_results_2.bash b/labs/1_basics/1_10_snail_fsm/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/10_hex_counter/09_visualize_asic_synthesis_results_2.bash rename to labs/1_basics/1_10_snail_fsm/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/12_snail_fsm/top.sv b/labs/1_basics/1_10_snail_fsm/lab_top.sv similarity index 79% rename from labs/12_snail_fsm/top.sv rename to labs/1_basics/1_10_snail_fsm/lab_top.sv index 3c79b20c..6f869d09 100644 --- a/labs/12_snail_fsm/top.sv +++ b/labs/1_basics/1_10_snail_fsm/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/12_snail_fsm/snail_mealy_fsm.sv b/labs/1_basics/1_10_snail_fsm/snail_mealy_fsm.sv similarity index 100% rename from labs/12_snail_fsm/snail_mealy_fsm.sv rename to labs/1_basics/1_10_snail_fsm/snail_mealy_fsm.sv diff --git a/labs/12_snail_fsm/snail_moore_fsm.sv b/labs/1_basics/1_10_snail_fsm/snail_moore_fsm.sv similarity index 100% rename from labs/12_snail_fsm/snail_moore_fsm.sv rename to labs/1_basics/1_10_snail_fsm/snail_moore_fsm.sv diff --git a/labs/15_uart/tb.sv b/labs/1_basics/1_10_snail_fsm/tb.sv similarity index 98% rename from labs/15_uart/tb.sv rename to labs/1_basics/1_10_snail_fsm/tb.sv index 878384bd..643cf7b7 100644 --- a/labs/15_uart/tb.sv +++ b/labs/1_basics/1_10_snail_fsm/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/11_note_recognition/01_clean.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/01_clean.bash similarity index 100% rename from labs/11_note_recognition/01_clean.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/01_clean.bash diff --git a/labs/11_note_recognition/02_simulate_rtl.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/02_simulate_rtl.bash similarity index 100% rename from labs/11_note_recognition/02_simulate_rtl.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/02_simulate_rtl.bash diff --git a/labs/11_note_recognition/03_synthesize_for_fpga.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/03_synthesize_for_fpga.bash similarity index 100% rename from labs/11_note_recognition/03_synthesize_for_fpga.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/03_synthesize_for_fpga.bash diff --git a/labs/11_note_recognition/04_configure_fpga.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/04_configure_fpga.bash similarity index 100% rename from labs/11_note_recognition/04_configure_fpga.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/04_configure_fpga.bash diff --git a/labs/11_note_recognition/05_run_gui_for_fpga_synthesis.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/11_note_recognition/05_run_gui_for_fpga_synthesis.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/11_note_recognition/06_choose_another_fpga_board.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/06_choose_another_fpga_board.bash similarity index 100% rename from labs/11_note_recognition/06_choose_another_fpga_board.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/06_choose_another_fpga_board.bash diff --git a/labs/11_note_recognition/07_synthesize_for_asic.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/07_synthesize_for_asic.bash similarity index 100% rename from labs/11_note_recognition/07_synthesize_for_asic.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/07_synthesize_for_asic.bash diff --git a/labs/11_note_recognition/08_visualize_asic_synthesis_results_1.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/11_note_recognition/08_visualize_asic_synthesis_results_1.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/11_note_recognition/09_visualize_asic_synthesis_results_2.bash b/labs/2_graphics/2_1_rectangle_ellipse_parabola/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/11_note_recognition/09_visualize_asic_synthesis_results_2.bash rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/06_vga/top.sv b/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv similarity index 52% rename from labs/06_vga/top.sv rename to labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv index f1e84090..605c8812 100644 --- a/labs/06_vga/top.sv +++ b/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv @@ -1,18 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -30,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -56,83 +62,44 @@ module top assign led = '0; assign abcdefgh = '0; assign digit = '0; - // assign vsync = '0; - // assign hsync = '0; // assign red = '0; // assign green = '0; // assign blue = '0; - // assign display_on = '0; - // assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; - //------------------------------------------------------------------------ - - localparam w_x = 10, w_y = 10; - - //------------------------------------------------------------------------ - - wire [w_x - 1:0] x; - wire [w_y - 1:0] y; - - vga - # ( - .HPOS_WIDTH ( w_x ), - .VPOS_WIDTH ( w_y ), - - .CLK_MHZ ( clk_mhz ), - .PIXEL_MHZ ( pixel_mhz ) - ) - i_vga - ( - .clk ( clk ), - .rst ( rst ), - .hsync ( hsync ), - .vsync ( vsync ), - .display_on ( display_on ), - .hpos ( x ), - .vpos ( y ), - .pixel_clk ( pixel_clk ) - ); - //------------------------------------------------------------------------ // Pattern 1 - /**/ - wire [w_x * 2 - 1:0] x_2 = x * x; + /**/ + always_comb begin red = '0; green = '0; blue = '0; - if (~ display_on) - begin - end - else if (x > 100 & y > 100 & x < 150 & y < 400) // Rectangle + if ( x >= screen_width / 2 + & x < screen_width * 2 / 3 + & y >= screen_height / 2 + & y < screen_height * 2 / 3 ) begin - red = x [w_x - 2 -: w_red]; - green = '1; - blue = y [w_y - 2 -: w_blue]; + green = x [w_x - 2 -: w_green]; end + `ifdef YOSYS - else if ((((x - 400) * (x - 400)) + 2 * (y - 300) * (y - 300) ) < (100 * 100)) // Ellipse + if (x * x + 2 * y * y < screen_width * screen_width / 4) // Ellipse `else - else if ((((x - 400) ** 2) + 2 * (y - 300) ** 2) < 100 ** 2) // Ellipse + if (x ** 2 + 2 * y ** 2 < (screen_width / 2) ** 2) // Ellipse `endif begin - red = '1; - green = x [w_x - 2 -: w_green]; - blue = y [w_y - 2 -: w_blue]; - end - else if (x_2 [9 +: w_y] < y) // Parabola - begin - red = x [w_x - 2 -: w_red]; - green = y [w_y - 2 -: w_green]; - blue = '1; + red = x [w_x - 2 -: w_red]; end + + if (x_2 [w_x +: w_y] < y) // Parabola + blue = y [w_y - 1 -: w_blue]; end /**/ @@ -177,16 +144,9 @@ module top always_comb begin - red = '0; - green = '0; - blue = '0; - - if (display_on) - begin - red = xc + xc + yc + dx; - green = xc - yc - dy; - blue = { 4 { & key } }; - end + red = xc + xc + yc + dx; + green = xc - yc - dy; + blue = { 4 { & key } }; end */ diff --git a/labs/2_graphics/2_1_rectangle_ellipse_parabola/tb.sv b/labs/2_graphics/2_1_rectangle_ellipse_parabola/tb.sv new file mode 100644 index 00000000..4c88f3b5 --- /dev/null +++ b/labs/2_graphics/2_1_rectangle_ellipse_parabola/tb.sv @@ -0,0 +1,57 @@ +`include "config.svh" + +module tb; + + localparam clk_mhz = 1, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100; + + //------------------------------------------------------------------------ + + logic clk; + logic rst; + logic [3:0] key; + logic [7:0] sw; + + //------------------------------------------------------------------------ + + lab_top + # ( + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ) + ) + i_lab_top + ( + .clk ( clk ), + .slow_clk ( clk ), + .rst ( rst ), + .key ( key ), + .sw ( sw ) + ); + + //------------------------------------------------------------------------ + + initial + begin + `ifdef __ICARUS__ + $dumpvars; + `endif + + repeat (8) + begin + # 10 + key <= $urandom (); + sw <= $urandom (); + end + + $finish; + end + +endmodule diff --git a/labs/12_snail_fsm/01_clean.bash b/labs/2_graphics/2_2_game/01_clean.bash similarity index 100% rename from labs/12_snail_fsm/01_clean.bash rename to labs/2_graphics/2_2_game/01_clean.bash diff --git a/labs/12_snail_fsm/02_simulate_rtl.bash b/labs/2_graphics/2_2_game/02_simulate_rtl.bash similarity index 100% rename from labs/12_snail_fsm/02_simulate_rtl.bash rename to labs/2_graphics/2_2_game/02_simulate_rtl.bash diff --git a/labs/12_snail_fsm/03_synthesize_for_fpga.bash b/labs/2_graphics/2_2_game/03_synthesize_for_fpga.bash similarity index 100% rename from labs/12_snail_fsm/03_synthesize_for_fpga.bash rename to labs/2_graphics/2_2_game/03_synthesize_for_fpga.bash diff --git a/labs/12_snail_fsm/04_configure_fpga.bash b/labs/2_graphics/2_2_game/04_configure_fpga.bash similarity index 100% rename from labs/12_snail_fsm/04_configure_fpga.bash rename to labs/2_graphics/2_2_game/04_configure_fpga.bash diff --git a/labs/12_snail_fsm/05_run_gui_for_fpga_synthesis.bash b/labs/2_graphics/2_2_game/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/12_snail_fsm/05_run_gui_for_fpga_synthesis.bash rename to labs/2_graphics/2_2_game/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/12_snail_fsm/06_choose_another_fpga_board.bash b/labs/2_graphics/2_2_game/06_choose_another_fpga_board.bash similarity index 100% rename from labs/12_snail_fsm/06_choose_another_fpga_board.bash rename to labs/2_graphics/2_2_game/06_choose_another_fpga_board.bash diff --git a/labs/12_snail_fsm/07_synthesize_for_asic.bash b/labs/2_graphics/2_2_game/07_synthesize_for_asic.bash similarity index 100% rename from labs/12_snail_fsm/07_synthesize_for_asic.bash rename to labs/2_graphics/2_2_game/07_synthesize_for_asic.bash diff --git a/labs/12_snail_fsm/08_visualize_asic_synthesis_results_1.bash b/labs/2_graphics/2_2_game/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/12_snail_fsm/08_visualize_asic_synthesis_results_1.bash rename to labs/2_graphics/2_2_game/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/12_snail_fsm/09_visualize_asic_synthesis_results_2.bash b/labs/2_graphics/2_2_game/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/12_snail_fsm/09_visualize_asic_synthesis_results_2.bash rename to labs/2_graphics/2_2_game/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/14_game/game_config.svh b/labs/2_graphics/2_2_game/game_config.svh similarity index 100% rename from labs/14_game/game_config.svh rename to labs/2_graphics/2_2_game/game_config.svh diff --git a/labs/14_game/game_master_fsm_1_regular_state_encoded.sv b/labs/2_graphics/2_2_game/game_master_fsm_1_regular_state_encoded.sv similarity index 100% rename from labs/14_game/game_master_fsm_1_regular_state_encoded.sv rename to labs/2_graphics/2_2_game/game_master_fsm_1_regular_state_encoded.sv diff --git a/labs/14_game/game_master_fsm_2_special_style_one_hot.sv b/labs/2_graphics/2_2_game/game_master_fsm_2_special_style_one_hot.sv similarity index 100% rename from labs/14_game/game_master_fsm_2_special_style_one_hot.sv rename to labs/2_graphics/2_2_game/game_master_fsm_2_special_style_one_hot.sv diff --git a/labs/14_game/game_master_fsm_3_special_style_signals_from_state.sv b/labs/2_graphics/2_2_game/game_master_fsm_3_special_style_signals_from_state.sv similarity index 100% rename from labs/14_game/game_master_fsm_3_special_style_signals_from_state.sv rename to labs/2_graphics/2_2_game/game_master_fsm_3_special_style_signals_from_state.sv diff --git a/labs/14_game/game_mixer.sv b/labs/2_graphics/2_2_game/game_mixer.sv similarity index 100% rename from labs/14_game/game_mixer.sv rename to labs/2_graphics/2_2_game/game_mixer.sv diff --git a/labs/14_game/game_overlap.sv b/labs/2_graphics/2_2_game/game_overlap.sv similarity index 100% rename from labs/14_game/game_overlap.sv rename to labs/2_graphics/2_2_game/game_overlap.sv diff --git a/labs/14_game/game_random.sv b/labs/2_graphics/2_2_game/game_random.sv similarity index 100% rename from labs/14_game/game_random.sv rename to labs/2_graphics/2_2_game/game_random.sv diff --git a/labs/14_game/game_sprite_control.sv b/labs/2_graphics/2_2_game/game_sprite_control.sv similarity index 100% rename from labs/14_game/game_sprite_control.sv rename to labs/2_graphics/2_2_game/game_sprite_control.sv diff --git a/labs/14_game/game_sprite_display.sv b/labs/2_graphics/2_2_game/game_sprite_display.sv similarity index 100% rename from labs/14_game/game_sprite_display.sv rename to labs/2_graphics/2_2_game/game_sprite_display.sv diff --git a/labs/14_game/game_sprite_display_pipelined.sv b/labs/2_graphics/2_2_game/game_sprite_display_pipelined.sv similarity index 100% rename from labs/14_game/game_sprite_display_pipelined.sv rename to labs/2_graphics/2_2_game/game_sprite_display_pipelined.sv diff --git a/labs/14_game/game_sprite_top.sv b/labs/2_graphics/2_2_game/game_sprite_top.sv similarity index 100% rename from labs/14_game/game_sprite_top.sv rename to labs/2_graphics/2_2_game/game_sprite_top.sv diff --git a/labs/14_game/game_strobe.sv b/labs/2_graphics/2_2_game/game_strobe.sv similarity index 100% rename from labs/14_game/game_strobe.sv rename to labs/2_graphics/2_2_game/game_strobe.sv diff --git a/labs/14_game/game_timer.sv b/labs/2_graphics/2_2_game/game_timer.sv similarity index 100% rename from labs/14_game/game_timer.sv rename to labs/2_graphics/2_2_game/game_timer.sv diff --git a/labs/14_game/game_top.sv b/labs/2_graphics/2_2_game/game_top.sv similarity index 100% rename from labs/14_game/game_top.sv rename to labs/2_graphics/2_2_game/game_top.sv diff --git a/labs/14_game/top.sv b/labs/2_graphics/2_2_game/lab_top.sv similarity index 74% rename from labs/14_game/top.sv rename to labs/2_graphics/2_2_game/lab_top.sv index 59ca941d..708cc046 100644 --- a/labs/14_game/top.sv +++ b/labs/2_graphics/2_2_game/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,47 +35,46 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio ); - localparam strobe_to_update_xy_counter_width - = $clog2 (clk_mhz * 1000 * 1000) - 6; - //------------------------------------------------------------------------ assign led = '0; assign abcdefgh = '0; assign digit = '0; - // assign vsync = '0; - // assign hsync = '0; // assign red = '0; // assign green = '0; // assign blue = '0; - // assign display_on = '0; - // assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; //------------------------------------------------------------------------ + localparam strobe_to_update_xy_counter_width + = $clog2 (clk_mhz * 1000 * 1000) - 6; + + //------------------------------------------------------------------------ + wire [2:0] rgb; game_top @@ -93,7 +98,7 @@ module top .rgb ( rgb ), .display_on ( display_on ), .pixel_clk ( pixel_clk ) - + ); assign red = { w_red { rgb [2] } }; diff --git a/labs/14_game/tb.sv b/labs/2_graphics/2_2_game/tb.sv similarity index 98% rename from labs/14_game/tb.sv rename to labs/2_graphics/2_2_game/tb.sv index 9112c087..3e875303 100644 --- a/labs/14_game/tb.sv +++ b/labs/2_graphics/2_2_game/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -29,7 +29,7 @@ module tb; .strobe_to_update_xy_counter_width (1) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/13_music_recognition/01_clean.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/01_clean.bash similarity index 100% rename from labs/13_music_recognition/01_clean.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/01_clean.bash diff --git a/labs/13_music_recognition/02_simulate_rtl.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/02_simulate_rtl.bash similarity index 100% rename from labs/13_music_recognition/02_simulate_rtl.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/02_simulate_rtl.bash diff --git a/labs/13_music_recognition/03_synthesize_for_fpga.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/03_synthesize_for_fpga.bash similarity index 100% rename from labs/13_music_recognition/03_synthesize_for_fpga.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/03_synthesize_for_fpga.bash diff --git a/labs/13_music_recognition/04_configure_fpga.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/04_configure_fpga.bash similarity index 100% rename from labs/13_music_recognition/04_configure_fpga.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/04_configure_fpga.bash diff --git a/labs/13_music_recognition/05_run_gui_for_fpga_synthesis.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/13_music_recognition/05_run_gui_for_fpga_synthesis.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/13_music_recognition/06_choose_another_fpga_board.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/06_choose_another_fpga_board.bash similarity index 100% rename from labs/13_music_recognition/06_choose_another_fpga_board.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/06_choose_another_fpga_board.bash diff --git a/labs/13_music_recognition/07_synthesize_for_asic.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/07_synthesize_for_asic.bash similarity index 100% rename from labs/13_music_recognition/07_synthesize_for_asic.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/07_synthesize_for_asic.bash diff --git a/labs/13_music_recognition/08_visualize_asic_synthesis_results_1.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/13_music_recognition/08_visualize_asic_synthesis_results_1.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/13_music_recognition/09_visualize_asic_synthesis_results_2.bash b/labs/2_graphics/2_3_crash_course_basics_and_graphics/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/13_music_recognition/09_visualize_asic_synthesis_results_2.bash rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/50_crash_course/top.sv b/labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv similarity index 88% rename from labs/50_crash_course/top.sv rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv index 03f882b4..32bb2200 100644 --- a/labs/50_crash_course/top.sv +++ b/labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv @@ -1,18 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -30,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -56,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - // assign vsync = '0; - // assign hsync = '0; // assign red = '0; // assign green = '0; // assign blue = '0; - // assign display_on = '0; - // assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/2_graphics/2_3_crash_course_basics_and_graphics/tb.sv b/labs/2_graphics/2_3_crash_course_basics_and_graphics/tb.sv new file mode 100644 index 00000000..4c88f3b5 --- /dev/null +++ b/labs/2_graphics/2_3_crash_course_basics_and_graphics/tb.sv @@ -0,0 +1,57 @@ +`include "config.svh" + +module tb; + + localparam clk_mhz = 1, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100; + + //------------------------------------------------------------------------ + + logic clk; + logic rst; + logic [3:0] key; + logic [7:0] sw; + + //------------------------------------------------------------------------ + + lab_top + # ( + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ) + ) + i_lab_top + ( + .clk ( clk ), + .slow_clk ( clk ), + .rst ( rst ), + .key ( key ), + .sw ( sw ) + ); + + //------------------------------------------------------------------------ + + initial + begin + `ifdef __ICARUS__ + $dumpvars; + `endif + + repeat (8) + begin + # 10 + key <= $urandom (); + sw <= $urandom (); + end + + $finish; + end + +endmodule diff --git a/labs/14_game/01_clean.bash b/labs/3_music/3_1_note_recognizer/01_clean.bash similarity index 100% rename from labs/14_game/01_clean.bash rename to labs/3_music/3_1_note_recognizer/01_clean.bash diff --git a/labs/14_game/02_simulate_rtl.bash b/labs/3_music/3_1_note_recognizer/02_simulate_rtl.bash similarity index 100% rename from labs/14_game/02_simulate_rtl.bash rename to labs/3_music/3_1_note_recognizer/02_simulate_rtl.bash diff --git a/labs/14_game/03_synthesize_for_fpga.bash b/labs/3_music/3_1_note_recognizer/03_synthesize_for_fpga.bash similarity index 100% rename from labs/14_game/03_synthesize_for_fpga.bash rename to labs/3_music/3_1_note_recognizer/03_synthesize_for_fpga.bash diff --git a/labs/14_game/04_configure_fpga.bash b/labs/3_music/3_1_note_recognizer/04_configure_fpga.bash similarity index 100% rename from labs/14_game/04_configure_fpga.bash rename to labs/3_music/3_1_note_recognizer/04_configure_fpga.bash diff --git a/labs/14_game/05_run_gui_for_fpga_synthesis.bash b/labs/3_music/3_1_note_recognizer/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/14_game/05_run_gui_for_fpga_synthesis.bash rename to labs/3_music/3_1_note_recognizer/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/14_game/06_choose_another_fpga_board.bash b/labs/3_music/3_1_note_recognizer/06_choose_another_fpga_board.bash similarity index 100% rename from labs/14_game/06_choose_another_fpga_board.bash rename to labs/3_music/3_1_note_recognizer/06_choose_another_fpga_board.bash diff --git a/labs/14_game/07_synthesize_for_asic.bash b/labs/3_music/3_1_note_recognizer/07_synthesize_for_asic.bash similarity index 100% rename from labs/14_game/07_synthesize_for_asic.bash rename to labs/3_music/3_1_note_recognizer/07_synthesize_for_asic.bash diff --git a/labs/14_game/08_visualize_asic_synthesis_results_1.bash b/labs/3_music/3_1_note_recognizer/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/14_game/08_visualize_asic_synthesis_results_1.bash rename to labs/3_music/3_1_note_recognizer/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/14_game/09_visualize_asic_synthesis_results_2.bash b/labs/3_music/3_1_note_recognizer/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/14_game/09_visualize_asic_synthesis_results_2.bash rename to labs/3_music/3_1_note_recognizer/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/11_note_recognition/gtkwave.tcl b/labs/3_music/3_1_note_recognizer/gtkwave.tcl similarity index 100% rename from labs/11_note_recognition/gtkwave.tcl rename to labs/3_music/3_1_note_recognizer/gtkwave.tcl diff --git a/labs/11_note_recognition/top.sv b/labs/3_music/3_1_note_recognizer/lab_top.sv similarity index 93% rename from labs/11_note_recognition/top.sv rename to labs/3_music/3_1_note_recognizer/lab_top.sv index ac679e7c..469bea5a 100644 --- a/labs/11_note_recognition/top.sv +++ b/labs/3_music/3_1_note_recognizer/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/11_note_recognition/mic_waves.png b/labs/3_music/3_1_note_recognizer/mic_waves.png similarity index 100% rename from labs/11_note_recognition/mic_waves.png rename to labs/3_music/3_1_note_recognizer/mic_waves.png diff --git a/labs/11_note_recognition/music_notes.pdf b/labs/3_music/3_1_note_recognizer/music_notes.pdf similarity index 100% rename from labs/11_note_recognition/music_notes.pdf rename to labs/3_music/3_1_note_recognizer/music_notes.pdf diff --git a/labs/11_note_recognition/tb.sv b/labs/3_music/3_1_note_recognizer/tb.sv similarity index 99% rename from labs/11_note_recognition/tb.sv rename to labs/3_music/3_1_note_recognizer/tb.sv index d4c3b78a..635253ca 100644 --- a/labs/11_note_recognition/tb.sv +++ b/labs/3_music/3_1_note_recognizer/tb.sv @@ -80,7 +80,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -89,7 +89,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/15_uart/01_clean.bash b/labs/3_music/3_2_melody_recognizer/01_clean.bash similarity index 100% rename from labs/15_uart/01_clean.bash rename to labs/3_music/3_2_melody_recognizer/01_clean.bash diff --git a/labs/15_uart/02_simulate_rtl.bash b/labs/3_music/3_2_melody_recognizer/02_simulate_rtl.bash similarity index 100% rename from labs/15_uart/02_simulate_rtl.bash rename to labs/3_music/3_2_melody_recognizer/02_simulate_rtl.bash diff --git a/labs/15_uart/03_synthesize_for_fpga.bash b/labs/3_music/3_2_melody_recognizer/03_synthesize_for_fpga.bash similarity index 100% rename from labs/15_uart/03_synthesize_for_fpga.bash rename to labs/3_music/3_2_melody_recognizer/03_synthesize_for_fpga.bash diff --git a/labs/15_uart/04_configure_fpga.bash b/labs/3_music/3_2_melody_recognizer/04_configure_fpga.bash similarity index 100% rename from labs/15_uart/04_configure_fpga.bash rename to labs/3_music/3_2_melody_recognizer/04_configure_fpga.bash diff --git a/labs/15_uart/05_run_gui_for_fpga_synthesis.bash b/labs/3_music/3_2_melody_recognizer/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/15_uart/05_run_gui_for_fpga_synthesis.bash rename to labs/3_music/3_2_melody_recognizer/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/15_uart/06_choose_another_fpga_board.bash b/labs/3_music/3_2_melody_recognizer/06_choose_another_fpga_board.bash similarity index 100% rename from labs/15_uart/06_choose_another_fpga_board.bash rename to labs/3_music/3_2_melody_recognizer/06_choose_another_fpga_board.bash diff --git a/labs/15_uart/07_synthesize_for_asic.bash b/labs/3_music/3_2_melody_recognizer/07_synthesize_for_asic.bash similarity index 100% rename from labs/15_uart/07_synthesize_for_asic.bash rename to labs/3_music/3_2_melody_recognizer/07_synthesize_for_asic.bash diff --git a/labs/15_uart/08_visualize_asic_synthesis_results_1.bash b/labs/3_music/3_2_melody_recognizer/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/15_uart/08_visualize_asic_synthesis_results_1.bash rename to labs/3_music/3_2_melody_recognizer/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/15_uart/09_visualize_asic_synthesis_results_2.bash b/labs/3_music/3_2_melody_recognizer/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/15_uart/09_visualize_asic_synthesis_results_2.bash rename to labs/3_music/3_2_melody_recognizer/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/13_music_recognition/top.sv b/labs/3_music/3_2_melody_recognizer/lab_top.sv similarity index 96% rename from labs/13_music_recognition/top.sv rename to labs/3_music/3_2_melody_recognizer/lab_top.sv index 71c131ea..cfa43142 100644 --- a/labs/13_music_recognition/top.sv +++ b/labs/3_music/3_2_melody_recognizer/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/13_music_recognition/music_notes.pdf b/labs/3_music/3_2_melody_recognizer/music_notes.pdf similarity index 100% rename from labs/13_music_recognition/music_notes.pdf rename to labs/3_music/3_2_melody_recognizer/music_notes.pdf diff --git a/labs/16_round_robin_arbiter/tb.sv b/labs/3_music/3_2_melody_recognizer/tb.sv similarity index 98% rename from labs/16_round_robin_arbiter/tb.sv rename to labs/3_music/3_2_melody_recognizer/tb.sv index 5284c427..6f6e5ddc 100644 --- a/labs/16_round_robin_arbiter/tb.sv +++ b/labs/3_music/3_2_melody_recognizer/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/16_round_robin_arbiter/01_clean.bash b/labs/3_music/3_3_note_synthesizer/01_clean.bash similarity index 100% rename from labs/16_round_robin_arbiter/01_clean.bash rename to labs/3_music/3_3_note_synthesizer/01_clean.bash diff --git a/labs/16_round_robin_arbiter/02_simulate_rtl.bash b/labs/3_music/3_3_note_synthesizer/02_simulate_rtl.bash similarity index 100% rename from labs/16_round_robin_arbiter/02_simulate_rtl.bash rename to labs/3_music/3_3_note_synthesizer/02_simulate_rtl.bash diff --git a/labs/16_round_robin_arbiter/03_synthesize_for_fpga.bash b/labs/3_music/3_3_note_synthesizer/03_synthesize_for_fpga.bash similarity index 100% rename from labs/16_round_robin_arbiter/03_synthesize_for_fpga.bash rename to labs/3_music/3_3_note_synthesizer/03_synthesize_for_fpga.bash diff --git a/labs/16_round_robin_arbiter/04_configure_fpga.bash b/labs/3_music/3_3_note_synthesizer/04_configure_fpga.bash similarity index 100% rename from labs/16_round_robin_arbiter/04_configure_fpga.bash rename to labs/3_music/3_3_note_synthesizer/04_configure_fpga.bash diff --git a/labs/16_round_robin_arbiter/05_run_gui_for_fpga_synthesis.bash b/labs/3_music/3_3_note_synthesizer/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/16_round_robin_arbiter/05_run_gui_for_fpga_synthesis.bash rename to labs/3_music/3_3_note_synthesizer/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/16_round_robin_arbiter/06_choose_another_fpga_board.bash b/labs/3_music/3_3_note_synthesizer/06_choose_another_fpga_board.bash similarity index 100% rename from labs/16_round_robin_arbiter/06_choose_another_fpga_board.bash rename to labs/3_music/3_3_note_synthesizer/06_choose_another_fpga_board.bash diff --git a/labs/16_round_robin_arbiter/07_synthesize_for_asic.bash b/labs/3_music/3_3_note_synthesizer/07_synthesize_for_asic.bash similarity index 100% rename from labs/16_round_robin_arbiter/07_synthesize_for_asic.bash rename to labs/3_music/3_3_note_synthesizer/07_synthesize_for_asic.bash diff --git a/labs/16_round_robin_arbiter/08_visualize_asic_synthesis_results_1.bash b/labs/3_music/3_3_note_synthesizer/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/16_round_robin_arbiter/08_visualize_asic_synthesis_results_1.bash rename to labs/3_music/3_3_note_synthesizer/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/16_round_robin_arbiter/09_visualize_asic_synthesis_results_2.bash b/labs/3_music/3_3_note_synthesizer/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/16_round_robin_arbiter/09_visualize_asic_synthesis_results_2.bash rename to labs/3_music/3_3_note_synthesizer/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/23_i2s_synthesizer/gen.py b/labs/3_music/3_3_note_synthesizer/gen.py similarity index 100% rename from labs/23_i2s_synthesizer/gen.py rename to labs/3_music/3_3_note_synthesizer/gen.py diff --git a/labs/23_i2s_synthesizer/gen_tone_table.sh b/labs/3_music/3_3_note_synthesizer/gen_tone_table.sh similarity index 100% rename from labs/23_i2s_synthesizer/gen_tone_table.sh rename to labs/3_music/3_3_note_synthesizer/gen_tone_table.sh diff --git a/labs/23_i2s_synthesizer/top.sv b/labs/3_music/3_3_note_synthesizer/lab_top.sv similarity index 81% rename from labs/23_i2s_synthesizer/top.sv rename to labs/3_music/3_3_note_synthesizer/lab_top.sv index a2f0805d..2b8b36f9 100644 --- a/labs/23_i2s_synthesizer/top.sv +++ b/labs/3_music/3_3_note_synthesizer/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; // assign sound = '0; assign uart_tx = '1; diff --git a/labs/23_i2s_synthesizer/tb.sv b/labs/3_music/3_3_note_synthesizer/tb.sv similarity index 98% rename from labs/23_i2s_synthesizer/tb.sv rename to labs/3_music/3_3_note_synthesizer/tb.sv index b4b136fa..9e0da220 100644 --- a/labs/23_i2s_synthesizer/tb.sv +++ b/labs/3_music/3_3_note_synthesizer/tb.sv @@ -18,7 +18,7 @@ module testbench; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module testbench; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/23_i2s_synthesizer/tone_sel.sv b/labs/3_music/3_3_note_synthesizer/tone_sel.sv similarity index 100% rename from labs/23_i2s_synthesizer/tone_sel.sv rename to labs/3_music/3_3_note_synthesizer/tone_sel.sv diff --git a/labs/23_i2s_synthesizer/tone_table.svh b/labs/3_music/3_3_note_synthesizer/tone_table.svh similarity index 100% rename from labs/23_i2s_synthesizer/tone_table.svh rename to labs/3_music/3_3_note_synthesizer/tone_table.svh diff --git a/labs/17_geiger_muller_radiation_counter/01_clean.bash b/labs/3_music/3_4_music_player/01_clean.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/01_clean.bash rename to labs/3_music/3_4_music_player/01_clean.bash diff --git a/labs/17_geiger_muller_radiation_counter/02_simulate_rtl.bash b/labs/3_music/3_4_music_player/02_simulate_rtl.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/02_simulate_rtl.bash rename to labs/3_music/3_4_music_player/02_simulate_rtl.bash diff --git a/labs/17_geiger_muller_radiation_counter/03_synthesize_for_fpga.bash b/labs/3_music/3_4_music_player/03_synthesize_for_fpga.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/03_synthesize_for_fpga.bash rename to labs/3_music/3_4_music_player/03_synthesize_for_fpga.bash diff --git a/labs/17_geiger_muller_radiation_counter/04_configure_fpga.bash b/labs/3_music/3_4_music_player/04_configure_fpga.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/04_configure_fpga.bash rename to labs/3_music/3_4_music_player/04_configure_fpga.bash diff --git a/labs/17_geiger_muller_radiation_counter/05_run_gui_for_fpga_synthesis.bash b/labs/3_music/3_4_music_player/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/05_run_gui_for_fpga_synthesis.bash rename to labs/3_music/3_4_music_player/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/17_geiger_muller_radiation_counter/06_choose_another_fpga_board.bash b/labs/3_music/3_4_music_player/06_choose_another_fpga_board.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/06_choose_another_fpga_board.bash rename to labs/3_music/3_4_music_player/06_choose_another_fpga_board.bash diff --git a/labs/17_geiger_muller_radiation_counter/07_synthesize_for_asic.bash b/labs/3_music/3_4_music_player/07_synthesize_for_asic.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/07_synthesize_for_asic.bash rename to labs/3_music/3_4_music_player/07_synthesize_for_asic.bash diff --git a/labs/17_geiger_muller_radiation_counter/08_visualize_asic_synthesis_results_1.bash b/labs/3_music/3_4_music_player/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/08_visualize_asic_synthesis_results_1.bash rename to labs/3_music/3_4_music_player/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/17_geiger_muller_radiation_counter/09_visualize_asic_synthesis_results_2.bash b/labs/3_music/3_4_music_player/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/09_visualize_asic_synthesis_results_2.bash rename to labs/3_music/3_4_music_player/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/24_i2s_music/gen.py b/labs/3_music/3_4_music_player/gen.py similarity index 100% rename from labs/24_i2s_music/gen.py rename to labs/3_music/3_4_music_player/gen.py diff --git a/labs/24_i2s_music/gen_tone_table.sh b/labs/3_music/3_4_music_player/gen_tone_table.sh similarity index 100% rename from labs/24_i2s_music/gen_tone_table.sh rename to labs/3_music/3_4_music_player/gen_tone_table.sh diff --git a/labs/24_i2s_music/top.sv b/labs/3_music/3_4_music_player/lab_top.sv similarity index 92% rename from labs/24_i2s_music/top.sv rename to labs/3_music/3_4_music_player/lab_top.sv index e1c98e53..7ccf650c 100644 --- a/labs/24_i2s_music/top.sv +++ b/labs/3_music/3_4_music_player/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; // assign sound = '0; assign uart_tx = '1; diff --git a/labs/24_i2s_music/tb.sv b/labs/3_music/3_4_music_player/tb.sv similarity index 98% rename from labs/24_i2s_music/tb.sv rename to labs/3_music/3_4_music_player/tb.sv index 6749eb5f..68085cc8 100644 --- a/labs/24_i2s_music/tb.sv +++ b/labs/3_music/3_4_music_player/tb.sv @@ -18,7 +18,7 @@ module testbench; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module testbench; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/24_i2s_music/tone_sel.sv b/labs/3_music/3_4_music_player/tone_sel.sv similarity index 100% rename from labs/24_i2s_music/tone_sel.sv rename to labs/3_music/3_4_music_player/tone_sel.sv diff --git a/labs/24_i2s_music/tone_table.svh b/labs/3_music/3_4_music_player/tone_table.svh similarity index 100% rename from labs/24_i2s_music/tone_table.svh rename to labs/3_music/3_4_music_player/tone_table.svh diff --git a/labs/18_pow5_single_cycle/01_clean.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/01_clean.bash similarity index 100% rename from labs/18_pow5_single_cycle/01_clean.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/01_clean.bash diff --git a/labs/18_pow5_single_cycle/02_simulate_rtl.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/02_simulate_rtl.bash similarity index 100% rename from labs/18_pow5_single_cycle/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/02_simulate_rtl.bash diff --git a/labs/18_pow5_single_cycle/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/03_synthesize_for_fpga.bash similarity index 100% rename from labs/18_pow5_single_cycle/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/03_synthesize_for_fpga.bash diff --git a/labs/18_pow5_single_cycle/04_configure_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/04_configure_fpga.bash similarity index 100% rename from labs/18_pow5_single_cycle/04_configure_fpga.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/04_configure_fpga.bash diff --git a/labs/18_pow5_single_cycle/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/18_pow5_single_cycle/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/18_pow5_single_cycle/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/06_choose_another_fpga_board.bash similarity index 100% rename from labs/18_pow5_single_cycle/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/06_choose_another_fpga_board.bash diff --git a/labs/18_pow5_single_cycle/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/07_synthesize_for_asic.bash similarity index 100% rename from labs/18_pow5_single_cycle/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/07_synthesize_for_asic.bash diff --git a/labs/18_pow5_single_cycle/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/18_pow5_single_cycle/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/18_pow5_single_cycle/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/18_pow5_single_cycle/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/18_pow5_single_cycle/top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/lab_top.sv similarity index 78% rename from labs/18_pow5_single_cycle/top.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/lab_top.sv index 9bf43494..93ee9e29 100644 --- a/labs/18_pow5_single_cycle/top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/18_pow5_single_cycle/tb.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/tb.sv similarity index 98% rename from labs/18_pow5_single_cycle/tb.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/tb.sv index 741b640f..98c15eb3 100644 --- a/labs/18_pow5_single_cycle/tb.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/19_pow5_pipelined/01_clean.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/01_clean.bash similarity index 100% rename from labs/19_pow5_pipelined/01_clean.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/01_clean.bash diff --git a/labs/19_pow5_pipelined/02_simulate_rtl.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/02_simulate_rtl.bash similarity index 100% rename from labs/19_pow5_pipelined/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/02_simulate_rtl.bash diff --git a/labs/19_pow5_pipelined/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/03_synthesize_for_fpga.bash similarity index 100% rename from labs/19_pow5_pipelined/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/03_synthesize_for_fpga.bash diff --git a/labs/19_pow5_pipelined/04_configure_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/04_configure_fpga.bash similarity index 100% rename from labs/19_pow5_pipelined/04_configure_fpga.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/04_configure_fpga.bash diff --git a/labs/19_pow5_pipelined/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/19_pow5_pipelined/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/19_pow5_pipelined/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/06_choose_another_fpga_board.bash similarity index 100% rename from labs/19_pow5_pipelined/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/06_choose_another_fpga_board.bash diff --git a/labs/19_pow5_pipelined/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/07_synthesize_for_asic.bash similarity index 100% rename from labs/19_pow5_pipelined/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/07_synthesize_for_asic.bash diff --git a/labs/19_pow5_pipelined/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/19_pow5_pipelined/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/19_pow5_pipelined/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/19_pow5_pipelined/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/19_pow5_pipelined/top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/lab_top.sv similarity index 85% rename from labs/19_pow5_pipelined/top.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/lab_top.sv index 541a7b01..e45d1217 100644 --- a/labs/19_pow5_pipelined/top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/19_pow5_pipelined/tb.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/tb.sv similarity index 98% rename from labs/19_pow5_pipelined/tb.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/tb.sv index 741b640f..98c15eb3 100644 --- a/labs/19_pow5_pipelined/tb.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/20_pow5_pipelined_valid/01_clean.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/01_clean.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/01_clean.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/01_clean.bash diff --git a/labs/20_pow5_pipelined_valid/02_simulate_rtl.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/02_simulate_rtl.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/02_simulate_rtl.bash diff --git a/labs/20_pow5_pipelined_valid/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/03_synthesize_for_fpga.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/03_synthesize_for_fpga.bash diff --git a/labs/20_pow5_pipelined_valid/04_configure_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/04_configure_fpga.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/04_configure_fpga.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/04_configure_fpga.bash diff --git a/labs/20_pow5_pipelined_valid/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/20_pow5_pipelined_valid/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/06_choose_another_fpga_board.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/06_choose_another_fpga_board.bash diff --git a/labs/20_pow5_pipelined_valid/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/07_synthesize_for_asic.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/07_synthesize_for_asic.bash diff --git a/labs/20_pow5_pipelined_valid/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/20_pow5_pipelined_valid/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/20_pow5_pipelined_valid/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/20_pow5_pipelined_valid/top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/lab_top.sv similarity index 89% rename from labs/20_pow5_pipelined_valid/top.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/lab_top.sv index fa63f932..dc1fd221 100644 --- a/labs/20_pow5_pipelined_valid/top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/20_pow5_pipelined_valid/tb.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/tb.sv similarity index 98% rename from labs/20_pow5_pipelined_valid/tb.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/tb.sv index af86c436..b0f1cb1a 100644 --- a/labs/20_pow5_pipelined_valid/tb.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/21_pow5_pipelined_valid_solution/01_clean.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/01_clean.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/01_clean.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/01_clean.bash diff --git a/labs/21_pow5_pipelined_valid_solution/02_simulate_rtl.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/02_simulate_rtl.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/02_simulate_rtl.bash diff --git a/labs/21_pow5_pipelined_valid_solution/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/03_synthesize_for_fpga.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/03_synthesize_for_fpga.bash diff --git a/labs/21_pow5_pipelined_valid_solution/04_configure_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/04_configure_fpga.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/04_configure_fpga.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/04_configure_fpga.bash diff --git a/labs/21_pow5_pipelined_valid_solution/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/21_pow5_pipelined_valid_solution/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/06_choose_another_fpga_board.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/06_choose_another_fpga_board.bash diff --git a/labs/21_pow5_pipelined_valid_solution/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/07_synthesize_for_asic.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/07_synthesize_for_asic.bash diff --git a/labs/21_pow5_pipelined_valid_solution/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/21_pow5_pipelined_valid_solution/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/21_pow5_pipelined_valid_solution/top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/lab_top.sv similarity index 87% rename from labs/21_pow5_pipelined_valid_solution/top.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/lab_top.sv index 9f06833e..0ad3927a 100644 --- a/labs/21_pow5_pipelined_valid_solution/top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/21_pow5_pipelined_valid_solution/tb.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/tb.sv similarity index 98% rename from labs/21_pow5_pipelined_valid_solution/tb.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/tb.sv index af86c436..b0f1cb1a 100644 --- a/labs/21_pow5_pipelined_valid_solution/tb.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/22_syst_ws/01_clean.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/01_clean.bash similarity index 100% rename from labs/22_syst_ws/01_clean.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/01_clean.bash diff --git a/labs/22_syst_ws/02_simulate_rtl.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/02_simulate_rtl.bash similarity index 100% rename from labs/22_syst_ws/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/02_simulate_rtl.bash diff --git a/labs/22_syst_ws/top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/lab_top.sv similarity index 99% rename from labs/22_syst_ws/top.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/lab_top.sv index b3f5c96e..147378e7 100644 --- a/labs/22_syst_ws/top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/lab_top.sv @@ -1,6 +1,6 @@ `timescale 1ns / 1ps -module top +module lab_top ( input logic clk, input logic rst, diff --git a/labs/22_syst_ws/syst_node.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/syst_node.sv similarity index 100% rename from labs/22_syst_ws/syst_node.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/syst_node.sv diff --git a/labs/22_syst_ws/tb.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/tb.sv similarity index 100% rename from labs/22_syst_ws/tb.sv rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_5_syst_ws/tb.sv diff --git a/labs/23_i2s_synthesizer/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/01_clean.bash similarity index 100% rename from labs/23_i2s_synthesizer/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/01_clean.bash diff --git a/labs/23_i2s_synthesizer/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/02_simulate_rtl.bash similarity index 100% rename from labs/23_i2s_synthesizer/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/02_simulate_rtl.bash diff --git a/labs/23_i2s_synthesizer/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/23_i2s_synthesizer/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/03_synthesize_for_fpga.bash diff --git a/labs/23_i2s_synthesizer/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/04_configure_fpga.bash similarity index 100% rename from labs/23_i2s_synthesizer/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/04_configure_fpga.bash diff --git a/labs/23_i2s_synthesizer/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/23_i2s_synthesizer/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/23_i2s_synthesizer/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/06_choose_another_fpga_board.bash similarity index 100% rename from labs/23_i2s_synthesizer/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/06_choose_another_fpga_board.bash diff --git a/labs/23_i2s_synthesizer/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/07_synthesize_for_asic.bash similarity index 100% rename from labs/23_i2s_synthesizer/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/07_synthesize_for_asic.bash diff --git a/labs/23_i2s_synthesizer/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/23_i2s_synthesizer/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/23_i2s_synthesizer/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/23_i2s_synthesizer/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/fifo_monitor.sv b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/fifo_monitor.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/fifo_monitor.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/fifo_monitor.sv diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/flip_flop_fifo_with_counter.sv b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/flip_flop_fifo_with_counter.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/flip_flop_fifo_with_counter.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/flip_flop_fifo_with_counter.sv diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv similarity index 88% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv index 42ef608a..90ba70b0 100644 --- a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/tb.sv diff --git a/labs/24_i2s_music/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/01_clean.bash similarity index 100% rename from labs/24_i2s_music/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/01_clean.bash diff --git a/labs/24_i2s_music/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/02_simulate_rtl.bash similarity index 100% rename from labs/24_i2s_music/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/02_simulate_rtl.bash diff --git a/labs/24_i2s_music/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/03_synthesize_for_fpga.bash similarity index 100% rename from labs/24_i2s_music/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/03_synthesize_for_fpga.bash diff --git a/labs/24_i2s_music/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/04_configure_fpga.bash similarity index 100% rename from labs/24_i2s_music/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/04_configure_fpga.bash diff --git a/labs/24_i2s_music/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/24_i2s_music/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/24_i2s_music/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/06_choose_another_fpga_board.bash similarity index 100% rename from labs/24_i2s_music/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/06_choose_another_fpga_board.bash diff --git a/labs/24_i2s_music/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/07_synthesize_for_asic.bash similarity index 100% rename from labs/24_i2s_music/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/07_synthesize_for_asic.bash diff --git a/labs/24_i2s_music/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/24_i2s_music/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/24_i2s_music/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/24_i2s_music/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv similarity index 87% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv index 9ae12ea2..7acaff50 100644 --- a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/shift_register_with_valid_and_debug.sv b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/shift_register_with_valid_and_debug.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/shift_register_with_valid_and_debug.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/shift_register_with_valid_and_debug.sv diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/tb.sv diff --git a/labs/30_schoolriscv/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/01_clean.bash similarity index 100% rename from labs/30_schoolriscv/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/01_clean.bash diff --git a/labs/30_schoolriscv/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/02_simulate_rtl.bash similarity index 100% rename from labs/30_schoolriscv/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/02_simulate_rtl.bash diff --git a/labs/30_schoolriscv/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/03_synthesize_for_fpga.bash similarity index 100% rename from labs/30_schoolriscv/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/03_synthesize_for_fpga.bash diff --git a/labs/30_schoolriscv/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/04_configure_fpga.bash similarity index 100% rename from labs/30_schoolriscv/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/04_configure_fpga.bash diff --git a/labs/30_schoolriscv/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/30_schoolriscv/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/30_schoolriscv/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/06_choose_another_fpga_board.bash similarity index 100% rename from labs/30_schoolriscv/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/06_choose_another_fpga_board.bash diff --git a/labs/30_schoolriscv/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/07_synthesize_for_asic.bash similarity index 100% rename from labs/30_schoolriscv/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/07_synthesize_for_asic.bash diff --git a/labs/30_schoolriscv/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/30_schoolriscv/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/30_schoolriscv/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/30_schoolriscv/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/fifo_monitor.sv b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/fifo_monitor.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/fifo_monitor.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/fifo_monitor.sv diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/flip_flop_fifo_with_counter_and_debug_1.sv b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/flip_flop_fifo_with_counter_and_debug_1.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/flip_flop_fifo_with_counter_and_debug_1.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/flip_flop_fifo_with_counter_and_debug_1.sv diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/lab_top.sv similarity index 87% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/lab_top.sv index 1338626f..96eadf30 100644 --- a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/tb.sv diff --git a/labs/50_crash_course/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/01_clean.bash similarity index 100% rename from labs/50_crash_course/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/01_clean.bash diff --git a/labs/50_crash_course/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/02_simulate_rtl.bash similarity index 100% rename from labs/50_crash_course/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/02_simulate_rtl.bash diff --git a/labs/50_crash_course/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/03_synthesize_for_fpga.bash similarity index 100% rename from labs/50_crash_course/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/03_synthesize_for_fpga.bash diff --git a/labs/50_crash_course/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/04_configure_fpga.bash similarity index 100% rename from labs/50_crash_course/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/04_configure_fpga.bash diff --git a/labs/50_crash_course/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/50_crash_course/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/50_crash_course/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/06_choose_another_fpga_board.bash similarity index 100% rename from labs/50_crash_course/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/06_choose_another_fpga_board.bash diff --git a/labs/50_crash_course/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/07_synthesize_for_asic.bash similarity index 100% rename from labs/50_crash_course/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/07_synthesize_for_asic.bash diff --git a/labs/50_crash_course/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/50_crash_course/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/50_crash_course/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/50_crash_course/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/fifo_monitor.sv b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/fifo_monitor.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/fifo_monitor.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/fifo_monitor.sv diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv similarity index 89% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv index ecc431d2..3fffcc8c 100644 --- a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/tb.sv diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/flip_flop_fifo_empty_full_optimized.sv b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/flip_flop_fifo_empty_full_optimized.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/flip_flop_fifo_empty_full_optimized.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/flip_flop_fifo_empty_full_optimized.sv diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv similarity index 87% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv index 2dbadf3b..f67ffae6 100644 --- a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/tb.sv diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_with_reg_empty_full.sv b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_with_reg_empty_full.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_with_reg_empty_full.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_with_reg_empty_full.sv diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv similarity index 87% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv index 2dbadf3b..f67ffae6 100644 --- a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/tb.sv diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/a_plus_b_using_fifos.sv b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/a_plus_b_using_fifos.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/a_plus_b_using_fifos.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/a_plus_b_using_fifos.sv diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/flip_flop_fifo.sv b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/flip_flop_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/flip_flop_fifo.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/flip_flop_fifo.sv diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv similarity index 89% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv index 2ae3aa4d..c648e020 100644 --- a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/tb.sv diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/01_clean.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/01_clean.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/02_simulate_rtl.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/04_configure_fpga.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/04_configure_fpga.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_1_single_allows_back_to_back.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_1_single_allows_back_to_back.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_1_single_allows_back_to_back.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_1_single_allows_back_to_back.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_2_single_half_perf_no_comb_path.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_2_single_half_perf_no_comb_path.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_2_single_half_perf_no_comb_path.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_2_single_half_perf_no_comb_path.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_3_single_for_pipes_with_global_stall.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_3_single_for_pipes_with_global_stall.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_3_single_for_pipes_with_global_stall.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_3_single_for_pipes_with_global_stall.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_4_wrapped_2_deep_fifo.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_4_wrapped_2_deep_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_4_wrapped_2_deep_fifo.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_4_wrapped_2_deep_fifo.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_5_double_buffer_from_dally_harting.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_5_double_buffer_from_dally_harting.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_5_double_buffer_from_dally_harting.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_5_double_buffer_from_dally_harting.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/ff_fifo_pow2_depth.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/ff_fifo_pow2_depth.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/ff_fifo_pow2_depth.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/ff_fifo_pow2_depth.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/gtkwave.tcl b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/gtkwave.tcl rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/top.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/lab_top.sv similarity index 82% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/top.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/lab_top.sv index d51ffca1..5e620e99 100644 --- a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/top.sv +++ b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/pow_5_single_cycle.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/pow_5_single_cycle.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/pow_5_single_cycle.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/pow_5_single_cycle.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/tb.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/tb.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/tb.sv diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/01_clean.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/01_clean.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_1_single_allows_back_to_back.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_1_single_allows_back_to_back.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_1_single_allows_back_to_back.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_1_single_allows_back_to_back.sv diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_2_single_half_perf_no_comb_path.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_2_single_half_perf_no_comb_path.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_2_single_half_perf_no_comb_path.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_2_single_half_perf_no_comb_path.sv diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_3_single_for_pipes_with_global_stall.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_3_single_for_pipes_with_global_stall.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_3_single_for_pipes_with_global_stall.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_3_single_for_pipes_with_global_stall.sv diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_4_wrapped_2_deep_fifo.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_4_wrapped_2_deep_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_4_wrapped_2_deep_fifo.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_4_wrapped_2_deep_fifo.sv diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_5_double_buffer_from_dally_harting.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_5_double_buffer_from_dally_harting.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/fcr_5_double_buffer_from_dally_harting.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/fcr_5_double_buffer_from_dally_harting.sv diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/ff_fifo_pow2_depth.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/ff_fifo_pow2_depth.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/ff_fifo_pow2_depth.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/ff_fifo_pow2_depth.sv diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/gtkwave.tcl b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/gtkwave.tcl rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/top.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/lab_top.sv similarity index 82% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/top.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/lab_top.sv index 07b372c9..07ddcad0 100644 --- a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/top.sv +++ b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/pow_5_pipelined.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/pow_5_pipelined.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/pow_5_pipelined.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/pow_5_pipelined.sv diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/tb.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/tb.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/tb.sv diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/01_clean.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/01_clean.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/gtkwave.tcl b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/gtkwave.tcl rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/top.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/lab_top.sv similarity index 81% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/top.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/lab_top.sv index c61c6ed8..147a327b 100644 --- a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/top.sv +++ b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/pow_5_pipelined_without_flow_control.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/pow_5_pipelined_without_flow_control.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/pow_5_pipelined_without_flow_control.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/pow_5_pipelined_without_flow_control.sv diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/reg_without_flow_control.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/reg_without_flow_control.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/reg_without_flow_control.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/reg_without_flow_control.sv diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/tb.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/tb.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/tb.sv diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/01_clean.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/01_clean.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/02_simulate_rtl.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/04_configure_fpga.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/04_configure_fpga.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/flip_flop_fifo_with_counter.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/flip_flop_fifo_with_counter.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/flip_flop_fifo_with_counter.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/flip_flop_fifo_with_counter.sv diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/gtkwave.tcl b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/gtkwave.tcl rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/top.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/lab_top.sv similarity index 82% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/top.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/lab_top.sv index 5e107789..b00b6d4f 100644 --- a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/top.sv +++ b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/pow_5_pipelined_with_credit_counter.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/pow_5_pipelined_with_credit_counter.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/pow_5_pipelined_with_credit_counter.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/pow_5_pipelined_with_credit_counter.sv diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/pow_5_pipelined_without_flow_control.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/pow_5_pipelined_without_flow_control.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/pow_5_pipelined_without_flow_control.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/pow_5_pipelined_without_flow_control.sv diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/reg_without_flow_control.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/reg_without_flow_control.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/reg_without_flow_control.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/reg_without_flow_control.sv diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/tb.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/tb.sv rename to labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/tb.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/01_clean.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/01_clean.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/02_simulate_rtl.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/04_configure_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/04_configure_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/16_round_robin_arbiter/arbiter_1_dumb_big_blob.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_1_dumb_big_blob.sv similarity index 100% rename from labs/16_round_robin_arbiter/arbiter_1_dumb_big_blob.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_1_dumb_big_blob.sv diff --git a/labs/16_round_robin_arbiter/arbiter_2_rotate_priority_rotate_verbose.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_2_rotate_priority_rotate_verbose.sv similarity index 100% rename from labs/16_round_robin_arbiter/arbiter_2_rotate_priority_rotate_verbose.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_2_rotate_priority_rotate_verbose.sv diff --git a/labs/16_round_robin_arbiter/arbiter_3_rotate_priority_case_rotate.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_3_rotate_priority_case_rotate.sv similarity index 100% rename from labs/16_round_robin_arbiter/arbiter_3_rotate_priority_case_rotate.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_3_rotate_priority_case_rotate.sv diff --git a/labs/16_round_robin_arbiter/arbiter_4_rotate_priority_3_assigns_rotate.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_4_rotate_priority_3_assigns_rotate.sv similarity index 100% rename from labs/16_round_robin_arbiter/arbiter_4_rotate_priority_3_assigns_rotate.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_4_rotate_priority_3_assigns_rotate.sv diff --git a/labs/16_round_robin_arbiter/arbiter_5_rotate_priority_rotate_brief.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_5_rotate_priority_rotate_brief.sv similarity index 100% rename from labs/16_round_robin_arbiter/arbiter_5_rotate_priority_rotate_brief.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/arbiter_5_rotate_priority_rotate_brief.sv diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/gtkwave.tcl b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/gtkwave.tcl new file mode 100644 index 00000000..c6866a7f --- /dev/null +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/gtkwave.tcl @@ -0,0 +1,15 @@ +# gtkwave::loadFile "dump.vcd" + +set all_signals [list] + +lappend all_signals tb.clk +lappend all_signals tb.rst +lappend all_signals tb.key +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit + +set num_added [ gtkwave::addSignalsFromList $all_signals ] + +gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_specific_board_config.svh b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_specific_board_config.svh new file mode 100644 index 00000000..2dc4de3d --- /dev/null +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_specific_board_config.svh @@ -0,0 +1,21 @@ +`ifndef LAB_SPECIFIC_CONFIG_SVH +`define LAB_SPECIFIC_CONFIG_SVH + + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE + + `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 +// `define CONCAT_TM1638_SIGNALS_AND_REGULAR + +// `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + +`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH + +// This is the default file included +// when there is no lab_specific_board_config.svh +// in the lab directory diff --git a/labs/16_round_robin_arbiter/top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_top.sv similarity index 85% rename from labs/16_round_robin_arbiter/top.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_top.sv index a1ba62aa..74f09831 100644 --- a/labs/16_round_robin_arbiter/top.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_top.sv @@ -4,18 +4,24 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -33,22 +39,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -59,13 +66,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/tb.sv similarity index 98% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/tb.sv index 5284c427..6f6e5ddc 100644 --- a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/01_clean.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/01_clean.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/02_simulate_rtl.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/04_configure_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/04_configure_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl new file mode 100644 index 00000000..4e017826 --- /dev/null +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl @@ -0,0 +1,25 @@ +# gtkwave::loadFile "dump.vcd" + +set all_signals [list] + +lappend all_signals tb.i_lab_top.clk +lappend all_signals tb.i_lab_top.rst +lappend all_signals tb.i_lab_top.a_valid +lappend all_signals tb.i_lab_top.a_ready +lappend all_signals tb.i_lab_top.a_data +lappend all_signals tb.i_lab_top.b_valid +lappend all_signals tb.i_lab_top.b_ready +lappend all_signals tb.i_lab_top.b_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_data +lappend all_signals tb.i_lab_top.out_valid +lappend all_signals tb.i_lab_top.out_ready +lappend all_signals tb.i_lab_top.out_data + +set num_added [ gtkwave::addSignalsFromList $all_signals ] + +gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 87% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/top.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index ee34fb00..d631f4d7 100644 --- a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/top.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_2_requests.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_2_requests.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_2_requests.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_2_requests.sv diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv diff --git a/labs/13_music_recognition/tb.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv similarity index 98% rename from labs/13_music_recognition/tb.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv index 5284c427..6f6e5ddc 100644 --- a/labs/13_music_recognition/tb.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/01_clean.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/01_clean.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/02_simulate_rtl.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/04_configure_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/04_configure_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_2_requests.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_2_requests.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_2_requests.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_2_requests.sv diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl new file mode 100644 index 00000000..4e017826 --- /dev/null +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl @@ -0,0 +1,25 @@ +# gtkwave::loadFile "dump.vcd" + +set all_signals [list] + +lappend all_signals tb.i_lab_top.clk +lappend all_signals tb.i_lab_top.rst +lappend all_signals tb.i_lab_top.a_valid +lappend all_signals tb.i_lab_top.a_ready +lappend all_signals tb.i_lab_top.a_data +lappend all_signals tb.i_lab_top.b_valid +lappend all_signals tb.i_lab_top.b_ready +lappend all_signals tb.i_lab_top.b_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_data +lappend all_signals tb.i_lab_top.out_valid +lappend all_signals tb.i_lab_top.out_ready +lappend all_signals tb.i_lab_top.out_data + +set num_added [ gtkwave::addSignalsFromList $all_signals ] + +gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 87% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index f8eecfba..7f4144fb 100644 --- a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv similarity index 98% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv index 5284c427..6f6e5ddc 100644 --- a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/01_clean.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/01_clean.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/02_simulate_rtl.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/04_configure_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/04_configure_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl new file mode 100644 index 00000000..4e017826 --- /dev/null +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl @@ -0,0 +1,25 @@ +# gtkwave::loadFile "dump.vcd" + +set all_signals [list] + +lappend all_signals tb.i_lab_top.clk +lappend all_signals tb.i_lab_top.rst +lappend all_signals tb.i_lab_top.a_valid +lappend all_signals tb.i_lab_top.a_ready +lappend all_signals tb.i_lab_top.a_data +lappend all_signals tb.i_lab_top.b_valid +lappend all_signals tb.i_lab_top.b_ready +lappend all_signals tb.i_lab_top.b_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_data +lappend all_signals tb.i_lab_top.out_valid +lappend all_signals tb.i_lab_top.out_ready +lappend all_signals tb.i_lab_top.out_data + +set num_added [ gtkwave::addSignalsFromList $all_signals ] + +gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 87% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index c5fad72c..c7bf95d3 100644 --- a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv new file mode 100644 index 00000000..6f6e5ddc --- /dev/null +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -0,0 +1,84 @@ +`include "config.svh" + +module tb; + + localparam clk_mhz = 1, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100; + + //------------------------------------------------------------------------ + + logic clk; + logic rst; + logic [3:0] key; + logic [7:0] sw; + + //------------------------------------------------------------------------ + + lab_top + # ( + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ) + ) + i_lab_top + ( + .clk ( clk ), + .slow_clk ( clk ), + .rst ( rst ), + .key ( key ), + .sw ( sw ) + ); + + //------------------------------------------------------------------------ + + initial + begin + clk = 1'b0; + + forever + # 5 clk = ~ clk; + end + + //------------------------------------------------------------------------ + + initial + begin + rst <= 1'bx; + repeat (2) @ (posedge clk); + rst <= 1'b1; + repeat (2) @ (posedge clk); + rst <= 1'b0; + end + + //------------------------------------------------------------------------ + + initial + begin + `ifdef __ICARUS__ + $dumpvars; + `endif + + key <= '0; + sw <= '0; + + @ (negedge rst); + + repeat (50) + begin + @ (posedge clk); + + key <= $urandom (); + sw <= $urandom (); + end + + $finish; + end + +endmodule diff --git a/labs/50_crash_course/tb.sv b/labs/50_crash_course/tb.sv deleted file mode 100644 index f8c334f3..00000000 --- a/labs/50_crash_course/tb.sv +++ /dev/null @@ -1,57 +0,0 @@ -`include "config.svh" - -module tb; - - localparam clk_mhz = 1, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100; - - //------------------------------------------------------------------------ - - logic clk; - logic rst; - logic [3:0] key; - logic [7:0] sw; - - //------------------------------------------------------------------------ - - top - # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_sw ), - .w_led ( w_led ), - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) - ) - i_top - ( - .clk ( clk ), - .slow_clk ( clk ), - .rst ( rst ), - .key ( key ), - .sw ( sw ) - ); - - //------------------------------------------------------------------------ - - initial - begin - `ifdef __ICARUS__ - $dumpvars; - `endif - - repeat (8) - begin - # 10 - key <= $urandom (); - sw <= $urandom (); - end - - $finish; - end - -endmodule diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash b/labs/5_cpu/5_1_schoolriscv/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash rename to labs/5_cpu/5_1_schoolriscv/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/5_cpu/5_1_schoolriscv/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/5_cpu/5_1_schoolriscv/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/5_cpu/5_1_schoolriscv/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/5_cpu/5_1_schoolriscv/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/5_cpu/5_1_schoolriscv/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/5_cpu/5_1_schoolriscv/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/5_cpu/5_1_schoolriscv/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/5_cpu/5_1_schoolriscv/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/5_cpu/5_1_schoolriscv/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/5_cpu/5_1_schoolriscv/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/5_cpu/5_1_schoolriscv/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/5_cpu/5_1_schoolriscv/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/5_cpu/5_1_schoolriscv/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/5_cpu/5_1_schoolriscv/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/5_cpu/5_1_schoolriscv/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/5_cpu/5_1_schoolriscv/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/30_schoolriscv/10_run_instruction_set_simulator.bash b/labs/5_cpu/5_1_schoolriscv/10_run_instruction_set_simulator.bash similarity index 100% rename from labs/30_schoolriscv/10_run_instruction_set_simulator.bash rename to labs/5_cpu/5_1_schoolriscv/10_run_instruction_set_simulator.bash diff --git a/labs/30_schoolriscv/asic_config.tcl b/labs/5_cpu/5_1_schoolriscv/asic_config.tcl similarity index 100% rename from labs/30_schoolriscv/asic_config.tcl rename to labs/5_cpu/5_1_schoolriscv/asic_config.tcl diff --git a/labs/30_schoolriscv/asic_top.sv b/labs/5_cpu/5_1_schoolriscv/asic_top.sv similarity index 98% rename from labs/30_schoolriscv/asic_top.sv rename to labs/5_cpu/5_1_schoolriscv/asic_top.sv index a3b8fdec..2e8dbf3a 100644 --- a/labs/30_schoolriscv/asic_top.sv +++ b/labs/5_cpu/5_1_schoolriscv/asic_top.sv @@ -26,7 +26,7 @@ module asic_top output logic [w_digit - 1:0] digit ); - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -35,7 +35,7 @@ module asic_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/labs/30_schoolriscv/gtkwave.tcl b/labs/5_cpu/5_1_schoolriscv/gtkwave.tcl similarity index 100% rename from labs/30_schoolriscv/gtkwave.tcl rename to labs/5_cpu/5_1_schoolriscv/gtkwave.tcl diff --git a/labs/30_schoolriscv/instruction_rom.sv b/labs/5_cpu/5_1_schoolriscv/instruction_rom.sv similarity index 100% rename from labs/30_schoolriscv/instruction_rom.sv rename to labs/5_cpu/5_1_schoolriscv/instruction_rom.sv diff --git a/labs/30_schoolriscv/top.sv b/labs/5_cpu/5_1_schoolriscv/lab_top.sv similarity index 78% rename from labs/30_schoolriscv/top.sv rename to labs/5_cpu/5_1_schoolriscv/lab_top.sv index 1f580683..b9e57eae 100644 --- a/labs/30_schoolriscv/top.sv +++ b/labs/5_cpu/5_1_schoolriscv/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/30_schoolriscv/program.s b/labs/5_cpu/5_1_schoolriscv/program.s similarity index 100% rename from labs/30_schoolriscv/program.s rename to labs/5_cpu/5_1_schoolriscv/program.s diff --git a/labs/30_schoolriscv/register_with_rst.sv b/labs/5_cpu/5_1_schoolriscv/register_with_rst.sv similarity index 100% rename from labs/30_schoolriscv/register_with_rst.sv rename to labs/5_cpu/5_1_schoolriscv/register_with_rst.sv diff --git a/labs/30_schoolriscv/screenshots/screen_01.png b/labs/5_cpu/5_1_schoolriscv/screenshots/screen_01.png similarity index 100% rename from labs/30_schoolriscv/screenshots/screen_01.png rename to labs/5_cpu/5_1_schoolriscv/screenshots/screen_01.png diff --git a/labs/30_schoolriscv/screenshots/screen_02.png b/labs/5_cpu/5_1_schoolriscv/screenshots/screen_02.png similarity index 100% rename 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a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/6_misc/6_1_geiger_muller_radiation_counter/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/6_misc/6_1_geiger_muller_radiation_counter/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/6_misc/6_1_geiger_muller_radiation_counter/gtkwave.tcl b/labs/6_misc/6_1_geiger_muller_radiation_counter/gtkwave.tcl new file mode 100644 index 00000000..c6866a7f --- /dev/null +++ b/labs/6_misc/6_1_geiger_muller_radiation_counter/gtkwave.tcl @@ -0,0 +1,15 @@ +# gtkwave::loadFile "dump.vcd" + +set all_signals [list] + +lappend all_signals tb.clk +lappend all_signals tb.rst +lappend all_signals tb.key +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit + +set num_added [ gtkwave::addSignalsFromList $all_signals ] + +gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_specific_board_config.svh b/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_specific_board_config.svh new file mode 100644 index 00000000..77e0113b --- /dev/null +++ b/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_specific_board_config.svh @@ -0,0 +1,17 @@ +`ifndef LAB_SPECIFIC_CONFIG_SVH +`define LAB_SPECIFIC_CONFIG_SVH + + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE + +// `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 + `define CONCAT_TM1638_SIGNALS_AND_REGULAR + +// `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + +`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/17_geiger_muller_radiation_counter/top.sv b/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_top.sv similarity index 89% rename from labs/17_geiger_muller_radiation_counter/top.sv rename to labs/6_misc/6_1_geiger_muller_radiation_counter/lab_top.sv index edbd6705..0bd84ae7 100644 --- a/labs/17_geiger_muller_radiation_counter/top.sv +++ b/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/10_hex_counter/tb.sv b/labs/6_misc/6_1_geiger_muller_radiation_counter/tb.sv similarity index 98% rename from labs/10_hex_counter/tb.sv rename to labs/6_misc/6_1_geiger_muller_radiation_counter/tb.sv index 878384bd..643cf7b7 100644 --- a/labs/10_hex_counter/tb.sv +++ b/labs/6_misc/6_1_geiger_muller_radiation_counter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/01_clean.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/02_03_serial_adder_using_logic_operations_only.sv b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/02_03_serial_adder_using_logic_operations_only.sv similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/02_03_serial_adder_using_logic_operations_only.sv rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/02_03_serial_adder_using_logic_operations_only.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/expected_log.txt b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/expected_log.txt similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/expected_log.txt rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/expected_log.txt diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/gtkwave.tcl b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/gtkwave.tcl similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/gtkwave.tcl rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/gtkwave.tcl diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/top.sv b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/lab_top.sv similarity index 81% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/top.sv rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/lab_top.sv index 6542d1b2..6f6fc281 100644 --- a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/top.sv +++ b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/lab_top.sv @@ -2,18 +2,24 @@ `ifndef SIMULATION -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/tb.sv b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/tb.sv similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/tb.sv rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/tb.sv diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/01_clean.bash b/labs/8_unfinished/8_1_uart/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/01_clean.bash rename to labs/8_unfinished/8_1_uart/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash b/labs/8_unfinished/8_1_uart/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash rename to labs/8_unfinished/8_1_uart/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash b/labs/8_unfinished/8_1_uart/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash rename to labs/8_unfinished/8_1_uart/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/04_configure_fpga.bash b/labs/8_unfinished/8_1_uart/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/04_configure_fpga.bash rename to labs/8_unfinished/8_1_uart/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/05_run_gui_for_fpga_synthesis.bash b/labs/8_unfinished/8_1_uart/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/05_run_gui_for_fpga_synthesis.bash rename to labs/8_unfinished/8_1_uart/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/06_choose_another_fpga_board.bash b/labs/8_unfinished/8_1_uart/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/06_choose_another_fpga_board.bash rename to labs/8_unfinished/8_1_uart/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/07_synthesize_for_asic.bash b/labs/8_unfinished/8_1_uart/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/07_synthesize_for_asic.bash rename to labs/8_unfinished/8_1_uart/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/08_visualize_asic_synthesis_results_1.bash b/labs/8_unfinished/8_1_uart/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/08_visualize_asic_synthesis_results_1.bash rename to labs/8_unfinished/8_1_uart/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/09_visualize_asic_synthesis_results_2.bash b/labs/8_unfinished/8_1_uart/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/09_visualize_asic_synthesis_results_2.bash rename to labs/8_unfinished/8_1_uart/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/15_uart/TODO b/labs/8_unfinished/8_1_uart/TODO similarity index 100% rename from labs/15_uart/TODO rename to labs/8_unfinished/8_1_uart/TODO diff --git a/labs/15_uart/top.sv b/labs/8_unfinished/8_1_uart/lab_top.sv similarity index 78% rename from labs/15_uart/top.sv rename to labs/8_unfinished/8_1_uart/lab_top.sv index 3c79b20c..63b9eee7 100644 --- a/labs/15_uart/top.sv +++ b/labs/8_unfinished/8_1_uart/lab_top.sv @@ -1,17 +1,25 @@ `include "config.svh" -module top +`ifndef SIMULATION + +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +37,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +64,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/8_unfinished/8_1_uart/tb.sv b/labs/8_unfinished/8_1_uart/tb.sv new file mode 100644 index 00000000..643cf7b7 --- /dev/null +++ b/labs/8_unfinished/8_1_uart/tb.sv @@ -0,0 +1,94 @@ +`include "config.svh" + +module tb; + + localparam clk_mhz = 1, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100; + + //------------------------------------------------------------------------ + + logic clk; + logic rst; + logic [3:0] key; + logic [7:0] sw; + + //------------------------------------------------------------------------ + + lab_top + # ( + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ) + ) + i_lab_top + ( + .clk ( clk ), + .slow_clk ( clk ), + .rst ( rst ), + .key ( key ), + .sw ( sw ) + ); + + //------------------------------------------------------------------------ + + initial + begin + clk = 1'b0; + + forever + # 5 clk = ~ clk; + end + + //------------------------------------------------------------------------ + + initial + begin + rst <= 1'bx; + repeat (2) @ (posedge clk); + rst <= 1'b1; + repeat (2) @ (posedge clk); + rst <= 1'b0; + end + + //------------------------------------------------------------------------ + + initial + begin + `ifdef __ICARUS__ + $dumpvars; + `endif + + key <= '0; + sw <= '0; + + @ (negedge rst); + + repeat (50) + begin + @ (posedge clk); + + key <= $urandom (); + sw <= $urandom (); + end + + // To change only one key + + key <= '0; + + repeat (50) + begin + @ (posedge clk); + key [0] <= $urandom (); + end + + $finish; + end + +endmodule diff --git a/labs/15_uart/to_integrate/check_which_port_is_used.bat b/labs/8_unfinished/8_1_uart/to_integrate/check_which_port_is_used.bat similarity index 100% rename from labs/15_uart/to_integrate/check_which_port_is_used.bat rename to labs/8_unfinished/8_1_uart/to_integrate/check_which_port_is_used.bat diff --git a/labs/15_uart/to_integrate/drive_uart.bat b/labs/8_unfinished/8_1_uart/to_integrate/drive_uart.bat similarity index 100% rename from labs/15_uart/to_integrate/drive_uart.bat rename to labs/8_unfinished/8_1_uart/to_integrate/drive_uart.bat diff --git a/labs/15_uart/to_integrate/hex_parser.sv b/labs/8_unfinished/8_1_uart/to_integrate/hex_parser.sv similarity index 100% rename from labs/15_uart/to_integrate/hex_parser.sv rename to labs/8_unfinished/8_1_uart/to_integrate/hex_parser.sv diff --git a/labs/15_uart/to_integrate/top.sv b/labs/8_unfinished/8_1_uart/to_integrate/lab_top.sv similarity index 99% rename from labs/15_uart/to_integrate/top.sv rename to labs/8_unfinished/8_1_uart/to_integrate/lab_top.sv index 0dd85f73..7cf6bf1a 100644 --- a/labs/15_uart/to_integrate/top.sv +++ b/labs/8_unfinished/8_1_uart/to_integrate/lab_top.sv @@ -1,6 +1,6 @@ // Asynchronous reset here is needed for the FPGA board we use -module top +module lab_top # ( parameter clk_frequency = 50 * 1000 * 1000, baud_rate = 115200, diff --git a/labs/15_uart/to_integrate/tb.sv b/labs/8_unfinished/8_1_uart/to_integrate/tb.sv similarity index 98% rename from labs/15_uart/to_integrate/tb.sv rename to labs/8_unfinished/8_1_uart/to_integrate/tb.sv index 9a0d07d1..0a53fb2e 100644 --- a/labs/15_uart/to_integrate/tb.sv +++ b/labs/8_unfinished/8_1_uart/to_integrate/tb.sv @@ -5,13 +5,13 @@ module tb; logic [3:0] key_sw; logic rx; - top + lab_top # ( .clk_frequency ( 50 ), .baud_rate ( 1 ), .timeout_in_seconds ( 1000 ) ) - i_top + i_lab_top ( .clk ( clk ), .reset_n ( reset_n ), diff --git a/labs/15_uart/to_integrate/top_extra.qsf b/labs/8_unfinished/8_1_uart/to_integrate/top_extra.qsf similarity index 100% rename from labs/15_uart/to_integrate/top_extra.qsf rename to labs/8_unfinished/8_1_uart/to_integrate/top_extra.qsf diff --git a/labs/15_uart/to_integrate/top_extra.sdc b/labs/8_unfinished/8_1_uart/to_integrate/top_extra.sdc similarity index 100% rename from labs/15_uart/to_integrate/top_extra.sdc rename to labs/8_unfinished/8_1_uart/to_integrate/top_extra.sdc diff --git a/labs/15_uart/to_integrate/uart_receiver.sv b/labs/8_unfinished/8_1_uart/to_integrate/uart_receiver.sv similarity index 100% rename from labs/15_uart/to_integrate/uart_receiver.sv rename to labs/8_unfinished/8_1_uart/to_integrate/uart_receiver.sv diff --git a/labs/15_uart/to_integrate/x_drive_uart.bash b/labs/8_unfinished/8_1_uart/to_integrate/x_drive_uart.bash similarity index 100% rename from labs/15_uart/to_integrate/x_drive_uart.bash rename to labs/8_unfinished/8_1_uart/to_integrate/x_drive_uart.bash diff --git a/labs/8_unfinished/8_1_uart/to_integrate/xx_gtkwave_extra.tcl b/labs/8_unfinished/8_1_uart/to_integrate/xx_gtkwave_extra.tcl new file mode 100644 index 00000000..af7ba9ae --- /dev/null +++ b/labs/8_unfinished/8_1_uart/to_integrate/xx_gtkwave_extra.tcl @@ -0,0 +1 @@ +lappend all_signals tb.i_lab_top.rx diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/01_clean.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/01_clean.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/01_clean.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/01_clean.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/02_simulate_rtl.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/02_simulate_rtl.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/03_synthesize_for_fpga.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/03_synthesize_for_fpga.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/04_configure_fpga.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/04_configure_fpga.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/04_configure_fpga.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/04_configure_fpga.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/05_run_gui_for_fpga_synthesis.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/05_run_gui_for_fpga_synthesis.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/06_choose_another_fpga_board.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/06_choose_another_fpga_board.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/06_choose_another_fpga_board.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/06_choose_another_fpga_board.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/07_synthesize_for_asic.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/07_synthesize_for_asic.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/07_synthesize_for_asic.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/07_synthesize_for_asic.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/08_visualize_asic_synthesis_results_1.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/08_visualize_asic_synthesis_results_1.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/09_visualize_asic_synthesis_results_2.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/09_visualize_asic_synthesis_results_2.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/flip_flop_fifo.sv b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/flip_flop_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/flip_flop_fifo.sv rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/flip_flop_fifo.sv diff --git a/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/gtkwave.tcl b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/gtkwave.tcl new file mode 100644 index 00000000..4e017826 --- /dev/null +++ b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/gtkwave.tcl @@ -0,0 +1,25 @@ +# gtkwave::loadFile "dump.vcd" + +set all_signals [list] + +lappend all_signals tb.i_lab_top.clk +lappend all_signals tb.i_lab_top.rst +lappend all_signals tb.i_lab_top.a_valid +lappend all_signals tb.i_lab_top.a_ready +lappend all_signals tb.i_lab_top.a_data +lappend all_signals tb.i_lab_top.b_valid +lappend all_signals tb.i_lab_top.b_ready +lappend all_signals tb.i_lab_top.b_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_data +lappend all_signals tb.i_lab_top.out_valid +lappend all_signals tb.i_lab_top.out_ready +lappend all_signals tb.i_lab_top.out_data + +set num_added [ gtkwave::addSignalsFromList $all_signals ] + +gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/lab_top.sv similarity index 87% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/lab_top.sv index ee34fb00..d631f4d7 100644 --- a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv +++ b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/lab_top.sv @@ -1,17 +1,23 @@ `include "config.svh" -module top +module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/round_robin_arbiter_2_requests.sv b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_2_requests.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/round_robin_arbiter_2_requests.sv rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_2_requests.sv diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv diff --git a/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/tb.sv b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/tb.sv new file mode 100644 index 00000000..6f6e5ddc --- /dev/null +++ b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/tb.sv @@ -0,0 +1,84 @@ +`include "config.svh" + +module tb; + + localparam clk_mhz = 1, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100; + + //------------------------------------------------------------------------ + + logic clk; + logic rst; + logic [3:0] key; + logic [7:0] sw; + + //------------------------------------------------------------------------ + + lab_top + # ( + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ) + ) + i_lab_top + ( + .clk ( clk ), + .slow_clk ( clk ), + .rst ( rst ), + .key ( key ), + .sw ( sw ) + ); + + //------------------------------------------------------------------------ + + initial + begin + clk = 1'b0; + + forever + # 5 clk = ~ clk; + end + + //------------------------------------------------------------------------ + + initial + begin + rst <= 1'bx; + repeat (2) @ (posedge clk); + rst <= 1'b1; + repeat (2) @ (posedge clk); + rst <= 1'b0; + end + + //------------------------------------------------------------------------ + + initial + begin + `ifdef __ICARUS__ + $dumpvars; + `endif + + key <= '0; + sw <= '0; + + @ (negedge rst); + + repeat (50) + begin + @ (posedge clk); + + key <= $urandom (); + sw <= $urandom (); + end + + $finish; + end + +endmodule diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl deleted file mode 100644 index f61d9458..00000000 --- a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# gtkwave::loadFile "dump.vcd" - -set all_signals [list] - -lappend all_signals tb.i_top.clk -lappend all_signals tb.i_top.rst -lappend all_signals tb.i_top.a_valid -lappend all_signals tb.i_top.a_ready -lappend all_signals tb.i_top.a_data -lappend all_signals tb.i_top.b_valid -lappend all_signals tb.i_top.b_ready -lappend all_signals tb.i_top.b_data -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_data -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_data -lappend all_signals tb.i_top.out_valid -lappend all_signals tb.i_top.out_ready -lappend all_signals tb.i_top.out_data - -set num_added [ gtkwave::addSignalsFromList $all_signals ] - -gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl deleted file mode 100644 index f61d9458..00000000 --- a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# gtkwave::loadFile "dump.vcd" - -set all_signals [list] - -lappend all_signals tb.i_top.clk -lappend all_signals tb.i_top.rst -lappend all_signals tb.i_top.a_valid -lappend all_signals tb.i_top.a_ready -lappend all_signals tb.i_top.a_data -lappend all_signals tb.i_top.b_valid -lappend all_signals tb.i_top.b_ready -lappend all_signals tb.i_top.b_data -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_data -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_data -lappend all_signals tb.i_top.out_valid -lappend all_signals tb.i_top.out_ready -lappend all_signals tb.i_top.out_data - -set num_added [ gtkwave::addSignalsFromList $all_signals ] - -gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl deleted file mode 100644 index f61d9458..00000000 --- a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# gtkwave::loadFile "dump.vcd" - -set all_signals [list] - -lappend all_signals tb.i_top.clk -lappend all_signals tb.i_top.rst -lappend all_signals tb.i_top.a_valid -lappend all_signals tb.i_top.a_ready -lappend all_signals tb.i_top.a_data -lappend all_signals tb.i_top.b_valid -lappend all_signals tb.i_top.b_ready -lappend all_signals tb.i_top.b_data -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_data -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_data -lappend all_signals tb.i_top.out_valid -lappend all_signals tb.i_top.out_ready -lappend all_signals tb.i_top.out_data - -set num_added [ gtkwave::addSignalsFromList $all_signals ] - -gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv deleted file mode 100644 index 5284c427..00000000 --- a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ /dev/null @@ -1,84 +0,0 @@ -`include "config.svh" - -module tb; - - localparam clk_mhz = 1, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100; - - //------------------------------------------------------------------------ - - logic clk; - logic rst; - logic [3:0] key; - logic [7:0] sw; - - //------------------------------------------------------------------------ - - top - # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_sw ), - .w_led ( w_led ), - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) - ) - i_top - ( - .clk ( clk ), - .slow_clk ( clk ), - .rst ( rst ), - .key ( key ), - .sw ( sw ) - ); - - //------------------------------------------------------------------------ - - initial - begin - clk = 1'b0; - - forever - # 5 clk = ~ clk; - end - - //------------------------------------------------------------------------ - - initial - begin - rst <= 1'bx; - repeat (2) @ (posedge clk); - rst <= 1'b1; - repeat (2) @ (posedge clk); - rst <= 1'b0; - end - - //------------------------------------------------------------------------ - - initial - begin - `ifdef __ICARUS__ - $dumpvars; - `endif - - key <= '0; - sw <= '0; - - @ (negedge rst); - - repeat (50) - begin - @ (posedge clk); - - key <= $urandom (); - sw <= $urandom (); - end - - $finish; - end - -endmodule diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl deleted file mode 100644 index f61d9458..00000000 --- a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# gtkwave::loadFile "dump.vcd" - -set all_signals [list] - -lappend all_signals tb.i_top.clk -lappend all_signals tb.i_top.rst -lappend all_signals tb.i_top.a_valid -lappend all_signals tb.i_top.a_ready -lappend all_signals tb.i_top.a_data -lappend all_signals tb.i_top.b_valid -lappend all_signals tb.i_top.b_ready -lappend all_signals tb.i_top.b_data -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_data -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_data -lappend all_signals tb.i_top.out_valid -lappend all_signals tb.i_top.out_ready -lappend all_signals tb.i_top.out_data - -set num_added [ gtkwave::addSignalsFromList $all_signals ] - -gtkwave::/Time/Zoom/Zoom_Full diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv deleted file mode 100644 index 5284c427..00000000 --- a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv +++ /dev/null @@ -1,84 +0,0 @@ -`include "config.svh" - -module tb; - - localparam clk_mhz = 1, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100; - - //------------------------------------------------------------------------ - - logic clk; - logic rst; - logic [3:0] key; - logic [7:0] sw; - - //------------------------------------------------------------------------ - - top - # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_sw ), - .w_led ( w_led ), - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) - ) - i_top - ( - .clk ( clk ), - .slow_clk ( clk ), - .rst ( rst ), - .key ( key ), - .sw ( sw ) - ); - - //------------------------------------------------------------------------ - - initial - begin - clk = 1'b0; - - forever - # 5 clk = ~ clk; - end - - //------------------------------------------------------------------------ - - initial - begin - rst <= 1'bx; - repeat (2) @ (posedge clk); - rst <= 1'b1; - repeat (2) @ (posedge clk); - rst <= 1'b0; - end - - //------------------------------------------------------------------------ - - initial - begin - `ifdef __ICARUS__ - $dumpvars; - `endif - - key <= '0; - sw <= '0; - - @ (negedge rst); - - repeat (50) - begin - @ (posedge clk); - - key <= $urandom (); - sw <= $urandom (); - end - - $finish; - end - -endmodule diff --git a/labs/common/lab_specific_config.svh b/labs/common/lab_specific_config.svh deleted file mode 100644 index 3c90f1a1..00000000 --- a/labs/common/lab_specific_config.svh +++ /dev/null @@ -1,20 +0,0 @@ -`ifndef LAB_SPECIFIC_CONFIG_SVH -`define LAB_SPECIFIC_CONFIG_SVH - -// This is the default file included -// when there is no lab_specific_config.svh -// in the lab directory - -// The following setting is needed for Gowin boards - `define ENABLE_TM1638 - -// HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 - -// `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS - - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM -// `define CONCAT_TM_SIGNALS_AND_REGULAR - -`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/misc/000_todo/epm240_blue/00_template/top.sv b/misc/000_todo/epm240_blue/00_template/lab_top.sv similarity index 99% rename from misc/000_todo/epm240_blue/00_template/top.sv rename to misc/000_todo/epm240_blue/00_template/lab_top.sv index 773ce17d..8db41f0f 100644 --- a/misc/000_todo/epm240_blue/00_template/top.sv +++ b/misc/000_todo/epm240_blue/00_template/lab_top.sv @@ -1,4 +1,4 @@ -module top +module lab_top ( input clk, output led, diff --git a/misc/000_todo/epm240_blue/11_vga/top.sv b/misc/000_todo/epm240_blue/11_vga/lab_top.sv similarity index 99% rename from misc/000_todo/epm240_blue/11_vga/top.sv rename to misc/000_todo/epm240_blue/11_vga/lab_top.sv index cd74360d..fb773cd7 100644 --- a/misc/000_todo/epm240_blue/11_vga/top.sv +++ b/misc/000_todo/epm240_blue/11_vga/lab_top.sv @@ -1,4 +1,4 @@ -module top +module lab_top ( input clk, input rst_n, diff --git a/misc/000_todo/epm240_red/00_template/top.sv b/misc/000_todo/epm240_red/00_template/lab_top.sv similarity index 99% rename from misc/000_todo/epm240_red/00_template/top.sv rename to misc/000_todo/epm240_red/00_template/lab_top.sv index 68a4062d..bd2e9435 100644 --- a/misc/000_todo/epm240_red/00_template/top.sv +++ b/misc/000_todo/epm240_red/00_template/lab_top.sv @@ -1,4 +1,4 @@ -module top +module lab_top ( input clk_12, clk_14, clk_62, clk_64, diff --git a/misc/review_for_style/labs/11_2_note_recognition_with_filtering/top.sv b/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv similarity index 99% rename from misc/review_for_style/labs/11_2_note_recognition_with_filtering/top.sv rename to misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv index fd8db781..479f98f2 100644 --- a/misc/review_for_style/labs/11_2_note_recognition_with_filtering/top.sv +++ b/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv @@ -1,9 +1,9 @@ `include "config.svh" `define ENABLE_TP1638 -`define HCW132 +`define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE `define ENABLE_INMP441 -module top +module lab_top # ( parameter clk_mhz = 50, w_key = 4, diff --git a/misc/review_for_style/labs/11_3_mic_to_uart/top.sv b/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv similarity index 98% rename from misc/review_for_style/labs/11_3_mic_to_uart/top.sv rename to misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv index 8726cdda..5efc68d1 100644 --- a/misc/review_for_style/labs/11_3_mic_to_uart/top.sv +++ b/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv @@ -1,9 +1,9 @@ `include "config.svh" `define ENABLE_TP1638 -`define HCW132 +`define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE `define ENABLE_INMP441 -module top +module lab_top # ( parameter clk_mhz = 50, w_key = 4, diff --git a/labs/common/digilent_pmod_mic3_spi_receiver.sv b/peripherals/digilent_pmod_mic3_spi_receiver.sv similarity index 100% rename from labs/common/digilent_pmod_mic3_spi_receiver.sv rename to peripherals/digilent_pmod_mic3_spi_receiver.sv diff --git a/labs/common/i2s_audio_out.sv b/peripherals/i2s_audio_out.sv similarity index 100% rename from labs/common/i2s_audio_out.sv rename to peripherals/i2s_audio_out.sv diff --git a/labs/common/inmp441.pdf b/peripherals/inmp441.pdf similarity index 100% rename from labs/common/inmp441.pdf rename to peripherals/inmp441.pdf diff --git a/labs/common/inmp441_mic_i2s_receiver.sv b/peripherals/inmp441_mic_i2s_receiver.sv similarity index 100% rename from labs/common/inmp441_mic_i2s_receiver.sv rename to peripherals/inmp441_mic_i2s_receiver.sv diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh new file mode 100644 index 00000000..d65a060b --- /dev/null +++ b/peripherals/lab_specific_board_config.svh @@ -0,0 +1,21 @@ +`ifndef LAB_SPECIFIC_BOARD_CONFIG_SVH +`define LAB_SPECIFIC_BOARD_CONFIG_SVH + + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE + + `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 +// `define CONCAT_TM1638_SIGNALS_AND_REGULAR + +// `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + +`endif // `ifndef LAB_SPECIFIC_BOARD_CONFIG_SVH + +// This is the default file included +// when there is no lab_specific_board_config.svh +// in the lab directory diff --git a/peripherals/lcd_480_272.sv b/peripherals/lcd_480_272.sv new file mode 100644 index 00000000..f1776e33 --- /dev/null +++ b/peripherals/lcd_480_272.sv @@ -0,0 +1,111 @@ +// This module is created based on https://github.com/sipeed/TangNano-9K-example/lcd_4.3/src/VGA_timing.v + +module lcd_480_272 +( + input PixelClk, + input nRST, + + output LCD_DE, + output LCD_HSYNC, + output LCD_VSYNC, + + // Modified for basic-graphics-music: Removed LCD_RGB ports. + // These output signals are assigned in the top module code + // using input from lab_top module. + + /* + output [4:0] LCD_B, + output [5:0] LCD_G, + output [4:0] LCD_R + */ + + // Modified for basic-graphics-music: Added x and y outputs + + output [8:0] x, + output [8:0] y +); + + // Horizen count to Hsync, then next Horizen line. + + parameter H_Pixel_Valid = 16'd480; + parameter H_FrontPorch = 16'd50; + parameter H_BackPorch = 16'd30; + + parameter PixelForHS = H_Pixel_Valid + H_FrontPorch + H_BackPorch; + + parameter V_Pixel_Valid = 16'd272; + parameter V_FrontPorch = 16'd20; + parameter V_BackPorch = 16'd5; + + parameter PixelForVS = V_Pixel_Valid + V_FrontPorch + V_BackPorch; + + // Horizen pixel count + + reg [15:0] H_PixelCount; + reg [15:0] V_PixelCount; + + always @( posedge PixelClk or negedge nRST )begin + if( !nRST ) begin + V_PixelCount <= 16'b0; + H_PixelCount <= 16'b0; + end + else if( H_PixelCount == PixelForHS ) begin + V_PixelCount <= V_PixelCount + 1'b1; + H_PixelCount <= 16'b0; + end + else if( V_PixelCount == PixelForVS ) begin + V_PixelCount <= 16'b0; + H_PixelCount <= 16'b0; + end + else begin + V_PixelCount <= V_PixelCount ; + H_PixelCount <= H_PixelCount + 1'b1; + end + end + + // SYNC-DE MODE + + assign LCD_HSYNC = H_PixelCount <= (PixelForHS-H_FrontPorch) ? 1'b0 : 1'b1; + + assign LCD_VSYNC = V_PixelCount <= (PixelForVS-0) ? 1'b0 : 1'b1; + + assign LCD_DE = ( H_PixelCount >= H_BackPorch ) && ( H_PixelCount <= H_Pixel_Valid + H_BackPorch ) && + ( V_PixelCount >= V_BackPorch ) && ( V_PixelCount <= V_Pixel_Valid + V_BackPorch ) && PixelClk; + + // Modified for basic-graphics-music: Removed LCD_RGB port assignments. + // These output signals are assigned in the top module code + // using input from lab_top module. + + `ifdef COMMENTED_OUT + + // color bar + localparam Colorbar_width = H_Pixel_Valid / 16; + + assign LCD_R = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 0 )) ? 5'b00000 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 1 )) ? 5'b00001 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 2 )) ? 5'b00010 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 3 )) ? 5'b00100 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 4 )) ? 5'b01000 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 5 )) ? 5'b10000 : 5'b00000; + + assign LCD_G = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 6 )) ? 6'b000001: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 7 )) ? 6'b000010: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 8 )) ? 6'b000100: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 9 )) ? 6'b001000: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 10 )) ? 6'b010000: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 11 )) ? 6'b100000: 6'b000000; + + assign LCD_B = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 12 )) ? 5'b00001 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 13 )) ? 5'b00010 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 14 )) ? 5'b00100 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 15 )) ? 5'b01000 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 16 )) ? 5'b10000 : 5'b00000; + + `endif + + // Modified for basic-graphics-music: Added x and y outputs + + assign x = 9' (H_PixelCount - H_BackPorch); + assign y = 9' (V_PixelCount - V_BackPorch); + +endmodule diff --git a/labs/common/pmodmic3_rm.pdf b/peripherals/pmodmic3_rm.pdf similarity index 100% rename from labs/common/pmodmic3_rm.pdf rename to peripherals/pmodmic3_rm.pdf diff --git a/labs/common/slow_clk_gen.sv b/peripherals/slow_clk_gen.sv similarity index 100% rename from labs/common/slow_clk_gen.sv rename to peripherals/slow_clk_gen.sv diff --git a/labs/common/tm1638_board.sv b/peripherals/tm1638_board.sv similarity index 98% rename from labs/common/tm1638_board.sv rename to peripherals/tm1638_board.sv index b611f5a5..5a318572 100644 --- a/labs/common/tm1638_board.sv +++ b/peripherals/tm1638_board.sv @@ -217,7 +217,7 @@ Copyright 2017 Alan Garfield /////////////////////////////////////////////////////////////////////////////////// `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module tm1638_board_controller # ( @@ -231,7 +231,7 @@ module tm1638_board_controller input [ 7:0] hgfedcba, input [ w_digit - 1:0] digit, input [ 7:0] ledr, - `ifdef HCW132 + `ifdef USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE output logic [ 15:0] keys, `else output logic [ 7:0] keys, @@ -241,7 +241,7 @@ module tm1638_board_controller inout sio_data ); - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS localparam static_hex = 1'b0; `else localparam static_hex = 1'b1; @@ -428,7 +428,7 @@ module tm1638_board_controller 2: {tm_latch, tm_in} <= {HIGH, C_READ_KEYS}; // read mode 3: {tm_latch, tm_rw} <= {HIGH, LOW}; - `ifdef HCW132 + `ifdef USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE // read back keys S1 - S16 4: {keys[0], keys[1], keys[8], keys[9]} <= {tm_out[2], tm_out[6], tm_out[1], tm_out[5]}; 5: tm_latch <= HIGH; @@ -459,7 +459,7 @@ module tm1638_board_controller 17: {sio_stb, tm_rw} <= {LOW, HIGH}; 18: {tm_latch, tm_in} <= {HIGH, C_SET_ADDR_0}; // set addr 0 pos - `ifdef HCW132 + `ifdef USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 has very weird display map 19: display_digit({hex7[0],hex6[0],hex5[0],hex4[0],hex3[0],hex2[0],hex1[0],hex0[0]}); 20: display_digit(8'b00000000); diff --git a/labs/common/vga.sv b/peripherals/vga.sv similarity index 100% rename from labs/common/vga.sv rename to peripherals/vga.sv diff --git a/scripts/admin/prepare_public_package.bash b/scripts/admin/prepare_public_package.bash index bd6d29e7..45d2b533 100755 --- a/scripts/admin/prepare_public_package.bash +++ b/scripts/admin/prepare_public_package.bash @@ -110,7 +110,7 @@ fi # For some reason "--exclude=\*.mk" does not work here exclude_space_ok="--exclude-dir=urgReport --exclude=*.xdc" -exclude_tabs_ok="$exclude_space_ok --exclude=Makefile --exclude=*.mk" +exclude_tabs_ok="$exclude_space_ok --exclude=Makefile --exclude=*.mk --exclude=*.vo" if grep -rqI $exclude_tabs_ok $'\t' "$pkg_src_root"/* then diff --git a/scripts/asic/asic_top.sv b/scripts/asic/asic_top.sv index a3b8fdec..2e8dbf3a 100644 --- a/scripts/asic/asic_top.sv +++ b/scripts/asic/asic_top.sv @@ -26,7 +26,7 @@ module asic_top output logic [w_digit - 1:0] digit ); - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), @@ -35,7 +35,7 @@ module asic_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/scripts/steps/00_setup.source_bash b/scripts/steps/00_setup.source_bash index ae36520d..07ff2c2b 100644 --- a/scripts/steps/00_setup.source_bash +++ b/scripts/steps/00_setup.source_bash @@ -36,6 +36,7 @@ package_dir=$(readlink -f "$(dirname "${BASH_SOURCE[0]}")/../..") bin_dir="$package_dir/bin" board_dir="$package_dir/boards" lab_dir="$package_dir/labs" +peripheral_dir="$package_dir/peripherals" script_dir="$package_dir/scripts" #----------------------------------------------------------------------------- @@ -425,14 +426,19 @@ fpga_board_setup () create_fpga_board_select_file - read -n 1 -r -p "Would you like to create the new run directories for the synthesis of all labs in the package, based on your FPGA board selection? We recommend to do this if you plan to work with Quartus GUI rather than with the synthesis scripts. [y/n] " - printf "\n" + if [ ] + then + # This option is rarely used, so I decided to comment it out - if [[ "$REPLY" =~ ^[Yy]$ ]]; then + read -n 1 -r -p "Would you like to create the new run directories for the synthesis of all labs in the package, based on your FPGA board selection? We recommend to do this if you plan to work with synthesis GUI rather than with the synthesis scripts. [y/n] " printf "\n" - update_fpga_toolchain_var - create_new_run_directories_for_fpga_synthesis + if [[ "$REPLY" =~ ^[Yy]$ ]]; then + printf "\n" + + update_fpga_toolchain_var + create_new_run_directories_for_fpga_synthesis + fi fi fi diff --git a/scripts/steps/00_setup_gowin.source_bash b/scripts/steps/00_setup_gowin.source_bash index 5847a944..3e10ce18 100644 --- a/scripts/steps/00_setup_gowin.source_bash +++ b/scripts/steps/00_setup_gowin.source_bash @@ -215,6 +215,7 @@ setup_run_directory_for_fpga_synthesis_gowin () for verilog_src_dir in \ "$main_src_dir" \ "$board_dir/$fpga_board" \ + "$peripheral_dir" \ "$lab_dir/common" do $find_to_run \ @@ -236,6 +237,7 @@ setup_run_directory_for_fpga_synthesis_gowin () for verilog_src_dir in \ "$main_src_dir" \ "$board_dir/$fpga_board" \ + "$peripheral_dir" \ "$lab_dir/common" do $find_to_run \ @@ -263,6 +265,7 @@ setup_run_directory_for_fpga_synthesis_gowin () printf ' \"%s\"\n' "$(adj_path_for_gowin_win "$main_src_dir")" >> "$dir/impl/project_process_config.json" printf ' \"%s\",\n' "$(adj_path_for_gowin_win "$board_dir")/$fpga_board" >> "$dir/impl/project_process_config.json" + printf ' \"%s\",\n' "$(adj_path_for_gowin_win "$peripheral_dir")" >> "$dir/impl/project_process_config.json" printf ' \"%s\",\n' "$(adj_path_for_gowin_win "$lab_dir")/common" >> "$dir/impl/project_process_config.json" cat "$board_dir/$fpga_board/project_process_config_02.json" >> "$dir/impl/project_process_config.json" diff --git a/scripts/steps/00_setup_intel_fpga.source_bash b/scripts/steps/00_setup_intel_fpga.source_bash index 7bac3e63..8581222f 100644 --- a/scripts/steps/00_setup_intel_fpga.source_bash +++ b/scripts/steps/00_setup_intel_fpga.source_bash @@ -408,9 +408,10 @@ setup_run_directory_for_fpga_synthesis_quartus () # because these particular relative paths # are expected to contain only alnums, underscores and slashes. - rel_main_src_dir=$(realpath --relative-to="$dir" "$main_src_dir") - rel_board_dir=$(realpath --relative-to="$dir" "$board_dir") - rel_lab_dir=$(realpath --relative-to="$dir" "$lab_dir") + rel_main_src_dir=$(realpath --relative-to="$dir" "$main_src_dir") + rel_board_dir=$(realpath --relative-to="$dir" "$board_dir") + rel_peripheral_dir=$(realpath --relative-to="$dir" "$peripheral_dir") + rel_lab_dir=$(realpath --relative-to="$dir" "$lab_dir") #------------------------------------------------------------------------- @@ -423,12 +424,13 @@ set_global_assignment -name SDC_FILE $rel_board_dir/$fpga_board/ set_global_assignment -name SEARCH_PATH $rel_main_src_dir set_global_assignment -name SEARCH_PATH $rel_board_dir/$fpga_board +set_global_assignment -name SEARCH_PATH $rel_peripheral_dir set_global_assignment -name SEARCH_PATH $rel_lab_dir/common EOF $find_to_run \ - "$main_src_dir" "$board_dir/$fpga_board" "$lab_dir/common" \ + "$main_src_dir" "$board_dir/$fpga_board" "$peripheral_dir" "$lab_dir/common" \ -type f -name '*.sv' -not -name tb.sv \ -printf "set_global_assignment -name SYSTEMVERILOG_FILE %f\n" \ >> "$dir/fpga_project.qsf" diff --git a/scripts/steps/00_setup_yosys.source_bash b/scripts/steps/00_setup_yosys.source_bash index 9b353198..8e521710 100644 --- a/scripts/steps/00_setup_yosys.source_bash +++ b/scripts/steps/00_setup_yosys.source_bash @@ -93,12 +93,13 @@ setup_run_directory_for_fpga_synthesis_yosys () > "$dir/Makefile" echo "NAME = `basename $main_src_dir`" >> "$dir/Makefile" - echo "INC = $lab_dir/common" >> "$dir/Makefile" + echo "INC = $peripheral_dir;$lab_dir/common" >> "$dir/Makefile" echo "BOARD = $fpga_board" >> "$dir/Makefile" for verilog_src_dir in \ "$main_src_dir" \ "$board_dir/$fpga_board" \ + "$peripheral_dir" \ "$lab_dir/common" do # TODO: Check if we really need adj_path_for_gowin_win here diff --git a/scripts/steps/01_clean.source_bash b/scripts/steps/01_clean.source_bash index 87ba984e..8b8b69f5 100644 --- a/scripts/steps/01_clean.source_bash +++ b/scripts/steps/01_clean.source_bash @@ -2,7 +2,7 @@ cd .. -rm -rf run log.txt +rm -rf run log.txt if [ -n "${openlane_dir-}" ] ; then rm -rf "$openlane_dir/designs/$lab_name" diff --git a/scripts/steps/07_synthesize_for_asic.source_bash b/scripts/steps/07_synthesize_for_asic.source_bash index fd21c53a..8ad40ab6 100644 --- a/scripts/steps/07_synthesize_for_asic.source_bash +++ b/scripts/steps/07_synthesize_for_asic.source_bash @@ -23,11 +23,9 @@ cp "$script_dir/asic/asic_top.sv" "$design_dir/src" for f in \ config.svh \ counter_with_enable.sv \ - lab_specific_config.svh \ seven_segment_display.sv \ shift_reg.sv \ - strobe_gen.sv \ - vga.sv + strobe_gen.sv do cp -f "$lab_dir/common/$f" "$design_dir/src" done