From 42577bc07d2f7c3d1c7a4ce1d76a9cee7157cea7 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 08:54:01 -0700 Subject: [PATCH 01/65] Renamed top.sv into lab_top.sv everywhere --- labs/01_and_or_not_xor_de_morgan/{top.sv => lab_top.sv} | 0 labs/02_mux/{top.sv => lab_top.sv} | 0 labs/03_decoder/{top.sv => lab_top.sv} | 0 labs/04_priority_encoder/{top.sv => lab_top.sv} | 0 labs/05_7seven_segment_letter/{top.sv => lab_top.sv} | 0 labs/06_vga/{top.sv => lab_top.sv} | 0 labs/07_binary_counter/{top.sv => lab_top.sv} | 0 labs/08_shift_register/{top.sv => lab_top.sv} | 0 labs/09_7segment_word/{top.sv => lab_top.sv} | 0 labs/10_hex_counter/{top.sv => lab_top.sv} | 0 labs/11_note_recognition/{top.sv => lab_top.sv} | 0 labs/12_snail_fsm/{top.sv => lab_top.sv} | 0 labs/13_music_recognition/{top.sv => lab_top.sv} | 0 labs/14_game/{top.sv => lab_top.sv} | 0 labs/15_uart/{top.sv => lab_top.sv} | 0 labs/15_uart/to_integrate/{top.sv => lab_top.sv} | 0 labs/16_round_robin_arbiter/{top.sv => lab_top.sv} | 0 labs/17_geiger_muller_radiation_counter/{top.sv => lab_top.sv} | 0 labs/18_pow5_single_cycle/{top.sv => lab_top.sv} | 0 labs/19_pow5_pipelined/{top.sv => lab_top.sv} | 0 labs/20_pow5_pipelined_valid/{top.sv => lab_top.sv} | 0 labs/21_pow5_pipelined_valid_solution/{top.sv => lab_top.sv} | 0 labs/22_syst_ws/{top.sv => lab_top.sv} | 0 labs/23_i2s_synthesizer/{top.sv => lab_top.sv} | 0 labs/24_i2s_music/{top.sv => lab_top.sv} | 0 labs/30_schoolriscv/{top.sv => lab_top.sv} | 0 labs/50_crash_course/{top.sv => lab_top.sv} | 0 .../{top.sv => lab_top.sv} | 0 .../07_shift_register_to_compare/{top.sv => lab_top.sv} | 0 .../08_fifo_with_better_debug_1/{top.sv => lab_top.sv} | 0 .../09_fifo_with_better_debug_2/{top.sv => lab_top.sv} | 0 .../16_ff_fifo_wrapped_in_valid_ready/{top.sv => lab_top.sv} | 0 .../{top.sv => lab_top.sv} | 0 .../18_a_plus_b_using_fifos/{top.sv => lab_top.sv} | 0 .../25_pow_5_single_cycle/{top.sv => lab_top.sv} | 0 .../26_pow_5_pipelined/{top.sv => lab_top.sv} | 0 .../{top.sv => lab_top.sv} | 0 .../29_pow_5_pipelined_with_credit_counter/{top.sv => lab_top.sv} | 0 .../{top.sv => lab_top.sv} | 0 .../{top.sv => lab_top.sv} | 0 .../{top.sv => lab_top.sv} | 0 .../41_round_robin_arbiter_from_2_fifos/{top.sv => lab_top.sv} | 0 .../{top.sv => lab_top.sv} | 0 misc/000_todo/epm240_blue/00_template/{top.sv => lab_top.sv} | 0 misc/000_todo/epm240_blue/11_vga/{top.sv => lab_top.sv} | 0 misc/000_todo/epm240_red/00_template/{top.sv => lab_top.sv} | 0 .../11_2_note_recognition_with_filtering/{top.sv => lab_top.sv} | 0 .../review_for_style/labs/11_3_mic_to_uart/{top.sv => lab_top.sv} | 0 48 files changed, 0 insertions(+), 0 deletions(-) rename labs/01_and_or_not_xor_de_morgan/{top.sv => lab_top.sv} (100%) rename labs/02_mux/{top.sv => lab_top.sv} (100%) rename labs/03_decoder/{top.sv => lab_top.sv} (100%) rename labs/04_priority_encoder/{top.sv => lab_top.sv} (100%) rename labs/05_7seven_segment_letter/{top.sv => lab_top.sv} (100%) rename labs/06_vga/{top.sv => lab_top.sv} (100%) rename labs/07_binary_counter/{top.sv => lab_top.sv} (100%) rename labs/08_shift_register/{top.sv => lab_top.sv} (100%) rename labs/09_7segment_word/{top.sv => lab_top.sv} (100%) rename labs/10_hex_counter/{top.sv => lab_top.sv} (100%) rename labs/11_note_recognition/{top.sv => lab_top.sv} (100%) rename labs/12_snail_fsm/{top.sv => lab_top.sv} (100%) rename labs/13_music_recognition/{top.sv => lab_top.sv} (100%) rename labs/14_game/{top.sv => lab_top.sv} (100%) rename labs/15_uart/{top.sv => lab_top.sv} (100%) rename labs/15_uart/to_integrate/{top.sv => lab_top.sv} (100%) rename labs/16_round_robin_arbiter/{top.sv => lab_top.sv} (100%) rename labs/17_geiger_muller_radiation_counter/{top.sv => lab_top.sv} (100%) rename labs/18_pow5_single_cycle/{top.sv => lab_top.sv} (100%) rename labs/19_pow5_pipelined/{top.sv => lab_top.sv} (100%) rename labs/20_pow5_pipelined_valid/{top.sv => lab_top.sv} (100%) rename labs/21_pow5_pipelined_valid_solution/{top.sv => lab_top.sv} (100%) rename labs/22_syst_ws/{top.sv => lab_top.sv} (100%) rename labs/23_i2s_synthesizer/{top.sv => lab_top.sv} (100%) rename labs/24_i2s_music/{top.sv => lab_top.sv} (100%) rename labs/30_schoolriscv/{top.sv => lab_top.sv} (100%) rename labs/50_crash_course/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/07_shift_register_to_compare/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/26_pow_5_pipelined/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/{top.sv => lab_top.sv} (100%) rename labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/{top.sv => lab_top.sv} (100%) rename labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/{top.sv => lab_top.sv} (100%) rename misc/000_todo/epm240_blue/00_template/{top.sv => lab_top.sv} (100%) rename misc/000_todo/epm240_blue/11_vga/{top.sv => lab_top.sv} (100%) rename misc/000_todo/epm240_red/00_template/{top.sv => lab_top.sv} (100%) rename misc/review_for_style/labs/11_2_note_recognition_with_filtering/{top.sv => lab_top.sv} (100%) rename misc/review_for_style/labs/11_3_mic_to_uart/{top.sv => lab_top.sv} (100%) diff --git a/labs/01_and_or_not_xor_de_morgan/top.sv b/labs/01_and_or_not_xor_de_morgan/lab_top.sv similarity index 100% rename from labs/01_and_or_not_xor_de_morgan/top.sv rename to labs/01_and_or_not_xor_de_morgan/lab_top.sv diff --git a/labs/02_mux/top.sv b/labs/02_mux/lab_top.sv similarity index 100% rename from labs/02_mux/top.sv rename to labs/02_mux/lab_top.sv diff --git a/labs/03_decoder/top.sv b/labs/03_decoder/lab_top.sv similarity index 100% rename from labs/03_decoder/top.sv rename to labs/03_decoder/lab_top.sv diff --git a/labs/04_priority_encoder/top.sv b/labs/04_priority_encoder/lab_top.sv similarity index 100% rename from labs/04_priority_encoder/top.sv rename to labs/04_priority_encoder/lab_top.sv diff --git a/labs/05_7seven_segment_letter/top.sv b/labs/05_7seven_segment_letter/lab_top.sv similarity index 100% rename from labs/05_7seven_segment_letter/top.sv rename to labs/05_7seven_segment_letter/lab_top.sv diff --git a/labs/06_vga/top.sv b/labs/06_vga/lab_top.sv similarity index 100% rename from labs/06_vga/top.sv rename to labs/06_vga/lab_top.sv diff --git a/labs/07_binary_counter/top.sv b/labs/07_binary_counter/lab_top.sv similarity index 100% rename from labs/07_binary_counter/top.sv rename to labs/07_binary_counter/lab_top.sv diff --git a/labs/08_shift_register/top.sv b/labs/08_shift_register/lab_top.sv similarity index 100% rename from labs/08_shift_register/top.sv rename to labs/08_shift_register/lab_top.sv diff --git a/labs/09_7segment_word/top.sv b/labs/09_7segment_word/lab_top.sv similarity index 100% rename from labs/09_7segment_word/top.sv rename to labs/09_7segment_word/lab_top.sv diff --git a/labs/10_hex_counter/top.sv b/labs/10_hex_counter/lab_top.sv similarity index 100% rename from labs/10_hex_counter/top.sv rename to labs/10_hex_counter/lab_top.sv diff --git a/labs/11_note_recognition/top.sv b/labs/11_note_recognition/lab_top.sv similarity index 100% rename from labs/11_note_recognition/top.sv rename to labs/11_note_recognition/lab_top.sv diff --git a/labs/12_snail_fsm/top.sv b/labs/12_snail_fsm/lab_top.sv similarity index 100% rename from labs/12_snail_fsm/top.sv rename to labs/12_snail_fsm/lab_top.sv diff --git a/labs/13_music_recognition/top.sv b/labs/13_music_recognition/lab_top.sv similarity index 100% rename from labs/13_music_recognition/top.sv rename to labs/13_music_recognition/lab_top.sv diff --git a/labs/14_game/top.sv b/labs/14_game/lab_top.sv similarity index 100% rename from labs/14_game/top.sv rename to labs/14_game/lab_top.sv diff --git a/labs/15_uart/top.sv b/labs/15_uart/lab_top.sv similarity index 100% rename from labs/15_uart/top.sv rename to labs/15_uart/lab_top.sv diff --git a/labs/15_uart/to_integrate/top.sv b/labs/15_uart/to_integrate/lab_top.sv similarity index 100% rename from labs/15_uart/to_integrate/top.sv rename to labs/15_uart/to_integrate/lab_top.sv diff --git a/labs/16_round_robin_arbiter/top.sv b/labs/16_round_robin_arbiter/lab_top.sv similarity index 100% rename from labs/16_round_robin_arbiter/top.sv rename to labs/16_round_robin_arbiter/lab_top.sv diff --git a/labs/17_geiger_muller_radiation_counter/top.sv b/labs/17_geiger_muller_radiation_counter/lab_top.sv similarity index 100% rename from labs/17_geiger_muller_radiation_counter/top.sv rename to labs/17_geiger_muller_radiation_counter/lab_top.sv diff --git a/labs/18_pow5_single_cycle/top.sv b/labs/18_pow5_single_cycle/lab_top.sv similarity index 100% rename from labs/18_pow5_single_cycle/top.sv rename to labs/18_pow5_single_cycle/lab_top.sv diff --git a/labs/19_pow5_pipelined/top.sv b/labs/19_pow5_pipelined/lab_top.sv similarity index 100% rename from labs/19_pow5_pipelined/top.sv rename to labs/19_pow5_pipelined/lab_top.sv diff --git a/labs/20_pow5_pipelined_valid/top.sv b/labs/20_pow5_pipelined_valid/lab_top.sv similarity index 100% rename from labs/20_pow5_pipelined_valid/top.sv rename to labs/20_pow5_pipelined_valid/lab_top.sv diff --git a/labs/21_pow5_pipelined_valid_solution/top.sv b/labs/21_pow5_pipelined_valid_solution/lab_top.sv similarity index 100% rename from labs/21_pow5_pipelined_valid_solution/top.sv rename to labs/21_pow5_pipelined_valid_solution/lab_top.sv diff --git a/labs/22_syst_ws/top.sv b/labs/22_syst_ws/lab_top.sv similarity index 100% rename from labs/22_syst_ws/top.sv rename to labs/22_syst_ws/lab_top.sv diff --git a/labs/23_i2s_synthesizer/top.sv b/labs/23_i2s_synthesizer/lab_top.sv similarity index 100% rename from labs/23_i2s_synthesizer/top.sv rename to labs/23_i2s_synthesizer/lab_top.sv diff --git a/labs/24_i2s_music/top.sv b/labs/24_i2s_music/lab_top.sv similarity index 100% rename from labs/24_i2s_music/top.sv rename to labs/24_i2s_music/lab_top.sv diff --git a/labs/30_schoolriscv/top.sv b/labs/30_schoolriscv/lab_top.sv similarity index 100% rename from labs/30_schoolriscv/top.sv rename to labs/30_schoolriscv/lab_top.sv diff --git a/labs/50_crash_course/top.sv b/labs/50_crash_course/lab_top.sv similarity index 100% rename from labs/50_crash_course/top.sv rename to labs/50_crash_course/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/top.sv b/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/top.sv rename to labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/top.sv b/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/top.sv rename to labs/90_valid_ready_etc_preview/07_shift_register_to_compare/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/top.sv b/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/top.sv rename to labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/top.sv b/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/top.sv rename to labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/top.sv b/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/top.sv rename to labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/top.sv b/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/top.sv rename to labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/top.sv b/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/top.sv rename to labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/top.sv b/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/top.sv rename to labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/top.sv b/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/26_pow_5_pipelined/top.sv rename to labs/90_valid_ready_etc_preview/26_pow_5_pipelined/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/top.sv b/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/top.sv rename to labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/top.sv b/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/top.sv rename to labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv rename to labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv rename to labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/top.sv rename to labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/top.sv b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/top.sv rename to labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/lab_top.sv diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/top.sv b/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/lab_top.sv similarity index 100% rename from labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/top.sv rename to labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/lab_top.sv diff --git a/misc/000_todo/epm240_blue/00_template/top.sv b/misc/000_todo/epm240_blue/00_template/lab_top.sv similarity index 100% rename from misc/000_todo/epm240_blue/00_template/top.sv rename to misc/000_todo/epm240_blue/00_template/lab_top.sv diff --git a/misc/000_todo/epm240_blue/11_vga/top.sv b/misc/000_todo/epm240_blue/11_vga/lab_top.sv similarity index 100% rename from misc/000_todo/epm240_blue/11_vga/top.sv rename to misc/000_todo/epm240_blue/11_vga/lab_top.sv diff --git a/misc/000_todo/epm240_red/00_template/top.sv b/misc/000_todo/epm240_red/00_template/lab_top.sv similarity index 100% rename from misc/000_todo/epm240_red/00_template/top.sv rename to misc/000_todo/epm240_red/00_template/lab_top.sv diff --git a/misc/review_for_style/labs/11_2_note_recognition_with_filtering/top.sv b/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv similarity index 100% rename from misc/review_for_style/labs/11_2_note_recognition_with_filtering/top.sv rename to misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv diff --git a/misc/review_for_style/labs/11_3_mic_to_uart/top.sv b/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv similarity index 100% rename from misc/review_for_style/labs/11_3_mic_to_uart/top.sv rename to misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv From c01f2d314fb133e1ba51bd55e71e1238b57e3d6f Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 09:15:28 -0700 Subject: [PATCH 02/65] Minor script improvement --- scripts/steps/00_setup.source_bash | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/scripts/steps/00_setup.source_bash b/scripts/steps/00_setup.source_bash index ae36520d..63b3d3c5 100644 --- a/scripts/steps/00_setup.source_bash +++ b/scripts/steps/00_setup.source_bash @@ -425,14 +425,19 @@ fpga_board_setup () create_fpga_board_select_file - read -n 1 -r -p "Would you like to create the new run directories for the synthesis of all labs in the package, based on your FPGA board selection? We recommend to do this if you plan to work with Quartus GUI rather than with the synthesis scripts. [y/n] " - printf "\n" + if [ ] + then + # This option is rarely used, so I decided to comment it out - if [[ "$REPLY" =~ ^[Yy]$ ]]; then + read -n 1 -r -p "Would you like to create the new run directories for the synthesis of all labs in the package, based on your FPGA board selection? We recommend to do this if you plan to work with synthesis GUI rather than with the synthesis scripts. [y/n] " printf "\n" - update_fpga_toolchain_var - create_new_run_directories_for_fpga_synthesis + if [[ "$REPLY" =~ ^[Yy]$ ]]; then + printf "\n" + + update_fpga_toolchain_var + create_new_run_directories_for_fpga_synthesis + fi fi fi From 8980704b8774b686784db11358b21f945c2d47c4 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 09:50:47 -0700 Subject: [PATCH 03/65] Renamed top modules to lab_top modules --- labs/01_and_or_not_xor_de_morgan/lab_top.sv | 2 +- labs/02_mux/lab_top.sv | 2 +- labs/03_decoder/lab_top.sv | 2 +- labs/04_priority_encoder/lab_top.sv | 2 +- labs/05_7seven_segment_letter/lab_top.sv | 2 +- labs/06_vga/lab_top.sv | 2 +- labs/07_binary_counter/lab_top.sv | 2 +- labs/08_shift_register/lab_top.sv | 2 +- labs/09_7segment_word/lab_top.sv | 2 +- labs/10_hex_counter/lab_top.sv | 2 +- labs/11_note_recognition/lab_top.sv | 2 +- labs/12_snail_fsm/lab_top.sv | 2 +- labs/13_music_recognition/lab_top.sv | 2 +- labs/14_game/lab_top.sv | 2 +- labs/15_uart/lab_top.sv | 2 +- labs/15_uart/to_integrate/lab_top.sv | 2 +- labs/16_round_robin_arbiter/lab_top.sv | 2 +- labs/17_geiger_muller_radiation_counter/lab_top.sv | 2 +- labs/18_pow5_single_cycle/lab_top.sv | 2 +- labs/19_pow5_pipelined/lab_top.sv | 2 +- labs/20_pow5_pipelined_valid/lab_top.sv | 2 +- labs/21_pow5_pipelined_valid_solution/lab_top.sv | 2 +- labs/22_syst_ws/lab_top.sv | 2 +- labs/23_i2s_synthesizer/lab_top.sv | 2 +- labs/24_i2s_music/lab_top.sv | 2 +- labs/30_schoolriscv/lab_top.sv | 2 +- labs/50_crash_course/lab_top.sv | 2 +- .../01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv | 2 +- .../07_shift_register_to_compare/lab_top.sv | 2 +- .../08_fifo_with_better_debug_1/lab_top.sv | 2 +- .../09_fifo_with_better_debug_2/lab_top.sv | 2 +- .../16_ff_fifo_wrapped_in_valid_ready/lab_top.sv | 2 +- .../lab_top.sv | 2 +- .../18_a_plus_b_using_fifos/lab_top.sv | 2 +- .../90_valid_ready_etc_preview/25_pow_5_single_cycle/lab_top.sv | 2 +- labs/90_valid_ready_etc_preview/26_pow_5_pipelined/lab_top.sv | 2 +- .../28_pow_5_pipelined_without_flow_control/lab_top.sv | 2 +- .../29_pow_5_pipelined_with_credit_counter/lab_top.sv | 2 +- .../lab_top.sv | 2 +- .../lab_top.sv | 2 +- .../lab_top.sv | 2 +- .../later/41_round_robin_arbiter_from_2_fifos/lab_top.sv | 2 +- .../02_03_serial_adder_using_logic_operations_only/lab_top.sv | 2 +- misc/000_todo/epm240_blue/00_template/lab_top.sv | 2 +- misc/000_todo/epm240_blue/11_vga/lab_top.sv | 2 +- misc/000_todo/epm240_red/00_template/lab_top.sv | 2 +- .../labs/11_2_note_recognition_with_filtering/lab_top.sv | 2 +- misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv | 2 +- 48 files changed, 48 insertions(+), 48 deletions(-) diff --git a/labs/01_and_or_not_xor_de_morgan/lab_top.sv b/labs/01_and_or_not_xor_de_morgan/lab_top.sv index 3c26ba54..6d18eff6 100644 --- a/labs/01_and_or_not_xor_de_morgan/lab_top.sv +++ b/labs/01_and_or_not_xor_de_morgan/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/02_mux/lab_top.sv b/labs/02_mux/lab_top.sv index a057b074..a2cd1722 100644 --- a/labs/02_mux/lab_top.sv +++ b/labs/02_mux/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/03_decoder/lab_top.sv b/labs/03_decoder/lab_top.sv index f9275241..cb6ff387 100644 --- a/labs/03_decoder/lab_top.sv +++ b/labs/03_decoder/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/04_priority_encoder/lab_top.sv b/labs/04_priority_encoder/lab_top.sv index 33a0566c..45791e32 100644 --- a/labs/04_priority_encoder/lab_top.sv +++ b/labs/04_priority_encoder/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/05_7seven_segment_letter/lab_top.sv b/labs/05_7seven_segment_letter/lab_top.sv index e9dd667d..60948ce0 100644 --- a/labs/05_7seven_segment_letter/lab_top.sv +++ b/labs/05_7seven_segment_letter/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/06_vga/lab_top.sv b/labs/06_vga/lab_top.sv index f1e84090..53edd4e3 100644 --- a/labs/06_vga/lab_top.sv +++ b/labs/06_vga/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/07_binary_counter/lab_top.sv b/labs/07_binary_counter/lab_top.sv index 2a2c44ca..7b31b334 100644 --- a/labs/07_binary_counter/lab_top.sv +++ b/labs/07_binary_counter/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/08_shift_register/lab_top.sv b/labs/08_shift_register/lab_top.sv index 549d790f..527e155d 100644 --- a/labs/08_shift_register/lab_top.sv +++ b/labs/08_shift_register/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/09_7segment_word/lab_top.sv b/labs/09_7segment_word/lab_top.sv index c4fb41a7..5a2070db 100644 --- a/labs/09_7segment_word/lab_top.sv +++ b/labs/09_7segment_word/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/10_hex_counter/lab_top.sv b/labs/10_hex_counter/lab_top.sv index 5f09e9ed..7098c712 100644 --- a/labs/10_hex_counter/lab_top.sv +++ b/labs/10_hex_counter/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/11_note_recognition/lab_top.sv b/labs/11_note_recognition/lab_top.sv index ac679e7c..33ec7371 100644 --- a/labs/11_note_recognition/lab_top.sv +++ b/labs/11_note_recognition/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/12_snail_fsm/lab_top.sv b/labs/12_snail_fsm/lab_top.sv index 3c79b20c..56abf527 100644 --- a/labs/12_snail_fsm/lab_top.sv +++ b/labs/12_snail_fsm/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/13_music_recognition/lab_top.sv b/labs/13_music_recognition/lab_top.sv index 71c131ea..3a9fd20e 100644 --- a/labs/13_music_recognition/lab_top.sv +++ b/labs/13_music_recognition/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/14_game/lab_top.sv b/labs/14_game/lab_top.sv index 59ca941d..49cf0eb9 100644 --- a/labs/14_game/lab_top.sv +++ b/labs/14_game/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/15_uart/lab_top.sv b/labs/15_uart/lab_top.sv index 3c79b20c..56abf527 100644 --- a/labs/15_uart/lab_top.sv +++ b/labs/15_uart/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/15_uart/to_integrate/lab_top.sv b/labs/15_uart/to_integrate/lab_top.sv index 0dd85f73..7cf6bf1a 100644 --- a/labs/15_uart/to_integrate/lab_top.sv +++ b/labs/15_uart/to_integrate/lab_top.sv @@ -1,6 +1,6 @@ // Asynchronous reset here is needed for the FPGA board we use -module top +module lab_top # ( parameter clk_frequency = 50 * 1000 * 1000, baud_rate = 115200, diff --git a/labs/16_round_robin_arbiter/lab_top.sv b/labs/16_round_robin_arbiter/lab_top.sv index a1ba62aa..13cdbdba 100644 --- a/labs/16_round_robin_arbiter/lab_top.sv +++ b/labs/16_round_robin_arbiter/lab_top.sv @@ -4,7 +4,7 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/17_geiger_muller_radiation_counter/lab_top.sv b/labs/17_geiger_muller_radiation_counter/lab_top.sv index edbd6705..70234c9c 100644 --- a/labs/17_geiger_muller_radiation_counter/lab_top.sv +++ b/labs/17_geiger_muller_radiation_counter/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/18_pow5_single_cycle/lab_top.sv b/labs/18_pow5_single_cycle/lab_top.sv index 9bf43494..f4364811 100644 --- a/labs/18_pow5_single_cycle/lab_top.sv +++ b/labs/18_pow5_single_cycle/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/19_pow5_pipelined/lab_top.sv b/labs/19_pow5_pipelined/lab_top.sv index 541a7b01..a533ff2d 100644 --- a/labs/19_pow5_pipelined/lab_top.sv +++ b/labs/19_pow5_pipelined/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/20_pow5_pipelined_valid/lab_top.sv b/labs/20_pow5_pipelined_valid/lab_top.sv index fa63f932..de45b99b 100644 --- a/labs/20_pow5_pipelined_valid/lab_top.sv +++ b/labs/20_pow5_pipelined_valid/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/21_pow5_pipelined_valid_solution/lab_top.sv b/labs/21_pow5_pipelined_valid_solution/lab_top.sv index 9f06833e..8126c399 100644 --- a/labs/21_pow5_pipelined_valid_solution/lab_top.sv +++ b/labs/21_pow5_pipelined_valid_solution/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/22_syst_ws/lab_top.sv b/labs/22_syst_ws/lab_top.sv index b3f5c96e..147378e7 100644 --- a/labs/22_syst_ws/lab_top.sv +++ b/labs/22_syst_ws/lab_top.sv @@ -1,6 +1,6 @@ `timescale 1ns / 1ps -module top +module lab_top ( input logic clk, input logic rst, diff --git a/labs/23_i2s_synthesizer/lab_top.sv b/labs/23_i2s_synthesizer/lab_top.sv index a2f0805d..00c38b8f 100644 --- a/labs/23_i2s_synthesizer/lab_top.sv +++ b/labs/23_i2s_synthesizer/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/24_i2s_music/lab_top.sv b/labs/24_i2s_music/lab_top.sv index e1c98e53..af184520 100644 --- a/labs/24_i2s_music/lab_top.sv +++ b/labs/24_i2s_music/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/30_schoolriscv/lab_top.sv b/labs/30_schoolriscv/lab_top.sv index 1f580683..15fe3c29 100644 --- a/labs/30_schoolriscv/lab_top.sv +++ b/labs/30_schoolriscv/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/50_crash_course/lab_top.sv b/labs/50_crash_course/lab_top.sv index 03f882b4..a81f3310 100644 --- a/labs/50_crash_course/lab_top.sv +++ b/labs/50_crash_course/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv b/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv index 42ef608a..7cc179a3 100644 --- a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/lab_top.sv b/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/lab_top.sv index 9ae12ea2..96aa28d4 100644 --- a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv b/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv index 1338626f..b2f587a4 100644 --- a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/lab_top.sv b/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/lab_top.sv index ecc431d2..606b8ee7 100644 --- a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/lab_top.sv b/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/lab_top.sv index 2dbadf3b..2ccf6e74 100644 --- a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv b/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv index 2dbadf3b..2ccf6e74 100644 --- a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/lab_top.sv b/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/lab_top.sv index 2ae3aa4d..f81ca417 100644 --- a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/lab_top.sv b/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/lab_top.sv index d51ffca1..5f8dbbed 100644 --- a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/lab_top.sv b/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/lab_top.sv index 07b372c9..77659af3 100644 --- a/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/26_pow_5_pipelined/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/lab_top.sv b/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/lab_top.sv index c61c6ed8..6b82b4c1 100644 --- a/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/lab_top.sv b/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/lab_top.sv index 5e107789..901a08f0 100644 --- a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index ee34fb00..ddeeb42a 100644 --- a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index f8eecfba..87b12574 100644 --- a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index c5fad72c..8ddb10ab 100644 --- a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/lab_top.sv b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/lab_top.sv index ee34fb00..ddeeb42a 100644 --- a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/lab_top.sv b/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/lab_top.sv index 6542d1b2..eb2bc8c7 100644 --- a/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/lab_top.sv +++ b/labs/91_systemverilog_homework_preview/02_03_serial_adder_using_logic_operations_only/lab_top.sv @@ -2,7 +2,7 @@ `ifndef SIMULATION -module top +module lab_top # ( parameter clk_mhz = 50, pixel_mhz = 25, diff --git a/misc/000_todo/epm240_blue/00_template/lab_top.sv b/misc/000_todo/epm240_blue/00_template/lab_top.sv index 773ce17d..8db41f0f 100644 --- a/misc/000_todo/epm240_blue/00_template/lab_top.sv +++ b/misc/000_todo/epm240_blue/00_template/lab_top.sv @@ -1,4 +1,4 @@ -module top +module lab_top ( input clk, output led, diff --git a/misc/000_todo/epm240_blue/11_vga/lab_top.sv b/misc/000_todo/epm240_blue/11_vga/lab_top.sv index cd74360d..fb773cd7 100644 --- a/misc/000_todo/epm240_blue/11_vga/lab_top.sv +++ b/misc/000_todo/epm240_blue/11_vga/lab_top.sv @@ -1,4 +1,4 @@ -module top +module lab_top ( input clk, input rst_n, diff --git a/misc/000_todo/epm240_red/00_template/lab_top.sv b/misc/000_todo/epm240_red/00_template/lab_top.sv index 68a4062d..bd2e9435 100644 --- a/misc/000_todo/epm240_red/00_template/lab_top.sv +++ b/misc/000_todo/epm240_red/00_template/lab_top.sv @@ -1,4 +1,4 @@ -module top +module lab_top ( input clk_12, clk_14, clk_62, clk_64, diff --git a/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv b/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv index fd8db781..fee6c3c6 100644 --- a/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv +++ b/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv @@ -3,7 +3,7 @@ `define HCW132 `define ENABLE_INMP441 -module top +module lab_top # ( parameter clk_mhz = 50, w_key = 4, diff --git a/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv b/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv index 8726cdda..955bdb5d 100644 --- a/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv +++ b/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv @@ -3,7 +3,7 @@ `define HCW132 `define ENABLE_INMP441 -module top +module lab_top # ( parameter clk_mhz = 50, w_key = 4, From 584efb47873e2c745b065cb928169680ce1cb29e Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 10:33:52 -0700 Subject: [PATCH 04/65] Renamed top module instances to lab_top 1 --- boards/alinx_ax4010/board_specific_top.sv | 2 +- boards/arty_a7/board_specific_top.sv | 2 +- boards/arty_a7_pmod_mic3/board_specific_top.sv | 2 +- boards/basys3/board_specific_top.sv | 2 +- boards/c5gx_audio/board_specific_top.sv | 2 +- boards/c5gx_vga666/board_specific_top.sv | 2 +- boards/c5gx_vga_pmod/board_specific_top.sv | 2 +- boards/cmod_a7/board_specific_top.sv | 2 +- boards/de0/board_specific_top.sv | 2 +- boards/de0_cv/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga666/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 2 +- boards/de0_nano_vga666/board_specific_top.sv | 2 +- boards/de0_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de1/board_specific_top.sv | 2 +- boards/de10_lite/board_specific_top.sv | 2 +- boards/de10_lite_tm1638_arduino/board_specific_top.sv | 2 +- boards/de10_nano_vga666/board_specific_top.sv | 2 +- boards/de10_nano_vga_mister/board_specific_top.sv | 2 +- boards/de10_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de1_soc/board_specific_top.sv | 2 +- boards/de2/board_specific_top.sv | 2 +- boards/de2_115/board_specific_top.sv | 2 +- boards/dk_dev_3c120n/board_specific_top.sv | 2 +- boards/emooc_cc/board_specific_top.sv | 2 +- boards/ice40hx8k_evb_yosys/board_specific_top.sv | 2 +- boards/karnix_ecp5_yosys/board_specific_top.sv | 2 +- boards/nexys4/board_specific_top.sv | 2 +- boards/nexys4_ddr/board_specific_top.sv | 2 +- boards/nexys_a7/board_specific_top.sv | 2 +- boards/omdazz/board_specific_top.sv | 2 +- boards/omdazz_pmod_mic3/board_specific_top.sv | 2 +- boards/orangecrab_ecp5_yosys/board_specific_top.sv | 2 +- boards/piswords6/board_specific_top.sv | 2 +- boards/qmtech_c4_starter/board_specific_top.sv | 2 +- boards/qmtech_kintex_7/board_specific_top.sv | 2 +- boards/runber/board_specific_top.sv | 2 +- boards/rzrd/board_specific_top.sv | 2 +- boards/rzrd_pmod_mic3/board_specific_top.sv | 2 +- boards/saylinx/board_specific_top.sv | 2 +- boards/saylinx_pmod_mic3/board_specific_top.sv | 2 +- boards/step_max10/board_specific_top.sv | 2 +- boards/tang_nano_1k/board_specific_top.sv | 2 +- boards/tang_nano_1k_min/board_specific_top.sv | 2 +- boards/tang_nano_20k/board_specific_top.sv | 2 +- boards/tang_nano_9k/board_specific_top.sv | 2 +- boards/tang_nano_9k_gowin_yosys/board_specific_top.sv | 2 +- boards/tang_nano_9k_hdmi/board_specific_top.sv | 2 +- boards/tang_nano_9k_lcd/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_alt/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv | 2 +- boards/tang_primer_20k_lite/board_specific_top.sv | 2 +- boards/tang_primer_25k_dock/board_specific_top.sv | 2 +- boards/tang_primer_25k_dock_dvi/board_specific_top.sv | 2 +- boards/trion_t20/board_specific_top.sv | 2 +- boards/zeowaa/board_specific_top.sv | 2 +- boards/zeowaa_wo_dig_0/board_specific_top.sv | 2 +- boards/zybo_z7/board_specific_top.sv | 2 +- labs/01_and_or_not_xor_de_morgan/tb.sv | 2 +- labs/02_mux/tb.sv | 2 +- labs/03_decoder/tb.sv | 2 +- labs/04_priority_encoder/tb.sv | 2 +- labs/05_7seven_segment_letter/tb.sv | 2 +- labs/06_vga/tb.sv | 2 +- labs/07_binary_counter/tb.sv | 2 +- labs/08_shift_register/tb.sv | 2 +- labs/09_7segment_word/tb.sv | 2 +- labs/10_hex_counter/tb.sv | 2 +- labs/11_note_recognition/tb.sv | 2 +- labs/12_snail_fsm/tb.sv | 2 +- labs/13_music_recognition/tb.sv | 2 +- labs/14_game/tb.sv | 2 +- labs/15_uart/tb.sv | 2 +- labs/15_uart/to_integrate/tb.sv | 2 +- labs/16_round_robin_arbiter/tb.sv | 2 +- labs/17_geiger_muller_radiation_counter/tb.sv | 2 +- labs/18_pow5_single_cycle/tb.sv | 2 +- labs/19_pow5_pipelined/tb.sv | 2 +- labs/20_pow5_pipelined_valid/tb.sv | 2 +- labs/21_pow5_pipelined_valid_solution/tb.sv | 2 +- labs/23_i2s_synthesizer/tb.sv | 2 +- labs/24_i2s_music/tb.sv | 2 +- labs/30_schoolriscv/asic_top.sv | 2 +- labs/50_crash_course/tb.sv | 2 +- .../tb.sv | 2 +- .../tb.sv | 2 +- .../tb.sv | 2 +- .../later/41_round_robin_arbiter_from_2_fifos/tb.sv | 2 +- scripts/asic/asic_top.sv | 2 +- 91 files changed, 91 insertions(+), 91 deletions(-) diff --git a/boards/alinx_ax4010/board_specific_top.sv b/boards/alinx_ax4010/board_specific_top.sv index 472ae6ef..63d7595d 100644 --- a/boards/alinx_ax4010/board_specific_top.sv +++ b/boards/alinx_ax4010/board_specific_top.sv @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index 064bb4c6..9d908afe 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -155,7 +155,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index d1977a1d..2bc86f9f 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -155,7 +155,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/basys3/board_specific_top.sv b/boards/basys3/board_specific_top.sv index 9a8575ed..4c85fdcd 100644 --- a/boards/basys3/board_specific_top.sv +++ b/boards/basys3/board_specific_top.sv @@ -72,7 +72,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index 4f0763c4..e281064d 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -62,7 +62,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index 53d7bde3..1f725466 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index 9950f975..97ee93f9 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -57,7 +57,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/cmod_a7/board_specific_top.sv b/boards/cmod_a7/board_specific_top.sv index 0384c0c8..83ad1568 100644 --- a/boards/cmod_a7/board_specific_top.sv +++ b/boards/cmod_a7/board_specific_top.sv @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index 48ca6181..017104e6 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -67,7 +67,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index 8e7bf401..f31abb54 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index 7bd35637..d0518079 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -122,7 +122,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 2c5d64e7..e4f1dd76 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -115,7 +115,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 3c36d43e..cd180c9b 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -121,7 +121,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 5d34e960..0c11b911 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -121,7 +121,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index 60210d3e..51c57aad 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index de2d75d1..467dc6bd 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 8dd044f8..b651b0f5 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -134,7 +134,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index 0663fd0b..6185bc6d 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -120,7 +120,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index f5332358..bba5f0b0 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -127,7 +127,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index cbd97cb1..b4d99c96 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -120,7 +120,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index a5f67c54..df7b2224 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -71,7 +71,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index 978224d4..bd9130f9 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -75,7 +75,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index f6dfdcf6..6c4e1a57 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -73,7 +73,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/dk_dev_3c120n/board_specific_top.sv b/boards/dk_dev_3c120n/board_specific_top.sv index 434e387b..5fe69766 100644 --- a/boards/dk_dev_3c120n/board_specific_top.sv +++ b/boards/dk_dev_3c120n/board_specific_top.sv @@ -81,7 +81,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/emooc_cc/board_specific_top.sv b/boards/emooc_cc/board_specific_top.sv index f0f3a6fd..a84a588d 100644 --- a/boards/emooc_cc/board_specific_top.sv +++ b/boards/emooc_cc/board_specific_top.sv @@ -76,7 +76,7 @@ module board_specific_top //------------------------------------------------------------------------ // "top" module is a parametrized type, here are numeric parameters - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 59a89c26..80121d92 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -102,7 +102,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index 68813be2..d08cb91f 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -106,7 +106,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/nexys4/board_specific_top.sv b/boards/nexys4/board_specific_top.sv index 73166078..674e980a 100644 --- a/boards/nexys4/board_specific_top.sv +++ b/boards/nexys4/board_specific_top.sv @@ -102,7 +102,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/nexys4_ddr/board_specific_top.sv b/boards/nexys4_ddr/board_specific_top.sv index ffb9946d..5059c74e 100644 --- a/boards/nexys4_ddr/board_specific_top.sv +++ b/boards/nexys4_ddr/board_specific_top.sv @@ -107,7 +107,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/nexys_a7/board_specific_top.sv b/boards/nexys_a7/board_specific_top.sv index ffb9946d..5059c74e 100644 --- a/boards/nexys_a7/board_specific_top.sv +++ b/boards/nexys_a7/board_specific_top.sv @@ -107,7 +107,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/omdazz/board_specific_top.sv b/boards/omdazz/board_specific_top.sv index dfe19f43..67471428 100644 --- a/boards/omdazz/board_specific_top.sv +++ b/boards/omdazz/board_specific_top.sv @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/omdazz_pmod_mic3/board_specific_top.sv b/boards/omdazz_pmod_mic3/board_specific_top.sv index 3b12c476..89bae14f 100644 --- a/boards/omdazz_pmod_mic3/board_specific_top.sv +++ b/boards/omdazz_pmod_mic3/board_specific_top.sv @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index 69c5ecc0..8d266acc 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -105,7 +105,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/piswords6/board_specific_top.sv b/boards/piswords6/board_specific_top.sv index 1ad6cd8e..e0f6a10b 100644 --- a/boards/piswords6/board_specific_top.sv +++ b/boards/piswords6/board_specific_top.sv @@ -60,7 +60,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/qmtech_c4_starter/board_specific_top.sv b/boards/qmtech_c4_starter/board_specific_top.sv index d01ca001..a6745781 100644 --- a/boards/qmtech_c4_starter/board_specific_top.sv +++ b/boards/qmtech_c4_starter/board_specific_top.sv @@ -63,7 +63,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( 1 ), // There are no keys diff --git a/boards/qmtech_kintex_7/board_specific_top.sv b/boards/qmtech_kintex_7/board_specific_top.sv index 1905732a..ba40c2f9 100644 --- a/boards/qmtech_kintex_7/board_specific_top.sv +++ b/boards/qmtech_kintex_7/board_specific_top.sv @@ -78,7 +78,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( 5 ), diff --git a/boards/runber/board_specific_top.sv b/boards/runber/board_specific_top.sv index 594cd50e..0623e74c 100644 --- a/boards/runber/board_specific_top.sv +++ b/boards/runber/board_specific_top.sv @@ -39,7 +39,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), diff --git a/boards/rzrd/board_specific_top.sv b/boards/rzrd/board_specific_top.sv index dfe19f43..67471428 100644 --- a/boards/rzrd/board_specific_top.sv +++ b/boards/rzrd/board_specific_top.sv @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/rzrd_pmod_mic3/board_specific_top.sv b/boards/rzrd_pmod_mic3/board_specific_top.sv index 3b12c476..89bae14f 100644 --- a/boards/rzrd_pmod_mic3/board_specific_top.sv +++ b/boards/rzrd_pmod_mic3/board_specific_top.sv @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/saylinx/board_specific_top.sv b/boards/saylinx/board_specific_top.sv index 472ae6ef..63d7595d 100644 --- a/boards/saylinx/board_specific_top.sv +++ b/boards/saylinx/board_specific_top.sv @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/saylinx_pmod_mic3/board_specific_top.sv b/boards/saylinx_pmod_mic3/board_specific_top.sv index b8d7b4d2..06928018 100644 --- a/boards/saylinx_pmod_mic3/board_specific_top.sv +++ b/boards/saylinx_pmod_mic3/board_specific_top.sv @@ -65,7 +65,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/step_max10/board_specific_top.sv b/boards/step_max10/board_specific_top.sv index feb938b0..970d8bc1 100644 --- a/boards/step_max10/board_specific_top.sv +++ b/boards/step_max10/board_specific_top.sv @@ -41,7 +41,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/tang_nano_1k/board_specific_top.sv b/boards/tang_nano_1k/board_specific_top.sv index 04103aab..ec28075e 100644 --- a/boards/tang_nano_1k/board_specific_top.sv +++ b/boards/tang_nano_1k/board_specific_top.sv @@ -48,7 +48,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), diff --git a/boards/tang_nano_1k_min/board_specific_top.sv b/boards/tang_nano_1k_min/board_specific_top.sv index 4f1f696f..fbf44d02 100644 --- a/boards/tang_nano_1k_min/board_specific_top.sv +++ b/boards/tang_nano_1k_min/board_specific_top.sv @@ -33,7 +33,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index aa5e82bd..3f90998f 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -100,7 +100,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index d7b43729..c29f3e73 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -99,7 +99,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index ab8d2bbc..1dfcbd6e 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -102,7 +102,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index 8bea48a9..848852c2 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -138,7 +138,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( `ifdef USE_HDMI .clk_mhz ( vid_clk_mhz ), diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index d825358c..96dd7a8f 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -145,7 +145,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index fce17aba..adccee67 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -105,7 +105,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index cea05441..4984a819 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -168,7 +168,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( `ifdef ENABLE_HDMI .clk_mhz ( vid_clk_mhz ), diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index 55bbb3f7..65d4661b 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -108,7 +108,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 94f29072..59b281a1 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -107,7 +107,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index ddb35492..b87b847e 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -107,7 +107,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), // The last key is used for a reset diff --git a/boards/tang_primer_25k_dock/board_specific_top.sv b/boards/tang_primer_25k_dock/board_specific_top.sv index cdc4e7d6..58a69d9c 100644 --- a/boards/tang_primer_25k_dock/board_specific_top.sv +++ b/boards/tang_primer_25k_dock/board_specific_top.sv @@ -82,7 +82,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), diff --git a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv index 9645a1de..abf5470a 100644 --- a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv +++ b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), diff --git a/boards/trion_t20/board_specific_top.sv b/boards/trion_t20/board_specific_top.sv index ac38a1a3..865a94be 100755 --- a/boards/trion_t20/board_specific_top.sv +++ b/boards/trion_t20/board_specific_top.sv @@ -60,7 +60,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/zeowaa/board_specific_top.sv b/boards/zeowaa/board_specific_top.sv index c3fb516e..b56aeae3 100644 --- a/boards/zeowaa/board_specific_top.sv +++ b/boards/zeowaa/board_specific_top.sv @@ -63,7 +63,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_top_key ), diff --git a/boards/zeowaa_wo_dig_0/board_specific_top.sv b/boards/zeowaa_wo_dig_0/board_specific_top.sv index 44b80919..2ace1f46 100644 --- a/boards/zeowaa_wo_dig_0/board_specific_top.sv +++ b/boards/zeowaa_wo_dig_0/board_specific_top.sv @@ -69,7 +69,7 @@ module board_specific_top //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/boards/zybo_z7/board_specific_top.sv b/boards/zybo_z7/board_specific_top.sv index aa59093a..f6f72802 100644 --- a/boards/zybo_z7/board_specific_top.sv +++ b/boards/zybo_z7/board_specific_top.sv @@ -100,7 +100,7 @@ module board_specific_top //------------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz (clk_mhz), .w_key (w_key_top), diff --git a/labs/01_and_or_not_xor_de_morgan/tb.sv b/labs/01_and_or_not_xor_de_morgan/tb.sv index f8c334f3..c4d4bdfa 100644 --- a/labs/01_and_or_not_xor_de_morgan/tb.sv +++ b/labs/01_and_or_not_xor_de_morgan/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/02_mux/tb.sv b/labs/02_mux/tb.sv index 77ea60ff..4a860004 100644 --- a/labs/02_mux/tb.sv +++ b/labs/02_mux/tb.sv @@ -19,7 +19,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/03_decoder/tb.sv b/labs/03_decoder/tb.sv index f8c334f3..c4d4bdfa 100644 --- a/labs/03_decoder/tb.sv +++ b/labs/03_decoder/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/04_priority_encoder/tb.sv b/labs/04_priority_encoder/tb.sv index f8c334f3..c4d4bdfa 100644 --- a/labs/04_priority_encoder/tb.sv +++ b/labs/04_priority_encoder/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/05_7seven_segment_letter/tb.sv b/labs/05_7seven_segment_letter/tb.sv index f8c334f3..c4d4bdfa 100644 --- a/labs/05_7seven_segment_letter/tb.sv +++ b/labs/05_7seven_segment_letter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/06_vga/tb.sv b/labs/06_vga/tb.sv index f8c334f3..c4d4bdfa 100644 --- a/labs/06_vga/tb.sv +++ b/labs/06_vga/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/07_binary_counter/tb.sv b/labs/07_binary_counter/tb.sv index 878384bd..36112be0 100644 --- a/labs/07_binary_counter/tb.sv +++ b/labs/07_binary_counter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/08_shift_register/tb.sv b/labs/08_shift_register/tb.sv index 715355d9..3639ca1f 100644 --- a/labs/08_shift_register/tb.sv +++ b/labs/08_shift_register/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/09_7segment_word/tb.sv b/labs/09_7segment_word/tb.sv index 715355d9..3639ca1f 100644 --- a/labs/09_7segment_word/tb.sv +++ b/labs/09_7segment_word/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/10_hex_counter/tb.sv b/labs/10_hex_counter/tb.sv index 878384bd..36112be0 100644 --- a/labs/10_hex_counter/tb.sv +++ b/labs/10_hex_counter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/11_note_recognition/tb.sv b/labs/11_note_recognition/tb.sv index d4c3b78a..22053552 100644 --- a/labs/11_note_recognition/tb.sv +++ b/labs/11_note_recognition/tb.sv @@ -80,7 +80,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/12_snail_fsm/tb.sv b/labs/12_snail_fsm/tb.sv index 878384bd..36112be0 100644 --- a/labs/12_snail_fsm/tb.sv +++ b/labs/12_snail_fsm/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/13_music_recognition/tb.sv b/labs/13_music_recognition/tb.sv index 5284c427..b2f6536d 100644 --- a/labs/13_music_recognition/tb.sv +++ b/labs/13_music_recognition/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/14_game/tb.sv b/labs/14_game/tb.sv index 9112c087..92d302de 100644 --- a/labs/14_game/tb.sv +++ b/labs/14_game/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/15_uart/tb.sv b/labs/15_uart/tb.sv index 878384bd..36112be0 100644 --- a/labs/15_uart/tb.sv +++ b/labs/15_uart/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/15_uart/to_integrate/tb.sv b/labs/15_uart/to_integrate/tb.sv index 9a0d07d1..ba2db027 100644 --- a/labs/15_uart/to_integrate/tb.sv +++ b/labs/15_uart/to_integrate/tb.sv @@ -5,7 +5,7 @@ module tb; logic [3:0] key_sw; logic rx; - top + lab_top # ( .clk_frequency ( 50 ), .baud_rate ( 1 ), diff --git a/labs/16_round_robin_arbiter/tb.sv b/labs/16_round_robin_arbiter/tb.sv index 5284c427..b2f6536d 100644 --- a/labs/16_round_robin_arbiter/tb.sv +++ b/labs/16_round_robin_arbiter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/17_geiger_muller_radiation_counter/tb.sv b/labs/17_geiger_muller_radiation_counter/tb.sv index 878384bd..36112be0 100644 --- a/labs/17_geiger_muller_radiation_counter/tb.sv +++ b/labs/17_geiger_muller_radiation_counter/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/18_pow5_single_cycle/tb.sv b/labs/18_pow5_single_cycle/tb.sv index 741b640f..92d827a9 100644 --- a/labs/18_pow5_single_cycle/tb.sv +++ b/labs/18_pow5_single_cycle/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/19_pow5_pipelined/tb.sv b/labs/19_pow5_pipelined/tb.sv index 741b640f..92d827a9 100644 --- a/labs/19_pow5_pipelined/tb.sv +++ b/labs/19_pow5_pipelined/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/20_pow5_pipelined_valid/tb.sv b/labs/20_pow5_pipelined_valid/tb.sv index af86c436..ad2d42af 100644 --- a/labs/20_pow5_pipelined_valid/tb.sv +++ b/labs/20_pow5_pipelined_valid/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/21_pow5_pipelined_valid_solution/tb.sv b/labs/21_pow5_pipelined_valid_solution/tb.sv index af86c436..ad2d42af 100644 --- a/labs/21_pow5_pipelined_valid_solution/tb.sv +++ b/labs/21_pow5_pipelined_valid_solution/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/23_i2s_synthesizer/tb.sv b/labs/23_i2s_synthesizer/tb.sv index b4b136fa..318c75fc 100644 --- a/labs/23_i2s_synthesizer/tb.sv +++ b/labs/23_i2s_synthesizer/tb.sv @@ -18,7 +18,7 @@ module testbench; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/24_i2s_music/tb.sv b/labs/24_i2s_music/tb.sv index 6749eb5f..6a7b7669 100644 --- a/labs/24_i2s_music/tb.sv +++ b/labs/24_i2s_music/tb.sv @@ -18,7 +18,7 @@ module testbench; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/30_schoolriscv/asic_top.sv b/labs/30_schoolriscv/asic_top.sv index a3b8fdec..92f39bb0 100644 --- a/labs/30_schoolriscv/asic_top.sv +++ b/labs/30_schoolriscv/asic_top.sv @@ -26,7 +26,7 @@ module asic_top output logic [w_digit - 1:0] digit ); - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/50_crash_course/tb.sv b/labs/50_crash_course/tb.sv index f8c334f3..c4d4bdfa 100644 --- a/labs/50_crash_course/tb.sv +++ b/labs/50_crash_course/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv index 5284c427..b2f6536d 100644 --- a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv index 5284c427..b2f6536d 100644 --- a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv index 5284c427..b2f6536d 100644 --- a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv index 5284c427..b2f6536d 100644 --- a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv +++ b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv @@ -18,7 +18,7 @@ module tb; //------------------------------------------------------------------------ - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), diff --git a/scripts/asic/asic_top.sv b/scripts/asic/asic_top.sv index a3b8fdec..92f39bb0 100644 --- a/scripts/asic/asic_top.sv +++ b/scripts/asic/asic_top.sv @@ -26,7 +26,7 @@ module asic_top output logic [w_digit - 1:0] digit ); - top + lab_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), From 544cf8f8fa95b12690487a6b2bb8fe291385a5ed Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 10:35:09 -0700 Subject: [PATCH 05/65] Renamed top module instances to lab_top 2 --- boards/alinx_ax4010/board_specific_top.sv | 2 +- boards/arty_a7/board_specific_top.sv | 2 +- boards/arty_a7_pmod_mic3/board_specific_top.sv | 2 +- boards/basys3/board_specific_top.sv | 2 +- boards/c5gx_audio/board_specific_top.sv | 2 +- boards/c5gx_vga666/board_specific_top.sv | 2 +- boards/c5gx_vga_pmod/board_specific_top.sv | 2 +- boards/cmod_a7/board_specific_top.sv | 2 +- boards/de0/board_specific_top.sv | 2 +- boards/de0_cv/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga666/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 2 +- boards/de0_nano_vga666/board_specific_top.sv | 2 +- boards/de0_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de1/board_specific_top.sv | 2 +- boards/de10_lite/board_specific_top.sv | 2 +- boards/de10_lite_tm1638_arduino/board_specific_top.sv | 2 +- boards/de10_nano_vga666/board_specific_top.sv | 2 +- boards/de10_nano_vga_mister/board_specific_top.sv | 2 +- boards/de10_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de1_soc/board_specific_top.sv | 2 +- boards/de2/board_specific_top.sv | 2 +- boards/de2_115/board_specific_top.sv | 2 +- boards/dk_dev_3c120n/board_specific_top.sv | 2 +- boards/emooc_cc/board_specific_top.sv | 2 +- boards/ice40hx8k_evb_yosys/board_specific_top.sv | 2 +- boards/karnix_ecp5_yosys/board_specific_top.sv | 2 +- boards/nexys4/board_specific_top.sv | 2 +- boards/nexys4_ddr/board_specific_top.sv | 2 +- boards/nexys_a7/board_specific_top.sv | 2 +- boards/omdazz/board_specific_top.sv | 2 +- boards/omdazz_pmod_mic3/board_specific_top.sv | 2 +- boards/orangecrab_ecp5_yosys/board_specific_top.sv | 2 +- boards/piswords6/board_specific_top.sv | 2 +- boards/qmtech_c4_starter/board_specific_top.sv | 2 +- boards/qmtech_kintex_7/board_specific_top.sv | 2 +- boards/runber/board_specific_top.sv | 2 +- boards/rzrd/board_specific_top.sv | 2 +- boards/rzrd_pmod_mic3/board_specific_top.sv | 2 +- boards/saylinx/board_specific_top.sv | 2 +- boards/saylinx_pmod_mic3/board_specific_top.sv | 2 +- boards/step_max10/board_specific_top.sv | 2 +- boards/tang_nano_1k/board_specific_top.sv | 2 +- boards/tang_nano_1k_min/board_specific_top.sv | 2 +- boards/tang_nano_20k/board_specific_top.sv | 2 +- boards/tang_nano_9k/board_specific_top.sv | 2 +- boards/tang_nano_9k_gowin_yosys/board_specific_top.sv | 2 +- boards/tang_nano_9k_hdmi/board_specific_top.sv | 2 +- boards/tang_nano_9k_lcd/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_alt/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv | 2 +- boards/tang_primer_20k_lite/board_specific_top.sv | 2 +- boards/tang_primer_25k_dock/board_specific_top.sv | 2 +- boards/tang_primer_25k_dock_dvi/board_specific_top.sv | 2 +- boards/trion_t20/board_specific_top.sv | 2 +- boards/zeowaa/board_specific_top.sv | 2 +- boards/zeowaa_wo_dig_0/board_specific_top.sv | 2 +- boards/zybo_z7/board_specific_top.sv | 2 +- labs/01_and_or_not_xor_de_morgan/tb.sv | 2 +- labs/02_mux/tb.sv | 2 +- labs/03_decoder/tb.sv | 2 +- labs/04_priority_encoder/tb.sv | 2 +- labs/05_7seven_segment_letter/tb.sv | 2 +- labs/06_vga/tb.sv | 2 +- labs/07_binary_counter/tb.sv | 2 +- labs/08_shift_register/tb.sv | 2 +- labs/09_7segment_word/tb.sv | 2 +- labs/10_hex_counter/tb.sv | 2 +- labs/11_note_recognition/tb.sv | 2 +- labs/12_snail_fsm/tb.sv | 2 +- labs/13_music_recognition/tb.sv | 2 +- labs/14_game/tb.sv | 2 +- labs/15_uart/tb.sv | 2 +- labs/15_uart/to_integrate/tb.sv | 2 +- labs/16_round_robin_arbiter/tb.sv | 2 +- labs/17_geiger_muller_radiation_counter/tb.sv | 2 +- labs/18_pow5_single_cycle/tb.sv | 2 +- labs/19_pow5_pipelined/tb.sv | 2 +- labs/20_pow5_pipelined_valid/tb.sv | 2 +- labs/21_pow5_pipelined_valid_solution/tb.sv | 2 +- labs/23_i2s_synthesizer/tb.sv | 2 +- labs/24_i2s_music/tb.sv | 2 +- labs/30_schoolriscv/asic_top.sv | 2 +- labs/50_crash_course/tb.sv | 2 +- .../tb.sv | 2 +- .../tb.sv | 2 +- .../tb.sv | 2 +- .../later/41_round_robin_arbiter_from_2_fifos/tb.sv | 2 +- scripts/asic/asic_top.sv | 2 +- 91 files changed, 91 insertions(+), 91 deletions(-) diff --git a/boards/alinx_ax4010/board_specific_top.sv b/boards/alinx_ax4010/board_specific_top.sv index 63d7595d..c2a48718 100644 --- a/boards/alinx_ax4010/board_specific_top.sv +++ b/boards/alinx_ax4010/board_specific_top.sv @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index 9d908afe..6c8857e4 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -164,7 +164,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index 2bc86f9f..e408771e 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -164,7 +164,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/basys3/board_specific_top.sv b/boards/basys3/board_specific_top.sv index 4c85fdcd..78f037b9 100644 --- a/boards/basys3/board_specific_top.sv +++ b/boards/basys3/board_specific_top.sv @@ -81,7 +81,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index e281064d..4d2b18f3 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -71,7 +71,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index 1f725466..6adb997b 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -73,7 +73,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index 97ee93f9..bc517436 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -66,7 +66,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .rst ( rst ), diff --git a/boards/cmod_a7/board_specific_top.sv b/boards/cmod_a7/board_specific_top.sv index 83ad1568..60d5a273 100644 --- a/boards/cmod_a7/board_specific_top.sv +++ b/boards/cmod_a7/board_specific_top.sv @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index 017104e6..d27833dc 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -76,7 +76,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO_0[7:2] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index f31abb54..d5b6b247 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -73,7 +73,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index d0518079..e7a0f628 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -131,7 +131,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index e4f1dd76..27033660 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -124,7 +124,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .rst ( rst ), diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index cd180c9b..285076bf 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -130,7 +130,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 0c11b911..13f455d7 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -130,7 +130,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index 51c57aad..6bed8027 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index 467dc6bd..1400f708 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -73,7 +73,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index b651b0f5..c1c70f4f 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -146,7 +146,7 @@ module board_specific_top // top gpio includes both ARDUINO and GPIO pins // GPIO [31], [33], [35] reserved for tm1638, GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index 6185bc6d..0fc2d6e5 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -129,7 +129,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index bba5f0b0..192819ca 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -136,7 +136,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index b4d99c96..36f06e74 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -129,7 +129,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index df7b2224..45da8d69 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -80,7 +80,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO_0[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index bd9130f9..dc8b8492 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -84,7 +84,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index 6c4e1a57..f67426a4 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -82,7 +82,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/dk_dev_3c120n/board_specific_top.sv b/boards/dk_dev_3c120n/board_specific_top.sv index 5fe69766..410d24b8 100644 --- a/boards/dk_dev_3c120n/board_specific_top.sv +++ b/boards/dk_dev_3c120n/board_specific_top.sv @@ -90,7 +90,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/emooc_cc/board_specific_top.sv b/boards/emooc_cc/board_specific_top.sv index a84a588d..307aaed1 100644 --- a/boards/emooc_cc/board_specific_top.sv +++ b/boards/emooc_cc/board_specific_top.sv @@ -86,7 +86,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) // i_top is an instance, passing signal mappings - ?.. - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 80121d92..2e4caaae 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -111,7 +111,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index d08cb91f..f8526e6c 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -115,7 +115,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/nexys4/board_specific_top.sv b/boards/nexys4/board_specific_top.sv index 674e980a..e7e76b00 100644 --- a/boards/nexys4/board_specific_top.sv +++ b/boards/nexys4/board_specific_top.sv @@ -111,7 +111,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/nexys4_ddr/board_specific_top.sv b/boards/nexys4_ddr/board_specific_top.sv index 5059c74e..fc031d8e 100644 --- a/boards/nexys4_ddr/board_specific_top.sv +++ b/boards/nexys4_ddr/board_specific_top.sv @@ -116,7 +116,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/nexys_a7/board_specific_top.sv b/boards/nexys_a7/board_specific_top.sv index 5059c74e..fc031d8e 100644 --- a/boards/nexys_a7/board_specific_top.sv +++ b/boards/nexys_a7/board_specific_top.sv @@ -116,7 +116,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/omdazz/board_specific_top.sv b/boards/omdazz/board_specific_top.sv index 67471428..4d4abd0b 100644 --- a/boards/omdazz/board_specific_top.sv +++ b/boards/omdazz/board_specific_top.sv @@ -96,7 +96,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/omdazz_pmod_mic3/board_specific_top.sv b/boards/omdazz_pmod_mic3/board_specific_top.sv index 89bae14f..cfc7aafd 100644 --- a/boards/omdazz_pmod_mic3/board_specific_top.sv +++ b/boards/omdazz_pmod_mic3/board_specific_top.sv @@ -96,7 +96,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index 8d266acc..bfd54e57 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -114,7 +114,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/piswords6/board_specific_top.sv b/boards/piswords6/board_specific_top.sv index e0f6a10b..1acd2e0f 100644 --- a/boards/piswords6/board_specific_top.sv +++ b/boards/piswords6/board_specific_top.sv @@ -69,7 +69,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/qmtech_c4_starter/board_specific_top.sv b/boards/qmtech_c4_starter/board_specific_top.sv index a6745781..75eca0a5 100644 --- a/boards/qmtech_c4_starter/board_specific_top.sv +++ b/boards/qmtech_c4_starter/board_specific_top.sv @@ -72,7 +72,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/qmtech_kintex_7/board_specific_top.sv b/boards/qmtech_kintex_7/board_specific_top.sv index ba40c2f9..1fcdad42 100644 --- a/boards/qmtech_kintex_7/board_specific_top.sv +++ b/boards/qmtech_kintex_7/board_specific_top.sv @@ -87,7 +87,7 @@ module board_specific_top .w_digit ( 4 ), .w_gpio ( 0 ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/runber/board_specific_top.sv b/boards/runber/board_specific_top.sv index 0623e74c..806499f6 100644 --- a/boards/runber/board_specific_top.sv +++ b/boards/runber/board_specific_top.sv @@ -55,7 +55,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/rzrd/board_specific_top.sv b/boards/rzrd/board_specific_top.sv index 67471428..4d4abd0b 100644 --- a/boards/rzrd/board_specific_top.sv +++ b/boards/rzrd/board_specific_top.sv @@ -96,7 +96,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/rzrd_pmod_mic3/board_specific_top.sv b/boards/rzrd_pmod_mic3/board_specific_top.sv index 89bae14f..cfc7aafd 100644 --- a/boards/rzrd_pmod_mic3/board_specific_top.sv +++ b/boards/rzrd_pmod_mic3/board_specific_top.sv @@ -96,7 +96,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/saylinx/board_specific_top.sv b/boards/saylinx/board_specific_top.sv index 63d7595d..c2a48718 100644 --- a/boards/saylinx/board_specific_top.sv +++ b/boards/saylinx/board_specific_top.sv @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/saylinx_pmod_mic3/board_specific_top.sv b/boards/saylinx_pmod_mic3/board_specific_top.sv index 06928018..fc86a20f 100644 --- a/boards/saylinx_pmod_mic3/board_specific_top.sv +++ b/boards/saylinx_pmod_mic3/board_specific_top.sv @@ -74,7 +74,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/step_max10/board_specific_top.sv b/boards/step_max10/board_specific_top.sv index 970d8bc1..f3df6cc0 100644 --- a/boards/step_max10/board_specific_top.sv +++ b/boards/step_max10/board_specific_top.sv @@ -50,7 +50,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_nano_1k/board_specific_top.sv b/boards/tang_nano_1k/board_specific_top.sv index ec28075e..41baf04f 100644 --- a/boards/tang_nano_1k/board_specific_top.sv +++ b/boards/tang_nano_1k/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_nano_1k_min/board_specific_top.sv b/boards/tang_nano_1k_min/board_specific_top.sv index fbf44d02..51b3619d 100644 --- a/boards/tang_nano_1k_min/board_specific_top.sv +++ b/boards/tang_nano_1k_min/board_specific_top.sv @@ -49,7 +49,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index 3f90998f..b71e744a 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -109,7 +109,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index c29f3e73..13040c0a 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -108,7 +108,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index 1dfcbd6e..2516f9d5 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -111,7 +111,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index 848852c2..aefded76 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -157,7 +157,7 @@ module board_specific_top .w_blue ( 8 ) `endif ) - i_top + i_lab_top ( `ifdef USE_HDMI .clk ( clk_hd ), diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index 96dd7a8f..55418fce 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -160,7 +160,7 @@ module board_specific_top .w_green ( w_green ), .w_blue ( w_blue ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index adccee67..a703ca16 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -114,7 +114,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 4984a819..021d47d4 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -184,7 +184,7 @@ module board_specific_top .w_green ( w_top_green ), .w_blue ( w_top_blue ) ) - i_top + i_lab_top ( `ifdef ENABLE_HDMI .clk ( clk_hd ), diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index 65d4661b..4f9a66ed 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -117,7 +117,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 59b281a1..08116ee2 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -116,7 +116,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index b87b847e..84a80845 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -116,7 +116,7 @@ module board_specific_top .w_digit ( w_top_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_primer_25k_dock/board_specific_top.sv b/boards/tang_primer_25k_dock/board_specific_top.sv index 58a69d9c..2bc6484e 100644 --- a/boards/tang_primer_25k_dock/board_specific_top.sv +++ b/boards/tang_primer_25k_dock/board_specific_top.sv @@ -98,7 +98,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv index abf5470a..bec954d4 100644 --- a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv +++ b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv @@ -103,7 +103,7 @@ module board_specific_top .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/trion_t20/board_specific_top.sv b/boards/trion_t20/board_specific_top.sv index 865a94be..d1a1b036 100755 --- a/boards/trion_t20/board_specific_top.sv +++ b/boards/trion_t20/board_specific_top.sv @@ -69,7 +69,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/zeowaa/board_specific_top.sv b/boards/zeowaa/board_specific_top.sv index b56aeae3..0aa829cb 100644 --- a/boards/zeowaa/board_specific_top.sv +++ b/boards/zeowaa/board_specific_top.sv @@ -72,7 +72,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/zeowaa_wo_dig_0/board_specific_top.sv b/boards/zeowaa_wo_dig_0/board_specific_top.sv index 2ace1f46..b7fae76f 100644 --- a/boards/zeowaa_wo_dig_0/board_specific_top.sv +++ b/boards/zeowaa_wo_dig_0/board_specific_top.sv @@ -78,7 +78,7 @@ module board_specific_top .w_digit ( w_top_digit ), // Note top_digit, not digit .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/boards/zybo_z7/board_specific_top.sv b/boards/zybo_z7/board_specific_top.sv index f6f72802..80cc5752 100644 --- a/boards/zybo_z7/board_specific_top.sv +++ b/boards/zybo_z7/board_specific_top.sv @@ -109,7 +109,7 @@ module board_specific_top .w_digit (w_digit_top), .w_gpio (w_gpio) ) - i_top + i_lab_top ( .clk (clk), .slow_clk (slow_clk), diff --git a/labs/01_and_or_not_xor_de_morgan/tb.sv b/labs/01_and_or_not_xor_de_morgan/tb.sv index c4d4bdfa..4c88f3b5 100644 --- a/labs/01_and_or_not_xor_de_morgan/tb.sv +++ b/labs/01_and_or_not_xor_de_morgan/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/02_mux/tb.sv b/labs/02_mux/tb.sv index 4a860004..0d6b9a62 100644 --- a/labs/02_mux/tb.sv +++ b/labs/02_mux/tb.sv @@ -28,7 +28,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/03_decoder/tb.sv b/labs/03_decoder/tb.sv index c4d4bdfa..4c88f3b5 100644 --- a/labs/03_decoder/tb.sv +++ b/labs/03_decoder/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/04_priority_encoder/tb.sv b/labs/04_priority_encoder/tb.sv index c4d4bdfa..4c88f3b5 100644 --- a/labs/04_priority_encoder/tb.sv +++ b/labs/04_priority_encoder/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/05_7seven_segment_letter/tb.sv b/labs/05_7seven_segment_letter/tb.sv index c4d4bdfa..4c88f3b5 100644 --- a/labs/05_7seven_segment_letter/tb.sv +++ b/labs/05_7seven_segment_letter/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/06_vga/tb.sv b/labs/06_vga/tb.sv index c4d4bdfa..4c88f3b5 100644 --- a/labs/06_vga/tb.sv +++ b/labs/06_vga/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/07_binary_counter/tb.sv b/labs/07_binary_counter/tb.sv index 36112be0..643cf7b7 100644 --- a/labs/07_binary_counter/tb.sv +++ b/labs/07_binary_counter/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/08_shift_register/tb.sv b/labs/08_shift_register/tb.sv index 3639ca1f..c6e02958 100644 --- a/labs/08_shift_register/tb.sv +++ b/labs/08_shift_register/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/09_7segment_word/tb.sv b/labs/09_7segment_word/tb.sv index 3639ca1f..c6e02958 100644 --- a/labs/09_7segment_word/tb.sv +++ b/labs/09_7segment_word/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/10_hex_counter/tb.sv b/labs/10_hex_counter/tb.sv index 36112be0..643cf7b7 100644 --- a/labs/10_hex_counter/tb.sv +++ b/labs/10_hex_counter/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/11_note_recognition/tb.sv b/labs/11_note_recognition/tb.sv index 22053552..635253ca 100644 --- a/labs/11_note_recognition/tb.sv +++ b/labs/11_note_recognition/tb.sv @@ -89,7 +89,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/12_snail_fsm/tb.sv b/labs/12_snail_fsm/tb.sv index 36112be0..643cf7b7 100644 --- a/labs/12_snail_fsm/tb.sv +++ b/labs/12_snail_fsm/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/13_music_recognition/tb.sv b/labs/13_music_recognition/tb.sv index b2f6536d..6f6e5ddc 100644 --- a/labs/13_music_recognition/tb.sv +++ b/labs/13_music_recognition/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/14_game/tb.sv b/labs/14_game/tb.sv index 92d302de..3e875303 100644 --- a/labs/14_game/tb.sv +++ b/labs/14_game/tb.sv @@ -29,7 +29,7 @@ module tb; .strobe_to_update_xy_counter_width (1) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/15_uart/tb.sv b/labs/15_uart/tb.sv index 36112be0..643cf7b7 100644 --- a/labs/15_uart/tb.sv +++ b/labs/15_uart/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/15_uart/to_integrate/tb.sv b/labs/15_uart/to_integrate/tb.sv index ba2db027..0a53fb2e 100644 --- a/labs/15_uart/to_integrate/tb.sv +++ b/labs/15_uart/to_integrate/tb.sv @@ -11,7 +11,7 @@ module tb; .baud_rate ( 1 ), .timeout_in_seconds ( 1000 ) ) - i_top + i_lab_top ( .clk ( clk ), .reset_n ( reset_n ), diff --git a/labs/16_round_robin_arbiter/tb.sv b/labs/16_round_robin_arbiter/tb.sv index b2f6536d..6f6e5ddc 100644 --- a/labs/16_round_robin_arbiter/tb.sv +++ b/labs/16_round_robin_arbiter/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/17_geiger_muller_radiation_counter/tb.sv b/labs/17_geiger_muller_radiation_counter/tb.sv index 36112be0..643cf7b7 100644 --- a/labs/17_geiger_muller_radiation_counter/tb.sv +++ b/labs/17_geiger_muller_radiation_counter/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/18_pow5_single_cycle/tb.sv b/labs/18_pow5_single_cycle/tb.sv index 92d827a9..98c15eb3 100644 --- a/labs/18_pow5_single_cycle/tb.sv +++ b/labs/18_pow5_single_cycle/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/19_pow5_pipelined/tb.sv b/labs/19_pow5_pipelined/tb.sv index 92d827a9..98c15eb3 100644 --- a/labs/19_pow5_pipelined/tb.sv +++ b/labs/19_pow5_pipelined/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/20_pow5_pipelined_valid/tb.sv b/labs/20_pow5_pipelined_valid/tb.sv index ad2d42af..b0f1cb1a 100644 --- a/labs/20_pow5_pipelined_valid/tb.sv +++ b/labs/20_pow5_pipelined_valid/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/21_pow5_pipelined_valid_solution/tb.sv b/labs/21_pow5_pipelined_valid_solution/tb.sv index ad2d42af..b0f1cb1a 100644 --- a/labs/21_pow5_pipelined_valid_solution/tb.sv +++ b/labs/21_pow5_pipelined_valid_solution/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/23_i2s_synthesizer/tb.sv b/labs/23_i2s_synthesizer/tb.sv index 318c75fc..9e0da220 100644 --- a/labs/23_i2s_synthesizer/tb.sv +++ b/labs/23_i2s_synthesizer/tb.sv @@ -27,7 +27,7 @@ module testbench; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/24_i2s_music/tb.sv b/labs/24_i2s_music/tb.sv index 6a7b7669..68085cc8 100644 --- a/labs/24_i2s_music/tb.sv +++ b/labs/24_i2s_music/tb.sv @@ -27,7 +27,7 @@ module testbench; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/30_schoolriscv/asic_top.sv b/labs/30_schoolriscv/asic_top.sv index 92f39bb0..2e8dbf3a 100644 --- a/labs/30_schoolriscv/asic_top.sv +++ b/labs/30_schoolriscv/asic_top.sv @@ -35,7 +35,7 @@ module asic_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), diff --git a/labs/50_crash_course/tb.sv b/labs/50_crash_course/tb.sv index c4d4bdfa..4c88f3b5 100644 --- a/labs/50_crash_course/tb.sv +++ b/labs/50_crash_course/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv index b2f6536d..6f6e5ddc 100644 --- a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv index b2f6536d..6f6e5ddc 100644 --- a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv index b2f6536d..6f6e5ddc 100644 --- a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv +++ b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv index b2f6536d..6f6e5ddc 100644 --- a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv +++ b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv @@ -27,7 +27,7 @@ module tb; .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( clk ), diff --git a/scripts/asic/asic_top.sv b/scripts/asic/asic_top.sv index 92f39bb0..2e8dbf3a 100644 --- a/scripts/asic/asic_top.sv +++ b/scripts/asic/asic_top.sv @@ -35,7 +35,7 @@ module asic_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - i_top + i_lab_top ( .clk ( clk ), .slow_clk ( slow_clk ), From 3dab3b22e041b37e1fd005ead638020cb8ad8f5e Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 10:46:45 -0700 Subject: [PATCH 06/65] Renamed top module instances to lab_top 3 --- boards/emooc_cc/board_specific_top.sv | 2 +- labs/02_mux/tb.sv | 8 ++++---- labs/08_shift_register/tb.sv | 4 ++-- labs/09_7segment_word/tb.sv | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/boards/emooc_cc/board_specific_top.sv b/boards/emooc_cc/board_specific_top.sv index 307aaed1..1d597bf9 100644 --- a/boards/emooc_cc/board_specific_top.sv +++ b/boards/emooc_cc/board_specific_top.sv @@ -85,7 +85,7 @@ module board_specific_top .w_digit ( w_digit ), .w_gpio ( w_gpio ) ) - // i_top is an instance, passing signal mappings - ?.. + // i_lab_top is an instance, passing signal mappings - ?.. i_lab_top ( .clk ( clk ), diff --git a/labs/02_mux/tb.sv b/labs/02_mux/tb.sv index 0d6b9a62..4417e6c6 100644 --- a/labs/02_mux/tb.sv +++ b/labs/02_mux/tb.sv @@ -57,8 +57,8 @@ module tb; //-------------------------------------------------------------------- // Checking multiple bits - if ($bits (i_top.all_muxes) < $bits (led)) - n_muxes_to_check = $bits (i_top.all_muxes); + if ($bits (i_lab_top.all_muxes) < $bits (led)) + n_muxes_to_check = $bits (i_lab_top.all_muxes); else n_muxes_to_check = $bits (led); @@ -74,9 +74,9 @@ module tb; //-------------------------------------------------------------------- // White-box testing - checking XMR (external module reference) - for (int i = 0; i < $bits (i_top.all_muxes); i ++) + for (int i = 0; i < $bits (i_lab_top.all_muxes); i ++) begin - result = i_top.all_muxes [i]; + result = i_lab_top.all_muxes [i]; if (result !== expected) $display ("Mismatch in mux %0d: %b ? %b : %b. expected: %b actual: %b", diff --git a/labs/08_shift_register/tb.sv b/labs/08_shift_register/tb.sv index c6e02958..a8b16f8d 100644 --- a/labs/08_shift_register/tb.sv +++ b/labs/08_shift_register/tb.sv @@ -75,9 +75,9 @@ module tb; // Enable override if (i == 20) - force i_top.enable = 1'b1; + force i_lab_top.enable = 1'b1; else if (i == 40) - release i_top.enable; + release i_lab_top.enable; @ (posedge clk); diff --git a/labs/09_7segment_word/tb.sv b/labs/09_7segment_word/tb.sv index c6e02958..a8b16f8d 100644 --- a/labs/09_7segment_word/tb.sv +++ b/labs/09_7segment_word/tb.sv @@ -75,9 +75,9 @@ module tb; // Enable override if (i == 20) - force i_top.enable = 1'b1; + force i_lab_top.enable = 1'b1; else if (i == 40) - release i_top.enable; + release i_lab_top.enable; @ (posedge clk); From 7c8d54dd18c9e4a991bcc10d6a8ab7b6f8406269 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 10:50:41 -0700 Subject: [PATCH 07/65] Renamed top module instances to lab_top 4 --- labs/02_mux/gtkwave.tcl | 2 +- labs/07_binary_counter/gtkwave.tcl | 8 ++--- labs/08_shift_register/gtkwave.tcl | 8 ++--- labs/09_7segment_word/gtkwave.tcl | 8 ++--- labs/10_hex_counter/gtkwave.tcl | 8 ++--- .../15_uart/to_integrate/xx_gtkwave_extra.tcl | 2 +- labs/16_round_robin_arbiter/gtkwave.tcl | 8 ++--- .../gtkwave.tcl | 8 ++--- .../gtkwave.tcl | 34 +++++++++---------- .../gtkwave.tcl | 34 +++++++++---------- .../gtkwave.tcl | 34 +++++++++---------- .../gtkwave.tcl | 34 +++++++++---------- 12 files changed, 94 insertions(+), 94 deletions(-) diff --git a/labs/02_mux/gtkwave.tcl b/labs/02_mux/gtkwave.tcl index 7a319bb3..de52ed19 100644 --- a/labs/02_mux/gtkwave.tcl +++ b/labs/02_mux/gtkwave.tcl @@ -8,7 +8,7 @@ lappend all_signals tb.b lappend all_signals tb.key lappend all_signals tb.led lappend all_signals {tb.led[0]} -lappend all_signals tb.i_top.all_muxes +lappend all_signals tb.i_lab_top.all_muxes set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/07_binary_counter/gtkwave.tcl b/labs/07_binary_counter/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/07_binary_counter/gtkwave.tcl +++ b/labs/07_binary_counter/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/08_shift_register/gtkwave.tcl b/labs/08_shift_register/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/08_shift_register/gtkwave.tcl +++ b/labs/08_shift_register/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/09_7segment_word/gtkwave.tcl b/labs/09_7segment_word/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/09_7segment_word/gtkwave.tcl +++ b/labs/09_7segment_word/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/10_hex_counter/gtkwave.tcl b/labs/10_hex_counter/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/10_hex_counter/gtkwave.tcl +++ b/labs/10_hex_counter/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/15_uart/to_integrate/xx_gtkwave_extra.tcl b/labs/15_uart/to_integrate/xx_gtkwave_extra.tcl index 9dbe0b34..af7ba9ae 100644 --- a/labs/15_uart/to_integrate/xx_gtkwave_extra.tcl +++ b/labs/15_uart/to_integrate/xx_gtkwave_extra.tcl @@ -1 +1 @@ -lappend all_signals tb.i_top.rx +lappend all_signals tb.i_lab_top.rx diff --git a/labs/16_round_robin_arbiter/gtkwave.tcl b/labs/16_round_robin_arbiter/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/16_round_robin_arbiter/gtkwave.tcl +++ b/labs/16_round_robin_arbiter/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/17_geiger_muller_radiation_counter/gtkwave.tcl b/labs/17_geiger_muller_radiation_counter/gtkwave.tcl index 7e659726..c6866a7f 100644 --- a/labs/17_geiger_muller_radiation_counter/gtkwave.tcl +++ b/labs/17_geiger_muller_radiation_counter/gtkwave.tcl @@ -5,10 +5,10 @@ set all_signals [list] lappend all_signals tb.clk lappend all_signals tb.rst lappend all_signals tb.key -lappend all_signals tb.i_top.cnt -lappend all_signals tb.i_top.led -lappend all_signals tb.i_top.abcdefgh -lappend all_signals tb.i_top.digit +lappend all_signals tb.i_lab_top.cnt +lappend all_signals tb.i_lab_top.led +lappend all_signals tb.i_lab_top.abcdefgh +lappend all_signals tb.i_lab_top.digit set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl index f61d9458..4e017826 100644 --- a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl +++ b/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl @@ -2,23 +2,23 @@ set all_signals [list] -lappend all_signals tb.i_top.clk -lappend all_signals tb.i_top.rst -lappend all_signals tb.i_top.a_valid -lappend all_signals tb.i_top.a_ready -lappend all_signals tb.i_top.a_data -lappend all_signals tb.i_top.b_valid -lappend all_signals tb.i_top.b_ready -lappend all_signals tb.i_top.b_data -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_data -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_data -lappend all_signals tb.i_top.out_valid -lappend all_signals tb.i_top.out_ready -lappend all_signals tb.i_top.out_data +lappend all_signals tb.i_lab_top.clk +lappend all_signals tb.i_lab_top.rst +lappend all_signals tb.i_lab_top.a_valid +lappend all_signals tb.i_lab_top.a_ready +lappend all_signals tb.i_lab_top.a_data +lappend all_signals tb.i_lab_top.b_valid +lappend all_signals tb.i_lab_top.b_ready +lappend all_signals tb.i_lab_top.b_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_data +lappend all_signals tb.i_lab_top.out_valid +lappend all_signals tb.i_lab_top.out_ready +lappend all_signals tb.i_lab_top.out_data set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl index f61d9458..4e017826 100644 --- a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl +++ b/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl @@ -2,23 +2,23 @@ set all_signals [list] -lappend all_signals tb.i_top.clk -lappend all_signals tb.i_top.rst -lappend all_signals tb.i_top.a_valid -lappend all_signals tb.i_top.a_ready -lappend all_signals tb.i_top.a_data -lappend all_signals tb.i_top.b_valid -lappend all_signals tb.i_top.b_ready -lappend all_signals tb.i_top.b_data -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_data -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_data -lappend all_signals tb.i_top.out_valid -lappend all_signals tb.i_top.out_ready -lappend all_signals tb.i_top.out_data +lappend all_signals tb.i_lab_top.clk +lappend all_signals tb.i_lab_top.rst +lappend all_signals tb.i_lab_top.a_valid +lappend all_signals tb.i_lab_top.a_ready +lappend all_signals tb.i_lab_top.a_data +lappend all_signals tb.i_lab_top.b_valid +lappend all_signals tb.i_lab_top.b_ready +lappend all_signals tb.i_lab_top.b_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_data +lappend all_signals tb.i_lab_top.out_valid +lappend all_signals tb.i_lab_top.out_ready +lappend all_signals tb.i_lab_top.out_data set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl index f61d9458..4e017826 100644 --- a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl +++ b/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl @@ -2,23 +2,23 @@ set all_signals [list] -lappend all_signals tb.i_top.clk -lappend all_signals tb.i_top.rst -lappend all_signals tb.i_top.a_valid -lappend all_signals tb.i_top.a_ready -lappend all_signals tb.i_top.a_data -lappend all_signals tb.i_top.b_valid -lappend all_signals tb.i_top.b_ready -lappend all_signals tb.i_top.b_data -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_data -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_data -lappend all_signals tb.i_top.out_valid -lappend all_signals tb.i_top.out_ready -lappend all_signals tb.i_top.out_data +lappend all_signals tb.i_lab_top.clk +lappend all_signals tb.i_lab_top.rst +lappend all_signals tb.i_lab_top.a_valid +lappend all_signals tb.i_lab_top.a_ready +lappend all_signals tb.i_lab_top.a_data +lappend all_signals tb.i_lab_top.b_valid +lappend all_signals tb.i_lab_top.b_ready +lappend all_signals tb.i_lab_top.b_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_data +lappend all_signals tb.i_lab_top.out_valid +lappend all_signals tb.i_lab_top.out_ready +lappend all_signals tb.i_lab_top.out_data set num_added [ gtkwave::addSignalsFromList $all_signals ] diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl index f61d9458..4e017826 100644 --- a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl +++ b/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl @@ -2,23 +2,23 @@ set all_signals [list] -lappend all_signals tb.i_top.clk -lappend all_signals tb.i_top.rst -lappend all_signals tb.i_top.a_valid -lappend all_signals tb.i_top.a_ready -lappend all_signals tb.i_top.a_data -lappend all_signals tb.i_top.b_valid -lappend all_signals tb.i_top.b_ready -lappend all_signals tb.i_top.b_data -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.a_down_data -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_valid -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_ready -lappend all_signals tb.i_top.i_rra_from_fifos.b_down_data -lappend all_signals tb.i_top.out_valid -lappend all_signals tb.i_top.out_ready -lappend all_signals tb.i_top.out_data +lappend all_signals tb.i_lab_top.clk +lappend all_signals tb.i_lab_top.rst +lappend all_signals tb.i_lab_top.a_valid +lappend all_signals tb.i_lab_top.a_ready +lappend all_signals tb.i_lab_top.a_data +lappend all_signals tb.i_lab_top.b_valid +lappend all_signals tb.i_lab_top.b_ready +lappend all_signals tb.i_lab_top.b_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.a_down_data +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_valid +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_ready +lappend all_signals tb.i_lab_top.i_rra_from_fifos.b_down_data +lappend all_signals tb.i_lab_top.out_valid +lappend all_signals tb.i_lab_top.out_ready +lappend all_signals tb.i_lab_top.out_data set num_added [ gtkwave::addSignalsFromList $all_signals ] From a4581da6d9e9d61895641b43cc852bdf2589b3e3 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 12:22:44 -0700 Subject: [PATCH 08/65] Started modifying VGA and graphics --- labs/06_vga/lab_top.sv | 53 +++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/labs/06_vga/lab_top.sv b/labs/06_vga/lab_top.sv index 53edd4e3..1fa8c6de 100644 --- a/labs/06_vga/lab_top.sv +++ b/labs/06_vga/lab_top.sv @@ -2,17 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -30,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -67,14 +73,7 @@ module lab_top assign uart_tx = '1; //------------------------------------------------------------------------ - - localparam w_x = 10, w_y = 10; - - //------------------------------------------------------------------------ - - wire [w_x - 1:0] x; - wire [w_y - 1:0] y; - +/* vga # ( .HPOS_WIDTH ( w_x ), @@ -94,7 +93,7 @@ module lab_top .vpos ( y ), .pixel_clk ( pixel_clk ) ); - +*/ //------------------------------------------------------------------------ // Pattern 1 From 89e670a9c25ce9e787b3762a0b0308e86357f6f5 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 12:24:54 -0700 Subject: [PATCH 09/65] Modifying VGA and graphics - renaming from VGA --- labs/{06_vga => 06_graphics}/01_clean.bash | 0 labs/{06_vga => 06_graphics}/02_simulate_rtl.bash | 0 labs/{06_vga => 06_graphics}/03_synthesize_for_fpga.bash | 0 labs/{06_vga => 06_graphics}/04_configure_fpga.bash | 0 labs/{06_vga => 06_graphics}/05_run_gui_for_fpga_synthesis.bash | 0 labs/{06_vga => 06_graphics}/06_choose_another_fpga_board.bash | 0 labs/{06_vga => 06_graphics}/07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 labs/{06_vga => 06_graphics}/lab_top.sv | 0 labs/{06_vga => 06_graphics}/tb.sv | 0 11 files changed, 0 insertions(+), 0 deletions(-) rename labs/{06_vga => 06_graphics}/01_clean.bash (100%) rename labs/{06_vga => 06_graphics}/02_simulate_rtl.bash (100%) rename labs/{06_vga => 06_graphics}/03_synthesize_for_fpga.bash (100%) rename labs/{06_vga => 06_graphics}/04_configure_fpga.bash (100%) rename labs/{06_vga => 06_graphics}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{06_vga => 06_graphics}/06_choose_another_fpga_board.bash (100%) rename labs/{06_vga => 06_graphics}/07_synthesize_for_asic.bash (100%) rename labs/{06_vga => 06_graphics}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{06_vga => 06_graphics}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{06_vga => 06_graphics}/lab_top.sv (100%) rename labs/{06_vga => 06_graphics}/tb.sv (100%) diff --git a/labs/06_vga/01_clean.bash b/labs/06_graphics/01_clean.bash similarity index 100% rename from labs/06_vga/01_clean.bash rename to labs/06_graphics/01_clean.bash diff --git a/labs/06_vga/02_simulate_rtl.bash b/labs/06_graphics/02_simulate_rtl.bash similarity index 100% rename from labs/06_vga/02_simulate_rtl.bash rename to labs/06_graphics/02_simulate_rtl.bash diff --git a/labs/06_vga/03_synthesize_for_fpga.bash b/labs/06_graphics/03_synthesize_for_fpga.bash similarity index 100% rename from labs/06_vga/03_synthesize_for_fpga.bash rename to labs/06_graphics/03_synthesize_for_fpga.bash diff --git a/labs/06_vga/04_configure_fpga.bash b/labs/06_graphics/04_configure_fpga.bash similarity index 100% rename from labs/06_vga/04_configure_fpga.bash rename to labs/06_graphics/04_configure_fpga.bash diff --git a/labs/06_vga/05_run_gui_for_fpga_synthesis.bash b/labs/06_graphics/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/06_vga/05_run_gui_for_fpga_synthesis.bash rename to labs/06_graphics/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/06_vga/06_choose_another_fpga_board.bash b/labs/06_graphics/06_choose_another_fpga_board.bash similarity index 100% rename from labs/06_vga/06_choose_another_fpga_board.bash rename to labs/06_graphics/06_choose_another_fpga_board.bash diff --git a/labs/06_vga/07_synthesize_for_asic.bash b/labs/06_graphics/07_synthesize_for_asic.bash similarity index 100% rename from labs/06_vga/07_synthesize_for_asic.bash rename to labs/06_graphics/07_synthesize_for_asic.bash diff --git a/labs/06_vga/08_visualize_asic_synthesis_results_1.bash b/labs/06_graphics/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/06_vga/08_visualize_asic_synthesis_results_1.bash rename to labs/06_graphics/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/06_vga/09_visualize_asic_synthesis_results_2.bash b/labs/06_graphics/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/06_vga/09_visualize_asic_synthesis_results_2.bash rename to labs/06_graphics/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/06_vga/lab_top.sv b/labs/06_graphics/lab_top.sv similarity index 100% rename from labs/06_vga/lab_top.sv rename to labs/06_graphics/lab_top.sv diff --git a/labs/06_vga/tb.sv b/labs/06_graphics/tb.sv similarity index 100% rename from labs/06_vga/tb.sv rename to labs/06_graphics/tb.sv From 6d9cff4b0b80390784b8cb340441cb4ea9b8c5e4 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 14:37:26 -0700 Subject: [PATCH 10/65] Editing DE2-115 top - 1 --- boards/de2_115/board_specific.qsf | 382 +++++++++--------- boards/de2_115/board_specific.sdc | 25 +- boards/de2_115/board_specific_top.sv | 78 ++-- .../board_specific_top.sv | 1 + 4 files changed, 247 insertions(+), 239 deletions(-) diff --git a/boards/de2_115/board_specific.qsf b/boards/de2_115/board_specific.qsf index e9c6a82e..6613fada 100644 --- a/boards/de2_115/board_specific.qsf +++ b/boards/de2_115/board_specific.qsf @@ -1,207 +1,207 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" + set_global_assignment -name DEVICE EP4CE115F29C7 + set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" #----------------------------------------------------------------------------- -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD -#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD -set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY* -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW* -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD + set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY* + set_instance_assignment -name IO_STANDARD "2.5 V" -to SW* + set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR* -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0* -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1* -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7* + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0* + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1* + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] + set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO* #----------------------------------------------------------------------------- -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -#set_location_assignment PIN_AG14 -to CLOCK2_50 -#set_location_assignment PIN_AG15 -to CLOCK3_50 -set_location_assignment PIN_Y2 -to CLOCK_50 +# set_location_assignment PIN_AG14 -to CLOCK2_50 +# set_location_assignment PIN_AG15 -to CLOCK3_50 + set_location_assignment PIN_Y2 -to CLOCK_50 -#set_location_assignment PIN_G9 -to UART_TXD -set_location_assignment PIN_G12 -to UART_RXD +# set_location_assignment PIN_G9 -to UART_TXD + set_location_assignment PIN_G12 -to UART_RXD -set_location_assignment PIN_M23 -to KEY[0] -set_location_assignment PIN_M21 -to KEY[1] -set_location_assignment PIN_N21 -to KEY[2] -set_location_assignment PIN_R24 -to KEY[3] + set_location_assignment PIN_M23 -to KEY[0] + set_location_assignment PIN_M21 -to KEY[1] + set_location_assignment PIN_N21 -to KEY[2] + set_location_assignment PIN_R24 -to KEY[3] -set_location_assignment PIN_AB28 -to SW[0] -set_location_assignment PIN_AC28 -to SW[1] -set_location_assignment PIN_AC27 -to SW[2] -set_location_assignment PIN_AD27 -to SW[3] -set_location_assignment PIN_AB27 -to SW[4] -set_location_assignment PIN_AC26 -to SW[5] -set_location_assignment PIN_AD26 -to SW[6] -set_location_assignment PIN_AB26 -to SW[7] -set_location_assignment PIN_AC25 -to SW[8] -set_location_assignment PIN_AB25 -to SW[9] -set_location_assignment PIN_AC24 -to SW[10] -set_location_assignment PIN_AB24 -to SW[11] -set_location_assignment PIN_AB23 -to SW[12] -set_location_assignment PIN_AA24 -to SW[13] -set_location_assignment PIN_AA23 -to SW[14] -set_location_assignment PIN_AA22 -to SW[15] -set_location_assignment PIN_Y24 -to SW[16] -set_location_assignment PIN_Y23 -to SW[17] + set_location_assignment PIN_AB28 -to SW[0] + set_location_assignment PIN_AC28 -to SW[1] + set_location_assignment PIN_AC27 -to SW[2] + set_location_assignment PIN_AD27 -to SW[3] + set_location_assignment PIN_AB27 -to SW[4] + set_location_assignment PIN_AC26 -to SW[5] + set_location_assignment PIN_AD26 -to SW[6] + set_location_assignment PIN_AB26 -to SW[7] + set_location_assignment PIN_AC25 -to SW[8] + set_location_assignment PIN_AB25 -to SW[9] + set_location_assignment PIN_AC24 -to SW[10] + set_location_assignment PIN_AB24 -to SW[11] + set_location_assignment PIN_AB23 -to SW[12] + set_location_assignment PIN_AA24 -to SW[13] + set_location_assignment PIN_AA23 -to SW[14] + set_location_assignment PIN_AA22 -to SW[15] + set_location_assignment PIN_Y24 -to SW[16] + set_location_assignment PIN_Y23 -to SW[17] -set_location_assignment PIN_G19 -to LEDR[0] -set_location_assignment PIN_F19 -to LEDR[1] -set_location_assignment PIN_E19 -to LEDR[2] -set_location_assignment PIN_F21 -to LEDR[3] -set_location_assignment PIN_F18 -to LEDR[4] -set_location_assignment PIN_E18 -to LEDR[5] -set_location_assignment PIN_J19 -to LEDR[6] -set_location_assignment PIN_H19 -to LEDR[7] -set_location_assignment PIN_J17 -to LEDR[8] -set_location_assignment PIN_G17 -to LEDR[9] -set_location_assignment PIN_J15 -to LEDR[10] -set_location_assignment PIN_H16 -to LEDR[11] -set_location_assignment PIN_J16 -to LEDR[12] -set_location_assignment PIN_H17 -to LEDR[13] -set_location_assignment PIN_F15 -to LEDR[14] -set_location_assignment PIN_G15 -to LEDR[15] -set_location_assignment PIN_G16 -to LEDR[16] -set_location_assignment PIN_H15 -to LEDR[17] + set_location_assignment PIN_G19 -to LEDR[0] + set_location_assignment PIN_F19 -to LEDR[1] + set_location_assignment PIN_E19 -to LEDR[2] + set_location_assignment PIN_F21 -to LEDR[3] + set_location_assignment PIN_F18 -to LEDR[4] + set_location_assignment PIN_E18 -to LEDR[5] + set_location_assignment PIN_J19 -to LEDR[6] + set_location_assignment PIN_H19 -to LEDR[7] + set_location_assignment PIN_J17 -to LEDR[8] + set_location_assignment PIN_G17 -to LEDR[9] + set_location_assignment PIN_J15 -to LEDR[10] + set_location_assignment PIN_H16 -to LEDR[11] + set_location_assignment PIN_J16 -to LEDR[12] + set_location_assignment PIN_H17 -to LEDR[13] + set_location_assignment PIN_F15 -to LEDR[14] + set_location_assignment PIN_G15 -to LEDR[15] + set_location_assignment PIN_G16 -to LEDR[16] + set_location_assignment PIN_H15 -to LEDR[17] -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] + set_location_assignment PIN_G18 -to HEX0[0] + set_location_assignment PIN_F22 -to HEX0[1] + set_location_assignment PIN_E17 -to HEX0[2] + set_location_assignment PIN_L26 -to HEX0[3] + set_location_assignment PIN_L25 -to HEX0[4] + set_location_assignment PIN_J22 -to HEX0[5] + set_location_assignment PIN_H22 -to HEX0[6] + set_location_assignment PIN_M24 -to HEX1[0] + set_location_assignment PIN_Y22 -to HEX1[1] + set_location_assignment PIN_W21 -to HEX1[2] + set_location_assignment PIN_W22 -to HEX1[3] + set_location_assignment PIN_W25 -to HEX1[4] + set_location_assignment PIN_U23 -to HEX1[5] + set_location_assignment PIN_U24 -to HEX1[6] + set_location_assignment PIN_AA25 -to HEX2[0] + set_location_assignment PIN_AA26 -to HEX2[1] + set_location_assignment PIN_Y25 -to HEX2[2] + set_location_assignment PIN_W26 -to HEX2[3] + set_location_assignment PIN_Y26 -to HEX2[4] + set_location_assignment PIN_W27 -to HEX2[5] + set_location_assignment PIN_W28 -to HEX2[6] + set_location_assignment PIN_V21 -to HEX3[0] + set_location_assignment PIN_U21 -to HEX3[1] + set_location_assignment PIN_AB20 -to HEX3[2] + set_location_assignment PIN_AA21 -to HEX3[3] + set_location_assignment PIN_AD24 -to HEX3[4] + set_location_assignment PIN_AF23 -to HEX3[5] + set_location_assignment PIN_Y19 -to HEX3[6] + set_location_assignment PIN_AB19 -to HEX4[0] + set_location_assignment PIN_AA19 -to HEX4[1] + set_location_assignment PIN_AG21 -to HEX4[2] + set_location_assignment PIN_AH21 -to HEX4[3] + set_location_assignment PIN_AE19 -to HEX4[4] + set_location_assignment PIN_AF19 -to HEX4[5] + set_location_assignment PIN_AE18 -to HEX4[6] + set_location_assignment PIN_AD18 -to HEX5[0] + set_location_assignment PIN_AC18 -to HEX5[1] + set_location_assignment PIN_AB18 -to HEX5[2] + set_location_assignment PIN_AH19 -to HEX5[3] + set_location_assignment PIN_AG19 -to HEX5[4] + set_location_assignment PIN_AF18 -to HEX5[5] + set_location_assignment PIN_AH18 -to HEX5[6] + set_location_assignment PIN_AA17 -to HEX6[0] + set_location_assignment PIN_AB16 -to HEX6[1] + set_location_assignment PIN_AA16 -to HEX6[2] + set_location_assignment PIN_AB17 -to HEX6[3] + set_location_assignment PIN_AB15 -to HEX6[4] + set_location_assignment PIN_AA15 -to HEX6[5] + set_location_assignment PIN_AC17 -to HEX6[6] + set_location_assignment PIN_AD17 -to HEX7[0] + set_location_assignment PIN_AE17 -to HEX7[1] + set_location_assignment PIN_AG17 -to HEX7[2] + set_location_assignment PIN_AH17 -to HEX7[3] + set_location_assignment PIN_AF17 -to HEX7[4] + set_location_assignment PIN_AG18 -to HEX7[5] + set_location_assignment PIN_AA14 -to HEX7[6] -set_location_assignment PIN_A12 -to VGA_CLK -set_location_assignment PIN_F11 -to VGA_BLANK_N -set_location_assignment PIN_C10 -to VGA_SYNC_N -set_location_assignment PIN_G13 -to VGA_HS -set_location_assignment PIN_C13 -to VGA_VS -set_location_assignment PIN_E12 -to VGA_R[0] -set_location_assignment PIN_E11 -to VGA_R[1] -set_location_assignment PIN_D10 -to VGA_R[2] -set_location_assignment PIN_F12 -to VGA_R[3] -set_location_assignment PIN_G10 -to VGA_R[4] -set_location_assignment PIN_J12 -to VGA_R[5] -set_location_assignment PIN_H8 -to VGA_R[6] -set_location_assignment PIN_H10 -to VGA_R[7] -set_location_assignment PIN_G8 -to VGA_G[0] -set_location_assignment PIN_G11 -to VGA_G[1] -set_location_assignment PIN_F8 -to VGA_G[2] -set_location_assignment PIN_H12 -to VGA_G[3] -set_location_assignment PIN_C8 -to VGA_G[4] -set_location_assignment PIN_B8 -to VGA_G[5] -set_location_assignment PIN_F10 -to VGA_G[6] -set_location_assignment PIN_C9 -to VGA_G[7] -set_location_assignment PIN_B10 -to VGA_B[0] -set_location_assignment PIN_A10 -to VGA_B[1] -set_location_assignment PIN_C11 -to VGA_B[2] -set_location_assignment PIN_B11 -to VGA_B[3] -set_location_assignment PIN_A11 -to VGA_B[4] -set_location_assignment PIN_C12 -to VGA_B[5] -set_location_assignment PIN_D11 -to VGA_B[6] -set_location_assignment PIN_D12 -to VGA_B[7] + set_location_assignment PIN_A12 -to VGA_CLK + set_location_assignment PIN_F11 -to VGA_BLANK_N + set_location_assignment PIN_C10 -to VGA_SYNC_N + set_location_assignment PIN_G13 -to VGA_HS + set_location_assignment PIN_C13 -to VGA_VS + set_location_assignment PIN_E12 -to VGA_R[0] + set_location_assignment PIN_E11 -to VGA_R[1] + set_location_assignment PIN_D10 -to VGA_R[2] + set_location_assignment PIN_F12 -to VGA_R[3] + set_location_assignment PIN_G10 -to VGA_R[4] + set_location_assignment PIN_J12 -to VGA_R[5] + set_location_assignment PIN_H8 -to VGA_R[6] + set_location_assignment PIN_H10 -to VGA_R[7] + set_location_assignment PIN_G8 -to VGA_G[0] + set_location_assignment PIN_G11 -to VGA_G[1] + set_location_assignment PIN_F8 -to VGA_G[2] + set_location_assignment PIN_H12 -to VGA_G[3] + set_location_assignment PIN_C8 -to VGA_G[4] + set_location_assignment PIN_B8 -to VGA_G[5] + set_location_assignment PIN_F10 -to VGA_G[6] + set_location_assignment PIN_C9 -to VGA_G[7] + set_location_assignment PIN_B10 -to VGA_B[0] + set_location_assignment PIN_A10 -to VGA_B[1] + set_location_assignment PIN_C11 -to VGA_B[2] + set_location_assignment PIN_B11 -to VGA_B[3] + set_location_assignment PIN_A11 -to VGA_B[4] + set_location_assignment PIN_C12 -to VGA_B[5] + set_location_assignment PIN_D11 -to VGA_B[6] + set_location_assignment PIN_D12 -to VGA_B[7] -set_location_assignment PIN_AB22 -to GPIO[0] -set_location_assignment PIN_AC15 -to GPIO[1] -set_location_assignment PIN_AB21 -to GPIO[2] -set_location_assignment PIN_Y17 -to GPIO[3] -set_location_assignment PIN_AC21 -to GPIO[4] -set_location_assignment PIN_Y16 -to GPIO[5] -set_location_assignment PIN_AD21 -to GPIO[6] -set_location_assignment PIN_AE16 -to GPIO[7] -set_location_assignment PIN_AD15 -to GPIO[8] -set_location_assignment PIN_AE15 -to GPIO[9] -set_location_assignment PIN_AC19 -to GPIO[10] -set_location_assignment PIN_AF16 -to GPIO[11] -set_location_assignment PIN_AD19 -to GPIO[12] -set_location_assignment PIN_AF15 -to GPIO[13] -set_location_assignment PIN_AF24 -to GPIO[14] -set_location_assignment PIN_AE21 -to GPIO[15] -set_location_assignment PIN_AF25 -to GPIO[16] -set_location_assignment PIN_AC22 -to GPIO[17] -set_location_assignment PIN_AE22 -to GPIO[18] -set_location_assignment PIN_AF21 -to GPIO[19] -set_location_assignment PIN_AF22 -to GPIO[20] -set_location_assignment PIN_AD22 -to GPIO[21] -set_location_assignment PIN_AG25 -to GPIO[22] -set_location_assignment PIN_AD25 -to GPIO[23] -set_location_assignment PIN_AH25 -to GPIO[24] -set_location_assignment PIN_AE25 -to GPIO[25] -set_location_assignment PIN_AG22 -to GPIO[26] -set_location_assignment PIN_AE24 -to GPIO[27] -set_location_assignment PIN_AH22 -to GPIO[28] -set_location_assignment PIN_AF26 -to GPIO[29] -set_location_assignment PIN_AE20 -to GPIO[30] -set_location_assignment PIN_AG23 -to GPIO[31] -set_location_assignment PIN_AF20 -to GPIO[32] -set_location_assignment PIN_AH26 -to GPIO[33] -set_location_assignment PIN_AH23 -to GPIO[34] -set_location_assignment PIN_AG26 -to GPIO[35] + set_location_assignment PIN_AB22 -to GPIO[0] + set_location_assignment PIN_AC15 -to GPIO[1] + set_location_assignment PIN_AB21 -to GPIO[2] + set_location_assignment PIN_Y17 -to GPIO[3] + set_location_assignment PIN_AC21 -to GPIO[4] + set_location_assignment PIN_Y16 -to GPIO[5] + set_location_assignment PIN_AD21 -to GPIO[6] + set_location_assignment PIN_AE16 -to GPIO[7] + set_location_assignment PIN_AD15 -to GPIO[8] + set_location_assignment PIN_AE15 -to GPIO[9] + set_location_assignment PIN_AC19 -to GPIO[10] + set_location_assignment PIN_AF16 -to GPIO[11] + set_location_assignment PIN_AD19 -to GPIO[12] + set_location_assignment PIN_AF15 -to GPIO[13] + set_location_assignment PIN_AF24 -to GPIO[14] + set_location_assignment PIN_AE21 -to GPIO[15] + set_location_assignment PIN_AF25 -to GPIO[16] + set_location_assignment PIN_AC22 -to GPIO[17] + set_location_assignment PIN_AE22 -to GPIO[18] + set_location_assignment PIN_AF21 -to GPIO[19] + set_location_assignment PIN_AF22 -to GPIO[20] + set_location_assignment PIN_AD22 -to GPIO[21] + set_location_assignment PIN_AG25 -to GPIO[22] + set_location_assignment PIN_AD25 -to GPIO[23] + set_location_assignment PIN_AH25 -to GPIO[24] + set_location_assignment PIN_AE25 -to GPIO[25] + set_location_assignment PIN_AG22 -to GPIO[26] + set_location_assignment PIN_AE24 -to GPIO[27] + set_location_assignment PIN_AH22 -to GPIO[28] + set_location_assignment PIN_AF26 -to GPIO[29] + set_location_assignment PIN_AE20 -to GPIO[30] + set_location_assignment PIN_AG23 -to GPIO[31] + set_location_assignment PIN_AF20 -to GPIO[32] + set_location_assignment PIN_AH26 -to GPIO[33] + set_location_assignment PIN_AH23 -to GPIO[34] + set_location_assignment PIN_AG26 -to GPIO[35] diff --git a/boards/de2_115/board_specific.sdc b/boards/de2_115/board_specific.sdc index 80c97317..ad055607 100644 --- a/boards/de2_115/board_specific.sdc +++ b/boards/de2_115/board_specific.sdc @@ -1,23 +1,14 @@ create_clock -period "50.0 MHz" [get_ports CLOCK_50] -# for calculating divide_by value see vga_clock parameter in boards/de2_115/board_specific_top.sv - -create_generated_clock -name vga_clk -divide_by 2 -source [get_ports { CLOCK_50 }] [get_registers { clk_en }] -create_generated_clock -name vga_clk_out -source [get_registers { clk_en }] [get_ports { VGA_CLK }] - derive_clock_uncertainty -set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] -set_false_path -from UART_RXD -to [all_clocks] -set_false_path -from [get_ports {SW[*]}] -to [all_clocks] -set_false_path -from [get_ports {GPIO[*]}] -to [all_clocks] + set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] + set_false_path -from UART_RXD -to [all_clocks] + set_false_path -from [get_ports {SW[*]}] -to [all_clocks] + set_false_path -from [get_ports {GPIO[*]}] -to [all_clocks] # set_false_path -from * -to UART_TXD - -set_false_path -from * -to [get_ports {LEDR[*]}] - -set_false_path -from * -to [get_ports {HEX*}] - -set_false_path -from * -to [get_ports {VGA_*}] - -set_false_path -from * -to [get_ports {GPIO[*]}] + set_false_path -from * -to [get_ports {LEDR[*]}] + set_false_path -from * -to [get_ports {HEX*}] + set_false_path -from * -to [get_ports {VGA_*}] + set_false_path -from * -to [get_ports {GPIO[*]}] diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index f67426a4..6dccade0 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -1,24 +1,40 @@ `include "config.svh" `include "lab_specific_config.svh" +`define USE_HIGH_LED_FOR_7SEG_DP + module board_specific_top # ( - parameter clk_mhz = 50, - w_key = 4, - w_sw = 18, - w_led = 18, - w_digit = 8, - w_gpio = 36, // GPIO[5:0] reserved for mic - vga_clock = 25 // Pixel clock of VGA in MHz, recommend be equal with VGA_CLOCK from labs/common/vga.sv + parameter clk_mhz = 50, + pixel_mhz = 25, + + w_key = 4, + w_sw = 18, + w_led = 18, + w_digit = 8, + w_gpio = 36 + + // gpio 0..5 are reserved for INMP 441 I2S microphone. + // Odd gpio .. are reserved I2S audio. + + screen_width = 640, + screen_height = 480, + + w_red = 8, + w_green = 8, + w_blue = 8, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input CLOCK_50, input [w_key - 1:0] KEY, input [w_sw - 1:0] SW, - output [w_led - 1:0] LEDR, // The last 8 LEDR are used like a 7SEG dp + output [w_led - 1:0] LEDR, // The last 8 LEDR are optionally used to output 7SEG dp - output logic [ 6:0] HEX0, // HEX[7] aka dp doesn't connected to FPGA at DE2-115 + output logic [ 6:0] HEX0, // HEX[7] aka dp are not connected to FPGA at DE2-115 output logic [ 6:0] HEX1, output logic [ 6:0] HEX2, output logic [ 6:0] HEX3, @@ -27,12 +43,12 @@ module board_specific_top output logic [ 6:0] HEX6, output logic [ 6:0] HEX7, - output VGA_CLK, // VGA DAC input triggers CLK + output VGA_CLK, output VGA_HS, output VGA_VS, - output [ 7:0] VGA_R, - output [ 7:0] VGA_G, - output [ 7:0] VGA_B, + output [w_red - 1:0] VGA_R, + output [w_green - 1:0] VGA_G, + output [w_blue - 1:0] VGA_B, output VGA_BLANK_N, output VGA_SYNC_N, @@ -43,26 +59,26 @@ module board_specific_top localparam w_top_sw = w_sw - 1; // One sw is used as a reset - wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + `ifdef USE_HIGH_LED_FOR_7SEG_DP + localparam w_top_led = w_led - w_digit; + `else + localparam w_top_led = w_led; + `endif //------------------------------------------------------------------------ - wire [w_led - w_digit - 1:0] top_led; - - wire [ 7:0] abcdefgh; - wire [ w_digit - 1:0] digit; + wire clk = CLOCK_50; + wire rst = SW [w_top_sw]; - wire [ 3:0] vga_red_4b,vga_green_4b,vga_blue_4b; + wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_key - 1:0] top_key = ~ KEY; + wire [w_top_led - 1:0] top_led; - wire [ 23:0] mic; - wire [ 15:0] sound; + wire [ 7:0] abcdefgh; + wire [w_digit - 1:0] digit; - // FIXME: Should be assigned to some GPIO! - wire UART_TX; - wire UART_RX = '1; + wire [ 23:0] mic; + wire [ 15:0] sound; //------------------------------------------------------------------------ @@ -76,7 +92,7 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_key ), + .w_key ( w_top_key ), .w_sw ( w_top_sw ), .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp .w_digit ( w_digit ), @@ -99,12 +115,12 @@ module board_specific_top .vsync ( VGA_VS ), .hsync ( VGA_HS ), - .red ( vga_red_4b ), + .red ( VGA_R ), .green ( vga_green_4b ), .blue ( vga_blue_4b ), - .uart_rx ( UART_RX ), - .uart_tx ( UART_TX ), + .uart_rx ( ), // TODO + .uart_tx ( ), // TODO .mic ( mic ), .sound ( sound ), diff --git a/boards/tang_primer_25k_dock/board_specific_top.sv b/boards/tang_primer_25k_dock/board_specific_top.sv index 2bc6484e..5f9c4b20 100644 --- a/boards/tang_primer_25k_dock/board_specific_top.sv +++ b/boards/tang_primer_25k_dock/board_specific_top.sv @@ -9,6 +9,7 @@ module board_specific_top # ( parameter clk_mhz = 50, pixel_mhz = 25, + w_key = 2, w_sw = 0, w_led = 0, From 616c4441ab10a2d41818934be588e171d6cbb960 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 14:40:28 -0700 Subject: [PATCH 11/65] More renaming top -> lab --- boards/arty_a7/board_specific_top.sv | 24 +++---- .../arty_a7_pmod_mic3/board_specific_top.sv | 24 +++---- boards/basys3/board_specific_top.sv | 6 +- boards/c5gx_audio/board_specific_top.sv | 6 +- boards/c5gx_vga666/board_specific_top.sv | 6 +- boards/c5gx_vga_pmod/board_specific_top.sv | 6 +- boards/de0/board_specific_top.sv | 8 +-- .../de0_nano_soc_vga666/board_specific_top.sv | 32 ++++----- .../board_specific_top.sv | 32 ++++----- boards/de0_nano_vga666/board_specific_top.sv | 32 ++++----- .../de0_nano_vga_pmod/board_specific_top.sv | 32 ++++----- boards/de1/board_specific_top.sv | 8 +-- boards/de10_lite/board_specific_top.sv | 6 +- .../board_specific_top.sv | 32 ++++----- boards/de10_nano_vga666/board_specific_top.sv | 34 +++++----- .../board_specific_top.sv | 34 +++++----- .../de10_nano_vga_pmod/board_specific_top.sv | 34 +++++----- boards/de1_soc/board_specific_top.sv | 8 +-- boards/de2/board_specific_top.sv | 8 +-- boards/de2_115/board_specific_top.sv | 16 ++--- boards/emooc_cc/board_specific_top.sv | 6 +- .../ice40hx8k_evb_yosys/board_specific_top.sv | 30 ++++---- .../karnix_ecp5_yosys/board_specific_top.sv | 30 ++++---- .../board_specific_top.sv | 30 ++++---- boards/piswords6/board_specific_top.sv | 8 +-- boards/step_max10/board_specific_top.sv | 8 +-- boards/tang_nano_20k/board_specific_top.sv | 30 ++++---- boards/tang_nano_9k/board_specific_top.sv | 30 ++++---- .../board_specific_top.sv | 30 ++++---- .../tang_nano_9k_hdmi/board_specific_top.sv | 30 ++++---- boards/tang_nano_9k_lcd/board_specific_top.sv | 30 ++++---- .../board_specific_top.sv | 32 ++++----- .../board_specific_top.sv | 68 +++++++++---------- .../board_specific_top.sv | 32 ++++----- .../board_specific_top.sv | 32 ++++----- .../board_specific_top.sv | 32 ++++----- boards/zeowaa/board_specific_top.sv | 6 +- boards/zeowaa_wo_dig_0/board_specific_top.sv | 6 +- 38 files changed, 429 insertions(+), 429 deletions(-) diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index 6c8857e4..8bed02cb 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -92,15 +92,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif @@ -108,9 +108,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -158,10 +158,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), + .w_key ( w_lab_key ), .w_sw ( w_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index e408771e..fea2f4e9 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -92,15 +92,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif @@ -108,9 +108,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -158,10 +158,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), + .w_key ( w_lab_key ), .w_sw ( w_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/basys3/board_specific_top.sv b/boards/basys3/board_specific_top.sv index 78f037b9..5737811f 100644 --- a/boards/basys3/board_specific_top.sv +++ b/boards/basys3/board_specific_top.sv @@ -42,10 +42,10 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire rst = sw [w_sw - 1]; - wire [w_top_sw - 1:0] top_sw = sw [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = sw [w_lab_sw - 1:0]; // FIXME: Should be assigned to some GPIO! wire UART_RX = '1; @@ -76,7 +76,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index 4d2b18f3..b9e46b10 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -33,12 +33,12 @@ module board_specific_top inout [w_gpio - 1:0] GPIO ); - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ KEY; //------------------------------------------------------------------------ @@ -66,7 +66,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index 6adb997b..6f2a99bf 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -33,12 +33,12 @@ module board_specific_top inout [w_gpio - 1:0] GPIO ); - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ KEY; //------------------------------------------------------------------------ @@ -68,7 +68,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index bc517436..e24cebae 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -33,12 +33,12 @@ module board_specific_top inout [w_gpio - 1:0] GPIO ); - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ KEY; //------------------------------------------------------------------------ @@ -61,7 +61,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index d27833dc..0e0812df 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -38,12 +38,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ BUTTON; //------------------------------------------------------------------------ @@ -71,7 +71,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO_0[7:2] reserved for mic diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index e7a0f628..584f6f6a 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -27,13 +27,13 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -59,15 +59,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -76,9 +76,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -125,10 +125,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] reserved for mic ) i_lab_top diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 27033660..59ff8aac 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -27,13 +27,13 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -59,15 +59,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -76,9 +76,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -118,10 +118,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] reserved for mic ) i_lab_top diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 285076bf..63595a7b 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -27,12 +27,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -58,15 +58,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -75,9 +75,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -124,10 +124,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] for mic ) i_lab_top diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 13f455d7..6f094e37 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -27,12 +27,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -58,15 +58,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -75,9 +75,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -124,10 +124,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638, GPIO_0[5:0] for mic ) i_lab_top diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index 6bed8027..f6e733c6 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -39,12 +39,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ KEY; //------------------------------------------------------------------------ @@ -69,7 +69,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index 1400f708..6a1a301c 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -35,12 +35,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = MAX10_CLK1_50; wire rst = SW [w_sw - 1]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ KEY; //------------------------------------------------------------------------ @@ -68,7 +68,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index c1c70f4f..6a8ef9d1 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -39,12 +39,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = MAX10_CLK1_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; assign ARDUINO_RESET_N = ~ rst; @@ -70,15 +70,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -87,9 +87,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -137,10 +137,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_arduino + w_gpio ) // top gpio includes both ARDUINO and GPIO pins diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index 0fc2d6e5..5984cecc 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -28,17 +28,17 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; `ifdef MISTER_IO_BOARD - wire rst = SW [w_top_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; + wire rst = SW [w_lab_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; `else - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; `endif - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -64,15 +64,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -81,9 +81,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -123,10 +123,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) i_lab_top diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index 192819ca..841c0813 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -28,17 +28,17 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; `ifdef MISTER_IO_BOARD - wire rst = SW [w_top_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; + wire rst = SW [w_lab_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; `else - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; `endif - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -64,15 +64,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -81,9 +81,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -130,10 +130,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) i_lab_top diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index 36f06e74..0f8e828a 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -28,17 +28,17 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = FPGA_CLK1_50; `ifdef MISTER_IO_BOARD - wire rst = SW [w_top_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; + wire rst = SW [w_lab_sw] | ~ GPIO_1 [14]; // GPIO_1 [14] (JP7 pin 17) is BTN_RESET key on MiSTer I/O board, internal FGPA weak pull-up enabled; `else - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; `endif - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -64,15 +64,15 @@ module board_specific_top `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR - localparam w_top_key = w_tm_key > w_key ? w_tm_key : w_key , - w_top_led = w_tm_led > w_led ? w_tm_led : w_led , - w_top_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; + localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , + w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , + w_lab_digit = w_tm_digit > w_digit ? w_tm_digit : w_digit ; `else // Concatenate the signals - localparam w_top_key = w_tm_key + w_key , - w_top_led = w_tm_led + w_led , - w_top_digit = w_tm_digit + w_digit ; + localparam w_lab_key = w_tm_key + w_key , + w_lab_led = w_tm_led + w_led , + w_lab_digit = w_tm_digit + w_digit ; `endif //------------------------------------------------------------------------ @@ -81,9 +81,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -123,10 +123,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) // GPIO_0 [31], [33], [35] reserved for tm1638; GPIO [11], [13], [15], [17] reserved for i2s audio; GPIO_0[5:0] reserved for mic ) i_lab_top diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index 45da8d69..64a19346 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -40,11 +40,11 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ KEY; //------------------------------------------------------------------------ @@ -75,7 +75,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 6 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO_0[5:0] reserved for mic diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index dc8b8492..98789821 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -47,12 +47,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ KEY; //------------------------------------------------------------------------ @@ -79,7 +79,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index 6dccade0..42108d2e 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -57,22 +57,22 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset `ifdef USE_HIGH_LED_FOR_7SEG_DP - localparam w_top_led = w_led - w_digit; + localparam w_lab_led = w_led - w_digit; `else - localparam w_top_led = w_led; + localparam w_lab_led = w_led; `endif //------------------------------------------------------------------------ wire clk = CLOCK_50; - wire rst = SW [w_top_sw]; + wire rst = SW [w_lab_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ KEY; - wire [w_top_led - 1:0] top_led; + wire [w_lab_led - 1:0] top_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -92,8 +92,8 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), - .w_sw ( w_top_sw ), + .w_key ( w_lab_key ), + .w_sw ( w_lab_sw ), .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp .w_digit ( w_digit ), .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic diff --git a/boards/emooc_cc/board_specific_top.sv b/boards/emooc_cc/board_specific_top.sv index 1d597bf9..34fccc51 100644 --- a/boards/emooc_cc/board_specific_top.sv +++ b/boards/emooc_cc/board_specific_top.sv @@ -48,12 +48,12 @@ module board_specific_top // locally useful numeric constants localparam w_gpio = w_gpio_j7 + w_gpio_p1 + w_gpio_p2, - w_top_sw = w_sw - 1; + w_lab_sw = w_sw - 1; // one switch is used as reset, others - as input signals; // for convenience, declare set of wires "top_sw" wire rst = SW [w_sw - 1]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; // need explicit wire to be able to invert wire [ 7:0] abcdefgh; @@ -80,7 +80,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), // only non-reset switches used as inputs + .w_sw ( w_lab_sw ), // only non-reset switches used as inputs .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 2e4caaae..e9ff7120 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -43,17 +43,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -63,9 +63,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -105,10 +105,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index f8526e6c..63716236 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -46,17 +46,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -66,9 +66,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -109,10 +109,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index bfd54e57..00fc36bb 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -46,17 +46,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -66,9 +66,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -108,10 +108,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/piswords6/board_specific_top.sv b/boards/piswords6/board_specific_top.sv index 1acd2e0f..fb416b90 100644 --- a/boards/piswords6/board_specific_top.sv +++ b/boards/piswords6/board_specific_top.sv @@ -33,10 +33,10 @@ module board_specific_top wire clk = CLK; - localparam w_top_key = w_key - 1; // One key is used as a reset + localparam w_lab_key = w_key - 1; // One key is used as a reset - wire rst = ~ KEY [w_top_key]; - wire [w_top_key - 1:0] top_key = ~ KEY [w_top_key - 1:0]; + wire rst = ~ KEY [w_lab_key]; + wire [w_lab_key - 1:0] top_key = ~ KEY [w_lab_key - 1:0]; //------------------------------------------------------------------------ @@ -63,7 +63,7 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), + .w_key ( w_lab_key ), .w_sw ( w_sw ), .w_led ( w_led ), .w_digit ( w_digit ), diff --git a/boards/step_max10/board_specific_top.sv b/boards/step_max10/board_specific_top.sv index f3df6cc0..511504eb 100644 --- a/boards/step_max10/board_specific_top.sv +++ b/boards/step_max10/board_specific_top.sv @@ -24,12 +24,12 @@ module board_specific_top //------------------------------------------------------------------------ - localparam w_top_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire clk = clk_in; - wire rst = SW [w_top_sw]; - wire [w_top_sw - 1:0] top_sw = SW [w_top_sw - 1:0]; + wire rst = SW [w_lab_sw]; + wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] top_key = ~ BTN; //------------------------------------------------------------------------ @@ -45,7 +45,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ), .w_key ( w_key ), - .w_sw ( w_top_sw ), + .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), .w_gpio ( w_gpio ) diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index b71e744a..2f16d290 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -37,17 +37,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -57,9 +57,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -103,10 +103,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index 13040c0a..f93d08d7 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -43,17 +43,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -63,9 +63,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -102,10 +102,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index 2516f9d5..b110320c 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -46,17 +46,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -66,9 +66,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -105,10 +105,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index aefded76..d022b433 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -46,17 +46,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -81,9 +81,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -145,10 +145,10 @@ module board_specific_top `else .clk_mhz ( clk_mhz ), `endif - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) `ifdef USE_HDMI , diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index 55418fce..2b857d4f 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -85,17 +85,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -105,9 +105,9 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -150,10 +150,10 @@ module board_specific_top .clk_mhz ( clk_mhz ), .pixel_mhz ( pixel_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_key ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_key ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ), .w_red ( w_red ), diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index a703ca16..8017429c 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -39,17 +39,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -59,10 +59,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + logic [w_lab_sw - 1:0] top_sw; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -108,10 +108,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 021d47d4..413dc4ce 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -53,39 +53,39 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif //------------------------------------------------------------------------ `ifdef ENABLE_VGA16 - localparam w_top_red = 5, - w_top_green = 6, - w_top_blue = 5; + localparam w_lab_red = 5, + w_lab_green = 6, + w_lab_blue = 5; `elsif ENABLE_VGA666 - localparam w_top_red = 6, - w_top_green = 6, - w_top_blue = 6; + localparam w_lab_red = 6, + w_lab_green = 6, + w_lab_blue = 6; `elsif ENABLE_HDMI localparam vid_clk_mhz = 125, - w_top_red = 8, - w_top_green = 8, - w_top_blue = 8; + w_lab_red = 8, + w_lab_green = 8, + w_lab_blue = 8; `else - localparam w_top_red = 4, - w_top_green = 4, - w_top_blue = 4; + localparam w_lab_red = 4, + w_lab_green = 4, + w_lab_blue = 4; `endif //------------------------------------------------------------------------ @@ -94,10 +94,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + logic [w_lab_sw - 1:0] top_sw; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -115,9 +115,9 @@ module board_specific_top wire VGA_HS; wire VGA_VS; - logic [ w_top_red - 1:0] VGA_R; - logic [ w_top_green - 1:0] VGA_G; - logic [ w_top_blue - 1:0] VGA_B; + logic [ w_lab_red - 1:0] VGA_R; + logic [ w_lab_green - 1:0] VGA_G; + logic [ w_lab_blue - 1:0] VGA_B; //------------------------------------------------------------------------ @@ -175,14 +175,14 @@ module board_specific_top `else .clk_mhz ( clk_mhz ), `endif - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ), - .w_red ( w_top_red ), - .w_green ( w_top_green ), - .w_blue ( w_top_blue ) + .w_red ( w_lab_red ), + .w_green ( w_lab_green ), + .w_blue ( w_lab_blue ) ) i_lab_top ( diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index 4f9a66ed..274b8394 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -42,17 +42,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -62,10 +62,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + logic [w_lab_sw - 1:0] top_sw; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -111,10 +111,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 08116ee2..7be8c0c8 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -41,17 +41,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -61,10 +61,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + logic [w_lab_sw - 1:0] top_sw; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -110,10 +110,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index 84a80845..d922cd10 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -41,17 +41,17 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected - localparam w_top_key = w_tm_key, - w_top_sw = w_sw, - w_top_led = w_tm_led, - w_top_digit = w_tm_digit; + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; `else // TM1638 module is not connected - localparam w_top_key = w_key, - w_top_sw = w_sw, - w_top_led = w_led, - w_top_digit = w_digit; + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; `endif @@ -61,10 +61,10 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_top_key - 1:0] top_key; - logic [w_top_sw - 1:0] top_sw; - wire [w_top_led - 1:0] top_led; - wire [w_top_digit - 1:0] top_digit; + logic [w_lab_key - 1:0] top_key; + logic [w_lab_sw - 1:0] top_sw; + wire [w_lab_led - 1:0] top_led; + wire [w_lab_digit - 1:0] top_digit; wire rst; wire [ 7:0] abcdefgh; @@ -110,10 +110,10 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), // The last key is used for a reset - .w_sw ( w_top_sw ), - .w_led ( w_top_led ), - .w_digit ( w_top_digit ), + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), .w_gpio ( w_gpio ) ) i_lab_top diff --git a/boards/zeowaa/board_specific_top.sv b/boards/zeowaa/board_specific_top.sv index 0aa829cb..f769d2bc 100644 --- a/boards/zeowaa/board_specific_top.sv +++ b/boards/zeowaa/board_specific_top.sv @@ -31,11 +31,11 @@ module board_specific_top inout [w_gpio - 1:0] GPIO ); - localparam w_top_key = w_key - 1; // One onboard key is used as a reset + localparam w_lab_key = w_key - 1; // One onboard key is used as a reset wire clk = CLK; wire rst = ~ KEY_N [w_key - 1]; - wire [w_top_key - 1:0] top_key = ~ KEY_N [w_top_key - 1:0]; + wire [w_lab_key - 1:0] top_key = ~ KEY_N [w_lab_key - 1:0]; //------------------------------------------------------------------------ @@ -66,7 +66,7 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .w_key ( w_top_key ), + .w_key ( w_lab_key ), .w_sw ( w_sw ), .w_led ( w_led ), .w_digit ( w_digit ), diff --git a/boards/zeowaa_wo_dig_0/board_specific_top.sv b/boards/zeowaa_wo_dig_0/board_specific_top.sv index b7fae76f..3b8718fa 100644 --- a/boards/zeowaa_wo_dig_0/board_specific_top.sv +++ b/boards/zeowaa_wo_dig_0/board_specific_top.sv @@ -55,8 +55,8 @@ module board_specific_top // This logic is necessary to compensate the defective board - localparam w_top_digit = w_digit - 1; // The right digit is not working on this board - wire [w_top_digit - 1:0] top_digit; + localparam w_lab_digit = w_digit - 1; // The right digit is not working on this board + wire [w_lab_digit - 1:0] top_digit; assign digit = { top_digit, 1'b0 }; @@ -75,7 +75,7 @@ module board_specific_top .w_key ( w_key ), .w_sw ( w_sw ), .w_led ( w_led ), - .w_digit ( w_top_digit ), // Note top_digit, not digit + .w_digit ( w_lab_digit ), // Note top_digit, not digit .w_gpio ( w_gpio ) ) i_lab_top From e995061f89650b944bd170a7d47a8eabe44c76bb Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 14:50:42 -0700 Subject: [PATCH 12/65] More renaming top -> lab_key --- boards/arty_a7/board_specific_top.sv | 14 +++++++------- boards/arty_a7_pmod_mic3/board_specific_top.sv | 14 +++++++------- boards/c5gx_audio/board_specific_top.sv | 4 ++-- boards/c5gx_vga666/board_specific_top.sv | 4 ++-- boards/c5gx_vga_pmod/board_specific_top.sv | 4 ++-- boards/de0/board_specific_top.sv | 4 ++-- boards/de0_cv/board_specific_top.sv | 4 ++-- boards/de0_nano_soc_vga666/board_specific_top.sv | 14 +++++++------- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 14 +++++++------- boards/de0_nano_vga666/board_specific_top.sv | 14 +++++++------- boards/de0_nano_vga_pmod/board_specific_top.sv | 14 +++++++------- boards/de1/board_specific_top.sv | 4 ++-- boards/de10_lite/board_specific_top.sv | 4 ++-- .../de10_lite_tm1638_arduino/board_specific_top.sv | 14 +++++++------- boards/de10_nano_vga666/board_specific_top.sv | 14 +++++++------- boards/de10_nano_vga_mister/board_specific_top.sv | 14 +++++++------- boards/de10_nano_vga_pmod/board_specific_top.sv | 14 +++++++------- boards/de1_soc/board_specific_top.sv | 4 ++-- boards/de2/board_specific_top.sv | 4 ++-- boards/de2_115/board_specific_top.sv | 4 ++-- boards/ice40hx8k_evb_yosys/board_specific_top.sv | 8 ++++---- boards/karnix_ecp5_yosys/board_specific_top.sv | 8 ++++---- boards/omdazz/board_specific_top.sv | 4 ++-- boards/omdazz_pmod_mic3/board_specific_top.sv | 4 ++-- boards/orangecrab_ecp5_yosys/board_specific_top.sv | 8 ++++---- boards/piswords6/board_specific_top.sv | 4 ++-- boards/rzrd/board_specific_top.sv | 4 ++-- boards/rzrd_pmod_mic3/board_specific_top.sv | 4 ++-- boards/step_max10/board_specific_top.sv | 4 ++-- boards/tang_nano_20k/board_specific_top.sv | 8 ++++---- boards/tang_nano_9k/board_specific_top.sv | 8 ++++---- .../tang_nano_9k_gowin_yosys/board_specific_top.sv | 8 ++++---- boards/tang_nano_9k_hdmi/board_specific_top.sv | 8 ++++---- boards/tang_nano_9k_lcd/board_specific_top.sv | 10 +++++----- boards/tang_primer_20k_dock/board_specific_top.sv | 8 ++++---- .../tang_primer_20k_dock_alt/board_specific_top.sv | 8 ++++---- .../board_specific_top.sv | 8 ++++---- .../board_specific_top.sv | 8 ++++---- boards/tang_primer_20k_lite/board_specific_top.sv | 8 ++++---- boards/zeowaa/board_specific_top.sv | 4 ++-- 40 files changed, 157 insertions(+), 157 deletions(-) diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index 8bed02cb..5c1eb0f8 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -108,7 +108,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -117,14 +117,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, KEY }; + assign lab_key = { tm_key, KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { KEY, tm_key }; + assign lab_key = { KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -133,10 +133,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -170,7 +170,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index fea2f4e9..c4b41e6f 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -108,7 +108,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -117,14 +117,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, KEY }; + assign lab_key = { tm_key, KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { KEY, tm_key }; + assign lab_key = { KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -133,10 +133,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -170,7 +170,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index b9e46b10..240e4d09 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -39,7 +39,7 @@ module board_specific_top wire rst = ~ CPU_RESET_n; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -77,7 +77,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index 6f2a99bf..51cc71ba 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -39,7 +39,7 @@ module board_specific_top wire rst = ~ CPU_RESET_n; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -79,7 +79,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index e24cebae..0329a539 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -39,7 +39,7 @@ module board_specific_top wire rst = ~ CPU_RESET_n; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -71,7 +71,7 @@ module board_specific_top .clk ( clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index 0e0812df..6d736dd8 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ BUTTON; + wire [w_key - 1:0] lab_key = ~ BUTTON; //------------------------------------------------------------------------ @@ -82,7 +82,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( LEDG ), diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index d5b6b247..24bcab90 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -40,7 +40,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = ~ RESET_N; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -79,7 +79,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( SW ), .led ( top_led ), diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index 584f6f6a..4299a8e9 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -76,7 +76,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -84,14 +84,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -100,10 +100,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -137,7 +137,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 59ff8aac..85a60c7f 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -76,7 +76,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -84,14 +84,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -100,10 +100,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -129,7 +129,7 @@ module board_specific_top .clk ( clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 63595a7b..bc336ec2 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -75,7 +75,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -83,14 +83,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -99,10 +99,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -136,7 +136,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 6f094e37..50d1bd00 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -75,7 +75,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -83,14 +83,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -99,10 +99,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -136,7 +136,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index f6e733c6..2ea0f088 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -45,7 +45,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ wire [ w_led - w_digit - 1:0] top_led; @@ -80,7 +80,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index 6a1a301c..b55363ef 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -41,7 +41,7 @@ module board_specific_top wire rst = SW [w_sw - 1]; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -79,7 +79,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( LEDR ), diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 6a8ef9d1..69c07176 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -87,7 +87,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -95,14 +95,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LEDR } = top_led; assign { tm_digit , digit } = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; assign { LEDR , tm_led } = top_led; assign { digit , tm_digit } = top_digit; @@ -111,10 +111,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LEDR = top_led [w_led - 1:0]; @@ -152,7 +152,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index 5984cecc..e8d35da7 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -81,7 +81,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -89,14 +89,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -105,10 +105,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -135,7 +135,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index 841c0813..c28d54c0 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -81,7 +81,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -89,14 +89,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -105,10 +105,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -142,7 +142,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index 0f8e828a..074dcad1 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -81,7 +81,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -89,14 +89,14 @@ module board_specific_top `ifdef CONCAT_TM_SIGNALS_AND_REGULAR - assign top_key = { tm_key, ~ KEY }; + assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = top_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM - assign top_key = { ~ KEY, tm_key }; + assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = top_led; assign tm_digit = top_digit; @@ -105,10 +105,10 @@ module board_specific_top always_comb begin - top_key = '0; + lab_key = '0; - top_key [w_key - 1:0] |= ~ KEY; - top_key [w_tm_key - 1:0] |= tm_key; + lab_key [w_key - 1:0] |= ~ KEY; + lab_key [w_tm_key - 1:0] |= tm_key; end assign LED = top_led [w_led - 1:0]; @@ -135,7 +135,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index 64a19346..9e2ecdbb 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -45,7 +45,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = SW [w_lab_sw]; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -86,7 +86,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index 98789821..7963c929 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -53,7 +53,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ wire [ w_led - w_digit - 1:0] top_led; @@ -90,7 +90,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index 42108d2e..534c29f2 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -71,7 +71,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; wire [w_lab_led - 1:0] top_led; wire [ 7:0] abcdefgh; @@ -104,7 +104,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index e9ff7120..00aa7d57 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -63,7 +63,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -76,7 +76,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = top_led; assign tm_digit = top_digit; @@ -84,7 +84,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign LED = ~ top_led; @@ -117,7 +117,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), .led ( top_led ), diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index 63716236..c92c1ebc 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -66,7 +66,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -79,7 +79,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = top_led; assign tm_digit = top_digit; @@ -88,7 +88,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = KEY [w_key - 1]; - assign top_key = KEY [w_key - 1:0]; + assign lab_key = KEY [w_key - 1:0]; assign LED = top_led; @@ -121,7 +121,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), .led ( top_led ), diff --git a/boards/omdazz/board_specific_top.sv b/boards/omdazz/board_specific_top.sv index 4d4abd0b..3deb00cb 100644 --- a/boards/omdazz/board_specific_top.sv +++ b/boards/omdazz/board_specific_top.sv @@ -60,7 +60,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -102,7 +102,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/omdazz_pmod_mic3/board_specific_top.sv b/boards/omdazz_pmod_mic3/board_specific_top.sv index cfc7aafd..4f37f1e0 100644 --- a/boards/omdazz_pmod_mic3/board_specific_top.sv +++ b/boards/omdazz_pmod_mic3/board_specific_top.sv @@ -60,7 +60,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -102,7 +102,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index 00fc36bb..18fca5ce 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -66,7 +66,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -79,7 +79,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = top_led; assign tm_digit = top_digit; @@ -87,7 +87,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign LED = ~ top_led; @@ -120,7 +120,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), .led ( top_led ), diff --git a/boards/piswords6/board_specific_top.sv b/boards/piswords6/board_specific_top.sv index fb416b90..c72ea8d7 100644 --- a/boards/piswords6/board_specific_top.sv +++ b/boards/piswords6/board_specific_top.sv @@ -36,7 +36,7 @@ module board_specific_top localparam w_lab_key = w_key - 1; // One key is used as a reset wire rst = ~ KEY [w_lab_key]; - wire [w_lab_key - 1:0] top_key = ~ KEY [w_lab_key - 1:0]; + wire [w_lab_key - 1:0] lab_key = ~ KEY [w_lab_key - 1:0]; //------------------------------------------------------------------------ @@ -75,7 +75,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ~ SW ), .led ( led ), diff --git a/boards/rzrd/board_specific_top.sv b/boards/rzrd/board_specific_top.sv index 4d4abd0b..3deb00cb 100644 --- a/boards/rzrd/board_specific_top.sv +++ b/boards/rzrd/board_specific_top.sv @@ -60,7 +60,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -102,7 +102,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/rzrd_pmod_mic3/board_specific_top.sv b/boards/rzrd_pmod_mic3/board_specific_top.sv index cfc7aafd..4f37f1e0 100644 --- a/boards/rzrd_pmod_mic3/board_specific_top.sv +++ b/boards/rzrd_pmod_mic3/board_specific_top.sv @@ -60,7 +60,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ KEY; + wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -102,7 +102,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/step_max10/board_specific_top.sv b/boards/step_max10/board_specific_top.sv index 511504eb..9c960ef7 100644 --- a/boards/step_max10/board_specific_top.sv +++ b/boards/step_max10/board_specific_top.sv @@ -30,7 +30,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] top_key = ~ BTN; + wire [w_key - 1:0] lab_key = ~ BTN; //------------------------------------------------------------------------ @@ -56,7 +56,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( WAT_LED ), diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index 2f16d290..84f039f8 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -57,7 +57,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -77,7 +77,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = top_led; assign tm_digit = top_digit; @@ -85,7 +85,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign LED = ~ top_led; @@ -115,7 +115,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index f93d08d7..79de16c7 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -63,7 +63,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -76,7 +76,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = top_led; assign tm_digit = top_digit; @@ -84,7 +84,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign LED = ~ top_led; @@ -114,7 +114,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), .led ( top_led ), diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index b110320c..489b8b6a 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -66,7 +66,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -79,7 +79,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = top_led; assign tm_digit = top_digit; @@ -87,7 +87,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign LED = ~ top_led; @@ -117,7 +117,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), .led ( top_led ), diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index d022b433..e17c32ff 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -81,7 +81,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -110,7 +110,7 @@ module board_specific_top `else assign rst = tm_key [w_tm_key - 1]; `endif - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = top_led; assign tm_digit = top_digit; @@ -122,7 +122,7 @@ module board_specific_top `else assign rst = ~KEY[w_key - 1]; `endif - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign LED = ~ top_led; @@ -167,7 +167,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ), .led ( top_led ), diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index 2b857d4f..74c611ca 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -105,7 +105,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -120,7 +120,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = top_led; assign tm_digit = top_digit; @@ -130,7 +130,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign LED = ~ top_led; @@ -166,8 +166,8 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), - .sw ( top_key ), + .key ( lab_key ), + .sw ( lab_key ), .led ( top_led ), diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index 8017429c..c9bb1334 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -59,7 +59,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] top_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -80,7 +80,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign top_sw = ~ SW; assign tm_led = top_led; @@ -89,7 +89,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign top_sw = ~ SW; assign LED = ~ top_led; @@ -120,7 +120,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 413dc4ce..c8b2c780 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -94,7 +94,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] top_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -139,7 +139,7 @@ module board_specific_top `else assign rst = tm_key [w_tm_key - 1]; `endif - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign top_sw = ~ SW; assign tm_led = top_led; @@ -152,7 +152,7 @@ module board_specific_top `else assign rst = ~KEY[w_key - 1]; `endif - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign top_sw = ~ SW; assign LED = ~ top_led; @@ -194,7 +194,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index 274b8394..315a8dff 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -62,7 +62,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] top_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -83,7 +83,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign top_sw = ~ SW; assign tm_led = top_led; @@ -92,7 +92,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign top_sw = ~ SW; assign LED = ~ top_led; @@ -123,7 +123,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 7be8c0c8..b53ce1d4 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -61,7 +61,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] top_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -82,7 +82,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign top_sw = ~ SW; assign tm_led = top_led; @@ -91,7 +91,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign top_sw = ~ SW; assign LED = ~ top_led; @@ -122,7 +122,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index d922cd10..33c42fbb 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -61,7 +61,7 @@ module board_specific_top wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; - logic [w_lab_key - 1:0] top_key; + logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] top_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -82,7 +82,7 @@ module board_specific_top `ifdef ENABLE_TM1638 // TM1638 module is connected assign rst = tm_key [w_tm_key - 1]; - assign top_key = tm_key [w_tm_key - 1:0]; + assign lab_key = tm_key [w_tm_key - 1:0]; assign top_sw = ~ SW; assign tm_led = top_led; @@ -91,7 +91,7 @@ module board_specific_top `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; - assign top_key = ~ KEY [w_key - 1:0]; + assign lab_key = ~ KEY [w_key - 1:0]; assign top_sw = ~ SW; assign LED = ~ top_led; @@ -122,7 +122,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( top_sw ), .led ( top_led ), diff --git a/boards/zeowaa/board_specific_top.sv b/boards/zeowaa/board_specific_top.sv index f769d2bc..aba5c008 100644 --- a/boards/zeowaa/board_specific_top.sv +++ b/boards/zeowaa/board_specific_top.sv @@ -35,7 +35,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ KEY_N [w_key - 1]; - wire [w_lab_key - 1:0] top_key = ~ KEY_N [w_lab_key - 1:0]; + wire [w_lab_key - 1:0] lab_key = ~ KEY_N [w_lab_key - 1:0]; //------------------------------------------------------------------------ @@ -78,7 +78,7 @@ module board_specific_top .slow_clk ( slow_clk ), .rst ( rst ), - .key ( top_key ), + .key ( lab_key ), .sw ( ~ SW_N ), .led ( led ), From bf179fb24dd259f821ffa767fd0af08248db73f1 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 14:51:27 -0700 Subject: [PATCH 13/65] More renaming top -> lab_sw --- boards/arty_a7/board_specific_top.sv | 4 ++-- boards/arty_a7_pmod_mic3/board_specific_top.sv | 4 ++-- boards/basys3/board_specific_top.sv | 2 +- boards/c5gx_audio/board_specific_top.sv | 4 ++-- boards/c5gx_vga666/board_specific_top.sv | 4 ++-- boards/c5gx_vga_pmod/board_specific_top.sv | 4 ++-- boards/de0/board_specific_top.sv | 4 ++-- boards/de0_nano_soc_vga666/board_specific_top.sv | 4 ++-- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 4 ++-- boards/de0_nano_vga666/board_specific_top.sv | 4 ++-- boards/de0_nano_vga_pmod/board_specific_top.sv | 4 ++-- boards/de1/board_specific_top.sv | 4 ++-- boards/de10_lite/board_specific_top.sv | 4 ++-- boards/de10_lite_tm1638_arduino/board_specific_top.sv | 4 ++-- boards/de10_nano_vga666/board_specific_top.sv | 4 ++-- boards/de10_nano_vga_mister/board_specific_top.sv | 4 ++-- boards/de10_nano_vga_pmod/board_specific_top.sv | 4 ++-- boards/de1_soc/board_specific_top.sv | 4 ++-- boards/de2/board_specific_top.sv | 4 ++-- boards/de2_115/board_specific_top.sv | 4 ++-- boards/emooc_cc/board_specific_top.sv | 6 +++--- boards/omdazz/board_specific_top.sv | 4 ++-- boards/omdazz_pmod_mic3/board_specific_top.sv | 4 ++-- boards/rzrd/board_specific_top.sv | 4 ++-- boards/rzrd_pmod_mic3/board_specific_top.sv | 4 ++-- boards/step_max10/board_specific_top.sv | 4 ++-- boards/tang_nano_20k/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock/board_specific_top.sv | 8 ++++---- boards/tang_primer_20k_dock_alt/board_specific_top.sv | 8 ++++---- .../board_specific_top.sv | 8 ++++---- .../tang_primer_20k_dock_no_tm1638/board_specific_top.sv | 8 ++++---- boards/tang_primer_20k_lite/board_specific_top.sv | 8 ++++---- 32 files changed, 73 insertions(+), 73 deletions(-) diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index 5c1eb0f8..deea5b22 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -84,7 +84,7 @@ module board_specific_top //------------------------------------------------------------------------ wire [ 3:0] KEY = { BTN_3, BTN_2, BTN_1, BTN_0 }; - wire [ w_sw - 1:0] top_sw = SW [w_sw - 1:0]; + wire [ w_sw - 1:0] lab_sw = SW [w_sw - 1:0]; localparam w_tm_key = 8, w_tm_led = 8, @@ -171,7 +171,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index c4b41e6f..448b1e22 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -84,7 +84,7 @@ module board_specific_top //------------------------------------------------------------------------ wire [ 3:0] KEY = { BTN_3, BTN_2, BTN_1, BTN_0 }; - wire [ w_sw - 1:0] top_sw = SW [w_sw - 1:0]; + wire [ w_sw - 1:0] lab_sw = SW [w_sw - 1:0]; localparam w_tm_key = 8, w_tm_led = 8, @@ -171,7 +171,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/basys3/board_specific_top.sv b/boards/basys3/board_specific_top.sv index 5737811f..e4e7012b 100644 --- a/boards/basys3/board_specific_top.sv +++ b/boards/basys3/board_specific_top.sv @@ -45,7 +45,7 @@ module board_specific_top localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset wire rst = sw [w_sw - 1]; - wire [w_lab_sw - 1:0] top_sw = sw [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = sw [w_lab_sw - 1:0]; // FIXME: Should be assigned to some GPIO! wire UART_RX = '1; diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index 240e4d09..40abc242 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -38,7 +38,7 @@ module board_specific_top wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -78,7 +78,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index 51cc71ba..32392588 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -38,7 +38,7 @@ module board_specific_top wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -80,7 +80,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index 0329a539..4dd40b46 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -38,7 +38,7 @@ module board_specific_top wire clk = CLOCK_50_B8A; wire rst = ~ CPU_RESET_n; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -72,7 +72,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index 6d736dd8..d7096468 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -43,7 +43,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ BUTTON; //------------------------------------------------------------------------ @@ -83,7 +83,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( LEDG ), diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index 4299a8e9..84b6dddb 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -33,7 +33,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -138,7 +138,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 85a60c7f..be2a18f0 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -33,7 +33,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -130,7 +130,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index bc336ec2..c00bbab1 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -32,7 +32,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -137,7 +137,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 50d1bd00..7ee0ad62 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -32,7 +32,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -137,7 +137,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index 2ea0f088..9ae0b167 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -81,7 +81,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index b55363ef..d4f37091 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -40,7 +40,7 @@ module board_specific_top wire clk = MAX10_CLK1_50; wire rst = SW [w_sw - 1]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -80,7 +80,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( LEDR ), diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 69c07176..1d3f6210 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top wire clk = MAX10_CLK1_50; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; assign ARDUINO_RESET_N = ~ rst; @@ -153,7 +153,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index e8d35da7..c921b3f0 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -38,7 +38,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; `endif - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -136,7 +136,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index c28d54c0..62828e04 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -38,7 +38,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; `endif - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -143,7 +143,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index 074dcad1..7f4076cd 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -38,7 +38,7 @@ module board_specific_top wire rst = SW [w_lab_sw]; `endif - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; //------------------------------------------------------------------------ @@ -136,7 +136,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index 9e2ecdbb..204e5328 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -87,7 +87,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index 7963c929..17285077 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -52,7 +52,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -91,7 +91,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index 534c29f2..bbd7e40d 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -70,7 +70,7 @@ module board_specific_top wire clk = CLOCK_50; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; wire [w_lab_led - 1:0] top_led; @@ -105,7 +105,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/emooc_cc/board_specific_top.sv b/boards/emooc_cc/board_specific_top.sv index 34fccc51..5cb63c79 100644 --- a/boards/emooc_cc/board_specific_top.sv +++ b/boards/emooc_cc/board_specific_top.sv @@ -51,9 +51,9 @@ module board_specific_top w_lab_sw = w_sw - 1; // one switch is used as reset, others - as input signals; - // for convenience, declare set of wires "top_sw" + // for convenience, declare set of wires "lab_sw" wire rst = SW [w_sw - 1]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; // need explicit wire to be able to invert wire [ 7:0] abcdefgh; @@ -93,7 +93,7 @@ module board_specific_top .rst ( rst ), .key ( ~ KEY_N ), // invert keys, bringing to standard - .sw ( top_sw ), + .sw ( lab_sw ), .led ( LED ), diff --git a/boards/omdazz/board_specific_top.sv b/boards/omdazz/board_specific_top.sv index 3deb00cb..21a430b7 100644 --- a/boards/omdazz/board_specific_top.sv +++ b/boards/omdazz/board_specific_top.sv @@ -59,7 +59,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; - wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; + wire [w_sw - 1:0] lab_sw = ~ KEY [w_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -103,7 +103,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/omdazz_pmod_mic3/board_specific_top.sv b/boards/omdazz_pmod_mic3/board_specific_top.sv index 4f37f1e0..3d971f74 100644 --- a/boards/omdazz_pmod_mic3/board_specific_top.sv +++ b/boards/omdazz_pmod_mic3/board_specific_top.sv @@ -59,7 +59,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; - wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; + wire [w_sw - 1:0] lab_sw = ~ KEY [w_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -103,7 +103,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/rzrd/board_specific_top.sv b/boards/rzrd/board_specific_top.sv index 3deb00cb..21a430b7 100644 --- a/boards/rzrd/board_specific_top.sv +++ b/boards/rzrd/board_specific_top.sv @@ -59,7 +59,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; - wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; + wire [w_sw - 1:0] lab_sw = ~ KEY [w_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -103,7 +103,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/rzrd_pmod_mic3/board_specific_top.sv b/boards/rzrd_pmod_mic3/board_specific_top.sv index 4f37f1e0..3d971f74 100644 --- a/boards/rzrd_pmod_mic3/board_specific_top.sv +++ b/boards/rzrd_pmod_mic3/board_specific_top.sv @@ -59,7 +59,7 @@ module board_specific_top wire clk = CLK; wire rst = ~ RESET; - wire [w_sw - 1:0] top_sw = ~ KEY [w_sw - 1:0]; + wire [w_sw - 1:0] lab_sw = ~ KEY [w_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ @@ -103,7 +103,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/step_max10/board_specific_top.sv b/boards/step_max10/board_specific_top.sv index 9c960ef7..5c401fda 100644 --- a/boards/step_max10/board_specific_top.sv +++ b/boards/step_max10/board_specific_top.sv @@ -29,7 +29,7 @@ module board_specific_top wire clk = clk_in; wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] top_sw = SW [w_lab_sw - 1:0]; + wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ BTN; //------------------------------------------------------------------------ @@ -57,7 +57,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( WAT_LED ), diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index 84f039f8..15ecc860 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -116,7 +116,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index c9bb1334..4fa8908b 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -60,7 +60,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - logic [w_lab_sw - 1:0] top_sw; + logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -81,7 +81,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign tm_led = top_led; assign tm_digit = top_digit; @@ -90,7 +90,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign LED = ~ top_led; @@ -121,7 +121,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index c8b2c780..6323fbb3 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -95,7 +95,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - logic [w_lab_sw - 1:0] top_sw; + logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -140,7 +140,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; `endif assign lab_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign tm_led = top_led; assign tm_digit = top_digit; @@ -153,7 +153,7 @@ module board_specific_top assign rst = ~KEY[w_key - 1]; `endif assign lab_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign LED = ~ top_led; @@ -195,7 +195,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index 315a8dff..f14fbab6 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -63,7 +63,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - logic [w_lab_sw - 1:0] top_sw; + logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -84,7 +84,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign tm_led = top_led; assign tm_digit = top_digit; @@ -93,7 +93,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign LED = ~ top_led; @@ -124,7 +124,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index b53ce1d4..68c33afe 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -62,7 +62,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - logic [w_lab_sw - 1:0] top_sw; + logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -83,7 +83,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign tm_led = top_led; assign tm_digit = top_digit; @@ -92,7 +92,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign LED = ~ top_led; @@ -123,7 +123,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index 33c42fbb..0a482f5e 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -62,7 +62,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - logic [w_lab_sw - 1:0] top_sw; + logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] top_led; wire [w_lab_digit - 1:0] top_digit; @@ -83,7 +83,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign tm_led = top_led; assign tm_digit = top_digit; @@ -92,7 +92,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign top_sw = ~ SW; + assign lab_sw = ~ SW; assign LED = ~ top_led; @@ -123,7 +123,7 @@ module board_specific_top .rst ( rst ), .key ( lab_key ), - .sw ( top_sw ), + .sw ( lab_sw ), .led ( top_led ), From 48e8acee7da870a217550e297a64a2e84909e179 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 14:52:42 -0700 Subject: [PATCH 14/65] More renaming top -> lab_led --- boards/arty_a7/board_specific_top.sv | 12 ++++++------ boards/arty_a7_pmod_mic3/board_specific_top.sv | 12 ++++++------ boards/c5gx_audio/board_specific_top.sv | 6 +++--- boards/c5gx_vga666/board_specific_top.sv | 6 +++--- boards/c5gx_vga_pmod/board_specific_top.sv | 6 +++--- boards/de0_cv/board_specific_top.sv | 6 +++--- boards/de0_nano_soc_vga666/board_specific_top.sv | 12 ++++++------ boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 12 ++++++------ boards/de0_nano_vga666/board_specific_top.sv | 12 ++++++------ boards/de0_nano_vga_pmod/board_specific_top.sv | 12 ++++++------ boards/de1/board_specific_top.sv | 6 +++--- .../de10_lite_tm1638_arduino/board_specific_top.sv | 12 ++++++------ boards/de10_nano_vga666/board_specific_top.sv | 12 ++++++------ boards/de10_nano_vga_mister/board_specific_top.sv | 12 ++++++------ boards/de10_nano_vga_pmod/board_specific_top.sv | 12 ++++++------ boards/de1_soc/board_specific_top.sv | 6 +++--- boards/de2/board_specific_top.sv | 6 +++--- boards/de2_115/board_specific_top.sv | 6 +++--- boards/ice40hx8k_evb_yosys/board_specific_top.sv | 8 ++++---- boards/karnix_ecp5_yosys/board_specific_top.sv | 10 +++++----- boards/omdazz/board_specific_top.sv | 6 +++--- boards/omdazz_pmod_mic3/board_specific_top.sv | 6 +++--- boards/orangecrab_ecp5_yosys/board_specific_top.sv | 8 ++++---- boards/rzrd/board_specific_top.sv | 6 +++--- boards/rzrd_pmod_mic3/board_specific_top.sv | 6 +++--- boards/tang_nano_20k/board_specific_top.sv | 8 ++++---- boards/tang_nano_9k/board_specific_top.sv | 8 ++++---- .../tang_nano_9k_gowin_yosys/board_specific_top.sv | 8 ++++---- boards/tang_nano_9k_hdmi/board_specific_top.sv | 8 ++++---- boards/tang_nano_9k_lcd/board_specific_top.sv | 10 +++++----- boards/tang_primer_20k_dock/board_specific_top.sv | 8 ++++---- .../tang_primer_20k_dock_alt/board_specific_top.sv | 8 ++++---- .../board_specific_top.sv | 8 ++++---- .../board_specific_top.sv | 8 ++++---- boards/tang_primer_20k_lite/board_specific_top.sv | 8 ++++---- 35 files changed, 150 insertions(+), 150 deletions(-) diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index deea5b22..2b162cda 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -109,7 +109,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; @@ -119,14 +119,14 @@ module board_specific_top assign lab_key = { tm_key, KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -139,8 +139,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -173,7 +173,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index 448b1e22..026588df 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -109,7 +109,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; @@ -119,14 +119,14 @@ module board_specific_top assign lab_key = { tm_key, KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -139,8 +139,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -173,7 +173,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index 40abc242..3f5990b0 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -43,7 +43,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -80,7 +80,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -103,7 +103,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // The last 4 LEDR are used like a 7SEG dp + assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // The last 4 LEDR are used like a 7SEG dp //------------------------------------------------------------------------ diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index 32392588..a8b1e0ba 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -43,7 +43,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -82,7 +82,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -103,7 +103,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // The last 4 LEDR are used like a 7SEG dp + assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // The last 4 LEDR are used like a 7SEG dp logic [ 3:0] reg_vga_r, reg_vga_g, reg_vga_b; logic reg_vga_vs, reg_vga_hs; diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index 4dd40b46..7c8d99e0 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -43,7 +43,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -74,7 +74,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -95,7 +95,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // The last 4 LEDR are used like a 7SEG dp + assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // The last 4 LEDR are used like a 7SEG dp logic [ 3:0] reg_vga_r, reg_vga_g, reg_vga_b; logic reg_vga_vs, reg_vga_hs; diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index 24bcab90..63ae1e25 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [w_led - w_digit - 1:0] top_led; + wire [w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -82,7 +82,7 @@ module board_specific_top .key ( lab_key ), .sw ( SW ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -105,7 +105,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LEDR [w_led - w_digit - 1:0] = top_led; // The last 6 LEDR are used like a 7SEG dp + assign LEDR [w_led - w_digit - 1:0] = lab_led; // The last 6 LEDR are used like a 7SEG dp //------------------------------------------------------------------------ diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index 84b6dddb..3b209b75 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -77,7 +77,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -86,14 +86,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -106,8 +106,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -140,7 +140,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index be2a18f0..8b1b3395 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -77,7 +77,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -86,14 +86,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -106,8 +106,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -132,7 +132,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index c00bbab1..0a161f1e 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -76,7 +76,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -85,14 +85,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -105,8 +105,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -139,7 +139,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 7ee0ad62..0c8f3cf9 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -76,7 +76,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -85,14 +85,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -105,8 +105,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -139,7 +139,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index 9ae0b167..adce1b74 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -48,7 +48,7 @@ module board_specific_top wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -83,7 +83,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -106,7 +106,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // The last 4 LEDR are used like a 7SEG dp + assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // The last 4 LEDR are used like a 7SEG dp //------------------------------------------------------------------------ diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 1d3f6210..de167531 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -88,7 +88,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -97,14 +97,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LEDR } = top_led; + assign { tm_led , LEDR } = lab_led; assign { tm_digit , digit } = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; - assign { LEDR , tm_led } = top_led; + assign { LEDR , tm_led } = lab_led; assign { digit , tm_digit } = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -117,8 +117,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LEDR = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LEDR = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign digit = top_digit [w_digit - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -155,7 +155,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index c921b3f0..eaa73021 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -82,7 +82,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -91,14 +91,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -111,8 +111,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -138,7 +138,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index 62828e04..acb5861f 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -82,7 +82,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -91,14 +91,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -111,8 +111,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -145,7 +145,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index 7f4076cd..511c1f90 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -82,7 +82,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; //------------------------------------------------------------------------ @@ -91,14 +91,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; - assign { tm_led , LED } = top_led; + assign { tm_led , LED } = lab_led; assign tm_digit = top_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; - assign { LED , tm_led } = top_led; + assign { LED , tm_led } = lab_led; assign tm_digit = top_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -111,8 +111,8 @@ module board_specific_top lab_key [w_tm_key - 1:0] |= tm_key; end - assign LED = top_led [w_led - 1:0]; - assign tm_led = top_led [w_tm_led - 1:0]; + assign LED = lab_led [w_led - 1:0]; + assign tm_led = lab_led [w_tm_led - 1:0]; assign tm_digit = top_digit [w_tm_digit - 1:0]; @@ -138,7 +138,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index 204e5328..ed6ea44f 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -49,7 +49,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [w_led - w_digit - 1:0] top_led; + wire [w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -89,7 +89,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -109,7 +109,7 @@ module board_specific_top ); //------------------------------------------------------------------------ - assign LEDR [w_led - w_digit - 1:0] = top_led; // The last 6 LEDR are used like a 7SEG dp + assign LEDR [w_led - w_digit - 1:0] = lab_led; // The last 6 LEDR are used like a 7SEG dp assign VGA_R = { vga_red_4b, 4'd0 }; assign VGA_G = { vga_green_4b, 4'd0 }; diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index 17285077..045c9004 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -56,7 +56,7 @@ module board_specific_top wire [w_key - 1:0] lab_key = ~ KEY; //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] top_led; + wire [ w_led - w_digit - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [ w_digit - 1:0] digit; @@ -93,7 +93,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -116,7 +116,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = top_led; // Last 8 LEDR are used like a 7SEG dp + assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // Last 8 LEDR are used like a 7SEG dp assign VGA_R = { vga_red_4b, 4'd0 }; assign VGA_G = { vga_green_4b, 4'd0 }; diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index bbd7e40d..bbf3da6a 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -72,7 +72,7 @@ module board_specific_top wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; wire [w_key - 1:0] lab_key = ~ KEY; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -107,7 +107,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -130,7 +130,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LEDR [w_led - w_digit - 1:0] = top_led; // The last 8 LEDR are used like a 7SEG dp + assign LEDR [w_led - w_digit - 1:0] = lab_led; // The last 8 LEDR are used like a 7SEG dp assign VGA_R = { vga_red_4b, 4'd0 }; assign VGA_G = { vga_green_4b, 4'd0 }; diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 00aa7d57..9d004427 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -78,7 +78,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -86,7 +86,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -120,7 +120,7 @@ module board_specific_top .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index c92c1ebc..88fb3fd2 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -67,7 +67,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -81,16 +81,16 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; - assign LED = top_led; + assign LED = lab_led; `else // TM1638 module is not connected assign rst = KEY [w_key - 1]; assign lab_key = KEY [w_key - 1:0]; - assign LED = top_led; + assign LED = lab_led; `endif @@ -124,7 +124,7 @@ module board_specific_top .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/omdazz/board_specific_top.sv b/boards/omdazz/board_specific_top.sv index 21a430b7..fea64299 100644 --- a/boards/omdazz/board_specific_top.sv +++ b/boards/omdazz/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [w_led - 1:0] top_led; + wire [w_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -105,7 +105,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -132,7 +132,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LED = ~ top_led; + assign LED = ~ lab_led; assign SEG = ~ abcdefgh; assign DIG = ~ digit; diff --git a/boards/omdazz_pmod_mic3/board_specific_top.sv b/boards/omdazz_pmod_mic3/board_specific_top.sv index 3d971f74..8676dd50 100644 --- a/boards/omdazz_pmod_mic3/board_specific_top.sv +++ b/boards/omdazz_pmod_mic3/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [w_led - 1:0] top_led; + wire [w_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -105,7 +105,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -132,7 +132,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LED = ~ top_led; + assign LED = ~ lab_led; assign SEG = ~ abcdefgh; assign DIG = ~ digit; diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index 18fca5ce..bbfd09c6 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -67,7 +67,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -81,7 +81,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -89,7 +89,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -123,7 +123,7 @@ module board_specific_top .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/rzrd/board_specific_top.sv b/boards/rzrd/board_specific_top.sv index 21a430b7..fea64299 100644 --- a/boards/rzrd/board_specific_top.sv +++ b/boards/rzrd/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [w_led - 1:0] top_led; + wire [w_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -105,7 +105,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -132,7 +132,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LED = ~ top_led; + assign LED = ~ lab_led; assign SEG = ~ abcdefgh; assign DIG = ~ digit; diff --git a/boards/rzrd_pmod_mic3/board_specific_top.sv b/boards/rzrd_pmod_mic3/board_specific_top.sv index 3d971f74..8676dd50 100644 --- a/boards/rzrd_pmod_mic3/board_specific_top.sv +++ b/boards/rzrd_pmod_mic3/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top //------------------------------------------------------------------------ - wire [w_led - 1:0] top_led; + wire [w_led - 1:0] lab_led; wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; @@ -105,7 +105,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -132,7 +132,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LED = ~ top_led; + assign LED = ~ lab_led; assign SEG = ~ abcdefgh; assign DIG = ~ digit; diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index 15ecc860..01dec717 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -58,7 +58,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -79,7 +79,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -87,7 +87,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -118,7 +118,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index 79de16c7..45740a28 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -78,7 +78,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -86,7 +86,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -117,7 +117,7 @@ module board_specific_top .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index 489b8b6a..f8f1d658 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -67,7 +67,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -81,7 +81,7 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -89,7 +89,7 @@ module board_specific_top assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -120,7 +120,7 @@ module board_specific_top .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index e17c32ff..2ff99a1d 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -82,7 +82,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -112,7 +112,7 @@ module board_specific_top `endif assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -124,7 +124,7 @@ module board_specific_top `endif assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -170,7 +170,7 @@ module board_specific_top .key ( lab_key ), .sw ( ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index 74c611ca..e1b748e3 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -106,7 +106,7 @@ module board_specific_top wire [w_tm_digit - 1:0] tm_digit; logic [w_lab_key - 1:0] lab_key; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -122,17 +122,17 @@ module board_specific_top assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; - assign LED = w_led' (~ top_led); + assign LED = w_led' (~ lab_led); `else // TM1638 module is not connected assign rst = ~ KEY [w_key - 1]; assign lab_key = ~ KEY [w_key - 1:0]; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -169,7 +169,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_key ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index 4fa8908b..10a8b746 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -61,7 +61,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -83,7 +83,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign lab_sw = ~ SW; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -92,7 +92,7 @@ module board_specific_top assign lab_key = ~ KEY [w_key - 1:0]; assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -123,7 +123,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 6323fbb3..c509957e 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -96,7 +96,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -142,7 +142,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign lab_sw = ~ SW; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -155,7 +155,7 @@ module board_specific_top assign lab_key = ~ KEY [w_key - 1:0]; assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -197,7 +197,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index f14fbab6..f6b43c98 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -86,7 +86,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign lab_sw = ~ SW; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -95,7 +95,7 @@ module board_specific_top assign lab_key = ~ KEY [w_key - 1:0]; assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -126,7 +126,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 68c33afe..7f4413a7 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -63,7 +63,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -85,7 +85,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign lab_sw = ~ SW; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -94,7 +94,7 @@ module board_specific_top assign lab_key = ~ KEY [w_key - 1:0]; assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -125,7 +125,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index 0a482f5e..aa0b4baf 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -63,7 +63,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; - wire [w_lab_led - 1:0] top_led; + wire [w_lab_led - 1:0] lab_led; wire [w_lab_digit - 1:0] top_digit; wire rst; @@ -85,7 +85,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign lab_sw = ~ SW; - assign tm_led = top_led; + assign tm_led = lab_led; assign tm_digit = top_digit; `else // TM1638 module is not connected @@ -94,7 +94,7 @@ module board_specific_top assign lab_key = ~ KEY [w_key - 1:0]; assign lab_sw = ~ SW; - assign LED = ~ top_led; + assign LED = ~ lab_led; `endif @@ -125,7 +125,7 @@ module board_specific_top .key ( lab_key ), .sw ( lab_sw ), - .led ( top_led ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( top_digit ), From 30663c1cd8446342a60b3d9ba6be2134aba6014f Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 14:53:53 -0700 Subject: [PATCH 15/65] More renaming top -> lab_digit --- boards/arty_a7/board_specific_top.sv | 10 +++++----- boards/arty_a7_pmod_mic3/board_specific_top.sv | 10 +++++----- boards/de0_nano_soc_vga666/board_specific_top.sv | 10 +++++----- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 10 +++++----- boards/de0_nano_vga666/board_specific_top.sv | 10 +++++----- boards/de0_nano_vga_pmod/board_specific_top.sv | 10 +++++----- .../de10_lite_tm1638_arduino/board_specific_top.sv | 12 ++++++------ boards/de10_nano_vga666/board_specific_top.sv | 10 +++++----- boards/de10_nano_vga_mister/board_specific_top.sv | 10 +++++----- boards/de10_nano_vga_pmod/board_specific_top.sv | 10 +++++----- boards/ice40hx8k_evb_yosys/board_specific_top.sv | 6 +++--- boards/karnix_ecp5_yosys/board_specific_top.sv | 6 +++--- boards/orangecrab_ecp5_yosys/board_specific_top.sv | 6 +++--- boards/tang_nano_20k/board_specific_top.sv | 6 +++--- boards/tang_nano_9k/board_specific_top.sv | 6 +++--- .../tang_nano_9k_gowin_yosys/board_specific_top.sv | 6 +++--- boards/tang_nano_9k_hdmi/board_specific_top.sv | 6 +++--- boards/tang_nano_9k_lcd/board_specific_top.sv | 6 +++--- boards/tang_primer_20k_dock/board_specific_top.sv | 6 +++--- .../tang_primer_20k_dock_alt/board_specific_top.sv | 6 +++--- .../board_specific_top.sv | 6 +++--- .../board_specific_top.sv | 6 +++--- boards/tang_primer_20k_lite/board_specific_top.sv | 6 +++--- boards/zeowaa_wo_dig_0/board_specific_top.sv | 8 ++++---- 24 files changed, 94 insertions(+), 94 deletions(-) diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index 2b162cda..da8ca171 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -110,7 +110,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -120,14 +120,14 @@ module board_specific_top assign lab_key = { tm_key, KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -142,7 +142,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -176,7 +176,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( JC [1] ), .hsync ( JC [0] ), diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index 026588df..75ec8dd2 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -110,7 +110,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -120,14 +120,14 @@ module board_specific_top assign lab_key = { tm_key, KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -142,7 +142,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -176,7 +176,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( JC [1] ), .hsync ( JC [0] ), diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index 3b209b75..0877ea0a 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -78,7 +78,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -87,14 +87,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -109,7 +109,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -143,7 +143,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 8b1b3395..3fa8d7bb 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -78,7 +78,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -87,14 +87,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -109,7 +109,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -135,7 +135,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 0a161f1e..34ac03e8 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -77,7 +77,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -86,14 +86,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -108,7 +108,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -142,7 +142,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 0c8f3cf9..de84f5da 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -77,7 +77,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -86,14 +86,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -108,7 +108,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -142,7 +142,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index de167531..9bb9ab74 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -89,7 +89,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -98,14 +98,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LEDR } = lab_led; - assign { tm_digit , digit } = top_digit; + assign { tm_digit , digit } = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; assign { LEDR , tm_led } = lab_led; - assign { digit , tm_digit } = top_digit; + assign { digit , tm_digit } = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -120,8 +120,8 @@ module board_specific_top assign LEDR = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign digit = top_digit [w_digit - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign digit = lab_digit [w_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -158,7 +158,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index eaa73021..25f3e907 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -83,7 +83,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -92,14 +92,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -114,7 +114,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -141,7 +141,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index acb5861f..c727752a 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -83,7 +83,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -92,14 +92,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -114,7 +114,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -148,7 +148,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index 511c1f90..d6d9644f 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -83,7 +83,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; //------------------------------------------------------------------------ @@ -92,14 +92,14 @@ module board_specific_top assign lab_key = { tm_key, ~ KEY }; assign { tm_led , LED } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `elsif CONCAT_REGULAR_SIGNALS_AND_TM assign lab_key = { ~ KEY, tm_key }; assign { LED , tm_led } = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR @@ -114,7 +114,7 @@ module board_specific_top assign LED = lab_led [w_led - 1:0]; assign tm_led = lab_led [w_tm_led - 1:0]; - assign tm_digit = top_digit [w_tm_digit - 1:0]; + assign tm_digit = lab_digit [w_tm_digit - 1:0]; `endif @@ -141,7 +141,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vga_vs ), .hsync ( vga_hs ), diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 9d004427..6fca4184 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -65,7 +65,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -79,7 +79,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -123,7 +123,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index 88fb3fd2..7add00e2 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -68,7 +68,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -82,7 +82,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; assign LED = lab_led; `else // TM1638 module is not connected @@ -127,7 +127,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index bbfd09c6..0cd7e75b 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -68,7 +68,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -82,7 +82,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -126,7 +126,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index 01dec717..69100997 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -59,7 +59,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -80,7 +80,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -121,7 +121,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index 45740a28..afc45dab 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -65,7 +65,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -79,7 +79,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -120,7 +120,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index f8f1d658..c5ff8115 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -68,7 +68,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -82,7 +82,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -123,7 +123,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index 2ff99a1d..c3834427 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -83,7 +83,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -113,7 +113,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -173,7 +173,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( vsync ), .hsync ( hsync ), diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index e1b748e3..1a5c211f 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -107,7 +107,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -123,7 +123,7 @@ module board_specific_top assign lab_key = tm_key [w_tm_key - 1:0]; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; assign LED = w_led' (~ lab_led); @@ -172,7 +172,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( LARGE_LCD_VS ), .hsync ( LARGE_LCD_HS ), diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index 10a8b746..09527439 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -62,7 +62,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -84,7 +84,7 @@ module board_specific_top assign lab_sw = ~ SW; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -126,7 +126,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index c509957e..001f87b8 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -97,7 +97,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -143,7 +143,7 @@ module board_specific_top assign lab_sw = ~ SW; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -200,7 +200,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index f6b43c98..f56b063e 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -65,7 +65,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -87,7 +87,7 @@ module board_specific_top assign lab_sw = ~ SW; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -129,7 +129,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 7f4413a7..685ebf9e 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -86,7 +86,7 @@ module board_specific_top assign lab_sw = ~ SW; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -128,7 +128,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index aa0b4baf..17d5c48d 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -64,7 +64,7 @@ module board_specific_top logic [w_lab_key - 1:0] lab_key; logic [w_lab_sw - 1:0] lab_sw; wire [w_lab_led - 1:0] lab_led; - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; wire rst; wire [ 7:0] abcdefgh; @@ -86,7 +86,7 @@ module board_specific_top assign lab_sw = ~ SW; assign tm_led = lab_led; - assign tm_digit = top_digit; + assign tm_digit = lab_digit; `else // TM1638 module is not connected @@ -128,7 +128,7 @@ module board_specific_top .led ( lab_led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), + .digit ( lab_digit ), .vsync ( VGA_VS ), .hsync ( VGA_HS ), diff --git a/boards/zeowaa_wo_dig_0/board_specific_top.sv b/boards/zeowaa_wo_dig_0/board_specific_top.sv index 3b8718fa..df54b45f 100644 --- a/boards/zeowaa_wo_dig_0/board_specific_top.sv +++ b/boards/zeowaa_wo_dig_0/board_specific_top.sv @@ -56,9 +56,9 @@ module board_specific_top // This logic is necessary to compensate the defective board localparam w_lab_digit = w_digit - 1; // The right digit is not working on this board - wire [w_lab_digit - 1:0] top_digit; + wire [w_lab_digit - 1:0] lab_digit; - assign digit = { top_digit, 1'b0 }; + assign digit = { lab_digit, 1'b0 }; //------------------------------------------------------------------------ @@ -75,7 +75,7 @@ module board_specific_top .w_key ( w_key ), .w_sw ( w_sw ), .w_led ( w_led ), - .w_digit ( w_lab_digit ), // Note top_digit, not digit + .w_digit ( w_lab_digit ), // Note lab_digit, not digit .w_gpio ( w_gpio ) ) i_lab_top @@ -90,7 +90,7 @@ module board_specific_top .led ( led ), .abcdefgh ( abcdefgh ), - .digit ( top_digit ), // Note top_digit, not digit + .digit ( lab_digit ), // Note lab_digit, not digit .vsync ( VGA_VSYNC ), .hsync ( VGA_HSYNC ), From 63fbd0f671f36218af43afab9eedb0b761ab827a Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 15:29:11 -0700 Subject: [PATCH 16/65] Incremental editing DE2-115 wrapper --- boards/de2_115/board_specific_top.sv | 133 +++++++++++++++------------ 1 file changed, 76 insertions(+), 57 deletions(-) diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index bbf3da6a..4fd8f1f2 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -32,9 +32,9 @@ module board_specific_top input [w_key - 1:0] KEY, input [w_sw - 1:0] SW, - output [w_led - 1:0] LEDR, // The last 8 LEDR are optionally used to output 7SEG dp + output [w_led - 1:0] LEDR, // The last 8 LEDR are optionally used to output 7SEG dp - output logic [ 6:0] HEX0, // HEX[7] aka dp are not connected to FPGA at DE2-115 + output logic [ 6:0] HEX0, // HEX[7] aka dp are not connected to FPGA at DE2-115 output logic [ 6:0] HEX1, output logic [ 6:0] HEX2, output logic [ 6:0] HEX3, @@ -60,25 +60,40 @@ module board_specific_top localparam w_lab_sw = w_sw - 1; // One sw is used as a reset `ifdef USE_HIGH_LED_FOR_7SEG_DP - localparam w_lab_led = w_led - w_digit; + localparam w_lab_led = w_led - w_digit; `else - localparam w_lab_led = w_led; + localparam w_lab_led = w_led; `endif //------------------------------------------------------------------------ - wire clk = CLOCK_50; - wire rst = SW [w_lab_sw]; + wire clk = CLOCK_50; + wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] lab_key = ~ KEY; - wire [w_lab_led - 1:0] lab_led; + // Keys, switches, LEDs - wire [ 7:0] abcdefgh; - wire [w_digit - 1:0] digit; + wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [ w_key - 1:0] lab_key = ~ KEY; + wire [ w_lab_led - 1:0] lab_led; - wire [ 23:0] mic; - wire [ 15:0] sound; + // A dynamic seven-segment display + + wire [ 7:0] abcdefgh; + wire [ w_digit - 1:0] digit; + + // Graphics + + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; + + wire [ w_red - 1:0] red; + wire [ w_green - 1:0] green; + wire [ w_blue - 1:0] blue; + + // Microphone, sound output and UART + + wire [ 23:0] mic; + wire [ 15:0] sound; //------------------------------------------------------------------------ @@ -91,46 +106,46 @@ module board_specific_top lab_top # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_lab_key ), - .w_sw ( w_lab_sw ), - .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_lab_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), - - .key ( lab_key ), - .sw ( lab_sw ), - - .led ( lab_led ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .abcdefgh ( abcdefgh ), - .digit ( digit ), + .key ( lab_key ), + .sw ( lab_sw ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + .led ( lab_led ), - .red ( VGA_R ), - .green ( vga_green_4b ), - .blue ( vga_blue_4b ), + .abcdefgh ( abcdefgh ), + .digit ( digit ), - .uart_rx ( ), // TODO - .uart_tx ( ), // TODO + .mic ( mic ), + .sound ( sound ), - .mic ( mic ), - .sound ( sound ), + .uart_rx ( ), // TODO + .uart_tx ( ), // TODO - .gpio ( GPIO ) + .gpio ( GPIO ) ); //------------------------------------------------------------------------ - assign LEDR [w_led - w_digit - 1:0] = lab_led; // The last 8 LEDR are used like a 7SEG dp + assign LEDR [w_lab_led:0] = lab_led; assign VGA_R = { vga_red_4b, 4'd0 }; assign VGA_G = { vga_green_4b, 4'd0 }; @@ -171,8 +186,8 @@ module board_specific_top //------------------------------------------------------------------------ - wire [$left (abcdefgh):0] hgfedcba; - logic [$left (digit):0] dp; + wire [$left ( abcdefgh ):0] hgfedcba; + logic [$left ( digit ):0] dp; generate genvar i; @@ -248,7 +263,9 @@ module board_specific_top end end - assign LEDR [w_led - 1:w_led - w_digit] = dp; // The last 8 LEDR are used like a 7SEG dp + `ifdef USE_HIGH_LED_FOR_7SEG_DP + assign LEDR [w_led - 1 : w_lb_led] = dp; + `endif `endif @@ -258,31 +275,33 @@ module board_specific_top ( .clk ( clk ), .rst ( rst ), - .lr ( GPIO [0] ), // JP5 pin 1 - .ws ( GPIO [2] ), // JP5 pin 3 - .sck ( GPIO [4] ), // JP5 pin 5 - .sd ( GPIO [5] ), // JP5 pin 6 + .lr ( GPIO [0] ), + .ws ( GPIO [2] ), + .sck ( GPIO [4] ), + .sd ( GPIO [5] ), .value ( mic ) ); - assign GPIO [1] = 1'b0; // GND - JP5 pin 2 - assign GPIO [3] = 1'b1; // VCC - JP5 pin 4 + assign GPIO [1] = 1'b0; // GND + assign GPIO [3] = 1'b1; // VCC //------------------------------------------------------------------------ i2s_audio_out # ( - .clk_mhz ( clk_mhz ) + .clk_mhz ( clk_mhz ) ) - o_audio + i_audio ( .clk ( clk ), .reset ( rst ), - .data_in ( sound ), // TODO - check all comments with pins - .mclk ( GPIO [33] ), // JP5 pin 38 - .bclk ( GPIO [31] ), // JP5 pin 36 - .lrclk ( GPIO [27] ), // JP5 pin 32 - .sdata ( GPIO [29] ) // JP5 pin 34 - ); // JP5 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + .data_in ( sound ), + .mclk ( GPIO [33] ), + .bclk ( GPIO [31] ), + .lrclk ( GPIO [27] ), + .sdata ( GPIO [29] ) + ); + + // VCC and GND for i2s_audio_out are on dedicated pins endmodule From c6ea880a5d8b926acc03e80f7c15321c64f449ce Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 16:53:05 -0700 Subject: [PATCH 17/65] New graphics draft for DE2-115 --- boards/de2_115/board_specific_top.sv | 95 +++++++++++++--------------- labs/06_graphics/lab_top.sv | 44 ++----------- 2 files changed, 49 insertions(+), 90 deletions(-) diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index 4fd8f1f2..999bb55e 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -122,68 +122,38 @@ module board_specific_top ) i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( lab_key ), - .sw ( lab_sw ), + .key ( lab_key ), + .sw ( lab_sw ), - .led ( lab_led ), + .led ( lab_led ), - .abcdefgh ( abcdefgh ), - .digit ( digit ), + .abcdefgh ( abcdefgh ), + .digit ( digit ), - .mic ( mic ), - .sound ( sound ), + .x ( x ), + .y ( y ), - .uart_rx ( ), // TODO - .uart_tx ( ), // TODO + .red ( VGA_R ), + .green ( VGA_G ), + .blue ( VGA_B ), - .gpio ( GPIO ) + .mic ( mic ), + .sound ( sound ), + + .uart_rx ( ), // TODO + .uart_tx ( ), // TODO + + .gpio ( GPIO ) ); //------------------------------------------------------------------------ assign LEDR [w_lab_led:0] = lab_led; - assign VGA_R = { vga_red_4b, 4'd0 }; - assign VGA_G = { vga_green_4b, 4'd0 }; - assign VGA_B = { vga_blue_4b, 4'd0 }; - - assign VGA_BLANK_N = 1'b1; - assign VGA_SYNC_N = 0; - - // Divide VGA DAC clock from clk_mhz to vga_clock - localparam CLK_DIV = $clog2 (clk_mhz / vga_clock) - 1; - - logic [CLK_DIV:0] clk_en_cnt; - logic clk_en; - - always_ff @ (posedge clk or posedge rst) - begin - if (rst) - begin - clk_en_cnt <= 'b0; - clk_en <= 'b0; - end - else - begin - if (clk_en_cnt == (clk_mhz / vga_clock) - 1) - begin - clk_en_cnt <= 'b0; - clk_en <= 'b1; - end - else - begin - clk_en_cnt <= clk_en_cnt + 1; - clk_en <= 'b0; - end - end - end - - assign VGA_CLK = clk_en; - //------------------------------------------------------------------------ wire [$left ( abcdefgh ):0] hgfedcba; @@ -271,6 +241,31 @@ module board_specific_top //------------------------------------------------------------------------ + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( VGA_CLK ) + ); + + assign VGA_BLANK_N = 1'b1; + assign VGA_SYNC_N = 0; + + //------------------------------------------------------------------------ + inmp441_mic_i2s_receiver i_microphone ( .clk ( clk ), diff --git a/labs/06_graphics/lab_top.sv b/labs/06_graphics/lab_top.sv index 1fa8c6de..85c982a0 100644 --- a/labs/06_graphics/lab_top.sv +++ b/labs/06_graphics/lab_top.sv @@ -62,39 +62,13 @@ module lab_top assign led = '0; assign abcdefgh = '0; assign digit = '0; - // assign vsync = '0; - // assign hsync = '0; // assign red = '0; // assign green = '0; // assign blue = '0; - // assign display_on = '0; - // assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; //------------------------------------------------------------------------ -/* - vga - # ( - .HPOS_WIDTH ( w_x ), - .VPOS_WIDTH ( w_y ), - - .CLK_MHZ ( clk_mhz ), - .PIXEL_MHZ ( pixel_mhz ) - ) - i_vga - ( - .clk ( clk ), - .rst ( rst ), - .hsync ( hsync ), - .vsync ( vsync ), - .display_on ( display_on ), - .hpos ( x ), - .vpos ( y ), - .pixel_clk ( pixel_clk ) - ); -*/ - //------------------------------------------------------------------------ // Pattern 1 /**/ @@ -107,10 +81,7 @@ module lab_top green = '0; blue = '0; - if (~ display_on) - begin - end - else if (x > 100 & y > 100 & x < 150 & y < 400) // Rectangle + if (x > 100 & y > 100 & x < 150 & y < 400) // Rectangle begin red = x [w_x - 2 -: w_red]; green = '1; @@ -176,16 +147,9 @@ module lab_top always_comb begin - red = '0; - green = '0; - blue = '0; - - if (display_on) - begin - red = xc + xc + yc + dx; - green = xc - yc - dy; - blue = { 4 { & key } }; - end + red = xc + xc + yc + dx; + green = xc - yc - dy; + blue = { 4 { & key } }; end */ From b45371ada7507e2b370b5da3190f116ad8508290 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 16:58:58 -0700 Subject: [PATCH 18/65] New graphics draft for DE2-115 - working --- boards/de2_115/board_specific_top.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index 999bb55e..cb77ff1f 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -12,7 +12,7 @@ module board_specific_top w_sw = 18, w_led = 18, w_digit = 8, - w_gpio = 36 + w_gpio = 36, // gpio 0..5 are reserved for INMP 441 I2S microphone. // Odd gpio .. are reserved I2S audio. @@ -152,7 +152,7 @@ module board_specific_top //------------------------------------------------------------------------ - assign LEDR [w_lab_led:0] = lab_led; + assign LEDR [w_lab_led - 1:0] = lab_led; //------------------------------------------------------------------------ @@ -234,7 +234,7 @@ module board_specific_top end `ifdef USE_HIGH_LED_FOR_7SEG_DP - assign LEDR [w_led - 1 : w_lb_led] = dp; + assign LEDR [w_led - 1 : w_lab_led] = dp; `endif `endif From 04e97bd85a78ea69c4a96dd4ae2dbe725c6237e7 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 17:19:18 -0700 Subject: [PATCH 19/65] New graphics draft for DE2-115 - minor --- boards/de2_115/board_specific_top.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index cb77ff1f..fb62e2eb 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -262,7 +262,7 @@ module board_specific_top ); assign VGA_BLANK_N = 1'b1; - assign VGA_SYNC_N = 0; + assign VGA_SYNC_N = 1'b0; //------------------------------------------------------------------------ From 59c175e06b659b0600bac254957880c9888c54df Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Fri, 19 Jul 2024 20:04:10 -0700 Subject: [PATCH 20/65] Added peripherals directory --- .../digilent_pmod_mic3_spi_receiver.sv | 0 {labs/common => peripherals}/i2s_audio_out.sv | 0 {labs/common => peripherals}/inmp441.pdf | Bin .../inmp441_mic_i2s_receiver.sv | 0 .../common => peripherals}/lab_specific_config.svh | 0 {labs/common => peripherals}/pmodmic3_rm.pdf | Bin {labs/common => peripherals}/slow_clk_gen.sv | 0 {labs/common => peripherals}/tm1638_board.sv | 0 {labs/common => peripherals}/vga.sv | 0 scripts/steps/00_setup.source_bash | 1 + scripts/steps/00_setup_gowin.source_bash | 3 +++ scripts/steps/00_setup_intel_fpga.source_bash | 10 ++++++---- scripts/steps/00_setup_yosys.source_bash | 3 ++- scripts/steps/07_synthesize_for_asic.source_bash | 4 +--- 14 files changed, 13 insertions(+), 8 deletions(-) rename {labs/common => peripherals}/digilent_pmod_mic3_spi_receiver.sv (100%) rename {labs/common => peripherals}/i2s_audio_out.sv (100%) rename {labs/common => peripherals}/inmp441.pdf (100%) rename {labs/common => peripherals}/inmp441_mic_i2s_receiver.sv (100%) rename {labs/common => peripherals}/lab_specific_config.svh (100%) rename {labs/common => peripherals}/pmodmic3_rm.pdf (100%) rename {labs/common => peripherals}/slow_clk_gen.sv (100%) rename {labs/common => peripherals}/tm1638_board.sv (100%) rename {labs/common => peripherals}/vga.sv (100%) diff --git a/labs/common/digilent_pmod_mic3_spi_receiver.sv b/peripherals/digilent_pmod_mic3_spi_receiver.sv similarity index 100% rename from labs/common/digilent_pmod_mic3_spi_receiver.sv rename to peripherals/digilent_pmod_mic3_spi_receiver.sv diff --git a/labs/common/i2s_audio_out.sv b/peripherals/i2s_audio_out.sv similarity index 100% rename from labs/common/i2s_audio_out.sv rename to peripherals/i2s_audio_out.sv diff --git a/labs/common/inmp441.pdf b/peripherals/inmp441.pdf similarity index 100% rename from labs/common/inmp441.pdf rename to peripherals/inmp441.pdf diff --git a/labs/common/inmp441_mic_i2s_receiver.sv b/peripherals/inmp441_mic_i2s_receiver.sv similarity index 100% rename from labs/common/inmp441_mic_i2s_receiver.sv rename to peripherals/inmp441_mic_i2s_receiver.sv diff --git a/labs/common/lab_specific_config.svh b/peripherals/lab_specific_config.svh similarity index 100% rename from labs/common/lab_specific_config.svh rename to peripherals/lab_specific_config.svh diff --git a/labs/common/pmodmic3_rm.pdf b/peripherals/pmodmic3_rm.pdf similarity index 100% rename from labs/common/pmodmic3_rm.pdf rename to peripherals/pmodmic3_rm.pdf diff --git a/labs/common/slow_clk_gen.sv b/peripherals/slow_clk_gen.sv similarity index 100% rename from labs/common/slow_clk_gen.sv rename to peripherals/slow_clk_gen.sv diff --git a/labs/common/tm1638_board.sv b/peripherals/tm1638_board.sv similarity index 100% rename from labs/common/tm1638_board.sv rename to peripherals/tm1638_board.sv diff --git a/labs/common/vga.sv b/peripherals/vga.sv similarity index 100% rename from labs/common/vga.sv rename to peripherals/vga.sv diff --git a/scripts/steps/00_setup.source_bash b/scripts/steps/00_setup.source_bash index 63b3d3c5..07ff2c2b 100644 --- a/scripts/steps/00_setup.source_bash +++ b/scripts/steps/00_setup.source_bash @@ -36,6 +36,7 @@ package_dir=$(readlink -f "$(dirname "${BASH_SOURCE[0]}")/../..") bin_dir="$package_dir/bin" board_dir="$package_dir/boards" lab_dir="$package_dir/labs" +peripheral_dir="$package_dir/peripherals" script_dir="$package_dir/scripts" #----------------------------------------------------------------------------- diff --git a/scripts/steps/00_setup_gowin.source_bash b/scripts/steps/00_setup_gowin.source_bash index 5847a944..3e10ce18 100644 --- a/scripts/steps/00_setup_gowin.source_bash +++ b/scripts/steps/00_setup_gowin.source_bash @@ -215,6 +215,7 @@ setup_run_directory_for_fpga_synthesis_gowin () for verilog_src_dir in \ "$main_src_dir" \ "$board_dir/$fpga_board" \ + "$peripheral_dir" \ "$lab_dir/common" do $find_to_run \ @@ -236,6 +237,7 @@ setup_run_directory_for_fpga_synthesis_gowin () for verilog_src_dir in \ "$main_src_dir" \ "$board_dir/$fpga_board" \ + "$peripheral_dir" \ "$lab_dir/common" do $find_to_run \ @@ -263,6 +265,7 @@ setup_run_directory_for_fpga_synthesis_gowin () printf ' \"%s\"\n' "$(adj_path_for_gowin_win "$main_src_dir")" >> "$dir/impl/project_process_config.json" printf ' \"%s\",\n' "$(adj_path_for_gowin_win "$board_dir")/$fpga_board" >> "$dir/impl/project_process_config.json" + printf ' \"%s\",\n' "$(adj_path_for_gowin_win "$peripheral_dir")" >> "$dir/impl/project_process_config.json" printf ' \"%s\",\n' "$(adj_path_for_gowin_win "$lab_dir")/common" >> "$dir/impl/project_process_config.json" cat "$board_dir/$fpga_board/project_process_config_02.json" >> "$dir/impl/project_process_config.json" diff --git a/scripts/steps/00_setup_intel_fpga.source_bash b/scripts/steps/00_setup_intel_fpga.source_bash index 7bac3e63..8581222f 100644 --- a/scripts/steps/00_setup_intel_fpga.source_bash +++ b/scripts/steps/00_setup_intel_fpga.source_bash @@ -408,9 +408,10 @@ setup_run_directory_for_fpga_synthesis_quartus () # because these particular relative paths # are expected to contain only alnums, underscores and slashes. - rel_main_src_dir=$(realpath --relative-to="$dir" "$main_src_dir") - rel_board_dir=$(realpath --relative-to="$dir" "$board_dir") - rel_lab_dir=$(realpath --relative-to="$dir" "$lab_dir") + rel_main_src_dir=$(realpath --relative-to="$dir" "$main_src_dir") + rel_board_dir=$(realpath --relative-to="$dir" "$board_dir") + rel_peripheral_dir=$(realpath --relative-to="$dir" "$peripheral_dir") + rel_lab_dir=$(realpath --relative-to="$dir" "$lab_dir") #------------------------------------------------------------------------- @@ -423,12 +424,13 @@ set_global_assignment -name SDC_FILE $rel_board_dir/$fpga_board/ set_global_assignment -name SEARCH_PATH $rel_main_src_dir set_global_assignment -name SEARCH_PATH $rel_board_dir/$fpga_board +set_global_assignment -name SEARCH_PATH $rel_peripheral_dir set_global_assignment -name SEARCH_PATH $rel_lab_dir/common EOF $find_to_run \ - "$main_src_dir" "$board_dir/$fpga_board" "$lab_dir/common" \ + "$main_src_dir" "$board_dir/$fpga_board" "$peripheral_dir" "$lab_dir/common" \ -type f -name '*.sv' -not -name tb.sv \ -printf "set_global_assignment -name SYSTEMVERILOG_FILE %f\n" \ >> "$dir/fpga_project.qsf" diff --git a/scripts/steps/00_setup_yosys.source_bash b/scripts/steps/00_setup_yosys.source_bash index 9b353198..8e521710 100644 --- a/scripts/steps/00_setup_yosys.source_bash +++ b/scripts/steps/00_setup_yosys.source_bash @@ -93,12 +93,13 @@ setup_run_directory_for_fpga_synthesis_yosys () > "$dir/Makefile" echo "NAME = `basename $main_src_dir`" >> "$dir/Makefile" - echo "INC = $lab_dir/common" >> "$dir/Makefile" + echo "INC = $peripheral_dir;$lab_dir/common" >> "$dir/Makefile" echo "BOARD = $fpga_board" >> "$dir/Makefile" for verilog_src_dir in \ "$main_src_dir" \ "$board_dir/$fpga_board" \ + "$peripheral_dir" \ "$lab_dir/common" do # TODO: Check if we really need adj_path_for_gowin_win here diff --git a/scripts/steps/07_synthesize_for_asic.source_bash b/scripts/steps/07_synthesize_for_asic.source_bash index fd21c53a..8ad40ab6 100644 --- a/scripts/steps/07_synthesize_for_asic.source_bash +++ b/scripts/steps/07_synthesize_for_asic.source_bash @@ -23,11 +23,9 @@ cp "$script_dir/asic/asic_top.sv" "$design_dir/src" for f in \ config.svh \ counter_with_enable.sv \ - lab_specific_config.svh \ seven_segment_display.sv \ shift_reg.sv \ - strobe_gen.sv \ - vga.sv + strobe_gen.sv do cp -f "$lab_dir/common/$f" "$design_dir/src" done From c7dca688f6a814c5099c927a23c1324dec2576ce Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 08:33:12 -0700 Subject: [PATCH 21/65] Renaming for clarity --- .../{lab_specific_config.svh => lab_specific_board_config.svh} | 0 .../{lab_specific_config.svh => lab_specific_board_config.svh} | 0 .../{lab_specific_config.svh => lab_specific_board_config.svh} | 0 .../{lab_specific_config.svh => lab_specific_board_config.svh} | 0 .../{lab_specific_config.svh => lab_specific_board_config.svh} | 0 5 files changed, 0 insertions(+), 0 deletions(-) rename labs/05_7seven_segment_letter/{lab_specific_config.svh => lab_specific_board_config.svh} (100%) rename labs/09_7segment_word/{lab_specific_config.svh => lab_specific_board_config.svh} (100%) rename labs/16_round_robin_arbiter/{lab_specific_config.svh => lab_specific_board_config.svh} (100%) rename labs/17_geiger_muller_radiation_counter/{lab_specific_config.svh => lab_specific_board_config.svh} (100%) rename peripherals/{lab_specific_config.svh => lab_specific_board_config.svh} (100%) diff --git a/labs/05_7seven_segment_letter/lab_specific_config.svh b/labs/05_7seven_segment_letter/lab_specific_board_config.svh similarity index 100% rename from labs/05_7seven_segment_letter/lab_specific_config.svh rename to labs/05_7seven_segment_letter/lab_specific_board_config.svh diff --git a/labs/09_7segment_word/lab_specific_config.svh b/labs/09_7segment_word/lab_specific_board_config.svh similarity index 100% rename from labs/09_7segment_word/lab_specific_config.svh rename to labs/09_7segment_word/lab_specific_board_config.svh diff --git a/labs/16_round_robin_arbiter/lab_specific_config.svh b/labs/16_round_robin_arbiter/lab_specific_board_config.svh similarity index 100% rename from labs/16_round_robin_arbiter/lab_specific_config.svh rename to labs/16_round_robin_arbiter/lab_specific_board_config.svh diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh similarity index 100% rename from labs/17_geiger_muller_radiation_counter/lab_specific_config.svh rename to labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh diff --git a/peripherals/lab_specific_config.svh b/peripherals/lab_specific_board_config.svh similarity index 100% rename from peripherals/lab_specific_config.svh rename to peripherals/lab_specific_board_config.svh From 53b78feb5270cf4d6e9b9ffc94bf8df8b7fc5004 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 08:37:20 -0700 Subject: [PATCH 22/65] More renaming --- boards/alinx_ax4010/board_specific_top.sv | 2 +- boards/arty_a7/board_specific_top.sv | 2 +- boards/arty_a7_pmod_mic3/board_specific_top.sv | 2 +- boards/basys3/board_specific_top.sv | 2 +- boards/c5gx_audio/board_specific_top.sv | 2 +- boards/c5gx_vga666/board_specific_top.sv | 2 +- boards/c5gx_vga_pmod/board_specific_top.sv | 2 +- boards/cmod_a7/board_specific_top.sv | 2 +- boards/de0/board_specific_top.sv | 2 +- boards/de0_cv/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga666/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 2 +- boards/de0_nano_vga666/board_specific_top.sv | 2 +- boards/de0_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de1/board_specific_top.sv | 2 +- boards/de10_lite/board_specific_top.sv | 2 +- boards/de10_lite_tm1638_arduino/board_specific_top.sv | 2 +- boards/de10_nano_vga666/board_specific_top.sv | 2 +- boards/de10_nano_vga_mister/board_specific_top.sv | 2 +- boards/de10_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de1_soc/board_specific_top.sv | 2 +- boards/de2/board_specific_top.sv | 2 +- boards/de2_115/board_specific_top.sv | 2 +- boards/dk_dev_3c120n/board_specific_top.sv | 2 +- boards/emooc_cc/board_specific_top.sv | 2 +- boards/ice40hx8k_evb_yosys/board_specific_top.sv | 2 +- boards/karnix_ecp5_yosys/board_specific_top.sv | 2 +- boards/nexys4/board_specific_top.sv | 2 +- boards/nexys4_ddr/board_specific_top.sv | 2 +- boards/nexys_a7/board_specific_top.sv | 2 +- boards/omdazz/board_specific_top.sv | 2 +- boards/omdazz_pmod_mic3/board_specific_top.sv | 2 +- boards/orangecrab_ecp5_yosys/board_specific_top.sv | 2 +- boards/piswords6/board_specific_top.sv | 2 +- boards/qmtech_c4_starter/board_specific_top.sv | 2 +- boards/qmtech_kintex_7/board_specific_top.sv | 2 +- boards/runber/board_specific_top.sv | 2 +- boards/rzrd/board_specific_top.sv | 2 +- boards/rzrd_pmod_mic3/board_specific_top.sv | 2 +- boards/saylinx/board_specific_top.sv | 2 +- boards/saylinx_pmod_mic3/board_specific_top.sv | 2 +- boards/step_max10/board_specific_top.sv | 2 +- boards/tang_nano_1k/board_specific_top.sv | 2 +- boards/tang_nano_1k_min/board_specific_top.sv | 2 +- boards/tang_nano_20k/board_specific_top.sv | 2 +- boards/tang_nano_9k/board_specific_top.sv | 2 +- boards/tang_nano_9k_gowin_yosys/board_specific_top.sv | 2 +- boards/tang_nano_9k_hdmi/board_specific_top.sv | 2 +- boards/tang_nano_9k_lcd/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_alt/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv | 2 +- boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv | 2 +- boards/tang_primer_20k_lite/board_specific_top.sv | 2 +- boards/tang_primer_25k_dock/board_specific_top.sv | 2 +- boards/tang_primer_25k_dock_dvi/board_specific_top.sv | 2 +- boards/trion_t20/board_specific_top.sv | 2 +- boards/zeowaa/board_specific_top.sv | 2 +- boards/zeowaa_wo_dig_0/board_specific_top.sv | 2 +- boards/zybo_z7/board_specific_top.sv | 2 +- peripherals/lab_specific_board_config.svh | 2 +- peripherals/tm1638_board.sv | 2 +- 62 files changed, 62 insertions(+), 62 deletions(-) diff --git a/boards/alinx_ax4010/board_specific_top.sv b/boards/alinx_ax4010/board_specific_top.sv index c2a48718..62e4f142 100644 --- a/boards/alinx_ax4010/board_specific_top.sv +++ b/boards/alinx_ax4010/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define USE_DIGILENT_PMOD_MIC3 diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index da8ca171..e2c03e85 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define INMP441_MIC diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index 75ec8dd2..e8801a80 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define INMP441_MIC diff --git a/boards/basys3/board_specific_top.sv b/boards/basys3/board_specific_top.sv index e4e7012b..e7f4e322 100644 --- a/boards/basys3/board_specific_top.sv +++ b/boards/basys3/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index 3f5990b0..2a620299 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index a8b1e0ba..f45fb4eb 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index 7c8d99e0..ae0f248e 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD diff --git a/boards/cmod_a7/board_specific_top.sv b/boards/cmod_a7/board_specific_top.sv index 60d5a273..72578f64 100644 --- a/boards/cmod_a7/board_specific_top.sv +++ b/boards/cmod_a7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index d7096468..2b6a383c 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index 63ae1e25..d058766b 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index 0877ea0a..a6453a9d 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 3fa8d7bb..45128814 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 34ac03e8..62ae8330 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index de84f5da..888fcdfa 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index adce1b74..d2e4e441 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index d4f37091..3e78835e 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 9bb9ab74..18129800 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index 25f3e907..293104bb 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- `define VGA666_BOARD diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index c727752a..846bca27 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index d6d9644f..4bd11f7e 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" //--- VGA external --- // `define VGA666_BOARD diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index ed6ea44f..4596f45e 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index 045c9004..e088fd9e 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index fb62e2eb..d713d774 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_HIGH_LED_FOR_7SEG_DP diff --git a/boards/dk_dev_3c120n/board_specific_top.sv b/boards/dk_dev_3c120n/board_specific_top.sv index 410d24b8..70201849 100644 --- a/boards/dk_dev_3c120n/board_specific_top.sv +++ b/boards/dk_dev_3c120n/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/emooc_cc/board_specific_top.sv b/boards/emooc_cc/board_specific_top.sv index 5cb63c79..8dd553c8 100644 --- a/boards/emooc_cc/board_specific_top.sv +++ b/boards/emooc_cc/board_specific_top.sv @@ -6,7 +6,7 @@ // for more details. `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 6fca4184..849f9725 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index 7add00e2..7755b3df 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `undef ENABLE_TM1638 `undef ENABLE_INMP441 diff --git a/boards/nexys4/board_specific_top.sv b/boards/nexys4/board_specific_top.sv index e7e76b00..7f6a179a 100644 --- a/boards/nexys4/board_specific_top.sv +++ b/boards/nexys4/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/nexys4_ddr/board_specific_top.sv b/boards/nexys4_ddr/board_specific_top.sv index fc031d8e..36eabd4a 100644 --- a/boards/nexys4_ddr/board_specific_top.sv +++ b/boards/nexys4_ddr/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/nexys_a7/board_specific_top.sv b/boards/nexys_a7/board_specific_top.sv index fc031d8e..36eabd4a 100644 --- a/boards/nexys_a7/board_specific_top.sv +++ b/boards/nexys_a7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/omdazz/board_specific_top.sv b/boards/omdazz/board_specific_top.sv index fea64299..dfe45fc6 100644 --- a/boards/omdazz/board_specific_top.sv +++ b/boards/omdazz/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define USE_DIGILENT_PMOD_MIC3 diff --git a/boards/omdazz_pmod_mic3/board_specific_top.sv b/boards/omdazz_pmod_mic3/board_specific_top.sv index 8676dd50..991d22c0 100644 --- a/boards/omdazz_pmod_mic3/board_specific_top.sv +++ b/boards/omdazz_pmod_mic3/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_DIGILENT_PMOD_MIC3 diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index 0cd7e75b..26c21ca4 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `undef ENABLE_TM1638 `undef ENABLE_INMP441 diff --git a/boards/piswords6/board_specific_top.sv b/boards/piswords6/board_specific_top.sv index c72ea8d7..a60d6c83 100644 --- a/boards/piswords6/board_specific_top.sv +++ b/boards/piswords6/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/qmtech_c4_starter/board_specific_top.sv b/boards/qmtech_c4_starter/board_specific_top.sv index 75eca0a5..10c88dde 100644 --- a/boards/qmtech_c4_starter/board_specific_top.sv +++ b/boards/qmtech_c4_starter/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/qmtech_kintex_7/board_specific_top.sv b/boards/qmtech_kintex_7/board_specific_top.sv index 1fcdad42..cfb52fa3 100644 --- a/boards/qmtech_kintex_7/board_specific_top.sv +++ b/boards/qmtech_kintex_7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/runber/board_specific_top.sv b/boards/runber/board_specific_top.sv index 806499f6..2b3be335 100644 --- a/boards/runber/board_specific_top.sv +++ b/boards/runber/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/rzrd/board_specific_top.sv b/boards/rzrd/board_specific_top.sv index fea64299..dfe45fc6 100644 --- a/boards/rzrd/board_specific_top.sv +++ b/boards/rzrd/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define USE_DIGILENT_PMOD_MIC3 diff --git a/boards/rzrd_pmod_mic3/board_specific_top.sv b/boards/rzrd_pmod_mic3/board_specific_top.sv index 8676dd50..991d22c0 100644 --- a/boards/rzrd_pmod_mic3/board_specific_top.sv +++ b/boards/rzrd_pmod_mic3/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_DIGILENT_PMOD_MIC3 diff --git a/boards/saylinx/board_specific_top.sv b/boards/saylinx/board_specific_top.sv index c2a48718..62e4f142 100644 --- a/boards/saylinx/board_specific_top.sv +++ b/boards/saylinx/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define USE_DIGILENT_PMOD_MIC3 diff --git a/boards/saylinx_pmod_mic3/board_specific_top.sv b/boards/saylinx_pmod_mic3/board_specific_top.sv index fc86a20f..2ccb336c 100644 --- a/boards/saylinx_pmod_mic3/board_specific_top.sv +++ b/boards/saylinx_pmod_mic3/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_DIGILENT_PMOD_MIC3 diff --git a/boards/step_max10/board_specific_top.sv b/boards/step_max10/board_specific_top.sv index 5c401fda..b80245ef 100644 --- a/boards/step_max10/board_specific_top.sv +++ b/boards/step_max10/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/tang_nano_1k/board_specific_top.sv b/boards/tang_nano_1k/board_specific_top.sv index 41baf04f..fc88393e 100644 --- a/boards/tang_nano_1k/board_specific_top.sv +++ b/boards/tang_nano_1k/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/tang_nano_1k_min/board_specific_top.sv b/boards/tang_nano_1k_min/board_specific_top.sv index 51b3619d..05524b62 100644 --- a/boards/tang_nano_1k_min/board_specific_top.sv +++ b/boards/tang_nano_1k_min/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index 69100997..055ff522 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index afc45dab..89179b21 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index c5ff8115..69bb9c11 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `undef ENABLE_TM1638 `undef ENABLE_INMP441 diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index c3834427..4dcead1e 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define USE_HDMI `undef ENABLE_TM1638 diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index 1a5c211f..53c58d25 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `undef ENABLE_TM1638 diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index 09527439..45120dc2 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 001f87b8..7990bed1 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" // `define ENABLE_VGA16 // `define ENABLE_VGA666 diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index f56b063e..21edd2e3 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `undef ENABLE_TM1638 `undef ENABLE_INMP441 diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 685ebf9e..81eddae4 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `undef ENABLE_TM1638 diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index 17d5c48d..1ee7b4cf 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `undef ENABLE_TM1638 diff --git a/boards/tang_primer_25k_dock/board_specific_top.sv b/boards/tang_primer_25k_dock/board_specific_top.sv index 5f9c4b20..cbe06f98 100644 --- a/boards/tang_primer_25k_dock/board_specific_top.sv +++ b/boards/tang_primer_25k_dock/board_specific_top.sv @@ -3,7 +3,7 @@ // Create a variant of 25K with 7-segment, leds and buttons on pmod. `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv index bec954d4..52d945b0 100644 --- a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv +++ b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv @@ -3,7 +3,7 @@ // Create a variant of 25K with 7-segment, leds and buttons on pmod. `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" `define ENABLE_DVI diff --git a/boards/trion_t20/board_specific_top.sv b/boards/trion_t20/board_specific_top.sv index d1a1b036..ddd665f1 100755 --- a/boards/trion_t20/board_specific_top.sv +++ b/boards/trion_t20/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/zeowaa/board_specific_top.sv b/boards/zeowaa/board_specific_top.sv index aba5c008..a45d923b 100644 --- a/boards/zeowaa/board_specific_top.sv +++ b/boards/zeowaa/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/zeowaa_wo_dig_0/board_specific_top.sv b/boards/zeowaa_wo_dig_0/board_specific_top.sv index df54b45f..5634d43a 100644 --- a/boards/zeowaa_wo_dig_0/board_specific_top.sv +++ b/boards/zeowaa_wo_dig_0/board_specific_top.sv @@ -1,7 +1,7 @@ // Asynchronous reset here is needed for some FPGA boards we use `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/boards/zybo_z7/board_specific_top.sv b/boards/zybo_z7/board_specific_top.sv index 80cc5752..b4d81717 100644 --- a/boards/zybo_z7/board_specific_top.sv +++ b/boards/zybo_z7/board_specific_top.sv @@ -1,5 +1,5 @@ `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module board_specific_top # ( diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index 3c90f1a1..34ccfae4 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -2,7 +2,7 @@ `define LAB_SPECIFIC_CONFIG_SVH // This is the default file included -// when there is no lab_specific_config.svh +// when there is no lab_specific_board_config.svh // in the lab directory // The following setting is needed for Gowin boards diff --git a/peripherals/tm1638_board.sv b/peripherals/tm1638_board.sv index b611f5a5..06c9ceb4 100644 --- a/peripherals/tm1638_board.sv +++ b/peripherals/tm1638_board.sv @@ -217,7 +217,7 @@ Copyright 2017 Alan Garfield /////////////////////////////////////////////////////////////////////////////////// `include "config.svh" -`include "lab_specific_config.svh" +`include "lab_specific_board_config.svh" module tm1638_board_controller # ( From 1204de45d01424bcee1970fea0e562a9538ae32e Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 08:55:01 -0700 Subject: [PATCH 23/65] More renaming --- boards/ice40hx8k_evb_yosys/board_specific_top.sv | 4 ++-- boards/karnix_ecp5_yosys/board_specific_top.sv | 4 ++-- boards/orangecrab_ecp5_yosys/board_specific_top.sv | 4 ++-- boards/tang_nano_20k/board_specific_top.sv | 4 ++-- boards/tang_nano_9k/board_specific_top.sv | 4 ++-- boards/tang_nano_9k_gowin_yosys/board_specific_top.sv | 4 ++-- boards/tang_nano_9k_hdmi/board_specific_top.sv | 4 ++-- boards/tang_nano_9k_lcd/board_specific_top.sv | 4 ++-- boards/tang_primer_20k_dock/board_specific_top.sv | 4 ++-- boards/tang_primer_20k_dock_alt/board_specific_top.sv | 4 ++-- boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv | 4 ++-- boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv | 4 ++-- boards/tang_primer_20k_lite/board_specific_top.sv | 4 ++-- 13 files changed, 26 insertions(+), 26 deletions(-) diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 849f9725..292fe102 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -41,7 +41,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -73,7 +73,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index 7755b3df..0cc17454 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -76,7 +76,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index 26c21ca4..a3715c84 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -76,7 +76,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/tang_nano_20k/board_specific_top.sv b/boards/tang_nano_20k/board_specific_top.sv index 055ff522..e5120411 100644 --- a/boards/tang_nano_20k/board_specific_top.sv +++ b/boards/tang_nano_20k/board_specific_top.sv @@ -35,7 +35,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -74,7 +74,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/tang_nano_9k/board_specific_top.sv b/boards/tang_nano_9k/board_specific_top.sv index 89179b21..77fc2b8a 100644 --- a/boards/tang_nano_9k/board_specific_top.sv +++ b/boards/tang_nano_9k/board_specific_top.sv @@ -41,7 +41,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -73,7 +73,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index 69bb9c11..69000f42 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -76,7 +76,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index 4dcead1e..bbc2d94d 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -44,7 +44,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -103,7 +103,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `ifdef USE_HDMI assign rst = ~ ( ~tm_key[w_tm_key - 1] & pll_lock ); diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index 53c58d25..c66dd53c 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -83,7 +83,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -117,7 +117,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/tang_primer_20k_dock/board_specific_top.sv b/boards/tang_primer_20k_dock/board_specific_top.sv index 45120dc2..86993a1c 100644 --- a/boards/tang_primer_20k_dock/board_specific_top.sv +++ b/boards/tang_primer_20k_dock/board_specific_top.sv @@ -37,7 +37,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -77,7 +77,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 7990bed1..01ad4c68 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -51,7 +51,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -132,7 +132,7 @@ module board_specific_top `endif //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `ifdef ENABLE_HDMI assign rst = ~ ( ~tm_key[w_tm_key - 1] & pll_lock ); diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index 21edd2e3..28391863 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -40,7 +40,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -80,7 +80,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index 81eddae4..c29bab4b 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -39,7 +39,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -79,7 +79,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index 1ee7b4cf..7e9443e0 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -39,7 +39,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE localparam w_lab_key = w_tm_key, w_lab_sw = w_sw, @@ -79,7 +79,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 // TM1638 module is connected + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; assign lab_key = tm_key [w_tm_key - 1:0]; From e7b731bbd8645d0503baffde25da23d43319bfaa Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 08:57:21 -0700 Subject: [PATCH 24/65] More renaming --- boards/ice40hx8k_evb_yosys/board_specific_top.sv | 4 ++-- boards/karnix_ecp5_yosys/board_specific_top.sv | 6 +++--- boards/orangecrab_ecp5_yosys/board_specific_top.sv | 6 +++--- boards/tang_nano_9k_gowin_yosys/board_specific_top.sv | 6 +++--- boards/tang_nano_9k_hdmi/board_specific_top.sv | 2 +- boards/tang_nano_9k_lcd/board_specific_top.sv | 6 +++--- boards/tang_primer_20k_dock_alt/board_specific_top.sv | 2 +- .../tang_primer_20k_dock_gowin_yosys/board_specific_top.sv | 6 +++--- boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv | 2 +- boards/tang_primer_20k_lite/board_specific_top.sv | 2 +- labs/05_7seven_segment_letter/lab_specific_board_config.svh | 2 +- labs/09_7segment_word/lab_specific_board_config.svh | 2 +- labs/16_round_robin_arbiter/lab_specific_board_config.svh | 2 +- .../lab_specific_board_config.svh | 2 +- peripherals/lab_specific_board_config.svh | 2 +- 15 files changed, 26 insertions(+), 26 deletions(-) diff --git a/boards/ice40hx8k_evb_yosys/board_specific_top.sv b/boards/ice40hx8k_evb_yosys/board_specific_top.sv index 292fe102..3cb28150 100644 --- a/boards/ice40hx8k_evb_yosys/board_specific_top.sv +++ b/boards/ice40hx8k_evb_yosys/board_specific_top.sv @@ -136,7 +136,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -158,7 +158,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/karnix_ecp5_yosys/board_specific_top.sv b/boards/karnix_ecp5_yosys/board_specific_top.sv index 0cc17454..6b3ab269 100644 --- a/boards/karnix_ecp5_yosys/board_specific_top.sv +++ b/boards/karnix_ecp5_yosys/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `undef ENABLE_INMP441 module board_specific_top @@ -140,7 +140,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -162,7 +162,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/orangecrab_ecp5_yosys/board_specific_top.sv b/boards/orangecrab_ecp5_yosys/board_specific_top.sv index a3715c84..6a250edd 100644 --- a/boards/orangecrab_ecp5_yosys/board_specific_top.sv +++ b/boards/orangecrab_ecp5_yosys/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `undef ENABLE_INMP441 module board_specific_top @@ -139,7 +139,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -161,7 +161,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv index 69000f42..bb39c77b 100644 --- a/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv +++ b/boards/tang_nano_9k_gowin_yosys/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `undef ENABLE_INMP441 module board_specific_top @@ -136,7 +136,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -158,7 +158,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index bbc2d94d..944b2f49 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -2,7 +2,7 @@ `include "lab_specific_board_config.svh" `define USE_HDMI -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index c66dd53c..d9054cd2 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -// `undef ENABLE_TM1638 +// `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( @@ -196,7 +196,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE wire [$left (abcdefgh):0] hgfedcba; @@ -213,7 +213,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_TM1638 + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 01ad4c68..7c638bce 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -6,7 +6,7 @@ `undef ENABLE_VGA16 `define ENABLE_HDMI -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( diff --git a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv index 28391863..4fc05a6f 100644 --- a/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_gowin_yosys/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE `undef ENABLE_INMP441 module board_specific_top @@ -142,7 +142,7 @@ module board_specific_top .uart_tx ( UART_TX ), .mic ( mic ), - `ifndef ENABLE_TM1638 + `ifndef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE .gpio ( GPIO ) `else .gpio ( ) @@ -164,7 +164,7 @@ module board_specific_top //------------------------------------------------------------------------ -`ifdef ENABLE_TM1638 +`ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE tm1638_board_controller # ( .clk_mhz ( clk_mhz ), diff --git a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv index c29bab4b..459f3a0a 100644 --- a/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_no_tm1638/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index 7e9443e0..0d85e74d 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`undef ENABLE_TM1638 +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( diff --git a/labs/05_7seven_segment_letter/lab_specific_board_config.svh b/labs/05_7seven_segment_letter/lab_specific_board_config.svh index 20899864..6ee87d3c 100644 --- a/labs/05_7seven_segment_letter/lab_specific_board_config.svh +++ b/labs/05_7seven_segment_letter/lab_specific_board_config.svh @@ -2,7 +2,7 @@ `define LAB_SPECIFIC_CONFIG_SVH // The following setting is needed for Gowin boards - `define ENABLE_TM1638 + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller // `define HCW132 diff --git a/labs/09_7segment_word/lab_specific_board_config.svh b/labs/09_7segment_word/lab_specific_board_config.svh index 20899864..6ee87d3c 100644 --- a/labs/09_7segment_word/lab_specific_board_config.svh +++ b/labs/09_7segment_word/lab_specific_board_config.svh @@ -2,7 +2,7 @@ `define LAB_SPECIFIC_CONFIG_SVH // The following setting is needed for Gowin boards - `define ENABLE_TM1638 + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller // `define HCW132 diff --git a/labs/16_round_robin_arbiter/lab_specific_board_config.svh b/labs/16_round_robin_arbiter/lab_specific_board_config.svh index 20899864..6ee87d3c 100644 --- a/labs/16_round_robin_arbiter/lab_specific_board_config.svh +++ b/labs/16_round_robin_arbiter/lab_specific_board_config.svh @@ -2,7 +2,7 @@ `define LAB_SPECIFIC_CONFIG_SVH // The following setting is needed for Gowin boards - `define ENABLE_TM1638 + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller // `define HCW132 diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh index ad213b90..93604b9e 100644 --- a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh +++ b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh @@ -2,7 +2,7 @@ `define LAB_SPECIFIC_CONFIG_SVH // The following setting is needed for Gowin boards - `define ENABLE_TM1638 + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller // `define HCW132 diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index 34ccfae4..2ab76108 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -6,7 +6,7 @@ // in the lab directory // The following setting is needed for Gowin boards - `define ENABLE_TM1638 + `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller // `define HCW132 From bb59f84e2f796fb00459481ffc26c3721cc0c156 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 08:59:57 -0700 Subject: [PATCH 25/65] More renaming --- labs/05_7seven_segment_letter/lab_specific_board_config.svh | 2 +- labs/09_7segment_word/lab_specific_board_config.svh | 2 +- labs/16_round_robin_arbiter/lab_specific_board_config.svh | 2 +- .../lab_specific_board_config.svh | 2 +- .../labs/11_2_note_recognition_with_filtering/lab_top.sv | 2 +- misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv | 2 +- peripherals/lab_specific_board_config.svh | 2 +- peripherals/tm1638_board.sv | 6 +++--- 8 files changed, 10 insertions(+), 10 deletions(-) diff --git a/labs/05_7seven_segment_letter/lab_specific_board_config.svh b/labs/05_7seven_segment_letter/lab_specific_board_config.svh index 6ee87d3c..c71fe88a 100644 --- a/labs/05_7seven_segment_letter/lab_specific_board_config.svh +++ b/labs/05_7seven_segment_letter/lab_specific_board_config.svh @@ -5,7 +5,7 @@ `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS diff --git a/labs/09_7segment_word/lab_specific_board_config.svh b/labs/09_7segment_word/lab_specific_board_config.svh index 6ee87d3c..c71fe88a 100644 --- a/labs/09_7segment_word/lab_specific_board_config.svh +++ b/labs/09_7segment_word/lab_specific_board_config.svh @@ -5,7 +5,7 @@ `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS diff --git a/labs/16_round_robin_arbiter/lab_specific_board_config.svh b/labs/16_round_robin_arbiter/lab_specific_board_config.svh index 6ee87d3c..c71fe88a 100644 --- a/labs/16_round_robin_arbiter/lab_specific_board_config.svh +++ b/labs/16_round_robin_arbiter/lab_specific_board_config.svh @@ -5,7 +5,7 @@ `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh index 93604b9e..d0b32132 100644 --- a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh +++ b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh @@ -5,7 +5,7 @@ `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE // `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS diff --git a/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv b/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv index fee6c3c6..479f98f2 100644 --- a/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv +++ b/misc/review_for_style/labs/11_2_note_recognition_with_filtering/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" `define ENABLE_TP1638 -`define HCW132 +`define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE `define ENABLE_INMP441 module lab_top diff --git a/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv b/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv index 955bdb5d..5efc68d1 100644 --- a/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv +++ b/misc/review_for_style/labs/11_3_mic_to_uart/lab_top.sv @@ -1,6 +1,6 @@ `include "config.svh" `define ENABLE_TP1638 -`define HCW132 +`define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE `define ENABLE_INMP441 module lab_top diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index 2ab76108..bb898a05 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -9,7 +9,7 @@ `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 variant of LED & KEY TM1638 board controller -// `define HCW132 +// `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE // `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS diff --git a/peripherals/tm1638_board.sv b/peripherals/tm1638_board.sv index 06c9ceb4..8f71e430 100644 --- a/peripherals/tm1638_board.sv +++ b/peripherals/tm1638_board.sv @@ -231,7 +231,7 @@ module tm1638_board_controller input [ 7:0] hgfedcba, input [ w_digit - 1:0] digit, input [ 7:0] ledr, - `ifdef HCW132 + `ifdef USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE output logic [ 15:0] keys, `else output logic [ 7:0] keys, @@ -428,7 +428,7 @@ module tm1638_board_controller 2: {tm_latch, tm_in} <= {HIGH, C_READ_KEYS}; // read mode 3: {tm_latch, tm_rw} <= {HIGH, LOW}; - `ifdef HCW132 + `ifdef USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE // read back keys S1 - S16 4: {keys[0], keys[1], keys[8], keys[9]} <= {tm_out[2], tm_out[6], tm_out[1], tm_out[5]}; 5: tm_latch <= HIGH; @@ -459,7 +459,7 @@ module tm1638_board_controller 17: {sio_stb, tm_rw} <= {LOW, HIGH}; 18: {tm_latch, tm_in} <= {HIGH, C_SET_ADDR_0}; // set addr 0 pos - `ifdef HCW132 + `ifdef USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE // HCW-132 has very weird display map 19: display_digit({hex7[0],hex6[0],hex5[0],hex4[0],hex3[0],hex2[0],hex1[0],hex0[0]}); 20: display_digit(8'b00000000); From c057b0c29c217c20403bdf3c164c5520ab11e256 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 09:04:21 -0700 Subject: [PATCH 26/65] More renaming --- boards/c5gx_audio/board_specific_top.sv | 2 +- boards/c5gx_vga666/board_specific_top.sv | 2 +- boards/c5gx_vga_pmod/board_specific_top.sv | 2 +- boards/de0/board_specific_top.sv | 2 +- boards/de0_cv/board_specific_top.sv | 2 +- boards/de1/board_specific_top.sv | 2 +- boards/de10_lite/board_specific_top.sv | 2 +- boards/de10_lite_tm1638_arduino/board_specific_top.sv | 2 +- boards/de1_soc/board_specific_top.sv | 2 +- boards/de2/board_specific_top.sv | 2 +- boards/de2_115/board_specific_top.sv | 2 +- .../05_7seven_segment_letter/lab_specific_board_config.svh | 2 +- labs/09_7segment_word/lab_specific_board_config.svh | 2 +- labs/16_round_robin_arbiter/lab_specific_board_config.svh | 2 +- .../lab_specific_board_config.svh | 2 +- peripherals/lab_specific_board_config.svh | 7 ++----- peripherals/tm1638_board.sv | 2 +- 17 files changed, 18 insertions(+), 21 deletions(-) diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index 2a620299..d2acc2e9 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -121,7 +121,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/c5gx_vga666/board_specific_top.sv b/boards/c5gx_vga666/board_specific_top.sv index f45fb4eb..4ddfe638 100644 --- a/boards/c5gx_vga666/board_specific_top.sv +++ b/boards/c5gx_vga666/board_specific_top.sv @@ -192,7 +192,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/c5gx_vga_pmod/board_specific_top.sv b/boards/c5gx_vga_pmod/board_specific_top.sv index ae0f248e..1940ccf3 100644 --- a/boards/c5gx_vga_pmod/board_specific_top.sv +++ b/boards/c5gx_vga_pmod/board_specific_top.sv @@ -184,7 +184,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index 2b6a383c..24bc98c2 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -121,7 +121,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index d058766b..bdc663d3 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -123,7 +123,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index d2e4e441..a0f3a9b7 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -124,7 +124,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index 3e78835e..915e65c9 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -118,7 +118,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 18129800..1ba1b7c8 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -191,7 +191,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de1_soc/board_specific_top.sv b/boards/de1_soc/board_specific_top.sv index 4596f45e..22562745 100644 --- a/boards/de1_soc/board_specific_top.sv +++ b/boards/de1_soc/board_specific_top.sv @@ -166,7 +166,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index e088fd9e..01c35651 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -171,7 +171,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index d713d774..e5a7e2ce 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -170,7 +170,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // Pro: This implementation is necessary for the lab 7segment_word // to properly demonstrate the idea of dynamic 7-segment display diff --git a/labs/05_7seven_segment_letter/lab_specific_board_config.svh b/labs/05_7seven_segment_letter/lab_specific_board_config.svh index c71fe88a..d32e3258 100644 --- a/labs/05_7seven_segment_letter/lab_specific_board_config.svh +++ b/labs/05_7seven_segment_letter/lab_specific_board_config.svh @@ -7,7 +7,7 @@ // HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE - `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS `define DUPLICATE_TM_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM diff --git a/labs/09_7segment_word/lab_specific_board_config.svh b/labs/09_7segment_word/lab_specific_board_config.svh index c71fe88a..d32e3258 100644 --- a/labs/09_7segment_word/lab_specific_board_config.svh +++ b/labs/09_7segment_word/lab_specific_board_config.svh @@ -7,7 +7,7 @@ // HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE - `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS `define DUPLICATE_TM_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM diff --git a/labs/16_round_robin_arbiter/lab_specific_board_config.svh b/labs/16_round_robin_arbiter/lab_specific_board_config.svh index c71fe88a..d32e3258 100644 --- a/labs/16_round_robin_arbiter/lab_specific_board_config.svh +++ b/labs/16_round_robin_arbiter/lab_specific_board_config.svh @@ -7,7 +7,7 @@ // HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE - `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS `define DUPLICATE_TM_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh index d0b32132..fc2197e9 100644 --- a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh +++ b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh @@ -7,7 +7,7 @@ // HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE -// `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS +// `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // `define DUPLICATE_TM_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index bb898a05..b9a80da0 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -5,16 +5,13 @@ // when there is no lab_specific_board_config.svh // in the lab directory -// The following setting is needed for Gowin boards `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - -// HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE -// `define EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM // `define CONCAT_TM_SIGNALS_AND_REGULAR +// `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/peripherals/tm1638_board.sv b/peripherals/tm1638_board.sv index 8f71e430..5a318572 100644 --- a/peripherals/tm1638_board.sv +++ b/peripherals/tm1638_board.sv @@ -241,7 +241,7 @@ module tm1638_board_controller inout sio_data ); - `ifdef EMULATE_DYNAMIC_7SEG_WITHOUT_STICKY_FLOPS + `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS localparam static_hex = 1'b0; `else localparam static_hex = 1'b1; From 257a801c72f5b4db49ae2d8600247bb58c8c2ac9 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 10:14:28 -0700 Subject: [PATCH 27/65] More renaming --- boards/arty_a7/board_specific_top.sv | 6 +++--- boards/arty_a7_pmod_mic3/board_specific_top.sv | 6 +++--- boards/de0_nano_soc_vga666/board_specific_top.sv | 6 +++--- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 6 +++--- boards/de0_nano_vga666/board_specific_top.sv | 6 +++--- boards/de0_nano_vga_pmod/board_specific_top.sv | 6 +++--- boards/de10_lite_tm1638_arduino/board_specific_top.sv | 6 +++--- boards/de10_nano_vga666/board_specific_top.sv | 6 +++--- boards/de10_nano_vga_mister/board_specific_top.sv | 6 +++--- boards/de10_nano_vga_pmod/board_specific_top.sv | 6 +++--- boards/zybo_z7/board_specific_top.sv | 6 +++--- labs/05_7seven_segment_letter/lab_specific_board_config.svh | 4 ++-- labs/09_7segment_word/lab_specific_board_config.svh | 4 ++-- labs/16_round_robin_arbiter/lab_specific_board_config.svh | 4 ++-- .../lab_specific_board_config.svh | 4 ++-- peripherals/lab_specific_board_config.svh | 4 ++-- 16 files changed, 43 insertions(+), 43 deletions(-) diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index e2c03e85..f37944bd 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -90,7 +90,7 @@ module board_specific_top w_tm_led = 8, w_tm_digit = 8; - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -115,7 +115,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, KEY }; @@ -129,7 +129,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index e8801a80..6f70caa6 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -90,7 +90,7 @@ module board_specific_top w_tm_led = 8, w_tm_digit = 8; - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -115,7 +115,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, KEY }; @@ -129,7 +129,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index a6453a9d..aff8f34e 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -57,7 +57,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -82,7 +82,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, ~ KEY }; @@ -96,7 +96,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 45128814..67190d04 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -57,7 +57,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -82,7 +82,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, ~ KEY }; @@ -96,7 +96,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 62ae8330..1e0304ff 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -56,7 +56,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -81,7 +81,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, ~ KEY }; @@ -95,7 +95,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 888fcdfa..38729384 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -56,7 +56,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -81,7 +81,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, ~ KEY }; @@ -95,7 +95,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 1ba1b7c8..cc6baf04 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -68,7 +68,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -93,7 +93,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, ~ KEY }; @@ -107,7 +107,7 @@ module board_specific_top assign { LEDR , tm_led } = lab_led; assign { digit , tm_digit } = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index 293104bb..40c82d17 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -62,7 +62,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, ~ KEY }; @@ -101,7 +101,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index 846bca27..411ceb6c 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -62,7 +62,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, ~ KEY }; @@ -101,7 +101,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index 4bd11f7e..c70d4d3a 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -62,7 +62,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_lab_key = w_tm_key > w_key ? w_tm_key : w_key , w_lab_led = w_tm_led > w_led ? w_tm_led : w_led , @@ -87,7 +87,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign lab_key = { tm_key, ~ KEY }; @@ -101,7 +101,7 @@ module board_specific_top assign { LED , tm_led } = lab_led; assign tm_digit = lab_digit; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin diff --git a/boards/zybo_z7/board_specific_top.sv b/boards/zybo_z7/board_specific_top.sv index b4d81717..b9c71939 100644 --- a/boards/zybo_z7/board_specific_top.sv +++ b/boards/zybo_z7/board_specific_top.sv @@ -45,7 +45,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef DUPLICATE_TM_SIGNALS_WITH_REGULAR + `ifdef DUPLICATE_TM1638_SIGNALS_WITH_REGULAR localparam w_key_top = w_key_tm > w_key ? w_key_tm : w_key, w_led_top = w_led_tm > w_led ? w_led_tm : w_led, w_digit_top = w_digit_tm > w_digit ? w_digit_tm : w_digit; @@ -67,7 +67,7 @@ module board_specific_top //------------------------------------------------------------------------------ - `ifdef CONCAT_TM_SIGNALS_AND_REGULAR + `ifdef CONCAT_TM1638_SIGNALS_AND_REGULAR assign key_top = {key_tm, key}; assign {led_tm, led} = led_top; assign {digit_tm, digit} = digit_top; @@ -77,7 +77,7 @@ module board_specific_top assign {led, led_tm} = led_top; assign {digit, digit_tm} = digit_top; - `else // DUPLICATE_TM_SIGNALS_WITH_REGULAR + `else // DUPLICATE_TM1638_SIGNALS_WITH_REGULAR always_comb begin key_top = '0; diff --git a/labs/05_7seven_segment_letter/lab_specific_board_config.svh b/labs/05_7seven_segment_letter/lab_specific_board_config.svh index d32e3258..a1ede29e 100644 --- a/labs/05_7seven_segment_letter/lab_specific_board_config.svh +++ b/labs/05_7seven_segment_letter/lab_specific_board_config.svh @@ -9,8 +9,8 @@ `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR + `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM -// `define CONCAT_TM_SIGNALS_AND_REGULAR +// `define CONCAT_TM1638_SIGNALS_AND_REGULAR `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/09_7segment_word/lab_specific_board_config.svh b/labs/09_7segment_word/lab_specific_board_config.svh index d32e3258..a1ede29e 100644 --- a/labs/09_7segment_word/lab_specific_board_config.svh +++ b/labs/09_7segment_word/lab_specific_board_config.svh @@ -9,8 +9,8 @@ `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR + `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM -// `define CONCAT_TM_SIGNALS_AND_REGULAR +// `define CONCAT_TM1638_SIGNALS_AND_REGULAR `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/16_round_robin_arbiter/lab_specific_board_config.svh b/labs/16_round_robin_arbiter/lab_specific_board_config.svh index d32e3258..a1ede29e 100644 --- a/labs/16_round_robin_arbiter/lab_specific_board_config.svh +++ b/labs/16_round_robin_arbiter/lab_specific_board_config.svh @@ -9,8 +9,8 @@ `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR + `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM -// `define CONCAT_TM_SIGNALS_AND_REGULAR +// `define CONCAT_TM1638_SIGNALS_AND_REGULAR `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh index fc2197e9..db3f26e8 100644 --- a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh +++ b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh @@ -9,8 +9,8 @@ // `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS -// `define DUPLICATE_TM_SIGNALS_WITH_REGULAR +// `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM - `define CONCAT_TM_SIGNALS_AND_REGULAR + `define CONCAT_TM1638_SIGNALS_AND_REGULAR `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index b9a80da0..649a2c21 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -8,9 +8,9 @@ `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE - `define DUPLICATE_TM_SIGNALS_WITH_REGULAR + `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM -// `define CONCAT_TM_SIGNALS_AND_REGULAR +// `define CONCAT_TM1638_SIGNALS_AND_REGULAR // `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS From 04d58dc40aacfae2a418c7e26ed263aab85f294d Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 10:36:19 -0700 Subject: [PATCH 28/65] More renaming --- boards/arty_a7/board_specific_top.sv | 2 +- boards/arty_a7_pmod_mic3/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga666/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 2 +- boards/de0_nano_vga666/board_specific_top.sv | 2 +- boards/de0_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de10_lite_tm1638_arduino/board_specific_top.sv | 2 +- boards/de10_nano_vga666/board_specific_top.sv | 2 +- boards/de10_nano_vga_mister/board_specific_top.sv | 2 +- boards/de10_nano_vga_pmod/board_specific_top.sv | 2 +- boards/zybo_z7/board_specific_top.sv | 2 +- labs/05_7seven_segment_letter/lab_specific_board_config.svh | 2 +- labs/09_7segment_word/lab_specific_board_config.svh | 2 +- labs/16_round_robin_arbiter/lab_specific_board_config.svh | 2 +- .../lab_specific_board_config.svh | 2 +- peripherals/lab_specific_board_config.svh | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/boards/arty_a7/board_specific_top.sv b/boards/arty_a7/board_specific_top.sv index f37944bd..ee443b8d 100644 --- a/boards/arty_a7/board_specific_top.sv +++ b/boards/arty_a7/board_specific_top.sv @@ -122,7 +122,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { KEY, tm_key }; diff --git a/boards/arty_a7_pmod_mic3/board_specific_top.sv b/boards/arty_a7_pmod_mic3/board_specific_top.sv index 6f70caa6..6100a5f3 100644 --- a/boards/arty_a7_pmod_mic3/board_specific_top.sv +++ b/boards/arty_a7_pmod_mic3/board_specific_top.sv @@ -122,7 +122,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { KEY, tm_key }; diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index aff8f34e..8bbdf03b 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -89,7 +89,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { ~ KEY, tm_key }; diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 67190d04..50050016 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -89,7 +89,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { ~ KEY, tm_key }; diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 1e0304ff..4f3e1ff6 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -88,7 +88,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { ~ KEY, tm_key }; diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index 38729384..cd870afb 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -88,7 +88,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { ~ KEY, tm_key }; diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index cc6baf04..075c521e 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -100,7 +100,7 @@ module board_specific_top assign { tm_led , LEDR } = lab_led; assign { tm_digit , digit } = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { ~ KEY, tm_key }; diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index 40c82d17..a1a1faf5 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -94,7 +94,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { ~ KEY, tm_key }; diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index 411ceb6c..c6339194 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -94,7 +94,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { ~ KEY, tm_key }; diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index c70d4d3a..5c05cdc9 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -94,7 +94,7 @@ module board_specific_top assign { tm_led , LED } = lab_led; assign tm_digit = lab_digit; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign lab_key = { ~ KEY, tm_key }; diff --git a/boards/zybo_z7/board_specific_top.sv b/boards/zybo_z7/board_specific_top.sv index b9c71939..20a05ef3 100644 --- a/boards/zybo_z7/board_specific_top.sv +++ b/boards/zybo_z7/board_specific_top.sv @@ -72,7 +72,7 @@ module board_specific_top assign {led_tm, led} = led_top; assign {digit_tm, digit} = digit_top; - `elsif CONCAT_REGULAR_SIGNALS_AND_TM + `elsif CONCAT_REGULAR_SIGNALS_AND_TM1638 assign key_top = {key, key_tm}; assign {led, led_tm} = led_top; assign {digit, digit_tm} = digit_top; diff --git a/labs/05_7seven_segment_letter/lab_specific_board_config.svh b/labs/05_7seven_segment_letter/lab_specific_board_config.svh index a1ede29e..e5e424e0 100644 --- a/labs/05_7seven_segment_letter/lab_specific_board_config.svh +++ b/labs/05_7seven_segment_letter/lab_specific_board_config.svh @@ -10,7 +10,7 @@ `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 // `define CONCAT_TM1638_SIGNALS_AND_REGULAR `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/09_7segment_word/lab_specific_board_config.svh b/labs/09_7segment_word/lab_specific_board_config.svh index a1ede29e..e5e424e0 100644 --- a/labs/09_7segment_word/lab_specific_board_config.svh +++ b/labs/09_7segment_word/lab_specific_board_config.svh @@ -10,7 +10,7 @@ `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 // `define CONCAT_TM1638_SIGNALS_AND_REGULAR `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/16_round_robin_arbiter/lab_specific_board_config.svh b/labs/16_round_robin_arbiter/lab_specific_board_config.svh index a1ede29e..e5e424e0 100644 --- a/labs/16_round_robin_arbiter/lab_specific_board_config.svh +++ b/labs/16_round_robin_arbiter/lab_specific_board_config.svh @@ -10,7 +10,7 @@ `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 // `define CONCAT_TM1638_SIGNALS_AND_REGULAR `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh index db3f26e8..6db2705e 100644 --- a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh +++ b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh @@ -10,7 +10,7 @@ // `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS // `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 `define CONCAT_TM1638_SIGNALS_AND_REGULAR `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index 649a2c21..fd38fc81 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -9,7 +9,7 @@ // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR -// `define CONCAT_REGULAR_SIGNALS_AND_TM +// `define CONCAT_REGULAR_SIGNALS_AND_TM1638 // `define CONCAT_TM1638_SIGNALS_AND_REGULAR // `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS From d64dab91de1a585384b1f267330311aae7b70107 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 11:05:03 -0700 Subject: [PATCH 29/65] cleaning up config files --- .../lab_specific_board_config.svh | 7 ++----- labs/09_7segment_word/lab_specific_board_config.svh | 7 ++----- .../lab_specific_board_config.svh | 11 ++++++----- .../lab_specific_board_config.svh | 7 ++----- peripherals/lab_specific_board_config.svh | 8 ++++---- 5 files changed, 16 insertions(+), 24 deletions(-) diff --git a/labs/05_7seven_segment_letter/lab_specific_board_config.svh b/labs/05_7seven_segment_letter/lab_specific_board_config.svh index e5e424e0..927dd152 100644 --- a/labs/05_7seven_segment_letter/lab_specific_board_config.svh +++ b/labs/05_7seven_segment_letter/lab_specific_board_config.svh @@ -1,16 +1,13 @@ `ifndef LAB_SPECIFIC_CONFIG_SVH `define LAB_SPECIFIC_CONFIG_SVH -// The following setting is needed for Gowin boards `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - -// HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE - `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS - `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM1638 // `define CONCAT_TM1638_SIGNALS_AND_REGULAR + `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/09_7segment_word/lab_specific_board_config.svh b/labs/09_7segment_word/lab_specific_board_config.svh index e5e424e0..927dd152 100644 --- a/labs/09_7segment_word/lab_specific_board_config.svh +++ b/labs/09_7segment_word/lab_specific_board_config.svh @@ -1,16 +1,13 @@ `ifndef LAB_SPECIFIC_CONFIG_SVH `define LAB_SPECIFIC_CONFIG_SVH -// The following setting is needed for Gowin boards `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - -// HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE - `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS - `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM1638 // `define CONCAT_TM1638_SIGNALS_AND_REGULAR + `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/16_round_robin_arbiter/lab_specific_board_config.svh b/labs/16_round_robin_arbiter/lab_specific_board_config.svh index e5e424e0..2d7a23a0 100644 --- a/labs/16_round_robin_arbiter/lab_specific_board_config.svh +++ b/labs/16_round_robin_arbiter/lab_specific_board_config.svh @@ -1,16 +1,17 @@ `ifndef LAB_SPECIFIC_CONFIG_SVH `define LAB_SPECIFIC_CONFIG_SVH -// The following setting is needed for Gowin boards `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - -// HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE - `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS - `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM1638 // `define CONCAT_TM1638_SIGNALS_AND_REGULAR +// `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH + +// This is the default file included +// when there is no lab_specific_board_config.svh +// in the lab directory diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh index 6db2705e..1cc1de3f 100644 --- a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh +++ b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh @@ -1,16 +1,13 @@ `ifndef LAB_SPECIFIC_CONFIG_SVH `define LAB_SPECIFIC_CONFIG_SVH -// The following setting is needed for Gowin boards `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - -// HCW-132 variant of LED & KEY TM1638 board controller // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE -// `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS - // `define DUPLICATE_TM1638_SIGNALS_WITH_REGULAR // `define CONCAT_REGULAR_SIGNALS_AND_TM1638 `define CONCAT_TM1638_SIGNALS_AND_REGULAR +// `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index fd38fc81..2d7a23a0 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -1,10 +1,6 @@ `ifndef LAB_SPECIFIC_CONFIG_SVH `define LAB_SPECIFIC_CONFIG_SVH -// This is the default file included -// when there is no lab_specific_board_config.svh -// in the lab directory - `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE @@ -15,3 +11,7 @@ // `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH + +// This is the default file included +// when there is no lab_specific_board_config.svh +// in the lab directory From d5eab2b1c20cfdc2f01b3468701eb44963021704 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 11:12:32 -0700 Subject: [PATCH 30/65] Checking the effect of config file on simulation time - 1 --- labs/01_and_or_not_xor_de_morgan/lab_top.sv | 45 +++++++++++---------- peripherals/lab_specific_board_config.svh | 4 ++ 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/labs/01_and_or_not_xor_de_morgan/lab_top.sv b/labs/01_and_or_not_xor_de_morgan/lab_top.sv index 6d18eff6..8f7df9c7 100644 --- a/labs/01_and_or_not_xor_de_morgan/lab_top.sv +++ b/labs/01_and_or_not_xor_de_morgan/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index 2d7a23a0..2dc4de3d 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -10,6 +10,10 @@ // `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH // This is the default file included From 1ef77c90c17a8aa85d12ec8c1cad8b85924acc67 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 12:23:14 -0700 Subject: [PATCH 31/65] Made instantiations conditional --- boards/de2_115/board_specific_top.sv | 108 +++++++++++++++------------ 1 file changed, 60 insertions(+), 48 deletions(-) diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index e5a7e2ce..bd6fb10e 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -241,62 +241,74 @@ module board_specific_top //------------------------------------------------------------------------ - wire [9:0] x10; assign x = x10; - wire [9:0] y10; assign y = y10; + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( VGA_CLK ) + ); + + assign VGA_BLANK_N = 1'b1; + assign VGA_SYNC_N = 1'b0; - vga - # ( - .CLK_MHZ ( clk_mhz ), - .PIXEL_MHZ ( pixel_mhz ) - ) - i_vga - ( - .clk ( clk ), - .rst ( rst ), - .hsync ( VGA_HS ), - .vsync ( VGA_VS ), - .display_on ( ), - .hpos ( x10 ), - .vpos ( y10 ), - .pixel_clk ( VGA_CLK ) - ); - - assign VGA_BLANK_N = 1'b1; - assign VGA_SYNC_N = 1'b0; + `endif //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( GPIO [0] ), - .ws ( GPIO [2] ), - .sck ( GPIO [4] ), - .sd ( GPIO [5] ), - .value ( mic ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE - assign GPIO [1] = 1'b0; // GND - assign GPIO [3] = 1'b1; // VCC + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( GPIO [0] ), + .ws ( GPIO [2] ), + .sck ( GPIO [4] ), + .sd ( GPIO [5] ), + .value ( mic ) + ); + + assign GPIO [1] = 1'b0; // GND + assign GPIO [3] = 1'b1; // VCC + + `endif //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - i_audio - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), - .mclk ( GPIO [33] ), - .bclk ( GPIO [31] ), - .lrclk ( GPIO [27] ), - .sdata ( GPIO [29] ) - ); + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + i_audio + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( GPIO [33] ), + .bclk ( GPIO [31] ), + .lrclk ( GPIO [27] ), + .sdata ( GPIO [29] ) + ); + + // VCC and GND for i2s_audio_out are on dedicated pins - // VCC and GND for i2s_audio_out are on dedicated pins + `endif endmodule From 6bd2bdb0154552f0e7ef43f58217d1bdf971788e Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 12:25:02 -0700 Subject: [PATCH 32/65] Made instantiations conditional --- labs/05_7seven_segment_letter/lab_specific_board_config.svh | 4 ++++ labs/09_7segment_word/lab_specific_board_config.svh | 4 ++++ labs/16_round_robin_arbiter/lab_specific_board_config.svh | 4 ++++ .../lab_specific_board_config.svh | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/labs/05_7seven_segment_letter/lab_specific_board_config.svh b/labs/05_7seven_segment_letter/lab_specific_board_config.svh index 927dd152..752d2929 100644 --- a/labs/05_7seven_segment_letter/lab_specific_board_config.svh +++ b/labs/05_7seven_segment_letter/lab_specific_board_config.svh @@ -10,4 +10,8 @@ `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/09_7segment_word/lab_specific_board_config.svh b/labs/09_7segment_word/lab_specific_board_config.svh index 927dd152..752d2929 100644 --- a/labs/09_7segment_word/lab_specific_board_config.svh +++ b/labs/09_7segment_word/lab_specific_board_config.svh @@ -10,4 +10,8 @@ `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH diff --git a/labs/16_round_robin_arbiter/lab_specific_board_config.svh b/labs/16_round_robin_arbiter/lab_specific_board_config.svh index 2d7a23a0..2dc4de3d 100644 --- a/labs/16_round_robin_arbiter/lab_specific_board_config.svh +++ b/labs/16_round_robin_arbiter/lab_specific_board_config.svh @@ -10,6 +10,10 @@ // `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH // This is the default file included diff --git a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh index 1cc1de3f..77e0113b 100644 --- a/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh +++ b/labs/17_geiger_muller_radiation_counter/lab_specific_board_config.svh @@ -10,4 +10,8 @@ // `define EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS + `define INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE + `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + `endif // `ifndef LAB_SPECIFIC_CONFIG_SVH From e9c424d338b8b700a2c8bb9f2ef794c750c21049 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 13:13:28 -0700 Subject: [PATCH 33/65] Note recognition DE2-115 --- labs/11_note_recognition/lab_top.sv | 45 +++++++++++++++-------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/labs/11_note_recognition/lab_top.sv b/labs/11_note_recognition/lab_top.sv index 33ec7371..469bea5a 100644 --- a/labs/11_note_recognition/lab_top.sv +++ b/labs/11_note_recognition/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; From b3a13176acb76dadff901b533847c1b6a1ca29ae Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sat, 20 Jul 2024 13:15:21 -0700 Subject: [PATCH 34/65] Sound output DE2-115 --- labs/23_i2s_synthesizer/lab_top.sv | 45 ++++++++++++++++-------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/labs/23_i2s_synthesizer/lab_top.sv b/labs/23_i2s_synthesizer/lab_top.sv index 00c38b8f..2b8b36f9 100644 --- a/labs/23_i2s_synthesizer/lab_top.sv +++ b/labs/23_i2s_synthesizer/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; // assign sound = '0; assign uart_tx = '1; From 316466cde9144d9cca0410099b28b69c279ed882 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 14:21:36 -0700 Subject: [PATCH 35/65] Added green led and UART to de2-115, improved config header --- boards/de2_115/board_specific.qsf | 23 +++- boards/de2_115/board_specific.sdc | 1 + boards/de2_115/board_specific_top.sv | 121 ++++++++---------- labs/08_shift_register/lab_top.sv | 45 ++++--- .../08_fifo_with_better_debug_1/lab_top.sv | 45 ++++--- peripherals/lab_specific_board_config.svh | 6 +- 6 files changed, 121 insertions(+), 120 deletions(-) diff --git a/boards/de2_115/board_specific.qsf b/boards/de2_115/board_specific.qsf index 6613fada..8999dc7b 100644 --- a/boards/de2_115/board_specific.qsf +++ b/boards/de2_115/board_specific.qsf @@ -4,11 +4,11 @@ #----------------------------------------------------------------------------- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* - set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD -# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD + set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY* set_instance_assignment -name IO_STANDARD "2.5 V" -to SW* set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR* + set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG* set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0* set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1* @@ -26,6 +26,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7* set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART* set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO* #----------------------------------------------------------------------------- @@ -36,9 +37,6 @@ # set_location_assignment PIN_AG15 -to CLOCK3_50 set_location_assignment PIN_Y2 -to CLOCK_50 -# set_location_assignment PIN_G9 -to UART_TXD - set_location_assignment PIN_G12 -to UART_RXD - set_location_assignment PIN_M23 -to KEY[0] set_location_assignment PIN_M21 -to KEY[1] set_location_assignment PIN_N21 -to KEY[2] @@ -82,6 +80,16 @@ set_location_assignment PIN_G16 -to LEDR[16] set_location_assignment PIN_H15 -to LEDR[17] + set_location_assignment PIN_E21 -to LEDG[0] + set_location_assignment PIN_E22 -to LEDG[1] + set_location_assignment PIN_E25 -to LEDG[2] + set_location_assignment PIN_E24 -to LEDG[3] + set_location_assignment PIN_H21 -to LEDG[4] + set_location_assignment PIN_G20 -to LEDG[5] + set_location_assignment PIN_G22 -to LEDG[6] + set_location_assignment PIN_G21 -to LEDG[7] + set_location_assignment PIN_F17 -to LEDG[8] + set_location_assignment PIN_G18 -to HEX0[0] set_location_assignment PIN_F22 -to HEX0[1] set_location_assignment PIN_E17 -to HEX0[2] @@ -169,6 +177,11 @@ set_location_assignment PIN_D11 -to VGA_B[6] set_location_assignment PIN_D12 -to VGA_B[7] + set_location_assignment PIN_G14 -to UART_RTS + set_location_assignment PIN_J13 -to UART_CTS + set_location_assignment PIN_G12 -to UART_RXD + set_location_assignment PIN_G9 -to UART_TXD + set_location_assignment PIN_AB22 -to GPIO[0] set_location_assignment PIN_AC15 -to GPIO[1] set_location_assignment PIN_AB21 -to GPIO[2] diff --git a/boards/de2_115/board_specific.sdc b/boards/de2_115/board_specific.sdc index ad055607..970f5d96 100644 --- a/boards/de2_115/board_specific.sdc +++ b/boards/de2_115/board_specific.sdc @@ -9,6 +9,7 @@ derive_clock_uncertainty # set_false_path -from * -to UART_TXD set_false_path -from * -to [get_ports {LEDR[*]}] + set_false_path -from * -to [get_ports {LEDG[*]}] set_false_path -from * -to [get_ports {HEX*}] set_false_path -from * -to [get_ports {VGA_*}] set_false_path -from * -to [get_ports {GPIO[*]}] diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index bd6fb10e..dfa87332 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -1,8 +1,6 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`define USE_HIGH_LED_FOR_7SEG_DP - module board_specific_top # ( parameter clk_mhz = 50, @@ -32,7 +30,8 @@ module board_specific_top input [w_key - 1:0] KEY, input [w_sw - 1:0] SW, - output [w_led - 1:0] LEDR, // The last 8 LEDR are optionally used to output 7SEG dp + output [w_led - 1:0] LEDR, + output logic [ 8:0] LEDG, output logic [ 6:0] HEX0, // HEX[7] aka dp are not connected to FPGA at DE2-115 output logic [ 6:0] HEX1, @@ -52,18 +51,18 @@ module board_specific_top output VGA_BLANK_N, output VGA_SYNC_N, + input UART_RTS, + input UART_RXD, + + output UART_CTS, + output UART_TXD, + inout [w_gpio - 1:0] GPIO ); //------------------------------------------------------------------------ - localparam w_lab_sw = w_sw - 1; // One sw is used as a reset - - `ifdef USE_HIGH_LED_FOR_7SEG_DP - localparam w_lab_led = w_led - w_digit; - `else - localparam w_lab_led = w_led; - `endif + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset //------------------------------------------------------------------------ @@ -73,8 +72,6 @@ module board_specific_top // Keys, switches, LEDs wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; - wire [ w_key - 1:0] lab_key = ~ KEY; - wire [ w_lab_led - 1:0] lab_led; // A dynamic seven-segment display @@ -106,58 +103,53 @@ module board_specific_top lab_top # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_lab_sw ), - .w_led ( w_lab_led ), - .w_digit ( w_digit ), - .w_gpio ( w_gpio ), - - .screen_width ( screen_width ), - .screen_height ( screen_height ), - - .w_red ( w_red ), - .w_green ( w_green ), - .w_blue ( w_blue ) + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( lab_key ), - .sw ( lab_sw ), + .key ( ~ KEY ), + .sw ( lab_sw ), - .led ( lab_led ), + .led ( LEDR ), - .abcdefgh ( abcdefgh ), - .digit ( digit ), + .abcdefgh ( abcdefgh ), + .digit ( digit ), - .x ( x ), - .y ( y ), + .x ( x ), + .y ( y ), - .red ( VGA_R ), - .green ( VGA_G ), - .blue ( VGA_B ), + .red ( VGA_R ), + .green ( VGA_G ), + .blue ( VGA_B ), - .mic ( mic ), - .sound ( sound ), + .mic ( mic ), + .sound ( sound ), - .uart_rx ( ), // TODO - .uart_tx ( ), // TODO + .uart_rx ( UART_RXD ), + .uart_tx ( UART_TXD ), - .gpio ( GPIO ) + .gpio ( GPIO ) ); //------------------------------------------------------------------------ - assign LEDR [w_lab_led - 1:0] = lab_led; - - //------------------------------------------------------------------------ - - wire [$left ( abcdefgh ):0] hgfedcba; - logic [$left ( digit ):0] dp; + wire [$left (abcdefgh):0] hgfedcba; generate genvar i; @@ -193,14 +185,13 @@ module board_specific_top // positive logic - assign LEDR [ w_led - w_digit] = digit [0] ? hgfedcba [$left (HEX0) + 1] : '0; - assign LEDR [w_led - w_digit + 1] = digit [1] ? hgfedcba [$left (HEX1) + 1] : '0; - assign LEDR [w_led - w_digit + 2] = digit [2] ? hgfedcba [$left (HEX2) + 1] : '0; - assign LEDR [w_led - w_digit + 3] = digit [3] ? hgfedcba [$left (HEX3) + 1] : '0; - assign LEDR [w_led - w_digit + 4] = digit [4] ? hgfedcba [$left (HEX4) + 1] : '0; - assign LEDR [w_led - w_digit + 5] = digit [5] ? hgfedcba [$left (HEX5) + 1] : '0; - assign LEDR [w_led - w_digit + 6] = digit [6] ? hgfedcba [$left (HEX6) + 1] : '0; - assign LEDR [w_led - w_digit + 7] = digit [7] ? hgfedcba [$left (HEX7) + 1] : '0; + always_comb + begin + LEDG = '0; + + for (int i = 0; i < w_digit; i ++) + LEDG [i] = digit [i] ? hgfedcba [$left (HEX0) + 1] : '0; + end `else @@ -209,7 +200,7 @@ module board_specific_top if (rst) begin { HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 } <= '1; - dp <= '0; + LEDG <= '0; end else begin @@ -222,21 +213,11 @@ module board_specific_top if (digit [6]) HEX6 <= ~ hgfedcba [$left (HEX6):0]; if (digit [7]) HEX7 <= ~ hgfedcba [$left (HEX7):0]; - if (digit [0]) dp[0] <= hgfedcba [$left (HEX0) + 1]; - if (digit [1]) dp[1] <= hgfedcba [$left (HEX1) + 1]; - if (digit [2]) dp[2] <= hgfedcba [$left (HEX2) + 1]; - if (digit [3]) dp[3] <= hgfedcba [$left (HEX3) + 1]; - if (digit [4]) dp[4] <= hgfedcba [$left (HEX4) + 1]; - if (digit [5]) dp[5] <= hgfedcba [$left (HEX5) + 1]; - if (digit [6]) dp[6] <= hgfedcba [$left (HEX6) + 1]; - if (digit [7]) dp[7] <= hgfedcba [$left (HEX7) + 1]; + for (int i = 0; i < w_digit; i ++) + if (digit [i]) LEDG [i] <= hgfedcba [$left (HEX0) + 1]; end end - `ifdef USE_HIGH_LED_FOR_7SEG_DP - assign LEDR [w_led - 1 : w_lab_led] = dp; - `endif - `endif //------------------------------------------------------------------------ diff --git a/labs/08_shift_register/lab_top.sv b/labs/08_shift_register/lab_top.sv index 527e155d..af332d93 100644 --- a/labs/08_shift_register/lab_top.sv +++ b/labs/08_shift_register/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv b/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv index b2f587a4..96eadf30 100644 --- a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv +++ b/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/peripherals/lab_specific_board_config.svh b/peripherals/lab_specific_board_config.svh index 2dc4de3d..d65a060b 100644 --- a/peripherals/lab_specific_board_config.svh +++ b/peripherals/lab_specific_board_config.svh @@ -1,5 +1,5 @@ -`ifndef LAB_SPECIFIC_CONFIG_SVH -`define LAB_SPECIFIC_CONFIG_SVH +`ifndef LAB_SPECIFIC_BOARD_CONFIG_SVH +`define LAB_SPECIFIC_BOARD_CONFIG_SVH `define INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE // `define USE_HCW132_VARIANT_OF_TM1638_BOARD_CONTROLLER_MODULE @@ -14,7 +14,7 @@ `define INSTANTIATE_MICROPHONE_INTERFACE_MODULE `define INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE -`endif // `ifndef LAB_SPECIFIC_CONFIG_SVH +`endif // `ifndef LAB_SPECIFIC_BOARD_CONFIG_SVH // This is the default file included // when there is no lab_specific_board_config.svh From 9484030bf31f097fac76a0c87f9fb29eadb5e329 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 15:23:37 -0700 Subject: [PATCH 36/65] Made maine led in DE2-115 green LED --- .../DE2_115_GOLDEN_TOP.qsf.for_reference | 1189 +++++++++++++++++ boards/de2_115/board_specific_top.sv | 21 +- 2 files changed, 1203 insertions(+), 7 deletions(-) create mode 100644 boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference diff --git a/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference b/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference new file mode 100644 index 00000000..bd9f24e1 --- /dev/null +++ b/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference @@ -0,0 +1,1189 @@ +#============================================================ +# Build by Terasic System Builder V1.0.0 +#============================================================ + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY DE2_115_GOLDEN_TOP +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 +set_global_assignment -name LAST_QUARTUS_VERSION 12.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:02:28 JANUARY 27,2010" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name SDC_FILE DE2_115_GOLDEN_TOP.SDC + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 + + +#============================================================ +# Sma +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] + +#============================================================ +# LCD +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON + +#============================================================ +# RS232 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS + +#============================================================ +# PS2 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 + +#============================================================ +# SDCARD +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] + +#============================================================ +# Audio +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK + +#============================================================ +# I2C for EEPROM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT + +#============================================================ +# I2C for Audioand Tv-Decode 1 and 2 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT + +#============================================================ +# Ethernet 0 +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO + +#============================================================ +# Ethernet 1 +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO + + +#============================================================ +# TV Decoder +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] + +#============================================================ +# USB +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N + +#============================================================ +# IR Receiver +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] + +#============================================================ +# SRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N + +#============================================================ +# Flash +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] + +#============================================================ +# HSMC, HSMC connect to HSMC Default +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 + +#============================================================ +# HSMC, HSMC connect to HSMC Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name SOPC_BUILDER_SIGNATURE_ID 002618860F9B000001268748D130 -qip DE2_115_SOPC.qip +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name MISC_FILE "D:/svn/DE2_115_GOLDEN_TOP/DE2_115_GOLDEN_TOP.dpf" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name MISC_FILE "D:/Document/de2c4/DE2_115_GOLDEN_TOP/DE2_115_GOLDEN_TOP.dpf" + +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_C19 -to ENET0_RST_N +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D22 -to ENET1_RST_N +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_Y15 -to IRDA_RXD +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_location_assignment PIN_F7 -to TD_DATA[7] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_G6 -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_location_assignment PIN_G14 -to UART_RTS +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_D12 -to VGA_B[7] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0 +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name MISC_FILE "D:/Projects/DE2C4/trunk/test/DE2_115_GOLDEN_TOP/DE2_115_GOLDEN_TOP.dpf" +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] + +set_location_assignment PIN_J10 -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_location_assignment PIN_E10 -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_D5 -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_location_assignment PIN_A14 -to ENETCLK_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0] +set_location_assignment PIN_F14 -to EX_IO[4] +set_location_assignment PIN_J13 -to UART_CTS +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_H12 -to VGA_G[3] +set_global_assignment -name MISC_FILE "D:/Document/de2c4/de2_115_golden_top/DE2_115_GOLDEN_TOP.dpf" + +set_global_assignment -name MISC_FILE "E:/SVN/DE2_115/trunk/test/de2_115_golden_top/DE2_115_GOLDEN_TOP.dpf" +set_global_assignment -name MISC_FILE "\\\\wuhan-file1\\R3\\RD\\cd_rom\\DE2_115_v1.0.5_CDROM\\DE2_115_demonstrations\\DE2_115_golden_top\\DE2_115_GOLDEN_TOP.dpf" +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name MISC_FILE "C:/Users/Administrator/Desktop/USB/de2_115_qsys/de2_115_qsys/DE2_115_golden_top/DE2_115_GOLDEN_TOP.dpf" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index dfa87332..28593d15 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -8,7 +8,7 @@ module board_specific_top w_key = 4, w_sw = 18, - w_led = 18, + w_led = 8, w_digit = 8, w_gpio = 36, @@ -30,7 +30,7 @@ module board_specific_top input [w_key - 1:0] KEY, input [w_sw - 1:0] SW, - output [w_led - 1:0] LEDR, + output logic [ 17:0] LEDR, output logic [ 8:0] LEDG, output logic [ 6:0] HEX0, // HEX[7] aka dp are not connected to FPGA at DE2-115 @@ -72,6 +72,7 @@ module board_specific_top // Keys, switches, LEDs wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [ w_led - 1:0] lab_led; // A dynamic seven-segment display @@ -126,7 +127,7 @@ module board_specific_top .key ( ~ KEY ), .sw ( lab_sw ), - .led ( LEDR ), + .led ( lab_led ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -149,6 +150,10 @@ module board_specific_top //------------------------------------------------------------------------ + assign LEDG = { { $bits (LEDG) - w_led { 1'b0 } }, lab_led }; + + //------------------------------------------------------------------------ + wire [$left (abcdefgh):0] hgfedcba; generate @@ -187,10 +192,11 @@ module board_specific_top always_comb begin - LEDG = '0; + LEDR = '0; for (int i = 0; i < w_digit; i ++) - LEDG [i] = digit [i] ? hgfedcba [$left (HEX0) + 1] : '0; + LEDR [$bits (LEDR) - w_digit + i] + = digit [i] ? hgfedcba [$left (HEX0) + 1] : '0; end `else @@ -200,7 +206,7 @@ module board_specific_top if (rst) begin { HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 } <= '1; - LEDG <= '0; + LEDR <= '0; end else begin @@ -214,7 +220,8 @@ module board_specific_top if (digit [7]) HEX7 <= ~ hgfedcba [$left (HEX7):0]; for (int i = 0; i < w_digit; i ++) - if (digit [i]) LEDG [i] <= hgfedcba [$left (HEX0) + 1]; + if (digit [i]) + LEDR [$bits (LEDR) - w_digit + i] <= hgfedcba [$left (HEX0) + 1]; end end From 3c01c9f6be8def9d6cb6231021d1bc8599d2f510 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 16:19:12 -0700 Subject: [PATCH 37/65] Minor change in .sdc script for DE2-115 --- boards/de2_115/board_specific.sdc | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/boards/de2_115/board_specific.sdc b/boards/de2_115/board_specific.sdc index 970f5d96..4ca2cee9 100644 --- a/boards/de2_115/board_specific.sdc +++ b/boards/de2_115/board_specific.sdc @@ -2,14 +2,16 @@ create_clock -period "50.0 MHz" [get_ports CLOCK_50] derive_clock_uncertainty - set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] - set_false_path -from UART_RXD -to [all_clocks] - set_false_path -from [get_ports {SW[*]}] -to [all_clocks] - set_false_path -from [get_ports {GPIO[*]}] -to [all_clocks] +set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] +set_false_path -from [get_ports {SW[*]}] -to [all_clocks] +set_false_path -from UART_RTS -to [all_clocks] +set_false_path -from UART_RXD -to [all_clocks] +set_false_path -from [get_ports {GPIO[*]}] -to [all_clocks] -# set_false_path -from * -to UART_TXD - set_false_path -from * -to [get_ports {LEDR[*]}] - set_false_path -from * -to [get_ports {LEDG[*]}] - set_false_path -from * -to [get_ports {HEX*}] - set_false_path -from * -to [get_ports {VGA_*}] - set_false_path -from * -to [get_ports {GPIO[*]}] +set_false_path -from * -to [get_ports {LEDR[*]}] +set_false_path -from * -to [get_ports {LEDG[*]}] +set_false_path -from * -to [get_ports {HEX*}] +set_false_path -from * -to [get_ports {VGA_*}] +set_false_path -from * -to UART_CTS +set_false_path -from * -to UART_TXD +set_false_path -from * -to [get_ports {GPIO[*]}] From 7e75601f75e951a18ad2546996a72baac51a1eae Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 17:06:38 -0700 Subject: [PATCH 38/65] Started moving labs into a new structure --- .../1_01_and_or_not_xor_de_morgan}/01_clean.bash | 0 .../02_simulate_rtl.bash | 0 .../03_synthesize_for_fpga.bash | 0 .../04_configure_fpga.bash | 0 .../05_run_gui_for_fpga_synthesis.bash | 0 .../06_choose_another_fpga_board.bash | 0 .../07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 .../1_01_and_or_not_xor_de_morgan}/lab_top.sv | 0 .../1_01_and_or_not_xor_de_morgan}/tb.sv | 0 labs/{02_mux => 1_basics/1_02_mux}/01_clean.bash | 0 .../1_02_mux}/02_simulate_rtl.bash | 0 .../1_02_mux}/03_synthesize_for_fpga.bash | 0 .../1_02_mux}/04_configure_fpga.bash | 0 .../1_02_mux}/05_run_gui_for_fpga_synthesis.bash | 0 .../1_02_mux}/06_choose_another_fpga_board.bash | 0 .../1_02_mux}/07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 labs/{02_mux => 1_basics/1_02_mux}/gtkwave.tcl | 0 labs/{02_mux => 1_basics/1_02_mux}/lab_top.sv | 0 labs/{02_mux => 1_basics/1_02_mux}/tb.sv | 0 .../1_03_decoder}/01_clean.bash | 0 .../1_03_decoder}/02_simulate_rtl.bash | 0 .../1_03_decoder}/03_synthesize_for_fpga.bash | 0 .../1_03_decoder}/04_configure_fpga.bash | 0 .../05_run_gui_for_fpga_synthesis.bash | 0 .../1_03_decoder}/06_choose_another_fpga_board.bash | 0 .../1_03_decoder}/07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 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.../01_clean.bash | 0 .../02_simulate_rtl.bash | 0 .../03_synthesize_for_fpga.bash | 0 .../04_configure_fpga.bash | 0 .../05_run_gui_for_fpga_synthesis.bash | 0 .../06_choose_another_fpga_board.bash | 0 .../07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 .../ff_fifo_wrapped_in_valid_ready.sv | 0 .../flip_flop_fifo.sv | 0 .../gtkwave.tcl | 0 .../lab_top.sv | 0 .../no_starvation_priority_arbiter_2_requests.sv | 0 ...vation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv | 0 .../round_robin_arbiter_8_requests.sv | 0 .../tb.sv | 0 233 files changed, 0 insertions(+), 0 deletions(-) rename labs/{16_round_robin_arbiter => 4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter}/01_clean.bash (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter}/02_simulate_rtl.bash (100%) rename labs/{16_round_robin_arbiter => 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labs/{90_valid_ready_etc_preview/08_fifo_with_better_debug_1 => 4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2}/fifo_monitor.sv (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2}/flip_flop_fifo_empty_full_optimized_and_debug_2.sv (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/09_fifo_with_better_debug_2 => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/ff_fifo_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/flip_flop_fifo_empty_full_optimized.sv (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/ff_fifo_with_reg_empty_full.sv (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/ff_fifo_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/a_plus_b_using_fifos.sv (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/ff_fifo_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/flip_flop_fifo.sv (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/18_a_plus_b_using_fifos => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/fcr_1_single_allows_back_to_back.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/fcr_2_single_half_perf_no_comb_path.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/fcr_3_single_for_pipes_with_global_stall.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/fcr_4_wrapped_2_deep_fifo.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/fcr_5_double_buffer_from_dally_harting.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/ff_fifo_pow2_depth.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/pow_5_single_cycle.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/25_pow_5_single_cycle => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/fcr_1_single_allows_back_to_back.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/fcr_2_single_half_perf_no_comb_path.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/fcr_3_single_for_pipes_with_global_stall.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/fcr_4_wrapped_2_deep_fifo.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/fcr_5_double_buffer_from_dally_harting.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/ff_fifo_pow2_depth.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/pow_5_pipelined.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/26_pow_5_pipelined => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/pow_5_pipelined_without_flow_control.sv (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/reg_without_flow_control.sv (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/28_pow_5_pipelined_without_flow_control => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/flip_flop_fifo_with_counter.sv (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/pow_5_pipelined_with_credit_counter.sv (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/pow_5_pipelined_without_flow_control.sv (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/reg_without_flow_control.sv (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/arbiter_1_dumb_big_blob.sv (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/arbiter_2_rotate_priority_rotate_verbose.sv (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/arbiter_3_rotate_priority_case_rotate.sv (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/arbiter_4_rotate_priority_3_assigns_rotate.sv (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/arbiter_5_rotate_priority_rotate_brief.sv (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/gtkwave.tcl (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/lab_specific_board_config.svh (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/lab_top.sv (100%) rename labs/{16_round_robin_arbiter => 4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/ff_fifo_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/flip_flop_fifo.sv (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/round_robin_arbiter_2_requests.sv (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/ff_fifo_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/fixed_priority_arbiter_2_requests.sv (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/flip_flop_fifo.sv (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/tb.sv (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/01_clean.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/02_simulate_rtl.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/03_synthesize_for_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/04_configure_fpga.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/06_choose_another_fpga_board.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/07_synthesize_for_asic.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/ff_fifo_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/flip_flop_fifo.sv (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/gtkwave.tcl (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/lab_top.sv (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/no_starvation_priority_arbiter_2_requests.sv (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/round_robin_arbiter_8_requests.sv (100%) rename labs/{90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready => 4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready}/tb.sv (100%) diff --git a/labs/16_round_robin_arbiter/01_clean.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/01_clean.bash similarity index 100% rename from labs/16_round_robin_arbiter/01_clean.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/01_clean.bash diff --git a/labs/16_round_robin_arbiter/02_simulate_rtl.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/02_simulate_rtl.bash similarity index 100% rename from labs/16_round_robin_arbiter/02_simulate_rtl.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/02_simulate_rtl.bash diff --git a/labs/16_round_robin_arbiter/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/16_round_robin_arbiter/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/03_synthesize_for_fpga.bash diff --git a/labs/16_round_robin_arbiter/04_configure_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/04_configure_fpga.bash similarity index 100% rename from labs/16_round_robin_arbiter/04_configure_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/04_configure_fpga.bash diff --git a/labs/16_round_robin_arbiter/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/16_round_robin_arbiter/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/16_round_robin_arbiter/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/06_choose_another_fpga_board.bash similarity index 100% rename from labs/16_round_robin_arbiter/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/06_choose_another_fpga_board.bash diff --git a/labs/16_round_robin_arbiter/07_synthesize_for_asic.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/07_synthesize_for_asic.bash similarity index 100% rename from labs/16_round_robin_arbiter/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/07_synthesize_for_asic.bash diff --git a/labs/16_round_robin_arbiter/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/16_round_robin_arbiter/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/16_round_robin_arbiter/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/16_round_robin_arbiter/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/fifo_monitor.sv b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/fifo_monitor.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/fifo_monitor.sv rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/fifo_monitor.sv diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/flip_flop_fifo_with_counter.sv b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/flip_flop_fifo_with_counter.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/flip_flop_fifo_with_counter.sv rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/flip_flop_fifo_with_counter.sv diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/gtkwave.tcl b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/gtkwave.tcl rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/lab_top.sv rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/tb.sv b/labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/tb.sv rename to labs/4_microarchitecture/2_fifo/4_2_1_flip_flop_fifo_with_counter/tb.sv diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/01_clean.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/01_clean.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/02_simulate_rtl.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/02_simulate_rtl.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/04_configure_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/04_configure_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/07_synthesize_for_asic.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/01_flip_flop_fifo_with_counter_and_slow_clock/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/gtkwave.tcl b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/gtkwave.tcl rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/lab_top.sv b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/lab_top.sv rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/shift_register_with_valid_and_debug.sv b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/shift_register_with_valid_and_debug.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/shift_register_with_valid_and_debug.sv rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/shift_register_with_valid_and_debug.sv diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/tb.sv b/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/tb.sv rename to labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/tb.sv diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/01_clean.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/01_clean.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/02_simulate_rtl.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/02_simulate_rtl.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/04_configure_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/04_configure_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/07_synthesize_for_asic.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/07_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/07_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/fifo_monitor.sv b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/fifo_monitor.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/fifo_monitor.sv rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/fifo_monitor.sv diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/flip_flop_fifo_with_counter_and_debug_1.sv b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/flip_flop_fifo_with_counter_and_debug_1.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/flip_flop_fifo_with_counter_and_debug_1.sv rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/flip_flop_fifo_with_counter_and_debug_1.sv diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/gtkwave.tcl b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/gtkwave.tcl rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/lab_top.sv rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/tb.sv b/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/tb.sv rename to labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/tb.sv diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/01_clean.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/01_clean.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/02_simulate_rtl.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/02_simulate_rtl.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/04_configure_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/04_configure_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/07_synthesize_for_asic.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/08_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/fifo_monitor.sv b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/fifo_monitor.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/fifo_monitor.sv rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/fifo_monitor.sv diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/gtkwave.tcl b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/gtkwave.tcl rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/lab_top.sv b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/lab_top.sv rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/tb.sv b/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/tb.sv rename to labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/tb.sv diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/01_clean.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/01_clean.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/02_simulate_rtl.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/02_simulate_rtl.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/04_configure_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/04_configure_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/07_synthesize_for_asic.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/09_fifo_with_better_debug_2/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/flip_flop_fifo_empty_full_optimized.sv b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/flip_flop_fifo_empty_full_optimized.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/flip_flop_fifo_empty_full_optimized.sv rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/flip_flop_fifo_empty_full_optimized.sv diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/gtkwave.tcl rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/lab_top.sv rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/tb.sv diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/01_clean.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/01_clean.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/16_ff_fifo_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_with_reg_empty_full.sv b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_with_reg_empty_full.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_with_reg_empty_full.sv rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_with_reg_empty_full.sv diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/gtkwave.tcl rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/tb.sv diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/01_clean.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/01_clean.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/17_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/a_plus_b_using_fifos.sv b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/a_plus_b_using_fifos.sv similarity index 100% rename from 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a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/gtkwave.tcl b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/gtkwave.tcl rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/lab_top.sv b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/lab_top.sv rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/tb.sv b/labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/tb.sv rename to labs/4_microarchitecture/2_fifo/4_2_7_a_plus_b_using_fifos/tb.sv diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/01_clean.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/01_clean.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/02_simulate_rtl.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/02_simulate_rtl.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/04_configure_fpga.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/04_configure_fpga.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/05_run_gui_for_fpga_synthesis.bash rename to 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a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/18_a_plus_b_using_fifos/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_1_single_allows_back_to_back.sv b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_1_single_allows_back_to_back.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_1_single_allows_back_to_back.sv rename to labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_1_single_allows_back_to_back.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_2_single_half_perf_no_comb_path.sv b/labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_2_single_half_perf_no_comb_path.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_2_single_half_perf_no_comb_path.sv rename to labs/4_microarchitecture/3_pipelines_2/4_3_1_pow_5_single_cycle/fcr_2_single_half_perf_no_comb_path.sv diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/fcr_3_single_for_pipes_with_global_stall.sv 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rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/04_configure_fpga.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/04_configure_fpga.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/05_run_gui_for_fpga_synthesis.bash rename to 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a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/25_pow_5_single_cycle/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/3_pipelines_2/4_3_2_pow_5_pipelined/09_visualize_asic_synthesis_results_2.bash diff --git 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labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/04_configure_fpga.bash b/labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/04_configure_fpga.bash rename to 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labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/29_pow_5_pipelined_with_credit_counter/08_visualize_asic_synthesis_results_1.bash rename to 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a/labs/16_round_robin_arbiter/arbiter_2_rotate_priority_rotate_verbose.sv b/labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/arbiter_2_rotate_priority_rotate_verbose.sv similarity index 100% rename from labs/16_round_robin_arbiter/arbiter_2_rotate_priority_rotate_verbose.sv rename to labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/arbiter_2_rotate_priority_rotate_verbose.sv diff --git a/labs/16_round_robin_arbiter/arbiter_3_rotate_priority_case_rotate.sv b/labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/arbiter_3_rotate_priority_case_rotate.sv similarity index 100% rename from labs/16_round_robin_arbiter/arbiter_3_rotate_priority_case_rotate.sv rename to labs/4_microarchitecture/4_arbitration/4_4_1_round_robin_arbiter/arbiter_3_rotate_priority_case_rotate.sv diff --git a/labs/16_round_robin_arbiter/arbiter_4_rotate_priority_3_assigns_rotate.sv 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diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash rename to labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from 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b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from 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a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/40_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv similarity index 100% rename from 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100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from 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a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/41_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to 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b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to 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labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv diff --git a/labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/42_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv From 0519256d9a9b15f21addde04a49b2da7bc6cdbe4 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 17:27:47 -0700 Subject: [PATCH 40/65] Finished moving labs into a new structure --- .../2_1_rectangle_ellipse_parabola}/01_clean.bash | 0 .../02_simulate_rtl.bash | 0 .../03_synthesize_for_fpga.bash | 0 .../04_configure_fpga.bash | 0 .../05_run_gui_for_fpga_synthesis.bash | 0 .../06_choose_another_fpga_board.bash | 0 .../07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 .../2_1_rectangle_ellipse_parabola}/lab_top.sv | 0 .../2_1_rectangle_ellipse_parabola}/tb.sv | 0 .../2_2_game}/01_clean.bash | 0 .../2_2_game}/02_simulate_rtl.bash | 0 .../2_2_game}/03_synthesize_for_fpga.bash | 0 .../2_2_game}/04_configure_fpga.bash | 0 .../2_2_game}/05_run_gui_for_fpga_synthesis.bash | 0 .../2_2_game}/06_choose_another_fpga_board.bash | 0 .../2_2_game}/07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 .../2_2_game}/game_config.svh | 0 .../game_master_fsm_1_regular_state_encoded.sv | 0 .../game_master_fsm_2_special_style_one_hot.sv | 0 ...master_fsm_3_special_style_signals_from_state.sv | 0 labs/{14_game => 2_graphics/2_2_game}/game_mixer.sv | 0 .../2_2_game}/game_overlap.sv | 0 .../{14_game => 2_graphics/2_2_game}/game_random.sv | 0 .../2_2_game}/game_sprite_control.sv | 0 .../2_2_game}/game_sprite_display.sv | 0 .../2_2_game}/game_sprite_display_pipelined.sv | 0 .../2_2_game}/game_sprite_top.sv | 0 .../{14_game => 2_graphics/2_2_game}/game_strobe.sv | 0 labs/{14_game => 2_graphics/2_2_game}/game_timer.sv | 0 labs/{14_game => 2_graphics/2_2_game}/game_top.sv | 0 labs/{14_game => 2_graphics/2_2_game}/lab_top.sv | 0 labs/{14_game => 2_graphics/2_2_game}/tb.sv | 0 .../01_clean.bash | 0 .../02_simulate_rtl.bash | 0 .../03_synthesize_for_fpga.bash | 0 .../04_configure_fpga.bash | 0 .../05_run_gui_for_fpga_synthesis.bash | 0 .../06_choose_another_fpga_board.bash | 0 .../07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 .../lab_top.sv | 0 .../2_3_crash_course_basics_and_graphics}/tb.sv | 0 .../3_1_note_recognizer}/01_clean.bash | 0 .../3_1_note_recognizer}/02_simulate_rtl.bash | 0 .../03_synthesize_for_fpga.bash | 0 .../3_1_note_recognizer}/04_configure_fpga.bash | 0 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.../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 labs/{15_uart => 8_unfinished/7_1_uart}/TODO | 0 labs/{15_uart => 8_unfinished/7_1_uart}/lab_top.sv | 0 .../7_1_uart}/tb.sv | 0 .../to_integrate/check_which_port_is_used.bat | 0 .../7_1_uart}/to_integrate/drive_uart.bat | 0 .../7_1_uart}/to_integrate/hex_parser.sv | 0 .../7_1_uart}/to_integrate/lab_top.sv | 0 .../7_1_uart}/to_integrate/tb.sv | 0 .../7_1_uart}/to_integrate/top_extra.qsf | 0 .../7_1_uart}/to_integrate/top_extra.sdc | 0 .../7_1_uart}/to_integrate/uart_receiver.sv | 0 .../7_1_uart}/to_integrate/x_drive_uart.bash | 0 .../7_1_uart}/to_integrate/xx_gtkwave_extra.tcl | 0 .../01_clean.bash | 0 .../02_simulate_rtl.bash | 0 .../03_synthesize_for_fpga.bash | 0 .../04_configure_fpga.bash | 0 .../05_run_gui_for_fpga_synthesis.bash | 0 .../06_choose_another_fpga_board.bash | 0 .../07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 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labs/2_graphics/2_3_crash_course_basics_and_graphics/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/50_crash_course/lab_top.sv b/labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv similarity index 100% rename from labs/50_crash_course/lab_top.sv rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv diff --git a/labs/50_crash_course/tb.sv b/labs/2_graphics/2_3_crash_course_basics_and_graphics/tb.sv similarity index 100% rename from labs/50_crash_course/tb.sv rename to labs/2_graphics/2_3_crash_course_basics_and_graphics/tb.sv diff --git a/labs/14_game/01_clean.bash b/labs/3_music/3_1_note_recognizer/01_clean.bash similarity index 100% rename from labs/14_game/01_clean.bash rename to labs/3_music/3_1_note_recognizer/01_clean.bash diff --git a/labs/14_game/02_simulate_rtl.bash b/labs/3_music/3_1_note_recognizer/02_simulate_rtl.bash similarity index 100% rename from labs/14_game/02_simulate_rtl.bash rename to labs/3_music/3_1_note_recognizer/02_simulate_rtl.bash diff --git a/labs/14_game/03_synthesize_for_fpga.bash b/labs/3_music/3_1_note_recognizer/03_synthesize_for_fpga.bash similarity index 100% rename from labs/14_game/03_synthesize_for_fpga.bash rename to labs/3_music/3_1_note_recognizer/03_synthesize_for_fpga.bash diff --git a/labs/14_game/04_configure_fpga.bash b/labs/3_music/3_1_note_recognizer/04_configure_fpga.bash similarity index 100% rename from labs/14_game/04_configure_fpga.bash rename to labs/3_music/3_1_note_recognizer/04_configure_fpga.bash diff --git a/labs/14_game/05_run_gui_for_fpga_synthesis.bash b/labs/3_music/3_1_note_recognizer/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/14_game/05_run_gui_for_fpga_synthesis.bash rename to labs/3_music/3_1_note_recognizer/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/14_game/06_choose_another_fpga_board.bash b/labs/3_music/3_1_note_recognizer/06_choose_another_fpga_board.bash similarity index 100% rename from labs/14_game/06_choose_another_fpga_board.bash rename to labs/3_music/3_1_note_recognizer/06_choose_another_fpga_board.bash diff --git a/labs/14_game/07_synthesize_for_asic.bash b/labs/3_music/3_1_note_recognizer/07_synthesize_for_asic.bash similarity index 100% rename from labs/14_game/07_synthesize_for_asic.bash rename to labs/3_music/3_1_note_recognizer/07_synthesize_for_asic.bash diff --git a/labs/14_game/08_visualize_asic_synthesis_results_1.bash b/labs/3_music/3_1_note_recognizer/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/14_game/08_visualize_asic_synthesis_results_1.bash rename to labs/3_music/3_1_note_recognizer/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/14_game/09_visualize_asic_synthesis_results_2.bash b/labs/3_music/3_1_note_recognizer/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/14_game/09_visualize_asic_synthesis_results_2.bash rename to labs/3_music/3_1_note_recognizer/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/11_note_recognition/gtkwave.tcl b/labs/3_music/3_1_note_recognizer/gtkwave.tcl similarity index 100% rename from labs/11_note_recognition/gtkwave.tcl rename to labs/3_music/3_1_note_recognizer/gtkwave.tcl diff --git a/labs/11_note_recognition/lab_top.sv b/labs/3_music/3_1_note_recognizer/lab_top.sv similarity index 100% rename from labs/11_note_recognition/lab_top.sv rename to labs/3_music/3_1_note_recognizer/lab_top.sv diff --git a/labs/11_note_recognition/mic_waves.png b/labs/3_music/3_1_note_recognizer/mic_waves.png similarity index 100% rename from labs/11_note_recognition/mic_waves.png rename to labs/3_music/3_1_note_recognizer/mic_waves.png diff --git a/labs/11_note_recognition/music_notes.pdf b/labs/3_music/3_1_note_recognizer/music_notes.pdf similarity index 100% rename from labs/11_note_recognition/music_notes.pdf rename to labs/3_music/3_1_note_recognizer/music_notes.pdf diff --git a/labs/11_note_recognition/tb.sv b/labs/3_music/3_1_note_recognizer/tb.sv similarity index 100% rename from labs/11_note_recognition/tb.sv rename to labs/3_music/3_1_note_recognizer/tb.sv diff --git a/labs/15_uart/01_clean.bash b/labs/3_music/3_2_melody_recognizer/01_clean.bash similarity index 100% rename from labs/15_uart/01_clean.bash rename to labs/3_music/3_2_melody_recognizer/01_clean.bash diff --git a/labs/15_uart/02_simulate_rtl.bash b/labs/3_music/3_2_melody_recognizer/02_simulate_rtl.bash similarity index 100% rename from labs/15_uart/02_simulate_rtl.bash rename to labs/3_music/3_2_melody_recognizer/02_simulate_rtl.bash diff --git a/labs/15_uart/03_synthesize_for_fpga.bash b/labs/3_music/3_2_melody_recognizer/03_synthesize_for_fpga.bash similarity index 100% rename from labs/15_uart/03_synthesize_for_fpga.bash rename to labs/3_music/3_2_melody_recognizer/03_synthesize_for_fpga.bash diff --git a/labs/15_uart/04_configure_fpga.bash b/labs/3_music/3_2_melody_recognizer/04_configure_fpga.bash similarity index 100% rename from labs/15_uart/04_configure_fpga.bash rename to labs/3_music/3_2_melody_recognizer/04_configure_fpga.bash diff --git a/labs/15_uart/05_run_gui_for_fpga_synthesis.bash b/labs/3_music/3_2_melody_recognizer/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/15_uart/05_run_gui_for_fpga_synthesis.bash rename to labs/3_music/3_2_melody_recognizer/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/15_uart/06_choose_another_fpga_board.bash b/labs/3_music/3_2_melody_recognizer/06_choose_another_fpga_board.bash similarity index 100% rename from labs/15_uart/06_choose_another_fpga_board.bash rename to labs/3_music/3_2_melody_recognizer/06_choose_another_fpga_board.bash diff --git a/labs/15_uart/07_synthesize_for_asic.bash b/labs/3_music/3_2_melody_recognizer/07_synthesize_for_asic.bash similarity index 100% rename from labs/15_uart/07_synthesize_for_asic.bash rename to labs/3_music/3_2_melody_recognizer/07_synthesize_for_asic.bash diff --git a/labs/15_uart/08_visualize_asic_synthesis_results_1.bash b/labs/3_music/3_2_melody_recognizer/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/15_uart/08_visualize_asic_synthesis_results_1.bash rename to labs/3_music/3_2_melody_recognizer/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/15_uart/09_visualize_asic_synthesis_results_2.bash b/labs/3_music/3_2_melody_recognizer/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/15_uart/09_visualize_asic_synthesis_results_2.bash rename to labs/3_music/3_2_melody_recognizer/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/13_music_recognition/lab_top.sv b/labs/3_music/3_2_melody_recognizer/lab_top.sv similarity index 100% rename from labs/13_music_recognition/lab_top.sv rename to labs/3_music/3_2_melody_recognizer/lab_top.sv diff --git a/labs/13_music_recognition/music_notes.pdf b/labs/3_music/3_2_melody_recognizer/music_notes.pdf similarity index 100% rename from labs/13_music_recognition/music_notes.pdf rename to labs/3_music/3_2_melody_recognizer/music_notes.pdf diff --git a/labs/13_music_recognition/tb.sv b/labs/3_music/3_2_melody_recognizer/tb.sv similarity index 100% rename from labs/13_music_recognition/tb.sv rename to labs/3_music/3_2_melody_recognizer/tb.sv diff --git a/labs/17_geiger_muller_radiation_counter/01_clean.bash b/labs/3_music/3_3_note_synthesizer/01_clean.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/01_clean.bash rename to labs/3_music/3_3_note_synthesizer/01_clean.bash diff --git a/labs/17_geiger_muller_radiation_counter/02_simulate_rtl.bash b/labs/3_music/3_3_note_synthesizer/02_simulate_rtl.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/02_simulate_rtl.bash rename to labs/3_music/3_3_note_synthesizer/02_simulate_rtl.bash diff --git a/labs/17_geiger_muller_radiation_counter/03_synthesize_for_fpga.bash b/labs/3_music/3_3_note_synthesizer/03_synthesize_for_fpga.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/03_synthesize_for_fpga.bash rename to labs/3_music/3_3_note_synthesizer/03_synthesize_for_fpga.bash diff --git a/labs/17_geiger_muller_radiation_counter/04_configure_fpga.bash b/labs/3_music/3_3_note_synthesizer/04_configure_fpga.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/04_configure_fpga.bash rename to labs/3_music/3_3_note_synthesizer/04_configure_fpga.bash diff --git a/labs/17_geiger_muller_radiation_counter/05_run_gui_for_fpga_synthesis.bash b/labs/3_music/3_3_note_synthesizer/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/05_run_gui_for_fpga_synthesis.bash rename to labs/3_music/3_3_note_synthesizer/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/17_geiger_muller_radiation_counter/06_choose_another_fpga_board.bash b/labs/3_music/3_3_note_synthesizer/06_choose_another_fpga_board.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/06_choose_another_fpga_board.bash rename to labs/3_music/3_3_note_synthesizer/06_choose_another_fpga_board.bash diff --git a/labs/17_geiger_muller_radiation_counter/07_synthesize_for_asic.bash b/labs/3_music/3_3_note_synthesizer/07_synthesize_for_asic.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/07_synthesize_for_asic.bash rename to labs/3_music/3_3_note_synthesizer/07_synthesize_for_asic.bash diff --git a/labs/17_geiger_muller_radiation_counter/08_visualize_asic_synthesis_results_1.bash b/labs/3_music/3_3_note_synthesizer/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/08_visualize_asic_synthesis_results_1.bash rename to labs/3_music/3_3_note_synthesizer/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/17_geiger_muller_radiation_counter/09_visualize_asic_synthesis_results_2.bash b/labs/3_music/3_3_note_synthesizer/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/17_geiger_muller_radiation_counter/09_visualize_asic_synthesis_results_2.bash rename to labs/3_music/3_3_note_synthesizer/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/23_i2s_synthesizer/gen.py b/labs/3_music/3_3_note_synthesizer/gen.py similarity index 100% rename from labs/23_i2s_synthesizer/gen.py rename to labs/3_music/3_3_note_synthesizer/gen.py diff --git a/labs/23_i2s_synthesizer/gen_tone_table.sh b/labs/3_music/3_3_note_synthesizer/gen_tone_table.sh similarity index 100% rename from labs/23_i2s_synthesizer/gen_tone_table.sh rename to labs/3_music/3_3_note_synthesizer/gen_tone_table.sh diff --git a/labs/23_i2s_synthesizer/lab_top.sv b/labs/3_music/3_3_note_synthesizer/lab_top.sv similarity index 100% rename from labs/23_i2s_synthesizer/lab_top.sv rename to labs/3_music/3_3_note_synthesizer/lab_top.sv diff --git a/labs/23_i2s_synthesizer/tb.sv b/labs/3_music/3_3_note_synthesizer/tb.sv similarity index 100% rename from labs/23_i2s_synthesizer/tb.sv rename to labs/3_music/3_3_note_synthesizer/tb.sv diff --git a/labs/23_i2s_synthesizer/tone_sel.sv b/labs/3_music/3_3_note_synthesizer/tone_sel.sv similarity index 100% rename from labs/23_i2s_synthesizer/tone_sel.sv rename to labs/3_music/3_3_note_synthesizer/tone_sel.sv diff --git a/labs/23_i2s_synthesizer/tone_table.svh b/labs/3_music/3_3_note_synthesizer/tone_table.svh similarity index 100% rename from labs/23_i2s_synthesizer/tone_table.svh rename to labs/3_music/3_3_note_synthesizer/tone_table.svh diff --git a/labs/23_i2s_synthesizer/01_clean.bash b/labs/3_music/3_4_music_player/01_clean.bash similarity index 100% rename from labs/23_i2s_synthesizer/01_clean.bash rename to labs/3_music/3_4_music_player/01_clean.bash diff --git a/labs/23_i2s_synthesizer/02_simulate_rtl.bash b/labs/3_music/3_4_music_player/02_simulate_rtl.bash similarity index 100% rename from labs/23_i2s_synthesizer/02_simulate_rtl.bash rename to labs/3_music/3_4_music_player/02_simulate_rtl.bash diff --git a/labs/23_i2s_synthesizer/03_synthesize_for_fpga.bash b/labs/3_music/3_4_music_player/03_synthesize_for_fpga.bash similarity index 100% rename from labs/23_i2s_synthesizer/03_synthesize_for_fpga.bash rename to labs/3_music/3_4_music_player/03_synthesize_for_fpga.bash diff --git a/labs/23_i2s_synthesizer/04_configure_fpga.bash b/labs/3_music/3_4_music_player/04_configure_fpga.bash similarity index 100% rename from labs/23_i2s_synthesizer/04_configure_fpga.bash rename to labs/3_music/3_4_music_player/04_configure_fpga.bash diff --git a/labs/23_i2s_synthesizer/05_run_gui_for_fpga_synthesis.bash b/labs/3_music/3_4_music_player/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/23_i2s_synthesizer/05_run_gui_for_fpga_synthesis.bash rename to labs/3_music/3_4_music_player/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/23_i2s_synthesizer/06_choose_another_fpga_board.bash b/labs/3_music/3_4_music_player/06_choose_another_fpga_board.bash similarity index 100% rename from labs/23_i2s_synthesizer/06_choose_another_fpga_board.bash rename to labs/3_music/3_4_music_player/06_choose_another_fpga_board.bash diff --git a/labs/23_i2s_synthesizer/07_synthesize_for_asic.bash b/labs/3_music/3_4_music_player/07_synthesize_for_asic.bash similarity index 100% rename from labs/23_i2s_synthesizer/07_synthesize_for_asic.bash rename to labs/3_music/3_4_music_player/07_synthesize_for_asic.bash diff --git a/labs/23_i2s_synthesizer/08_visualize_asic_synthesis_results_1.bash b/labs/3_music/3_4_music_player/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/23_i2s_synthesizer/08_visualize_asic_synthesis_results_1.bash rename to labs/3_music/3_4_music_player/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/23_i2s_synthesizer/09_visualize_asic_synthesis_results_2.bash b/labs/3_music/3_4_music_player/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/23_i2s_synthesizer/09_visualize_asic_synthesis_results_2.bash rename to labs/3_music/3_4_music_player/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/24_i2s_music/gen.py b/labs/3_music/3_4_music_player/gen.py similarity index 100% rename from labs/24_i2s_music/gen.py rename to labs/3_music/3_4_music_player/gen.py diff --git a/labs/24_i2s_music/gen_tone_table.sh b/labs/3_music/3_4_music_player/gen_tone_table.sh similarity index 100% rename from labs/24_i2s_music/gen_tone_table.sh rename to labs/3_music/3_4_music_player/gen_tone_table.sh diff --git a/labs/24_i2s_music/lab_top.sv b/labs/3_music/3_4_music_player/lab_top.sv similarity index 100% rename from labs/24_i2s_music/lab_top.sv rename to labs/3_music/3_4_music_player/lab_top.sv diff --git a/labs/24_i2s_music/tb.sv b/labs/3_music/3_4_music_player/tb.sv similarity index 100% rename from labs/24_i2s_music/tb.sv rename to labs/3_music/3_4_music_player/tb.sv diff --git a/labs/24_i2s_music/tone_sel.sv b/labs/3_music/3_4_music_player/tone_sel.sv similarity index 100% rename from labs/24_i2s_music/tone_sel.sv rename to labs/3_music/3_4_music_player/tone_sel.sv diff --git a/labs/24_i2s_music/tone_table.svh b/labs/3_music/3_4_music_player/tone_table.svh similarity index 100% rename from labs/24_i2s_music/tone_table.svh rename to labs/3_music/3_4_music_player/tone_table.svh diff --git a/labs/24_i2s_music/01_clean.bash b/labs/5_cpu/5_1_schoolriscv/01_clean.bash similarity index 100% rename from labs/24_i2s_music/01_clean.bash rename to labs/5_cpu/5_1_schoolriscv/01_clean.bash diff --git a/labs/24_i2s_music/02_simulate_rtl.bash b/labs/5_cpu/5_1_schoolriscv/02_simulate_rtl.bash similarity index 100% rename from labs/24_i2s_music/02_simulate_rtl.bash rename to labs/5_cpu/5_1_schoolriscv/02_simulate_rtl.bash diff --git a/labs/24_i2s_music/03_synthesize_for_fpga.bash b/labs/5_cpu/5_1_schoolriscv/03_synthesize_for_fpga.bash similarity index 100% rename from labs/24_i2s_music/03_synthesize_for_fpga.bash rename to labs/5_cpu/5_1_schoolriscv/03_synthesize_for_fpga.bash diff --git a/labs/24_i2s_music/04_configure_fpga.bash b/labs/5_cpu/5_1_schoolriscv/04_configure_fpga.bash similarity index 100% rename from labs/24_i2s_music/04_configure_fpga.bash rename to labs/5_cpu/5_1_schoolriscv/04_configure_fpga.bash diff --git a/labs/24_i2s_music/05_run_gui_for_fpga_synthesis.bash b/labs/5_cpu/5_1_schoolriscv/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/24_i2s_music/05_run_gui_for_fpga_synthesis.bash rename to labs/5_cpu/5_1_schoolriscv/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/24_i2s_music/06_choose_another_fpga_board.bash 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--git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/01_clean.bash b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/01_clean.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/01_clean.bash rename to labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/01_clean.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash rename to labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash similarity index 100% rename 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a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/08_visualize_asic_synthesis_results_1.bash b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/08_visualize_asic_synthesis_results_1.bash rename to labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/09_visualize_asic_synthesis_results_2.bash b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/09_visualize_asic_synthesis_results_2.bash rename to labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/flip_flop_fifo.sv b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/flip_flop_fifo.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/flip_flop_fifo.sv rename to labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/flip_flop_fifo.sv diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/gtkwave.tcl similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/gtkwave.tcl rename to labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/gtkwave.tcl diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/lab_top.sv b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/lab_top.sv similarity index 100% rename from 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labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv diff --git a/labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/tb.sv similarity index 100% rename from labs/90_valid_ready_etc_preview/later/41_round_robin_arbiter_from_2_fifos/tb.sv rename to labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/tb.sv From 5cf07645ab3040d356b58c0365be61d58ea49398 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 17:33:02 -0700 Subject: [PATCH 41/65] Finished moving labs into a new structure - 2 --- .../4_1_1_pow5_single_cycle/01_clean.bash | 0 .../4_1_1_pow5_single_cycle/02_simulate_rtl.bash | 0 .../4_1_1_pow5_single_cycle/03_synthesize_for_fpga.bash | 0 .../4_1_1_pow5_single_cycle/04_configure_fpga.bash | 0 .../4_1_1_pow5_single_cycle/05_run_gui_for_fpga_synthesis.bash | 0 .../4_1_1_pow5_single_cycle/06_choose_another_fpga_board.bash | 0 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b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/01_clean.bash similarity index 100% rename from labs/4_microarchitecture/1_pipelines_1/4_1_1_pow5_single_cycle/01_clean.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/01_clean.bash diff --git a/labs/4_microarchitecture/1_pipelines_1/4_1_1_pow5_single_cycle/02_simulate_rtl.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/02_simulate_rtl.bash similarity index 100% rename from labs/4_microarchitecture/1_pipelines_1/4_1_1_pow5_single_cycle/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/02_simulate_rtl.bash diff --git a/labs/4_microarchitecture/1_pipelines_1/4_1_1_pow5_single_cycle/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/03_synthesize_for_fpga.bash similarity index 100% rename from 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a/labs/4_microarchitecture/1_pipelines_1/4_1_1_pow5_single_cycle/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/4_microarchitecture/1_pipelines_1/4_1_1_pow5_single_cycle/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/4_microarchitecture/1_pipelines_1/4_1_1_pow5_single_cycle/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/4_microarchitecture/1_pipelines_1/4_1_1_pow5_single_cycle/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/09_visualize_asic_synthesis_results_2.bash diff --git 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labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/06_choose_another_fpga_board.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/07_synthesize_for_asic.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/07_synthesize_for_asic.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/gtkwave.tcl similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/gtkwave.tcl diff --git a/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/lab_top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/lab_top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv diff --git a/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/shift_register_with_valid_and_debug.sv b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/shift_register_with_valid_and_debug.sv similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/shift_register_with_valid_and_debug.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/shift_register_with_valid_and_debug.sv diff --git a/labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/tb.sv similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_2_shift_register_to_compare/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/tb.sv diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/01_clean.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/01_clean.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/02_simulate_rtl.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/02_simulate_rtl.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/03_synthesize_for_fpga.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/03_synthesize_for_fpga.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/04_configure_fpga.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/04_configure_fpga.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/06_choose_another_fpga_board.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/06_choose_another_fpga_board.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/07_synthesize_for_asic.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/07_synthesize_for_asic.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from 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index 100% rename from labs/4_microarchitecture/2_fifo/4_2_3_fifo_with_better_debug_1/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_3_fifo_with_better_debug_1/tb.sv diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/01_clean.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/01_clean.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/02_simulate_rtl.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/02_simulate_rtl.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/03_synthesize_for_fpga.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/03_synthesize_for_fpga.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/04_configure_fpga.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/04_configure_fpga.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/06_choose_another_fpga_board.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/06_choose_another_fpga_board.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/07_synthesize_for_asic.bash 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rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/flip_flop_fifo_empty_full_optimized_and_debug_2.sv diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/gtkwave.tcl b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/gtkwave.tcl similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/gtkwave.tcl rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/gtkwave.tcl diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv diff --git a/labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/tb.sv b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/tb.sv similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_4_fifo_with_better_debug_2/tb.sv rename to labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/tb.sv diff --git a/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/01_clean.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/01_clean.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/02_simulate_rtl.bash rename to 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from labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash 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a/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/4_microarchitecture/2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to 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b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_2_requests.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_2_requests.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_2_requests.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_2_requests.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/01_clean.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/02_simulate_rtl.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/03_synthesize_for_fpga.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/04_configure_fpga.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/06_choose_another_fpga_board.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/07_synthesize_for_asic.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/ff_fifo_wrapped_in_valid_ready.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/flip_flop_fifo.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/gtkwave.tcl diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_2_requests.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/round_robin_arbiter_8_requests.sv diff --git a/labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv similarity index 100% rename from labs/4_microarchitecture/4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv rename to labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/tb.sv From 95027098488812e02bba4f72893a49eaedb5f9fe Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 18:24:30 -0700 Subject: [PATCH 42/65] Unified lab headers everywhere --- labs/1_basics/1_02_mux/lab_top.sv | 45 ++++++++-------- labs/1_basics/1_03_decoder/lab_top.sv | 45 ++++++++-------- .../1_basics/1_04_priority_encoder/lab_top.sv | 45 ++++++++-------- .../1_05_7seven_segment_letter/lab_top.sv | 45 ++++++++-------- labs/1_basics/1_06_binary_counter/lab_top.sv | 45 ++++++++-------- labs/1_basics/1_08_7segment_word/lab_top.sv | 45 ++++++++-------- labs/1_basics/1_09_hex_counter/lab_top.sv | 45 ++++++++-------- labs/1_basics/1_10_snail_fsm/lab_top.sv | 45 ++++++++-------- labs/2_graphics/2_2_game/lab_top.sv | 53 ++++++++++--------- .../lab_top.sv | 46 ++++++++-------- labs/3_music/3_2_melody_recognizer/lab_top.sv | 45 ++++++++-------- labs/3_music/3_4_music_player/lab_top.sv | 45 ++++++++-------- .../4_1_1_pow5_single_cycle/lab_top.sv | 45 ++++++++-------- .../4_1_2_pow5_pipelined/lab_top.sv | 45 ++++++++-------- .../4_1_3_pow5_pipelined_valid/lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../4_2_4_fifo_with_better_debug_2/lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../4_2_7_a_plus_b_using_fifos/lab_top.sv | 45 ++++++++-------- .../4_3_1_pow_5_single_cycle/lab_top.sv | 45 ++++++++-------- .../4_3_2_pow_5_pipelined/lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../4_4_1_round_robin_arbiter/lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- labs/5_cpu/5_1_schoolriscv/lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- labs/8_unfinished/7_1_uart/lab_top.sv | 47 ++++++++-------- .../lab_top.sv | 45 ++++++++-------- 35 files changed, 847 insertions(+), 739 deletions(-) diff --git a/labs/1_basics/1_02_mux/lab_top.sv b/labs/1_basics/1_02_mux/lab_top.sv index a2cd1722..d46a5fb3 100644 --- a/labs/1_basics/1_02_mux/lab_top.sv +++ b/labs/1_basics/1_02_mux/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/1_basics/1_03_decoder/lab_top.sv b/labs/1_basics/1_03_decoder/lab_top.sv index cb6ff387..f9e8f378 100644 --- a/labs/1_basics/1_03_decoder/lab_top.sv +++ b/labs/1_basics/1_03_decoder/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/1_basics/1_04_priority_encoder/lab_top.sv b/labs/1_basics/1_04_priority_encoder/lab_top.sv index 45791e32..f42a1c00 100644 --- a/labs/1_basics/1_04_priority_encoder/lab_top.sv +++ b/labs/1_basics/1_04_priority_encoder/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/1_basics/1_05_7seven_segment_letter/lab_top.sv b/labs/1_basics/1_05_7seven_segment_letter/lab_top.sv index 60948ce0..19f4d02a 100644 --- a/labs/1_basics/1_05_7seven_segment_letter/lab_top.sv +++ b/labs/1_basics/1_05_7seven_segment_letter/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/1_basics/1_06_binary_counter/lab_top.sv b/labs/1_basics/1_06_binary_counter/lab_top.sv index 7b31b334..aec29cec 100644 --- a/labs/1_basics/1_06_binary_counter/lab_top.sv +++ b/labs/1_basics/1_06_binary_counter/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; assign abcdefgh = '0; assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/1_basics/1_08_7segment_word/lab_top.sv b/labs/1_basics/1_08_7segment_word/lab_top.sv index 5a2070db..3b9edea4 100644 --- a/labs/1_basics/1_08_7segment_word/lab_top.sv +++ b/labs/1_basics/1_08_7segment_word/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/1_basics/1_09_hex_counter/lab_top.sv b/labs/1_basics/1_09_hex_counter/lab_top.sv index 7098c712..c4c97265 100644 --- a/labs/1_basics/1_09_hex_counter/lab_top.sv +++ b/labs/1_basics/1_09_hex_counter/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/1_basics/1_10_snail_fsm/lab_top.sv b/labs/1_basics/1_10_snail_fsm/lab_top.sv index 56abf527..6f869d09 100644 --- a/labs/1_basics/1_10_snail_fsm/lab_top.sv +++ b/labs/1_basics/1_10_snail_fsm/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/2_graphics/2_2_game/lab_top.sv b/labs/2_graphics/2_2_game/lab_top.sv index 49cf0eb9..d139191b 100644 --- a/labs/2_graphics/2_2_game/lab_top.sv +++ b/labs/2_graphics/2_2_game/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,47 +35,46 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio ); - localparam strobe_to_update_xy_counter_width - = $clog2 (clk_mhz * 1000 * 1000) - 6; - //------------------------------------------------------------------------ assign led = '0; assign abcdefgh = '0; assign digit = '0; - // assign vsync = '0; - // assign hsync = '0; // assign red = '0; // assign green = '0; // assign blue = '0; - // assign display_on = '0; - // assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; //------------------------------------------------------------------------ + localparam strobe_to_update_xy_counter_width + = $clog2 (clk_mhz * 1000 * 1000) - 6; + + //------------------------------------------------------------------------ + wire [2:0] rgb; game_top diff --git a/labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv b/labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv index a81f3310..32bb2200 100644 --- a/labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv +++ b/labs/2_graphics/2_3_crash_course_basics_and_graphics/lab_top.sv @@ -2,17 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -30,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -56,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - // assign vsync = '0; - // assign hsync = '0; // assign red = '0; // assign green = '0; // assign blue = '0; - // assign display_on = '0; - // assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/3_music/3_2_melody_recognizer/lab_top.sv b/labs/3_music/3_2_melody_recognizer/lab_top.sv index 3a9fd20e..cfa43142 100644 --- a/labs/3_music/3_2_melody_recognizer/lab_top.sv +++ b/labs/3_music/3_2_melody_recognizer/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/3_music/3_4_music_player/lab_top.sv b/labs/3_music/3_4_music_player/lab_top.sv index af184520..7ccf650c 100644 --- a/labs/3_music/3_4_music_player/lab_top.sv +++ b/labs/3_music/3_4_music_player/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; // assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/lab_top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/lab_top.sv index f4364811..93ee9e29 100644 --- a/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/lab_top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_1_pow5_single_cycle/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/lab_top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/lab_top.sv index a533ff2d..e45d1217 100644 --- a/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/lab_top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_2_pow5_pipelined/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/lab_top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/lab_top.sv index de45b99b..dc1fd221 100644 --- a/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/lab_top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_3_pow5_pipelined_valid/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/lab_top.sv b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/lab_top.sv index 8126c399..0ad3927a 100644 --- a/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/lab_top.sv +++ b/labs/4_microarchitecture/4_1_pipelines_1/4_1_4_pow5_pipelined_valid_solution/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv index 7cc179a3..90ba70b0 100644 --- a/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_1_flip_flop_fifo_with_counter/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv index 96aa28d4..7acaff50 100644 --- a/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_2_shift_register_to_compare/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv index 606b8ee7..3fffcc8c 100644 --- a/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_4_fifo_with_better_debug_2/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv index 2ccf6e74..f67ffae6 100644 --- a/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_5_ff_fifo_wrapped_in_valid_ready/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv index 2ccf6e74..f67ffae6 100644 --- a/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_6_ff_fifo_with_reg_empty_full_wrapped_in_valid_ready/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv index f81ca417..c648e020 100644 --- a/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv +++ b/labs/4_microarchitecture/4_2_fifo/4_2_7_a_plus_b_using_fifos/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/lab_top.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/lab_top.sv index 5f8dbbed..5e620e99 100644 --- a/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/lab_top.sv +++ b/labs/4_microarchitecture/4_3_pipelines_2/4_3_1_pow_5_single_cycle/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/lab_top.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/lab_top.sv index 77659af3..07ddcad0 100644 --- a/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/lab_top.sv +++ b/labs/4_microarchitecture/4_3_pipelines_2/4_3_2_pow_5_pipelined/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/lab_top.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/lab_top.sv index 6b82b4c1..147a327b 100644 --- a/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/lab_top.sv +++ b/labs/4_microarchitecture/4_3_pipelines_2/4_3_3_pow_5_pipelined_without_flow_control/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/lab_top.sv b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/lab_top.sv index 901a08f0..b00b6d4f 100644 --- a/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/lab_top.sv +++ b/labs/4_microarchitecture/4_3_pipelines_2/4_3_4_pow_5_pipelined_with_credit_counter/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_top.sv index 13cdbdba..74f09831 100644 --- a/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_top.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_1_round_robin_arbiter/lab_top.sv @@ -6,16 +6,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -33,22 +39,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -59,13 +66,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index ddeeb42a..d631f4d7 100644 --- a/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_2_round_robin_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index 87b12574..7f4144fb 100644 --- a/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_3_fixed_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv index 8ddb10ab..c7bf95d3 100644 --- a/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv +++ b/labs/4_microarchitecture/4_4_arbitration/4_4_4_no_starvation_priority_arbiter_from_2_fifos_wrapped_in_valid_ready/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/5_cpu/5_1_schoolriscv/lab_top.sv b/labs/5_cpu/5_1_schoolriscv/lab_top.sv index 15fe3c29..b9e57eae 100644 --- a/labs/5_cpu/5_1_schoolriscv/lab_top.sv +++ b/labs/5_cpu/5_1_schoolriscv/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_top.sv b/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_top.sv index 70234c9c..0bd84ae7 100644 --- a/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_top.sv +++ b/labs/6_misc/6_1_geiger_muller_radiation_counter/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/lab_top.sv b/labs/7_homework/1_serial_adder_using_logic_operations_only/lab_top.sv index eb2bc8c7..6f6fc281 100644 --- a/labs/7_homework/1_serial_adder_using_logic_operations_only/lab_top.sv +++ b/labs/7_homework/1_serial_adder_using_logic_operations_only/lab_top.sv @@ -4,16 +4,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -31,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -57,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/8_unfinished/7_1_uart/lab_top.sv b/labs/8_unfinished/7_1_uart/lab_top.sv index 56abf527..63b9eee7 100644 --- a/labs/8_unfinished/7_1_uart/lab_top.sv +++ b/labs/8_unfinished/7_1_uart/lab_top.sv @@ -1,17 +1,25 @@ `include "config.svh" +`ifndef SIMULATION + module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +37,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +64,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; diff --git a/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/lab_top.sv b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/lab_top.sv index ddeeb42a..d631f4d7 100644 --- a/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/lab_top.sv +++ b/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/lab_top.sv @@ -2,16 +2,22 @@ module lab_top # ( - parameter clk_mhz = 50, - pixel_mhz = 25, - w_key = 4, - w_sw = 8, - w_led = 8, - w_digit = 8, - w_gpio = 100, - w_red = 4, - w_green = 4, - w_blue = 4 + parameter clk_mhz = 50, + w_key = 4, + w_sw = 8, + w_led = 8, + w_digit = 8, + w_gpio = 100, + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input clk, @@ -29,22 +35,23 @@ module lab_top output logic [ 7:0] abcdefgh, output logic [w_digit - 1:0] digit, - // VGA + // Graphics + + input [w_x - 1:0] x, + input [w_y - 1:0] y, - output logic vsync, - output logic hsync, output logic [w_red - 1:0] red, output logic [w_green - 1:0] green, output logic [w_blue - 1:0] blue, - output display_on, - output pixel_clk, - input uart_rx, - output uart_tx, + // Microphone, sound output and UART input [ 23:0] mic, output [ 15:0] sound, + input uart_rx, + output uart_tx, + // General-purpose Input/Output inout [w_gpio - 1:0] gpio @@ -55,13 +62,9 @@ module lab_top // assign led = '0; // assign abcdefgh = '0; // assign digit = '0; - assign vsync = '0; - assign hsync = '0; assign red = '0; assign green = '0; assign blue = '0; - assign display_on = '0; - assign pixel_clk = '0; assign sound = '0; assign uart_tx = '1; From fda4d0d5579796c3b06a4dbd9eda690ae4a3fb79 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 18:28:06 -0700 Subject: [PATCH 43/65] More renaming --- .../01_clean.bash | 0 .../02_03_serial_adder_using_logic_operations_only.sv | 0 .../02_simulate_rtl.bash | 0 .../03_synthesize_for_fpga.bash | 0 .../04_configure_fpga.bash | 0 .../05_run_gui_for_fpga_synthesis.bash | 0 .../06_choose_another_fpga_board.bash | 0 .../07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 .../expected_log.txt | 0 .../gtkwave.tcl | 0 .../lab_top.sv | 0 .../tb.sv | 0 labs/8_unfinished/{7_1_uart => 8_1_uart}/01_clean.bash | 0 labs/8_unfinished/{7_1_uart => 8_1_uart}/02_simulate_rtl.bash | 0 .../{7_1_uart => 8_1_uart}/03_synthesize_for_fpga.bash | 0 labs/8_unfinished/{7_1_uart => 8_1_uart}/04_configure_fpga.bash | 0 .../{7_1_uart => 8_1_uart}/05_run_gui_for_fpga_synthesis.bash | 0 .../{7_1_uart => 8_1_uart}/06_choose_another_fpga_board.bash | 0 .../{7_1_uart => 8_1_uart}/07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 labs/8_unfinished/{7_1_uart => 8_1_uart}/TODO | 0 labs/8_unfinished/{7_1_uart => 8_1_uart}/lab_top.sv | 0 labs/8_unfinished/{7_1_uart => 8_1_uart}/tb.sv | 0 .../to_integrate/check_which_port_is_used.bat | 0 .../{7_1_uart => 8_1_uart}/to_integrate/drive_uart.bat | 0 .../{7_1_uart => 8_1_uart}/to_integrate/hex_parser.sv | 0 labs/8_unfinished/{7_1_uart => 8_1_uart}/to_integrate/lab_top.sv | 0 labs/8_unfinished/{7_1_uart => 8_1_uart}/to_integrate/tb.sv | 0 .../{7_1_uart => 8_1_uart}/to_integrate/top_extra.qsf | 0 .../{7_1_uart => 8_1_uart}/to_integrate/top_extra.sdc | 0 .../{7_1_uart => 8_1_uart}/to_integrate/uart_receiver.sv | 0 .../{7_1_uart => 8_1_uart}/to_integrate/x_drive_uart.bash | 0 .../{7_1_uart => 8_1_uart}/to_integrate/xx_gtkwave_extra.tcl | 0 .../01_clean.bash | 0 .../02_simulate_rtl.bash | 0 .../03_synthesize_for_fpga.bash | 0 .../04_configure_fpga.bash | 0 .../05_run_gui_for_fpga_synthesis.bash | 0 .../06_choose_another_fpga_board.bash | 0 .../07_synthesize_for_asic.bash | 0 .../08_visualize_asic_synthesis_results_1.bash | 0 .../09_visualize_asic_synthesis_results_2.bash | 0 .../flip_flop_fifo.sv | 0 .../gtkwave.tcl | 0 .../lab_top.sv | 0 .../round_robin_arbiter_2_requests.sv | 0 .../round_robin_arbiter_from_2_fifos.sv | 0 .../tb.sv | 0 51 files changed, 0 insertions(+), 0 deletions(-) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/01_clean.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/02_03_serial_adder_using_logic_operations_only.sv (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/02_simulate_rtl.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/03_synthesize_for_fpga.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/04_configure_fpga.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/06_choose_another_fpga_board.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/07_synthesize_for_asic.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/expected_log.txt (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/gtkwave.tcl (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/lab_top.sv (100%) rename labs/7_homework/{1_serial_adder_using_logic_operations_only => 7_1_serial_adder_using_logic_operations_only}/tb.sv (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/01_clean.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/02_simulate_rtl.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/03_synthesize_for_fpga.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/04_configure_fpga.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/05_run_gui_for_fpga_synthesis.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/06_choose_another_fpga_board.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/07_synthesize_for_asic.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/08_visualize_asic_synthesis_results_1.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/09_visualize_asic_synthesis_results_2.bash (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/TODO (100%) rename labs/8_unfinished/{7_1_uart => 8_1_uart}/lab_top.sv (100%) rename labs/8_unfinished/{7_1_uart => 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a/labs/7_homework/1_serial_adder_using_logic_operations_only/01_clean.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/01_clean.bash similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/01_clean.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/01_clean.bash diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/02_03_serial_adder_using_logic_operations_only.sv b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/02_03_serial_adder_using_logic_operations_only.sv similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/02_03_serial_adder_using_logic_operations_only.sv rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/02_03_serial_adder_using_logic_operations_only.sv diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/02_simulate_rtl.bash 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rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/04_configure_fpga.bash diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/05_run_gui_for_fpga_synthesis.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/05_run_gui_for_fpga_synthesis.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/05_run_gui_for_fpga_synthesis.bash diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/06_choose_another_fpga_board.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/06_choose_another_fpga_board.bash similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/06_choose_another_fpga_board.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/06_choose_another_fpga_board.bash diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/07_synthesize_for_asic.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/07_synthesize_for_asic.bash similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/07_synthesize_for_asic.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/07_synthesize_for_asic.bash diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/08_visualize_asic_synthesis_results_1.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/08_visualize_asic_synthesis_results_1.bash similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/08_visualize_asic_synthesis_results_1.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/08_visualize_asic_synthesis_results_1.bash diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/09_visualize_asic_synthesis_results_2.bash b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/09_visualize_asic_synthesis_results_2.bash similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/09_visualize_asic_synthesis_results_2.bash rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/09_visualize_asic_synthesis_results_2.bash diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/expected_log.txt b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/expected_log.txt similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/expected_log.txt rename to labs/7_homework/7_1_serial_adder_using_logic_operations_only/expected_log.txt diff --git a/labs/7_homework/1_serial_adder_using_logic_operations_only/gtkwave.tcl b/labs/7_homework/7_1_serial_adder_using_logic_operations_only/gtkwave.tcl similarity index 100% rename from labs/7_homework/1_serial_adder_using_logic_operations_only/gtkwave.tcl rename to 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a/labs/8_unfinished/7_1_uart/02_simulate_rtl.bash b/labs/8_unfinished/8_1_uart/02_simulate_rtl.bash similarity index 100% rename from labs/8_unfinished/7_1_uart/02_simulate_rtl.bash rename to labs/8_unfinished/8_1_uart/02_simulate_rtl.bash diff --git a/labs/8_unfinished/7_1_uart/03_synthesize_for_fpga.bash b/labs/8_unfinished/8_1_uart/03_synthesize_for_fpga.bash similarity index 100% rename from labs/8_unfinished/7_1_uart/03_synthesize_for_fpga.bash rename to labs/8_unfinished/8_1_uart/03_synthesize_for_fpga.bash diff --git a/labs/8_unfinished/7_1_uart/04_configure_fpga.bash b/labs/8_unfinished/8_1_uart/04_configure_fpga.bash similarity index 100% rename from labs/8_unfinished/7_1_uart/04_configure_fpga.bash rename to labs/8_unfinished/8_1_uart/04_configure_fpga.bash diff --git a/labs/8_unfinished/7_1_uart/05_run_gui_for_fpga_synthesis.bash b/labs/8_unfinished/8_1_uart/05_run_gui_for_fpga_synthesis.bash similarity index 100% rename from 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diff --git a/labs/8_unfinished/7_1_uart/to_integrate/check_which_port_is_used.bat b/labs/8_unfinished/8_1_uart/to_integrate/check_which_port_is_used.bat similarity index 100% rename from labs/8_unfinished/7_1_uart/to_integrate/check_which_port_is_used.bat rename to labs/8_unfinished/8_1_uart/to_integrate/check_which_port_is_used.bat diff --git a/labs/8_unfinished/7_1_uart/to_integrate/drive_uart.bat b/labs/8_unfinished/8_1_uart/to_integrate/drive_uart.bat similarity index 100% rename from labs/8_unfinished/7_1_uart/to_integrate/drive_uart.bat rename to labs/8_unfinished/8_1_uart/to_integrate/drive_uart.bat diff --git a/labs/8_unfinished/7_1_uart/to_integrate/hex_parser.sv b/labs/8_unfinished/8_1_uart/to_integrate/hex_parser.sv similarity index 100% rename from labs/8_unfinished/7_1_uart/to_integrate/hex_parser.sv rename to labs/8_unfinished/8_1_uart/to_integrate/hex_parser.sv diff --git a/labs/8_unfinished/7_1_uart/to_integrate/lab_top.sv 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b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/01_clean.bash similarity index 100% rename from labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/01_clean.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/01_clean.bash diff --git a/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash similarity index 100% rename from labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/02_simulate_rtl.bash diff --git a/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash similarity index 100% rename from labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/03_synthesize_for_fpga.bash rename to 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labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_2_requests.sv rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_2_requests.sv diff --git a/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv similarity index 100% rename from labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/round_robin_arbiter_from_2_fifos.sv diff --git a/labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/tb.sv b/labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/tb.sv similarity index 100% rename from labs/8_unfinished/7_2_round_robin_arbiter_from_2_fifos/tb.sv rename to labs/8_unfinished/8_2_round_robin_arbiter_from_2_fifos/tb.sv From 44c5bdea18f609cb396de05acce4f44c48b07e9d Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 19:24:23 -0700 Subject: [PATCH 44/65] Run dos2unix --- .../board_specific.cst | 10 +- .../board_specific_top.sv | 234 +- boards/tang_primer_20k_dock_alt/dvi_tx.ipc | 32 +- boards/tang_primer_20k_dock_alt/dvi_tx.v | 2250 +++--- boards/tang_primer_20k_dock_alt/dvi_tx.vo | 6738 ++++++++--------- .../tang_primer_20k_dock_alt/gowin_rpll.ipc | 48 +- .../tang_primer_20k_dock_alt/gowin_rpll.mod | 62 +- boards/tang_primer_20k_dock_alt/gowin_rpll.v | 128 +- 8 files changed, 4751 insertions(+), 4751 deletions(-) diff --git a/boards/tang_primer_20k_dock_alt/board_specific.cst b/boards/tang_primer_20k_dock_alt/board_specific.cst index 5eeb82cb..472cbfd0 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific.cst +++ b/boards/tang_primer_20k_dock_alt/board_specific.cst @@ -137,8 +137,8 @@ IO_PORT "GPIO_0[1]" IO_TYPE=LVCMOS33; IO_LOC "GPIO_0[0]" T6; IO_PORT "GPIO_0[0]" IO_TYPE=LVCMOS33; -// HDMI Output -IO_LOC "tmds_d_p[0]" H14,H16; -IO_LOC "tmds_d_p[1]" J15,K16; -IO_LOC "tmds_d_p[2]" K14,K15; -IO_LOC "tmds_clk_p" G16,H15; +// HDMI Output +IO_LOC "tmds_d_p[0]" H14,H16; +IO_LOC "tmds_d_p[1]" J15,K16; +IO_LOC "tmds_d_p[2]" K14,K15; +IO_LOC "tmds_clk_p" G16,H15; diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 7c638bce..981a5c08 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -1,12 +1,12 @@ `include "config.svh" `include "lab_specific_board_config.svh" - -// `define ENABLE_VGA16 -// `define ENABLE_VGA666 - `undef ENABLE_VGA16 - `define ENABLE_HDMI - -`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + +// `define ENABLE_VGA16 +// `define ENABLE_VGA666 + `undef ENABLE_VGA16 + `define ENABLE_HDMI + +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( @@ -29,16 +29,16 @@ module board_specific_top output [w_led - 1:0] LED, inout [w_gpio / 4 - 1:0] GPIO_0, - inout [w_gpio / 4 - 1:0] GPIO_1, + inout [w_gpio / 4 - 1:0] GPIO_1, inout [w_gpio / 4 - 1:0] GPIO_2, - inout [w_gpio / 4 - 1:0] GPIO_3 - + inout [w_gpio / 4 - 1:0] GPIO_3 + `ifdef ENABLE_HDMI - , output tmds_clk_n - , output tmds_clk_p - , output [ 2:0] tmds_d_n - , output [ 2:0] tmds_d_p -`endif + , output tmds_clk_n + , output tmds_clk_p + , output [ 2:0] tmds_d_n + , output [ 2:0] tmds_d_p +`endif ); wire clk = CLK; @@ -69,27 +69,27 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef ENABLE_VGA16 - localparam w_lab_red = 5, - w_lab_green = 6, - w_lab_blue = 5; - `elsif ENABLE_VGA666 - localparam w_lab_red = 6, - w_lab_green = 6, - w_lab_blue = 6; - `elsif ENABLE_HDMI - localparam vid_clk_mhz = 125, - w_lab_red = 8, - w_lab_green = 8, - w_lab_blue = 8; - `else - localparam w_lab_red = 4, - w_lab_green = 4, - w_lab_blue = 4; - `endif - - //------------------------------------------------------------------------ - + `ifdef ENABLE_VGA16 + localparam w_lab_red = 5, + w_lab_green = 6, + w_lab_blue = 5; + `elsif ENABLE_VGA666 + localparam w_lab_red = 6, + w_lab_green = 6, + w_lab_blue = 6; + `elsif ENABLE_HDMI + localparam vid_clk_mhz = 125, + w_lab_red = 8, + w_lab_green = 8, + w_lab_blue = 8; + `else + localparam w_lab_red = 4, + w_lab_green = 4, + w_lab_blue = 4; + `endif + + //------------------------------------------------------------------------ + wire [w_tm_key - 1:0] tm_key; wire [w_tm_led - 1:0] tm_led; wire [w_tm_digit - 1:0] tm_digit; @@ -103,15 +103,15 @@ module board_specific_top wire [ 7:0] abcdefgh; wire [ 23:0] mic; - //------------------------------------------------------------------------ - - wire clk_hdl; - wire clk_hd; - wire clk_px; - wire pll_lock; - wire sys_resetn; - wire display_on; - + //------------------------------------------------------------------------ + + wire clk_hdl; + wire clk_hd; + wire clk_px; + wire pll_lock; + wire sys_resetn; + wire display_on; + wire VGA_HS; wire VGA_VS; @@ -120,25 +120,25 @@ module board_specific_top logic [ w_lab_blue - 1:0] VGA_B; //------------------------------------------------------------------------ - - `ifdef ENABLE_HDMI - BUFG clHD(.I(clk_hdl), .O(clk_hd)); - - Gowin_rPLL hdPLL( - .clkout( clk_hdl ), //output clkout - .clkin ( clk ), //input clkin - .lock ( pll_lock ) - ); - `endif - //------------------------------------------------------------------------ + + `ifdef ENABLE_HDMI + BUFG clHD(.I(clk_hdl), .O(clk_hd)); + + Gowin_rPLL hdPLL( + .clkout( clk_hdl ), //output clkout + .clkin ( clk ), //input clkin + .lock ( pll_lock ) + ); + `endif + //------------------------------------------------------------------------ `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE - `ifdef ENABLE_HDMI - assign rst = ~ ( ~tm_key[w_tm_key - 1] & pll_lock ); - `else - assign rst = tm_key [w_tm_key - 1]; - `endif + `ifdef ENABLE_HDMI + assign rst = ~ ( ~tm_key[w_tm_key - 1] & pll_lock ); + `else + assign rst = tm_key [w_tm_key - 1]; + `endif assign lab_key = tm_key [w_tm_key - 1:0]; assign lab_sw = ~ SW; @@ -147,11 +147,11 @@ module board_specific_top `else // TM1638 module is not connected - `ifdef ENABLE_HDMI - assign rst = ~ ( KEY[w_key - 1] & pll_lock ); - `else - assign rst = ~KEY[w_key - 1]; - `endif + `ifdef ENABLE_HDMI + assign rst = ~ ( KEY[w_key - 1] & pll_lock ); + `else + assign rst = ~KEY[w_key - 1]; + `endif assign lab_key = ~ KEY [w_key - 1:0]; assign lab_sw = ~ SW; @@ -159,7 +159,7 @@ module board_specific_top `endif - //------------------------------------------------------------------------ + //------------------------------------------------------------------------ wire slow_clk; @@ -170,26 +170,26 @@ module board_specific_top lab_top # ( -`ifdef ENABLE_HDMI - .clk_mhz ( vid_clk_mhz ), -`else - .clk_mhz ( clk_mhz ), -`endif +`ifdef ENABLE_HDMI + .clk_mhz ( vid_clk_mhz ), +`else + .clk_mhz ( clk_mhz ), +`endif .w_key ( w_lab_key ), // The last key is used for a reset .w_sw ( w_lab_sw ), .w_led ( w_lab_led ), .w_digit ( w_lab_digit ), - .w_gpio ( w_gpio ), - .w_red ( w_lab_red ), - .w_green ( w_lab_green ), - .w_blue ( w_lab_blue ) + .w_gpio ( w_gpio ), + .w_red ( w_lab_red ), + .w_green ( w_lab_green ), + .w_blue ( w_lab_blue ) ) i_lab_top - ( -`ifdef ENABLE_HDMI - .clk ( clk_hd ), + ( +`ifdef ENABLE_HDMI + .clk ( clk_hd ), `else - .clk ( clk ), + .clk ( clk ), `endif .slow_clk ( slow_clk ), .rst ( rst ), @@ -207,8 +207,8 @@ module board_specific_top .red ( VGA_R ), .green ( VGA_G ), - .blue ( VGA_B ), - .display_on( display_on ), + .blue ( VGA_B ), + .display_on( display_on ), .pixel_clk ( clk_px ), .uart_rx ( UART_RX ), @@ -268,40 +268,40 @@ module board_specific_top // assign GPIO_3 = {VGA_B, VGA_R}; // assign GPIO_2 = {VGA_HS, VGA_VS, 2'bz, VGA_G}; - `ifdef ENABLE_VGA16 - - assign GPIO_3 = {2'bz, VGA_R[3], VGA_R[1], 2'bz, VGA_R[4], VGA_R[2]}; - assign GPIO_2 = {VGA_G[5], VGA_G[3], VGA_G[1], VGA_B[4], VGA_R[0], VGA_G[4], VGA_G[2], VGA_G[0]}; - assign GPIO_1 = {VGA_B[2], VGA_B[0], VGA_HS, 1'bz, VGA_B[3], VGA_B[1], VGA_VS, 1'bz}; - - `elsif ENABLE_VGA666 - - assign GPIO_3 = { VGA_G[4], VGA_G[5], VGA_R[2], VGA_B[4], VGA_VS, VGA_HS, VGA_B[0], VGA_R[1] }; - assign GPIO_2 = { VGA_B[3], VGA_G[2], VGA_R[0], VGA_R[4], VGA_G[0], VGA_B[5], VGA_G[1], VGA_B[1] }; - assign GPIO_1 = { VGA_R[5], 3'bz, VGA_B[2], VGA_G[3], VGA_R[3], 1'bz }; - - `elsif ENABLE_HDMI - DVI_TX_Top myDVI( - .I_rst_n ( ~rst ), //input I_rst_n - .I_serial_clk ( clk_hd ), //input I_serial_clk - .I_rgb_clk ( clk_px ), //input I_rgb_clk - .I_rgb_vs ( ~VGA_VS ), //input I_rgb_vs - .I_rgb_hs ( ~VGA_HS ), //input I_rgb_hs - .I_rgb_de ( display_on ), //input I_rgb_de - .I_rgb_r ( VGA_R ), //input [7:0] I_rgb_r - .I_rgb_g ( VGA_G ), //input [7:0] I_rgb_g - .I_rgb_b ( VGA_B ), //input [7:0] I_rgb_b - .O_tmds_clk_p ( tmds_clk_p ), //output O_tmds_clk_p - .O_tmds_clk_n ( tmds_clk_n ), //output O_tmds_clk_n - .O_tmds_data_p( tmds_d_p ), //output [2:0] O_tmds_data_p - .O_tmds_data_n( tmds_d_n ) //output [2:0] O_tmds_data_n - ); - - `else - - assign GPIO_2 = { VGA_B, VGA_R }; - assign GPIO_3 = { 2'bz, VGA_VS, VGA_HS, VGA_G }; - - `endif + `ifdef ENABLE_VGA16 + + assign GPIO_3 = {2'bz, VGA_R[3], VGA_R[1], 2'bz, VGA_R[4], VGA_R[2]}; + assign GPIO_2 = {VGA_G[5], VGA_G[3], VGA_G[1], VGA_B[4], VGA_R[0], VGA_G[4], VGA_G[2], VGA_G[0]}; + assign GPIO_1 = {VGA_B[2], VGA_B[0], VGA_HS, 1'bz, VGA_B[3], VGA_B[1], VGA_VS, 1'bz}; + + `elsif ENABLE_VGA666 + + assign GPIO_3 = { VGA_G[4], VGA_G[5], VGA_R[2], VGA_B[4], VGA_VS, VGA_HS, VGA_B[0], VGA_R[1] }; + assign GPIO_2 = { VGA_B[3], VGA_G[2], VGA_R[0], VGA_R[4], VGA_G[0], VGA_B[5], VGA_G[1], VGA_B[1] }; + assign GPIO_1 = { VGA_R[5], 3'bz, VGA_B[2], VGA_G[3], VGA_R[3], 1'bz }; + + `elsif ENABLE_HDMI + DVI_TX_Top myDVI( + .I_rst_n ( ~rst ), //input I_rst_n + .I_serial_clk ( clk_hd ), //input I_serial_clk + .I_rgb_clk ( clk_px ), //input I_rgb_clk + .I_rgb_vs ( ~VGA_VS ), //input I_rgb_vs + .I_rgb_hs ( ~VGA_HS ), //input I_rgb_hs + .I_rgb_de ( display_on ), //input I_rgb_de + .I_rgb_r ( VGA_R ), //input [7:0] I_rgb_r + .I_rgb_g ( VGA_G ), //input [7:0] I_rgb_g + .I_rgb_b ( VGA_B ), //input [7:0] I_rgb_b + .O_tmds_clk_p ( tmds_clk_p ), //output O_tmds_clk_p + .O_tmds_clk_n ( tmds_clk_n ), //output O_tmds_clk_n + .O_tmds_data_p( tmds_d_p ), //output [2:0] O_tmds_data_p + .O_tmds_data_n( tmds_d_n ) //output [2:0] O_tmds_data_n + ); + + `else + + assign GPIO_2 = { VGA_B, VGA_R }; + assign GPIO_3 = { 2'bz, VGA_VS, VGA_HS, VGA_G }; + + `endif endmodule diff --git a/boards/tang_primer_20k_dock_alt/dvi_tx.ipc b/boards/tang_primer_20k_dock_alt/dvi_tx.ipc index 49ace32f..64143584 100644 --- a/boards/tang_primer_20k_dock_alt/dvi_tx.ipc +++ b/boards/tang_primer_20k_dock_alt/dvi_tx.ipc @@ -1,16 +1,16 @@ -[General] -ipc_version=4 -file=dvi_tx -module=DVI_TX_Top -target_device=gw2a18c-011 -type=dvi_tx -version=1.0 - -[Config] -DISABLE_IO_INSERTION=true -ELVDS=true -LANG=0 -RX_CLOCK_IN_FREQUENCY=40 -Synthesis_tool=GowinSynthesis -TLVDS=false -USING_EXTERNAL_CLOCK=true +[General] +ipc_version=4 +file=dvi_tx +module=DVI_TX_Top +target_device=gw2a18c-011 +type=dvi_tx +version=1.0 + +[Config] +DISABLE_IO_INSERTION=true +ELVDS=true +LANG=0 +RX_CLOCK_IN_FREQUENCY=40 +Synthesis_tool=GowinSynthesis +TLVDS=false +USING_EXTERNAL_CLOCK=true diff --git a/boards/tang_primer_20k_dock_alt/dvi_tx.v b/boards/tang_primer_20k_dock_alt/dvi_tx.v index 27647424..895c637e 100644 --- a/boards/tang_primer_20k_dock_alt/dvi_tx.v +++ b/boards/tang_primer_20k_dock_alt/dvi_tx.v @@ -1,1125 +1,1125 @@ -// -//Written by GowinSynthesis -//Tool Version "V1.9.9.03 (64-bit)" -//Sun Jun 2 18:05:56 2024 - -//Source file index table: -//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/DVI_TX/data/dvi_tx_top.v" -//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/DVI_TX/data/rgb2dvi.v" -`timescale 100 ps/100 ps -`pragma protect begin_protected -`pragma protect version="2.3" -`pragma protect author="default" -`pragma protect author_info="default" -`pragma protect encrypt_agent="GOWIN" -`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3" - -`pragma protect encoding=(enctype="base64", line_length=76, bytes=256) -`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa" -`pragma protect key_block -al6vro4MZ1BEEUNKHyex8TrSQas6QVBVJhpXhBzRnuZuJ7JEmoYoEOcD8cbwqnxILAMligQh8clz -2kiaBde0ZVKCbjqACyNEd4iWaSBHjcT71leNC8k2hdxWGqdY4iaMTueebLuGJ5M+Viob6yxFbSy9 -KGCeEveTSZKM1/Gb9ek+8QKTcMAKRtcMBKMPQHjVqo/yjDY9NpcOXHSfI31n+TDaXM6hydDiqGAJ -W97xt0kpzA2DkVaMBPMUgPLfN4gKjQg9N1bbKmErZlJb4whyOHJ54/yQ73zzPg0eIh4+AKMVsJPJ -sWLq4+YqxepTedSeZ970LDAZOjW6eBcboG6lrQ== - -`pragma protect encoding=(enctype="base64", line_length=76, bytes=59136) -`pragma protect data_keyowner="default-ip-vendor" -`pragma protect data_keyname="default-ip-key" -`pragma protect data_method="aes128-cfb" -`pragma protect data_block -7mTxKdQOH2ImYodBh4aGPvmLSPzEmKXRBXSYQ9zPW6+7Z2k2FXkL+shomy8FZ7P+pc2JOHqB9uWz -AcQ3dC0ecQBG62bHoiZNBGta1FYuLUprDVdvx0TfDkMmOmGQbSYH97knQTkP1SIf9mnplrAaA3Q7 -qEDggvlp4CgAxLc3ggXlcgykaKEWcSNJDtIlU8OQVbuzkFN5pVUmTtyLrjJAI5FVglcLoZb3iZuw -/So1tdvJBe2id2j+7zozWMr+j7PFFPrgVMQELSvE2RAzWosz3RFZ21p/D9fyiux2+YpykSeaEG+C -fkSsx7jvN7PV9aOWYNotDszh9b9VbRovfEZ4jGyRQA/6yVnGzZF/SEmiwnzEeiyzGdCalIeVw6S1 -zDaM4U2mPvfRdBMI+tB0GtvwBKcHKbL5NXg0Z6NIDnUaHv1jxY9zMGH2Tly9Fp3sczrLmezbPlNw -wWutlIbbaPxFR6/Cc6//2SSgJ7EBNp0TWoTsMKPX+fHJV368kV9qCMLZuCtkwIn9gQhNLKhw3Fnf -A9TQgcD7ZevV5PL27J4uiDoyF3OoczHx0aaIHCeoTWPx19eBqsv8TkeLh3a8+p630YFcJ+65Pvi0 -exAExkq2NiQQg3ZpkvvDJv6wKTx5y2nF5cJ2KFI7tGgA9qSJFiOqC1LqBSzmhMyMFIokhFoykfKR -tVCmaatxqCc+FgA3HECIW9m0biw5H03JnmIH+/Cy6zGnX6I9iGnI1ojfhTUHd01t3KneYLqKsHiB -KcQcCp9797V91087gHI7JclOY77kVPV23+u6eD69foRehFp6ag4RPEnGDOGrqZiy/e4s+pSrRQxQ -L0joJ/bUnZJfB/HjapZtTlpez7UjIYIvtC8vfWNmTMDsUZ45Mh8tZdpQMbUFgIkCkJq0WEGpauc0 -9xBMmmiV4L9B2v3Ay31b+R1dUngbs0T/GxvCJPclMo7oM2FwDvYo8LQ463o2QSWFxGfPPPvBTy6T -lXlBBKh3ExOO00nFWjmnF9YurT1qM6Sne5MYVeOhY5X48ATc8LyFcHIbf1LqNJfknWTQJ/wsGGMQ -rI/Q02iDf7uMk4Ed5l3WHQop9xq8q9Jyf5slslTKjGl2XGVv+fBFWgdgitNVSIWhhnscU2NdMtpG -960eJ2o1HFgiNWtdScrWtT2NV2PAAuTvBjy4YM1b1fGYSzeufJy8fBFeaHsgd2WwJUQsnSKFlfzW -dNzYjof0YzCm+SvmsDwu0d8zLhR68xnS56DHR0e/IoP+rT9f3XZZroSJGngbKQJQ+MOlMxKZL3+I -Q2wndY1vrO6fNFBL0kFbqRude3cd9ak+W7L8pY3wD5yyGeXkXuNeyzwDKLz59LUlyBTm4YUGt5+m -6Dls8748NqyscIYlZmd2RFEy+Y1UaqoyknS+45ZEKOqJ1ZoOmbcQDbiLguEFAhMcHB+Djxih4itx -9MTy7SQBNfqbLM3ohwJhpBCHBM9mtI20uIiMXBtd2gMBOnyRqvaum44zPH+4mz8nCMVUoAS23w1R -OqLWNKMWak9McYexncpz94Dd9esSPiTcMPILiRI6kDVWZZ9AEus9yVi19xyHWr8WXuPTMESWhp0w -mIOxvA0dFoJwc4Cv4vkTfyTWWWE0TIWgICAy32RLyPvLytOSTMTZwX5IuuYdRBsayIsHO385zanU -zNjrbDOryAsFWKUT1LS6dsA0zZuTxJTjtNdcSAfkTtQa9bYNcMV0bcmGhQqD6giF9Qxkle3VFSqr -5CxNTPNpFJLLyydKd9pbT7TO0HNpW4oLpd1qZFN/WFk+IxaNU/ZGRU3F9VbUmClp8zx5LdhTDiKs -+K+cmVKBI8B/qms+hRzGCz1FrnR1vMUa60BFDNbBZt2QelTtd62yDFKUAR2atlGL+tDXTd+9yBOl -zl513F3Q+1mWu7NV50zRi7jQf6l841QYhyY+h4cs76kZsosHR6U+tDnQfG3l23aTkjp1zj78uZIs -Xk/D947932glq3Dr7lQkFCmz9Pqfj5nXJy01JnUAC3WekB2KGmbqsNkE2T69rDx9jM+4f71UnG/v -jALu+jxf+78qdoKfJYUZmel8q33ZnylfvmH2LQTjoFufd9OWlKgI2Vp9+L2kWEzYtmwT4nmLOs/m -ML8vIaljUha5YRwVpxdeseOvp3Blgz/MivHlvONCcrMNesQ2K2gHnPw55pNCq19CMXx4K6o7/zSu -sgcRRAxaFgIyEcqe9RdoqPu3KmqO5EyrHV5b3BlFYuPTaUS4JvKHeWXnERMn+Wd9/WMByiwl1Pn5 -n4oJWBL6sDG/+M0qbwXMFoUr1HzuXO2bnUGbCKusMEOVqG1ahKreWaKYcKLcj3RFXUe4QOBUSp10 -5G9ol/56ZeYN5VTkcBxSNRptd1HenUyOonT8LBdggvlg6o9qciYt9BI7foCYmHRXE1wjgGTeGFgv -EhoU156BOj+d4UvKnAuBv2YVloK13vzbyyD/KD9GaVbKYkx8KmJ8fm4B4HD3kprGubDQTy0JHQmE -+C4mikjgEv0tYPFpRqDHFEyuNdAm50ISxxuQJw5Wk1c+GRRFU9UWMk3GVwy//vtAuAKm4jzsZsnD -qFtaAQzCOavyerJQ+ky0CHdIXCAeOd+MDtxn8h+KE/5klx0aaVBjtkFbzIPKwbCT9eBwHhGsZXVH -JrL7j164xIh8pw6Rux1lY8xzwY6jZGFSuxzmXm+jpfKr5+X0P+W5EkbYl88F2aTuzp7mJiZBifz/ -VCN3lpiuq60kiVDFlf1/0WGI1apNJUcgnjURMUmthbBfdtfHfBmkDahzkWW0fSFJ0lHr8UFN9XD8 -T5LOZVttnDrYKghGmBGMRDjGsg9XN74GrF3fWFjbQyDTM/WYH6iGNq/0TMAutCdqkKdZk0qcMIc1 -qgwEzXbEbFpYiadC7q9dJzcFLFybU7BBf9WLaedNE5AOX2N7KxmKMSbPEBdg4p2Ze0Er1MgsQT/j -ZgUvua+QQ+s2T58xb7U71LQHykpK9zV0TdtM2vkVclVSQcvdABrW/MSe9w3+BdYZnAwUcPO+/uRx -AR3SkY5szH964oUXuH7M8iHV9/PnMyKq2peDviwcf5yzZyQ3YdzrtHblPa+rQJBoX7Bpv225SOD8 -qBzOhZ65cocLASIuJTArT6kJRulxXC+9FQqkrFQ2LCS/VjLcak4W9CtjJtsyHwyS7vn5SgS4YN9a -cG5VUYn3XpkYCHROkmjaRqUDogw0WQDsRnQDJJPQU1TcT4pkRQlb5TDDfYbVcUvtXGvaUdzaEhII -0VF5o7pN+6IVsoZW25io3YY8attfwa+/FxpgQ4MXEkMHiI75lCfI5ft08trwYTsuGF3tjPFyJbwP -pCPP5lxlGTOjjLyNS795cf4xBILjBM9fdLBRGSTiqOkabQc/dbuzygPZ6orCUVy16cupzgvNkCwr -ZgHre2j+b8ioLyrBLrT56xtmgXmo2C4uG0UTtVE5AWMl+IMDLW59t1gOG3+1SZCySN0J/gRxPy6Q -mHcdqysNU/0/uhrm3Zn1H6aMwqcMgv09si/vCN/v2zQWhGMwlHRnqWSVEE0kyUABaAMOjgi8n3xa -/y9TSDwJAurQ4Q6hEk6T8B/IHANYYPPbSSsVjvBRC4JFwbuyuBLTDdCyWEK1Tay9rB207Rpe60RK -CJLTRrqQuFfdE7gBpvsXcHiQ3uO6hE9Y4png+NWfPSovayUotF5K9UwPBQ/5EbLaky/DcH3E8vtN -gGVWq6ciafr3mY16/ssq/eiFz3Ynyz9Cc0apMHM0kTGLj2lLuIwrtJ8wjis1ie4gIia0u/c1w251 -AT+q9YSoKsI1bKlQHt+81NH0wifDU3zdUCp0Wn+zInyeFefg5f0qbb2fTvoDABs50EykaoYQ1Pwh -5poUmY4TB0GHSUN36b198HCcM8R/E/kZS9nXIozgMFafevBuEIUmBl1TIG7DlqP/W/h3k22UkVNK -CnQmQRdX+d/X2fOKVxv7OoUBMTBYPHkqg3vOVApFhM2eRt2ILTw8GbvSFikyycL5NOCJGNXRMMs/ -HQYFe2pcOLEo1yZjot/evruLUFKk9+YLkoyrJQil5S9Uvf8qubYvfRIOiebotQxPymy3z9BkFdpy -IAmGtI/vyVRXggRLOpzrAMAAQA7L1glN1hyAgBN7QKQV4wCg2Xrts5YS29MCpbgrdnTwIbBKxgEp -Yjhk1jgNzVE8nntrbUZFIx/uIp4xVOooCJwWS8fRc9eElFZhKfPhWD6gBRll9KK/KKVz0bIyryRz -m4aVhnBokZMvxzNkR+z/2WP10c+jgA43wc+qaX3bleVoZ5j55ELJcGAQYs2mNzMWiPK3zPTw5mpT -l3Uh2mILA3vJj38Htw0cvrTIRYsG9uAQvIMkj55QvW8HKHLHIu2Czd9095fkrOdi4E1Fazms/ocy -nd5aBEt2TSnv1VcXkzwqm2ihKkKl7ON4uevAUrQHhvVQ/62FFuQBvFBrj0z83MtYXpCh85jOoUhX -SXc/dZU+cQHDj/iGSigQqo1pkxmDQ1/b+zsL3YCQR6nmy3dczt5kESII4+iDchk0TaYT8Ms3sal1 -B7G5XtmO3v/bB0i4hJIeoDjjDHiNnqyPL6NRsuA6Hq3z4JkvSy9tG0kngXrdT03Ynh1YUaWEqDml -PXIV6r064G8fv9iJAy+0DcYXF6SvRZAzg4RsxydV1YUAdMSrEdHYB2ZzpeOXq0DQH5uh6wqddjBq -BOkNWOREj1N7uagViq1cHmYni/O+6ZlHsNT7puQemfNXcEPDgNlhGHMa3rq/UOncSPXu+0/R5Vs+ -19r+DKbuR7GX4Zu/xc0cmk9XwfumcsqWRPmoqFHap8HiRRAH2rL4SCvIEF7kY42AHFjRD20+p4ho -mqbHQr19OnLDpOVwDXq7wIxh2idsH/Da3FExh8z9ZbvF/L5TijHwQPGWr32MU+87yWzVLvHNCajc -LJSNesMPYeI/GdMbeJtARLppOtqfkHYUtEjNyzDA/QWOhEX9WpTdxlAxRnTNdYMKB4mam98+5y+X -locU9QtYWwUvK5PjMLJ96/vhNIZ9nz3ORrDYaqbbJ7NB50/mGhMr+oyUOpg8kBDiW7GogM75p0U9 -b+hee1LrXsUrtQ1THRx5gabiayUFpe1+Sy+C8AtqWekB//kJELFK/AoKhTuBYtMsn9C6W8HJZqLG -H6+EUW7AvCPyyRTMLtAQfyM3GP+r+hEVNKjH/XwDBYCDuevAIAs7yRHizV/tTBvHFy7cF30RG6ix -WzKjwud5QD5bVDChA4V4bp7JsgNxJM12tydAGwm/1k73ztsGPq6qSwISIy0l7XAnjyhizbnykW8b -1GTuZEM06A9cPl7UBgmcbawtIrNZDBL2Jvn6KVtQCiHWHD5QMy/LYMEuDUoXwSiD9LKsZ2anotDz -0oBp3QTrcsto0KDUVMQ7rnXfeVFbhIr5zh7/6nR8y6Bl8OcCuFQ78Nxv048X35kVEle6uR9AHZNu -8TkU16ePZUWEwG6qDaRmE5+oDIR0c1scn9S9lxoKVF5cl8Zw8bZR1fRXEgApnwBVuMGVxWrpHtS7 -WNBZRse+fjE10dgaJ4CWWrAur5uYShSjFQkvh0WjU75xJBrvNMNqNAQiNSR1fmpzx580TA+VOCaC -vZ1c16yQTUlXwnVoW84aa3UcGsoU3LwGJ23XFSQ+HBaprUf9UWJ540nsKdiMDlvpsXqLqhGCnGJu -O3bR0gdB5pVP5TIP54DOiqYgB9TXuOqgEvPx3cREcpYYmZyiDlYOnejTH4HVjiCfwnrWbqlDZnrt -pPmW2VR3IWNDe7wvjIQkepNRt72sgInUmhrFpzMuRewIQ9FyHBp2X4Hu7DO640zv17tWqejpUQUH -U/12z1MDJ52DcD1sovsN8avv3QLdz7ZZ35eJon+TBxfi0T++7CXo0AdIgiSSZoyVNNu4hbzA2pmo -HjuSk4MldB+Sle+lNq/ZuwES/dQXPx4EK4XHhrNC6lPAz+gHCkxNw2LIb2PCy0Oq45K+rMHccWpb -lPhKaWhlZxb0wcDMFZAQbvM6He+9x1aLmATmej/tQhXNry3Wu4LHaWkBSIwl7SWQzg+K9+wS5v10 -szo5YJlim3WLcMHQSxMerhiYLGt8ChDdfabe92aSQXuNhntCPJWI5z42HDdzyzDEUGuDbtVS9pX5 -RgfcPjxJnMUOBH5hNGPBVDFrkY9o+8/LGxg5NKEBSbbD5bUSc+HbJovnrxMLo848xIzIgY4onZGN -6e2ikPXJL6zkHRJQWOwHV4krC8DF8hTk2mRzaDfliQRCB8PNnarpbfTx2e0n7WKjqShLo/odnqz3 -hLm8iM7yNynQO6BZtoMBEZNzOjpiCJ6XjpC4jeDdc27QePbPfDeQEXk2cUx8ZZxeJotWMIw/rTyt -O5rtzuA5B5rZJTcszoE/eQLj+9xovVUwEzgUa4IFUOFnNHzNaOZqHrIRuy+DxJQ64CRlSGraSpP4 -DJ/QWSlcTDcaDc90e0omKfFkz8VlMu8UxGwVFLGeL9WMyRikQkwIdkh5hg01RAL1I0B03xyZd+xr -aFAaDwMjZJ0LaKzgNus0kk1riV5XEgIzdNzuI2X6nRhdXNtP+Z4TqR1DPYBL3Q46mzC8/cFkqBUd -vuaMvbMamWqtbcT6Ivb+5Gl3PzpczmgwlAjBUnrfsw/zCLp340JJ+xtd2dvUixW6FzlYwxoCLYRK -lHKAFnfwqV9k1+GRp4fUnLwisRBCYeNyAsM1i0Nhi1w4SAChjyNwQ3W00MswZbuJy/H2NPhTcoDs -xN7ZQAbdqSLO80RYWJSizkSLMOxvl/cFt5oOVWieU/Gv9r3okzSwhU8BfzvGyPimQF1cHgWvAL3p -AYZAYDFDBLu0GCl6nIemMxLrHoWYqEzSVGN+G4AjKSVnkVXT3jh47sv2J2TJMFYCPbOqwmW3q3bz -ZuYYlOO53ifQsOUcdgMdzjvI1j4tc0yPhWQZhZ34oa52F2TfvJrSXACqyqt5w4n85lqN+FZARi6a -N5Cz2ttHBnEn56FjBw5HkKnRc5I1z3WtRSBwYyy+J7XVk5GX9UEx5E8/5XoT3aeSxd8no/1oOtKD -0Wbo+uBaXjlCNXK/6pJchrbubRj5vOvrW79QY3dPvLYQlwLv4MlPI6cK/28J4eMRpLCOKQIQF0KM -T3RIRBfUrmO7n7e0jluFf2hcGLcWAsuKC8xAMnyEzfskjYJZtUhmAIbKwcOKQvSq7ZrLJV8z9RZy -aIr/4axyBwTja/+Qg6B+tiu4L32xgvnLI7T+KwgWXHkUtXx9bVGqH8vr9O9yY+cGLvOVx/ciXdC3 -WBkAKaQIdt/CVg84QgFrWoC72lWoN0MOaXK3SQRSa5vf2Ja3fXLva6Dnq/wa9MTZiZ22qs+kCHG5 -6BO3avj+D/2GzgcNorJGpXlx4FgLi9yNVdSHEobf5u76KXkXiRlYNs0AlRK9HF2aotDdcawYBokN -Y7mc6pTwVHjWy3egE1WcR28mL/BhfKoAABCxO3yOqTJNyZuZIuha+hQRNRPjySyId9OocRl0Tebj -atSoFHwO8VOIRzSHd9ufvvyNIxzi1B9wkEMMelG5Rv6P6b3Qiduv8MvgMrEYKinm9v/ZY4u9Qc/N -RKMeWoMZanJcrGKh1FHXvvGf8nfp1z+an/+GVAXIt39ZY8tphVHQujRw+5xtcUsS11hlTyjaei2w -Ts0kxurh3wZ5uS18e6wvln8b0uy2T5f4UKavSXb/EkHol9IBfKDUT16dM+95rd09JQj7jYffRHTA -NLG+kLdkK1DudenymWRvyEQFjV+JvsU7KAcBdjjjGJi9LipNwBydCrDbHITq/PfKVvvUnsP8dqvi -NSBseN+hnVdufZrOCixi5bIkY6xPvTIWmVkSzSjniE3dK7f3gNQPS6zKBDABvAzqJuHgsUCZ4jEk -DCCvCocWC8LXbEkpr3mmO1hitvPXN0GZbhI9H9D2U3226SUiBAZCm6KQEr1AhLUJfyRM+HCAHmlm -zjkzW8t10VfFBDLNtk0haUZHJFA9wOcJ1Imla5UEWVtUkzdN2X7bW1QXXxSjb9Ug6EAz9zZziQE2 -YRXHwqW7vOTRNlnHMtSTJ7ppVJ5kFgrg3QOrxYyk37voxph3Sv2s2OHXHJj0yK0N0VrJefaQpuvN -wyTygLA9PAWUvdjdrMZJ4XUJdcAS2fiDmx2QMrI2osY7dSn/ReldejaMH3FerM6wWHlCznchs98w -ovC4qkDugeehwXIDOpYXEfofcOEaWR5goqTkqUV22KOHdPdh05aHdCNguN9HFy+ApYBplL737N40 -rkJt5f/5SfsGuz86GwXSCrqh/V5Q9PRMzVR4+L6LtoYKebrLHeFm1Qo3lb7OwgBKL4FJc03mwW1y -nPNZdH2OIODEHz5QPt0uM96yOD+Os82ghAO2Bs6Y1TUtZ2vsOSvuw3r5kd/Ds6C2PVYMIOk9x4Ku -L9zXcylBTcRoxAnXNrZFF/VxzviWNJcDYnfBN/KOwUcLzLaLucpP+tUWx+d0lji1Be94OTv5WneI -5rEjz9Ram/PpYDSbVMujyWEXwfadd1tvd9w4XGKGPlCgMh0cvHuTsWh9n6oSP06TByO7OH3BIa3D -yui21+j2tesZvyCSUuweaO6RC/cm36pXIP7sEsq8hif1x1AADVOdb16SPyM+xc86eHRTaFuWWEIm -ByLEItrUkAkeadujlv/S/PAAxwNrknJuPtnmfGnsqVMTEBOypTU+QtQpO+pWVcXRTB6V4Ng06uVm -OW0wzWOuITOo8QFuedW1qZ409QgKMfb4wktLZESvRBS2Lv0HFze2nbPsy1R+Lm2bUjn7yEDxbFqi -uRCnYBJD1a8ZKFXQtoXPNZbCBu/5wGdPo/MKm+JXJse/WZN3Ck9KnszV6VJ+k2VDsbzLmuHcJOAb -V8bu1C068jftH+LPwhplE3qL8sTP67IjzjajevtstWkah4lAzEDNcHugjE2uIDxIEGVZ7rmeYivh -phEx6/WUAp7gSaFmSFY1oBf+QhT9IjZ1ogmwiI5ECH65C1HMCwh9hy5kq48Ovw++VP/doW7SMvMS -F3mWg3XL651uGE1reLPBUBXhKLSf8oUODjHudG9PjQENb63HUr9TbNQEAZd15zJa0EvXxx48htk3 -wJRGCo/1qeMIroaR5VSg3nohiZ0h2EPmzeV+171ZKzyG6EFmY3RlfZvF3B8QVkcj4AUp8b+ddSlD -cpnVkdeYO/edsBKi6iKqTfWPdLv/qht4+fRwlFSjPbW9QPkUjhDMnMePSc/U14E8sXO5wyEbsFMs -Tw7V/jj3hVa9TWWXynEX2YIVPjLPvvpSZnFhczYHXF47IR1w/r5U1t1M6QCKW0P75zob9usSDo6X -hvxQ/1VKbGcxxG0Q29hOn5cCCBeHOJ73zws/64VdAbaOfqx6XnT9AMZxnfvG1j1jPifzpgSG8yzW -OflAGy6jyoLwJRQH0604gz+paQLwa3O5MNRZS52tpmxJPmmXFhiISkpcrzGBCJ7GpTvrV/gS8N9J -mX6c+u+bQD8GjyEvbmlSzJ9Gvngbvdjzs0lJ3NaPLKE7J4VszBoHjhk6xktTik19H0R+mSTvHNBx -XAiCeCGAKpm9tqKduxxMgrz5TJu+Dl/maorTde6bNGNtvXuVLzHWWlnt1IRJZcYCoDKPfYW5b1VX -l5sg5ATF9WSJQcu2Qo1AOLIggb9f/2srlR14JF7Ium6ZHFUw2Dqw2JyHXJDz69AHBkS80hGRU8YF -Mv4eE95E7Y0eTpTGmo28wdjKG3yZfdOz9bOxcEJd8/Otyb0Y8NoXr1W7aE4BpgzL6U2J79iKaEhK -8KkYVt/lfVS8dSrs8P1F53+WGsn80XEOqRHTYpifvhLWVDAYlPMxG1MNJxATyyCt8FO4AEE4ocA2 -ZFEMl8hbr7xWGkuPp24Y0hZJVO/1GivCbEv71PSUhMyGlXN+uTFmF37T6svbVQp8OnNiZMwsQcbt -UTlgQB985NKxw+hpZWg57GQrcoFzkFnv319iBYfiJUolgZK1NogDyUaZX4lo/xwkJlzaeMwYMRLv -PbI+dL8ODBp8qXaya/k0BP2ZcU4X6zbBTgKrCMdG9IxoAgTd91thCbQpHUKDO+oeHMO+7E7BRF1o -eZYrgueEXc30oEBEvcH9mWyg7s4+SYHjnuA0OQ6vq+fDIeo+MOiOuueHJbfOeABVb+g41FPVDxta -jMgxLefIWMx7h3vXMwsrq6SLpDAzcrjxxvaGEB9b1zb2MCYAH1s/l2uRDCZ0gFZwd2epHx+/A9HC -duOxSR0qn72cnJI6VwTBZkuOX2zJNKqjrkzZCLK8MPRaqHsnXfjkdeTCQ9BeYp/qbZtmgsUEm1V9 -7uyqzeTfAwjT1FsJCtlA5F2YECEgIXumnSkmkvk3KYFSNKEbljQJvb2tcR7jpiaDnnZzUA39jLHu -3kWotuuzdVvuFhrrszyay+BM3F8FVJKCU0fhYTGthIREEX1hyV+tol4kK9MLlR6rYJTegdkirDds -2mWWAS5V7i9XSHTCR/AtvkR3ZzGwUUYoZzlobnmNaJooknZ1sBqrViSMjZGrMt7kgE+NLl3Np9ZJ -dp+L31R97ydoUo4cRAiTqTxuNAS6CWgNUKkvHSr/ViqhMqysYS1FvZJaO44n6LeXiWGdsEYPBRPq -JG4Klge9JntjaTseS3FT/8EfzuBhNUwnanhmhMoEybJODYpot7rthRGl5o83xcrdYOmE6CCrlQQc -8JMiB81aIIDJQVcnt+SvUb8c6n1rIq5fdObn0hTo2wAkW8e0EMkUgXSg8TWHvYA2VY3ZE8yo0pmB -JsABxradGN1Tc4D6FvPlSGFx7FaGL4zlLCu/iTIGwAV2VwSVjb91Nh3JFzaVR1JkBEPFZi3pZyMD -9FhfksUhOPlUmJ4wqHerQxKbDxbF6Y+M80IMPDMOX8NnNqCmJch4kWmR8QHkeBpKlFPB4HKW1Gbw -Zl00+KjWQBrh8Q/PEKRlzspzf5/QuxBm8GpZp6khtjjjTJKRUw3zQBoma9zPIbXpR7kEclF8SB6U -Z0pE9hMsCXHl5Os6JDlcUwPGr2GXt2/cZRf2lKk9TgUGpIJVr9hFzwe51GbL7YB9Sf84DnpRI7ki -eCTEdKXMiUVIrUzGUz21szCFx8ayKJKfiFM++mT8kb34eqsX7D/uC4l14F4H4rXJVtpCBMTgaLRJ -EDjwjtwBN4hwLvOKLxoYk6qP3D9zYX2voCH9galXXDRB9S/RrxFkvRL/xsmueg8G6ETxSkzPA41/ -E19qS/gkKFO59dCVRzmeOKznmEF/k+NxGLLpkgMt6hqctt4rVVRXHvlcmupX84qGYriXoA+GjxEK -K5IXyl8MIk8lD0Sfa4dIlwl3s0eM5t1PxNNkISQizM+n3k7InqAsk9jSKHKvpJDugsxRDYBVyA/j -S4GVXJ5VXqI0K4dRhhLV2bFTU47ASmkXsfLxZI5pptuj50P1GhQV43aZXmCUPqyV6MYgZZhhHAvx -HUpDQWYbieZQ+ok1sZf7A9B7b1PCjZqvk4ql4zgjGDKbCO8yunVqFgyL2D6GNYvo4DV/ekwNnEHH -HrdxqQHSyGW/yKraZ73SgpJ93wGcL3vL5tmR59uDeoaPHXOwfP6ChsHW5XlozwoKQHpJ+CgnBclk -9XWPMQc0C//4vsv4bRqgQ26LnWPHQ5JP9tkK+CQImtlJD5hd3UhFdo4RkqFGfK7JjJjDwX2OJhxU -wE/0Drbe5Vhtk96EqRRKPiVBOICOEF5V622SbKh8tAqKixuGnXdHc5sswu1G1H+MTB5WM9j3Uvpu -HiPKKkgDH2yDXoum73dl+OE5LAg0uxYw1fH+RqV4qeJWeuv9OzdfPTGlpUnptOGXA3gDRoTGn529 -dhyp0g9q+xIiP2pGWsMOVF9QsWL82MZ6Sh30CDjcIGl0cM9uNCWBHaKLEJKViQwWaZemhRByccx8 -ZKDab8QCWfDafD4GLFx6zUvmCzVw3uaz5+Uhl7MszaatKTCVp8WDsb+g5RwO/nTfKBrFcG2VLlrF -SVSt/AW/Y8P4jCBbgyeuIz9gv9m8RJ0l5kmgg5c6f0n2ao8X7Hfk3UcE02aIy9YzUyOsVi2dJ6B4 -BYec43INL3jDcje+oo7CjG2MLW/uWPNABBXcTBvIcFUH00acNvGIee2m62uRRCsZm5I5mW8Q9q2i -Z94BF4OvXbHXZzJxCo5VEGcA2twk4rLhc1xD/T3HRg2RmYsxf8dsYPs0y1QNRF8GbxFn9Q1nHgJT -Z5cdoFL5eIqZh9se02XI7GeYU5eSMzUGxEZC07pSQdmVDtsc0h0695vyYkI2J7wE/mkqeQm8MEGt -IHocy/EYp2i87M0aDq0qn3yXKxyUJMYhq4B3z8CRJrMl6tn4/ZfbCknLle1WMY6kHrB4Ta6epM8T -jrVuPrWfCHYIun5FUCA6tU1o65Kg7hbfvoiTo/XpL/by7XyABOh3ZxXuqk+RSrMHYCGYjM/zgR2Z -JLW4oBFH+jSgnecjJea5Grrl+S74W+xithohgB/eIQfLlpxVqs335PkgZEpBi6+ZNj/KunmtRVeC -a57t3CMSINiNpVwigJre/gUrhAlJd6pH4YKlQRDMrfCFH3d4SUWpBfps8dMlsANJObaZAvZGZ1z0 -f8c6jRXlCeUTQ4ftR5uRC6u96GqKISjlAK3S5RQwgIirqImwjAJlfL0DGSkCthBLEJDgxeCCa9BZ -qCLXIePa3hfP03Pv8PSV+A0lNkQAZK3wTp+xIhh/wMjufb/R063yqR3slApIV6PcG3viwnMJHhA2 -KztVfauANYpyZiFF7Sl4WFmB1NfnC/DT61TJ1sqJOZ9ywn1WkRl58hZiCUA89rMwyoyTtNWXUpQA -APJ3bbXkITgbCuiHN5mdnNgu31sb7d7rpxRaymILLk4OXovH2vVslQecJn+8nuG2nH8GOVBzJCHK -xISndEeRCDl5RI36zFjzJI8FgwcygByxYzYjqr9Zg5DO5LLxZf5ETfIVc+UY062FUqb1nv+S4N7b -DGzpMqUfLSPu29gn4Q4t/wD2CphezCK4y2rG0oaH8nEVnLsHxqiuZI77Q5ALRpBfvJ9piOyDj4yj -egNcfKWMU96Jd64ODD06Gb8GOv/m8UQegW1q9iOtfATgFvk5ttjj97BxLh+FPIZHkLIe5hgfluU5 -2wSdpdjzpGTyngqY33/tZ6jmxfoZBA2c6KE/RTXHW+koDRik5uBuZYkNsnkau+WP6urOgXGstkVG -HK4xeWf0JEmXRl8Fatfw8wAOs2zuDH3VfAuHtS8R8gGwoXwq/bK+0OwRBfEcOVNA8L+sSNoym/Dz -1CBI4BqXN5t3iBD1sf+V0+xc19MXxcpCiY7Jo/qTgY0VnNweuQJcaOg4rs0VwYwYMeVb3jPQFtor -F0qzdk1tVRLlryq6j+O/c1nBoedT1NWcXZwDClPJ/Hb1+qryDQjOL2eG2Lyi+DKELD6DikLSV8SS -0W6lpUUvcN9b6uLbOpuI0biPOttjy66GHOUycYbT5YTYokrhF6qbL772CicjXcby9JUhNHDobwla -UMAODqfatfO8+Rm8bxMZ+WXCPSbzC9Xr7bWjqcqXIbrEe9jKkl1nB2POsTOouzTgMLLYqZVbtqbM -Yo1Vq+63pw4nG0MPNW5gPiqMZ51+I+6niuZHB4IvggMiat7vaY58SicfoDZ17hG4pYGT1fu/RuXJ -Zg0EKz+gmUfXzIH8jEh8YUwTbk7p9vZQ4R/Ww5pY1gHd+Zt+aEzBQEC/scnKU+aQvUsqUY9VZ2I6 -hZ0qvsxBan/mNMDi44IaorV+haKLfbkGNHMIV4hm2RGKdJRLryHfjG6c2VljHclxW+R2jNUpKJhd -joH+4OqMcgJJVgbGXCgAxBOhuiZeiEV0MCAy15YICBiy1IanUT+DKb2FF6iUeh/IwXSx3O95MKYb -9dGhTp7Wj2jaihz8OjdSu3x0e5z8ztYSvFam4/FbjVhfBC1iIZhUBVhtvYL8And+Gk+FuObz4N6F -l1adoF0bTQjyTCRINBqMa+dK/ALhwvbfLBxvqEP8b9Pe80QNd9YA5/2Ajh1J/r/dMoth/1H89b2y -fFoBTxsJNbnEVNOd7yWvP2Bec2eekO8gCw/tU62cxX0F85XChfVohHn986EY5JIj8KYGDtYXAtka -XVfdfTGON1mzhiqE8JftiiPrkgXwY8+C8Gu+IURODl0tDTyWmaBoDuVDlhRYwyHs3ZKo3g3J/tgt -3GCZh2gxhG6N9knuTxn9sh/7c1Q2uRerHbE+C9WaJmAytWK9pw5CUEocwaBH3zmJ5uUEYklBLC27 -D8Q/6x+XUOBQbHMGO5FnIrXP6cSMLTsf1/QX0N944y+zhytgfAec+9iNXwx/X7z4yEQEd1rHTyKd -b0922T5fnEL0LFrr5aaCRn2Avt4xi6z7pdJIbVAZ/z250fW3kDIXTIUQVmThNpFyNyGGnbupsEMs -alRBcMa7dXP+gH3sgaUvPQJ0PFEKdNyZki1OV73zU6/hHkr1bVcCWCYLXS5CnWVjawNA366708VG -tW5ukuRyNmyyg664OAqqv52yyFpVTRUHFEL9JCwM2FgGlIouZxk+sb6wM1XBx8Ml3t7h/TWj3yR0 -ksCsXqv+Myj0BnzWOE5hzYwIvweEzDlddBAqm99biQr61W1LrJdq3wz8YqqpxazsLpcUuaSAMEMD -pZu/eHQ65Vt2S2fmNKC1tnCeno+W46juh3IU8PVOTjRC2/eBezUVkfd0pA/Lg9Mn2CPvGAaZ82mt -mI2L2whK4jZmCxE9uvyDxqMmIQ9ttxBCSWZZFEpkePrCJr/KSjVZqYCYYNmTJ+C8zpqYxrCgCdjd -/O7Hc4W2diivmgbrmaR4sOSoBijZvdZu55UD2gsa5b3PYCKCFOcMTE7CLEYuL+pC2kNn1Gg8fiNn -qDXDfHnuvTZ9uIQ0OFclyXGS3D/1FKy1Z6tyN4YHu5w18bFNjb8+F+Y+HgezDMWHiqqLU+zeq2l/ -EHnV4o64rc5rIcD0t8JDk8GRafCD4ghxaV0E6JKFa+bysZhnyCQ/c4q96/g5PXNwI/25gNY6Pf+k -7gUV8xD++rmYBsWtIPDpnUj37sW5MtaFbTvRi6qU34Cpp0byDwvm8VKtrMCHJtvk4EQwea2TgybP -8+dMYDAWQyxBoH8QmIVT2i1n5SxTLYMjq/AFfqdJeluYogQ7+tUTubu74Z9yA8Ls/u8v3LaFys/T -3sTiJJuM19bYW5Ftc/Bn1gnwTq9/y6yegDCGfX0srdCc6/6DFa5EqqqYL8TjSgsL1UQIu+Fu2c/1 -5Y0NvBIskiQC8UFomEdG2zcJmlsiAR/O11+yBkd006ZgpBX3pF/HFDvN851+QawJaezgO2CHnVkL -cR8EZxKRDl4MlHqX7cRvPDLwsToNpM64WtzQFwZNK37ed1PhIVsy5wNzkei/9fwGaFOmlKHM2WFU -23TOpr4/WBBaI+Uq5APVnQQcnlK/iK2iB2LpCUTjq/cd+qt5mLqIeawAwD9X+noWOIHUluRutCLM -C6hfG/b6+0VPGb7XRAmQSx3phvpw+Yy2sIo1AlzX7IXigxaXSjFMyKBP/JqXurVVCPWeyZJHxxAr -lLlSmyxl6j8JrdKwVSMabi4xg8FnhOTF+tSoDw6Dq1UbN8s4WMyy+owZ2m5irnf9wu/5IOAt6c0L -rHC8/iq7oFudzNCAUW/HOMHnrNxXTEcauXykeaXuTWiuERPUWUeR3TYX5gxH/FyE3jXm/Uav3k3j -a4BfEP2/wfzMAWtE83AMbLjLHNFVGtfR5H8QnjorPvPOXQsYb5B03sTkGS27PpmB1Bl7Iqbb4luB -B2U9fU+OEWhN+h+UChkz1RXC8DiATxShwaLj9glJJKFRM+gQS6qzUZr9ebTFZkzgh8hc9npk0shm -zBOThc2t2KGFGXc69bNTD6zYvTc9WO1jXO+0bNorokLp/82+PU4xxnULEUpuRWBg+QxW3t9we2qV -7J60yvMNQARTKTV5EbKUYcUKwmqj0fAn0Qdtobe/8jFN5julB8k+GCh9PiPeXtPI7vNL7/ZZIFwc -3AL2+SzpE7gXssHLYL0O4bRobyUan44kTZCze/bGqoUY1abW7lOxtqgYcBQ7MlEDBB5PsSwU6kb3 -qUu06SzBrxDwUuENbT4bdtVGK7oJt9CHSzzRDx0v4oFm9yswQAZPTqXvCGyHlOAG4JlQ8EkrREnW -+aYN6/mR3ENAjE7qHc34WPN47GAhUwXGwZp15ZJwYsqOugDSEYLpVZuNKCihWNEZt4/aLqRVqzgV -BAXRuVPR4W7xI/SWem/UHYQCHUQvXtyNJyLEDq47PRtq02V6qv1T4cqPMMI4RBIBqbv0PUpTAxUN -7ImiZI1ABHvio+DbsznE+SkVaBdPjYvJgJkiwQfB+bhe9707KMSmtTNTGjri2ctnBzXC3sb0DKBn -LC31xxU9cAhGpiRwH+lxP103EtIkHSB1D3QGTRTPkQIzDSusQ0PttAV2PHawBxxQec67fh07J8Gm -JPJubMsdvzoFle+a/BzJKqn2lS1hdWIvTILuJqiEBN2gcSVNoHQoaz90eFx4x+bQCAoW+hJ/Btla -wZdHcA+ZTfsfo45rj8lyapoQ5IP98US7cFR5A5vm+TSL+TdHjQuZdKAUP+biBNVWTqbmTPzwDOjw -5B2N37w8sFc2gAATWKybuHrnQGqRgZv20KIV1BDSesYWVrJMgzc5hfvpMlHX0yOy+bSTPJoziktb -YsfpvPSTxPRWjWEnW/yVZJcSWA/No0dVii5buA1WxWNLIYyXxwKigodHTn0J2LnQEWCSTEXesjNn -MxfHo/4wYNwnzsfmNdQZn0H53YpJnIPQfAzxOqw1xq6g1KMrJXF0Du/6VnqXnIpqJNowBf0oRk81 -a0AcgE/ISDHMyb1wzhhVjkyqitH7HrY2KCC2xWWaYOf+zpM4Sh1XC2sqWv9xga5ngK6NSPS8m3Ue -+Jacj5tJyxZZGzxvpeFyUoa0h+EW1WwWNzvfsHlgLnxe5YDxdeKOxKvZiy/XIf9RgH707ffoqRjm -4/FiM0TLr56s1gEErbdHXqKE8y/MHRj+8+yJi83sGVOQqMt0LMLCh+gF+epmDtdj4u1rmgyyQcnu -nk48CVfBMZrwsPo5aUoW7wE60XGfcghCtoY8bKL/x3slpN/2aifAh3cSDMdbFNrvVmgnirCYVa1h -+MxKVJp+eo0RFHM+njRfSPjfMICDXe3R12NCQpfTeqSgArUoFhwO53x0TRvQdiBAX40d/Sk+P1wd -BnpxcjuJ/0BnDL6IF09heN93TaJaC0NOAXqF55MHDT2sPYIRj9+QmJMO/QD/pTYdbWuTcI8ke/C+ -Y1fpL8J9SGLa6Re9dsS1Fzwo3ceVNc4Ok7hQMymQ9YF0//A6NCUR6FaROGhBe602vxN7NUtbx4en -G6PzSZ8tNcvAFQOkW5PeCld2UCnbcmg+wXEiQZLLqNEWDNVTGTJKuRT4KoE8He833lH4uN2lEyo9 -l3XVGlSS0WjAfrw2StaiHRabFlpRD8OpxWLkrfUC29KuTUFeaL4XM5ifhEbSDTj60oqwYVoj5QvR -HLwNX3eE4qlC+9ed3ksTOgD0o4uV0MgCmuvD1kJo+YEfynJxr9IpRNfZYt+PsxN6KCracEswPNN2 -JhlPbpy5ObVCoNsmHiyx1ub9GFZNXTM4buYuTiwqmXx4+i5EH/R7eBSiO7/0Bmb0JorCr6pAJCON -QAz0PfGgiijvpVvok/EBUgARaz3XjwaM3Cmq17Bff4wQt/hSXWkSNUuXChWucI7/YY7QbIbwkGkm -z0DH0YUXekLLJ1uA5eDF2fZCQXM0l1ERGdjIOgA0irSBqrI7e7zCFfJBZdr7gE7A6oCOECHNj1x1 -SqzfBwO1xicjG1l2ZPGr+WhR6u2hqNjFOOeU3bLTENOX8A0c8XH/G7tsbZD1mLSmd0LoVlUDfKAf -QMeEKuPi9bJoAw32cQx3Zqcq2NnvwRBiR4b6x/JqwuZf6Yk1JtANanhJPqwEujBsskVtA5G6R2qs -t5wT0axG+T3OvYiFKg2OVpXsExqpesoA1aimQrQrL6MEEOaz5kWPB5rbZEINxghXbIj27vAyhrKY -ECf3SLDy+2fZnetOxKaSEzHEK3TXxNs+vNBRcuzP4xSBsSERFPLmOdF5AqL5KhZ6vsxYCEWkgyHf -se5EYO5HyHBac7vQtnJshuzrmXlUzNOzu12pupi9GvH304s7X48XKjeir4PVz0yHYQG6P/SIBvso -vjSbb+9dRrCGJZpXai7H4025TyawbGPN0P8L178Xe1KVzjD2lmjgwHe9Ojbs5HwG4PaAxlxUYOSq -xjGLYYAi6fFZ91z+BoA+MGlpXXRW2V5Y2qsWQjKUK7jTEoEHhZRTmI6NYaxMEgYZQTje2m46SQ4C -044O366H5oD9ABpcbqap4lKg1rKeGS4kPHv86KgMRQ3BUS2XY6v2YTQFy8vXQUNETtbMopnLD1V5 -xFhKNdaC5wBXc5Ky+QFT8sfY8INRZQnG5sOUV8YlnpD3AzQv3KD9V4x860Tvqd8B6vjIF0PV3ezx -p8kGQIhx9EDmXc/i8D0sjtmOwlmftxkX7zFe83M0EHunBzRK+E/EMyb8DvfzZvvMEZtueyEOqmVn -ZJV+6tWFNsgQ/YhR9a6k8tvepSMYYjuqtAKwzDEMK6RRb0NSKX077q9h9Pxv4BNUkJaYjvAWBGpC -/+G0ByBG99f2MsSnnP+XCX5Z6lPWeYzuENRwR8A3r0XbdEc5WxAuBJUAx2bt7GQKP2a9xMNan81p -Aez4a4Q4Np4kACKDTpi6Ck4WsF4hp7DwWxJdpv1HRfuWTZ6Z0fHYd8Xt4FDsGvgNg6a45gIx/2Ph -weDIcFBZejbTnofz1eAx3FMPy87MzwDciIt56RxckrnYiZkJ3iPR8Dpy2rqgw/s0FA/zlWQdwdBI -qSG642aq+70nIj/38sOeMnPKK3xyagyAra0oHCnYqo/FvboXwFw1Vw8B2idYpyrEIqzZJIRIAj4q -DcavuIO29IMU0z5XmulYgrjH96uqZzCeOvP4KIfFsDJChuvCEeyc2yKX1YK4iBAfCOgOckcMX8XU -snZt3lVmZOxe2K6aJ2m+QmwWFot8Bigwu1+utrx8Qo80/VBADn3KXKWe13RuRCRBTyESk/6d5CBC -qC4e8tkgzxv7c3Vhh/xq5CGPuLzRZNJdaUZ2JAdbWICYew/S0jxnP9MI+64RL5Xpdv4AN6/oLoHH -swDnWD3PO87LC5ZzOmypTDGVo4m09kWLhbhDI6N2CkJ3WWNAvv4TVn6BvrwxiFLumerCYjglO2Fv -bhPGu5+S8av0RFCb1zV6EA8/T6PiKD31XxURqkv8V7OVpv+aOuNRItSLiBNybcuiWk+2Hk4QZ5Hv -ra/GTtC2qYXBt6Gn4lmkw8J2zGyouuUKezMilCHCA1ivl6eCq4v82bk2aLxY9+kA8zQeuZmsC/N6 -m4wtxXmoBd7m/hSX4XVRKtoDThckdBNPWzGbewxNnxqgs1Xhqo2Jz9MiSRCBG3XESOxWxJZK0Dzf -sdFMwTDWUXtiY+bvxz25VVXm/wwjTLjSczHnvvAoH9+fc5CFZlG5s+ah8spRQuQ1OpcvSG8bwUJS -sl2KyFzBTA9zRcU6qHAsd7kaZcZueshFWh4Qrrf2lZakRWxwpMsE3fHaUA35tGa03MFDohFiyxoO -V593MjjfsNWaypAbjzfLAAivwFlPhW3LbPEwZUqWQ/djkDeLShD9B3ouC5AhCZTmwxXu2tSB2RMD -E3u2fFu4p+UNgC5srRSnZaW+B1+ssZQK6CW4S5jG9JCYtEob8n3m7zwWaq4c3DWxEF4Q44HZziny -UTsMB9ExdHm7N9TzdB0jzf+DfbkLCLzlGe1NJlwNu7ix9wTi+2cHH8Rl12HYpaW2cWXLMmQAFK2V -imf15Mvoz7TYBy6BtXhiTHobqpWgkyUNMXwDd9iHbap/sTUTUu9q6FDazY/fr2NNsUCc80j9Nrq8 -xxcIEX7jrkHRPF4JdJw6CMJwufqwWZ3yhsSWskOAsqZvaggdifbRGzplSX5KMrUapC4r3N11eVAI -4Jm9pPFYOEXuj+A+avxwJz3kq4s0+TDFlO2NepVm3SZwpCVbHjeWAtaFTV7LVF8lHtIRunmAM0DH -HjrkRRnei5Iejnp3QN0VSd0CF7W5oeFuo/WfNBDGlVWYkNr1I9enonQgjU+qMr/sK1UOjBZlykzC -VuoAwgInuSBuNaHX8IF8zNOXrgOgg8pZYK7yFAR5primmGsuJZNDUYXagpFcdP0k0UBL17VvVx69 -FgTMnO2QXVF+0paghsxS0FnJPfw6PzufpS6P5WaQHBiw5bt53/PMvfXmNcsHGF6clZUHqKMFnbg5 -HuUehghW95DqRD7EHxmOzFt8txonkG+nWbvSz/e0m18qKV5RbZ9+1xynWrDpllwO/4Wfk4vcINIj -usT3CiIWhy/cD8jSyFnQqtOWgg/BPi39+P7tHKDwimtXY2wiHFLAlnjyrM0xv4hs3pP+lJotQNjY -rYDmqvWCW33ay4k2ashIWgciowYbQO9PcJwpMl+hhv2Zivl4iOJZ/M+avFFCmdubUE9sUylxwrHl -0at6G7W/Ly+sxAm4q7kWTQR+Ve9Tfj/qX5Ty6jrqi2vYIx/0n/cyZDOu1eWQMmrjJZO9Tzp+p/9r -8Ekh3S9AZPIfXhvIViUKakiMGXGqF6lat4gTIlS8pXDX8is78NXnYSRvIx+rsPp2WX5mLeuF7XvF -B3dDcmvYwKBhcm/75PiUJtPniah107wsWbLtpj2rSUIi3FKamIGq1an9op5/0Py/JkXJYgkOREf+ -uyzuka2w41iX6ZE6Yl+1clHLLh+066Xmy6O+Rt9mufJIYArp/bdYvpUyf6om9zfaLIw7kzxrXafn -OOM9B6blGNcSuI8fQJxjABiX/zAG9Pz7uK20ZhksZjnz67GHhSGICZayNwJzc8BVbDHFHSYcO4pu -VmYoRz+5MP1J0TcvUfnJNlnNApvQdeovWSV9VEPTuAvECIcGAPu8hyYpalK148Y2UoJfoJyomFLC -fkE8cTy91mClvrqtjGFDFq0pvsmnM4h3/K365ikn+vhySiEHhJJfjbSUEd5sn+lw6BqZxUqiqfwM -A0ZXH4m3Lav//hIeJRRhHJ7Zs7sFS+ed/kc6l8rUEIkla9i8dTtwjviqfHIamuRXAhsWdBMjpmeR -OOEA4vcKHYhHCsHP21DK1n5XAmeYLe554+p/tFu1yDFKqgBpf2f8qh3Y+OcHK2HNA/jHGyH6BEdl -13mEEeWf5tLXiyBhAUvNOkFeiZe7ApUxlU9EPnzcoro+F3OZEMbF1HXNeT6i5Mb/mCBT8hXLk+pj -1yDHNuYFDoFdIW6m3W7/mjBVhnegIcHylHNMpkjUN3dT9UWMMYS2yl7b1PdJFdoBaPHXZgTF0gZJ -0mDZJ4k+TDYfL+7x/2btKp6Ke0uPNdWKfkVX7dyilN3lDfC5B8oMnlyLcehdELQRKfq4QrHh7GcT -E+8T+WpdOZXC3M99FlP0KT1pDRupCIAm+lZ+Ffw7Gf4Byot5r/aK/q4gC8omOqk+qgQwlIVNdpnw -XUkmfPfrK7rdEx1mkNZ4XWBmA8zjimo+KGZBmwMaJHk7hIf6J3/K2QZpfLdTwJaoSWgjsVfojhl8 -+Giodiq1x7wUExLDHouicRTnjAMdGfV7772ZhEmyK5Cpeg5weP10Pw6EQ+nb9rguS869oHeVfg9I -XBODmf0C1jGMaqlGixTpOu8f6yJ79oZpsJtxoxsbp3jaiLvNSWEL1hqQRLDTcqlVQIAtpq0D7LTF -880OfyNXm/uz4kT3RdLk5Cs+y/QShTZgAQqH7MmH6jiwVI814PB9Js5rPmLR2QN8ysyrqeStDG/9 -JwAup3jBtjHjcl2X/GWhRbmwhZ1/2iyMhM5uAz4Vn9gggY4rMeIVV/42hpvkeTRdbk9Vs3bCaNyt -rRK37CqteMFx4JhD47avU+AGd18TqY8MiTyXGPlNZ89U6sgZ1zyEqemdHVbdKLGdxU1umWiD5ee3 -HH+YUu84aHfIC4u53uysNx958Rf8fTdAdi2vvubFfd3QWA014M06/HZuVFe8iAvB0KxcPlhcuSfv -Rauc0ii1LWrDq5HomoTxk1oX9Tx1CPrzJjabz/rw1yt6vbvZj65nhYl9G9G54krJHeyZdsDSeAkL -dZXeKh8dYKIHFFwFxMzJk7aTz6FOzlNoV31Nu4XKrWb4r/zIHBX4KlQBSRoiDICeA3nDTkiSFM2Q -ce+Qew4UWn0axANif43PBgc/pbNYJ4itZmuoIFVebqgWNV1sid6CivT3QR3tKP1YCjq4P/nTprXo -Jgw5oBsxQ5dd+HHQQ8Bnnkd54OcmnAl4DpuMrSzwYzealgcyS84XmCo2dOkTNteoG3c5umQJyU76 -fvH1OJdRIgnoPOJanexMKrJvsWP75RwD5pKbBRyNRy4UM2MDGSsTSBvqTMx8fD0Fqq99ASeC1/ZU -UdllEFe0CNG8L6ye2oAwCKtg9gIfmzt4PYGsbflRRj5xpaRBwvFlp/FKLNt/KOQ1CXokLYdCy1mT -k37wt7nHtVxcjGXlTkHKl25uYiyelXRjX2zcgESq1UDiWL3XLVIzF1sb4An646BB6oizxTQl2LpL -S5vFxU1LQgk0hk+RN6V6zGYItUlm/8b4O45j3nziHb7wEcJa0+L4ERl/5oAT2R4KLuHLVMJARnaT -SIGo4PfKDKJ3QBRnf2VEcE6KTNFeYlb4mNRdFfj9GmPqzwfWvwR5n4/7G9xjwveGvoLCYHwr9nnz -BXVdGWqW3yRYv/IhdbMBSpkikYRP2rErmKW/fMX0W/jyZWJ/xhKxWsz5ilQtPS1LkIj2nXzbe+1g -VVGCyekDjZjknUzLVngixRl36wBsbNpYzRJ+RtAU0N8Eh0vIRf4gBZZawdzXOKjvRVZXDaozZfYr -NRl5PgtgSZrLHSJnk8oTzkZfVSB92z8yi6bO+84hcIxsJGKkY7YHudDoZ88vRT+Z0uM6XvdpuXIb -+WHb8U+9fBxYYDmFxHiNuteKicNJfiDJL9OCUyzM1fcXTBDKgEpN3F3agkMnGzwhzgObsIa2290W -GLvWJyKor93U2MEpoQQs75/hXq0t64mwF5YhSYnWVFG0g9JN1QXZxK8aMY6CUZz0ajy85riF/6N5 -tkRDWkGHB93fM1Mu/pfsXUuY+tHWxhrN5dpc2VJCewUgzmkvsGoGrkIHOmslsBCaR6Ng26jtk+Df -WmAYjbeAvaX/yl0cM40XDVvPLdM/jwVBfiVHGP/l1sF+YZcK3UP8CMV7VvMVW56Uw1azTp9+Gu6l -/UrDR3aaY6cyk+QbjK6K/p9jyhj0aV+4O7QnFfG97LLH/5YrSpUVhVDNXCS7VzSQiqOiK6Intc0/ -eK+vzMTSNYNy1Q/j6uJzx89QpRKDEjWWFdNcVxXZe2Uit8Z1n3sl9EWvEQv67XxaKwbfCcQm1OBV -Y+NDnjrsPcpoRGK2YBRazmZJt0TrpRo3I1PeFE+hwmwSvsCFgkC0P3Owc1QomodUuHxNvCKwogUR -Vfx6+rqytgxPDsuwVpO/U0JswwYIB564gxYityWse9fyS914AFpyFWcswky6Le9Ax0yyVy0Mm2bY -0JMsv0hwM2vYc2hLxskjvhxXixd2D+1VoYkCEATHmUltXrL+qdBaVLWC0luTai+OBnC1K08G0w4Y -zq6oVBQEzQgmF7qIUHvtd34ZwxpAbtjPB6l6f3sL3od6ywWhInHnomlj2ct46+Il99hFfFwFhhxR -uYJCigO7Wlzmrxldm3FLlg/Oh5xRCuYXzrf+GphdEtnylV/oqVViv1zOLxwTuBO2doSGCB4xGQZz -4BqbwqiuI9cvQSFSsj0a+dyWczN7HMbsd+ZhgYuRVePpG4mzXcMCVGt2kE889JJX+NwI3q2j80+X -48rhnvKmgXnGRpOgbwhKwhT2Xm7M2pIXYgtOPLP2trp3TTwc5wFDxvtdd54Eb7tcFVYtYEmqQM2f -g1b8UQ34Md6mOLc/CVwEbvjB19rwdjHgIoIfZHjb7vpGUfHqR6SNB82ZdCfXJWAWriLAHagA7oHj -Hc141eW6pmkzNV8bQd2tXcFwNGRhpd2NL4B00aFlzKCs3yozO9GyEkaUrj8+9BVNsp4Zywug/FoC -7vq9oIYEE/KAjYRTtGLgjOX2HKoeJYEm2Z7fi2dX7fOJGDMTz0aaDc+tdRc7LKCNZT0LrbQe0D1+ -3r7doNqBmo6d6GsbbFmePvCNDgdubb0NmXJCBezoHQW3OBV2+fGh1+mll/3Bq6P3hn9efEpUno7N -s39oGbYg1frKGDTRe2sIfjCl+/jXH65mzo/0zpUP36aedirWoTYJpmHMpINnOeGPUZrYI1DaMds3 -aNQ0GVH759z28JMhAbbO251jLnEoa4kZRVI8SXT9q7QCQei63HYoh2lQ0GHEsYf9e3u70VCuchps -U/99DYvdGg4ZXt8Tc4rq1a8gy0SgSKAfcHCLHhacvUKl+WBZnJ9jOOUsKW0GNm2P+AHLD0WrWSFQ -TzYcjXEF8Fd6BQx61JcLQTWiQOEBGLYYeGVeFmR4xFIB96+MC+GhVKaBOJv/LOk5N7r4OzjfAjWW -3YvMP5nSNtpkheMNFejRAMZNfKJLWeVoNgYVs+lqC17qKktNoHNKBAQFqc2iopfdnvajnFVwugng -bQ0y59H287MmPNNTxdDzPPkW6osD8r3SKIxIG5FZwnFXrzFQx3QyJ3ZyrobJiZuE0HanWWzjwjzP -yQlCTWif61tUllrpuSFwGMh23Kb0skIVIwru6rCSVUxL87C+9D+xWsYBLWLQadt7oL2viUiwoJPW -gzDeTL4T4hc65mEfPugGgcG2yCg5iMW/sLaEm7RxI1ycuue9ZBVtmiGyJwBDM44sOi/bpyGEfBqN -n21zQwKDODSyXYCvoohmGSl+qSWc2OVwXG28PUgDRNCHx9T5J5TS8eAsWHWa2iMj5IhcBrfVjfGk -2pkFSazUNx4pgw4mW6iEkTPveUyPvhDIjoj6T24nbOiLBDQyZCYZZrLrt+6aj+uMvfubuUf336KK -vPfRlO/kJDYxkR2nWaOU2MguTPBFvOK0ZDbsrP75iccLSdq5OcytSXMXzatwODr2drkozWuRpGBy -Uu6RgyvJxdaLW5vzh5WwL3UdnmBE3OhjbdbrJLgmjZRd8bvLSSlohl4aLZ9RZPTYPACFvjinoMVu -3lbEHb53TleteCnWlburzwQ/SR1j96GzTrp8epF4ZiNicGockkk1KQs8s3qrJxMyB4vWnhgZlmcW -jytYTdwZG+sORIAg4Ulbih1n+kVzwee+99cz1ZGPcih1LFmDVaWlXTQjdzLbu0QAnWtBcZcR8JY5 -VywuvrzfnEhxwF/WbpqI5iel4vnsZjFU1Oqn1Ews0BsrgAnOiyFj2gqrSGJcmz/bKGDWYN4T7ZHm -tQPP5F3l7GRUOS+c5YjiJwjd7OFStPa/5toRAxUFythWvrSa4SRNHQuuX9iz9ig33GrUUVRDYGa0 -iikbkK/EtMkw4GnED8+Z1WjK0Pv2EI2OaRRMz+qW+1TgBFqi3feWxFADAHuXSh1BFujERfVKEggr -qdQO1CHQAsvoZRKhNPkTJ6zB3c/DzXT65yIVTGmrbhrGQcXay/xs10f0NqQ0vZb35O6wyHRJVPik -cjXPwSeNXdB6zrg0AhfsPJwM2POC/FM8A78fmUzBDOYzTH8Xm7I70uwX+mQPHXiIvLvk+ky3YmQd -NTxwKnu4KU7DaD84gRgkp4hPbqa475RpNOrAGPeQJLY7XHzwKf9Z9wUVAM4kqm5vxtHTlZ3loEkd -QqzAAwfnVk2GuRRhkTQiX4GpAK6dIX9+f5iGCTOE6/A2zdKc/WC8RbUCFmVPpef98PQjPyGlN7fm -Wf5mtPMtmp6ZrbTzlI5W4PG4BRVdXLo5YtRkxAFhIyXxL1N+BhUmTjrCBB19WwZPzdwXIwsDLvqV -qQK+uc0sxY+PIsKuZ4iZ17mci3rJ/xNog9PC7ArEOOHPWTtLDqHFhpFEO4h0PVQmR8QHZUril9TQ -vKciodvRTIKZ94WxqgePf129KM9gAiy/maA0A+6M/+AoHvkrxZumhLn4mXkdnh9E0oe62gYHgWmW -KpkkixIm9kSciDWE1rgoUjeirV4owho6EEMKusrOgvRWYSsP1mtErIIE1KxEyP5+VaLG35C9xrpT -Vw0JSijCMrx21vhI25v0hSlC9wVJpi2sa/xs8NcAe6kIcXUr4AtjFz24wFF05WYtFQ4xOdIU54Mj -MIJOETUpgaGj8wD+O5JWJF/IViiyesfIJkBpnghqDmb97hLSqfcgXXcuUtG6oaj6HH8mzN3aR6qp -jXQflccOZ4KQedD6RPM2ziSTJTPt/wlQmbJQky28bZfJM+qi/4vqxIvXAuBq/BTZL+urp3i0hYdF -Rz5nXQtSXjPiiQNsc5KbbDv9XsChTNrn6tmbF1EhCB+Xb2NR1xk+B53opwPdcQ6hEIPtJz52RLGF -VbdMczoTHUG54C6Ubwwt6egVHS+BkkL3xzFWFrqR6XwQAi6HEx4Qi0kLlobJeltevm4EL66qAyth -FVWvJ5dexnOaALVk/NpnzSyim0kT67S7HMxf7v+R5FrIRo77afu0+qL/gVlSvWsZY9eaXnHe2NjH -zGVZ7KuQ51cKuDzD7XyBKDJntLURTbwxVHlXHHQRAaDQc+Sz8i+N41d0quqCBI8JjS6gxx65jP/O -Z5sj8OMXfUAJtDsmMoY8QBv8oKa+r6BoRm6iMmaRbIFhWdull9lglflm9Y8xeFymgmpSiWLuIyhg -+G9c5xrjTJYdDW9XeYhskEdpvPf2pSg4PFFTKz8tOl1IZ+ruso9VHhl1oiBryI4e9+Bt7WyLjZKp -QGsYAPrReSJhxH+pb8HVtHDEZ3FBdmKepe0IN+as28fsvtgNVbx0otMrfrNtv3J1/mo3sRs9ediL -AD9BwjAAZ+DNZdsWy/HnK63Ia+JL+NBwf6IY4IDGZmst15/qXR2tZZEO0qaoF8FlG6nNnfiz5Qvw -bY+ZxLI1KC2OKtIQkq3Tg1bcOhrNnm/S4es8CkhzQZ8fbMWEi9w4Vgh6IzOqi5wiSGd2vJYDPQj9 -yh7QvvkRmYZs5AU+NaVcnYox4Err1CQw1K543KeO2OuSrmcF+oZmrQqH9L560iVKMD5Y+KMAZ+1y -nEeiBF5SJ9Gz8HNtxSFI+j3QxzO6VIZx0ycDDnLaUK9M2Z7f8YaWfFU+X1qh3gecGZGuT1ePDwJs -NWp+eD2XoqkGovqNiPMTHRls4iWQwSTVSYNKpT6uLEYLPpRZbKDZHWqXJYWUl1syy/qG0wkYAI6b -7wnNsm4rF6svYB84wmQCrY6ohhV5o07JL77XmyeRqWTz9OAXWTkjFOLithbgMEZ+Bflo8KU54IaD -3htdArNQmX2ELJBxLu/DoB0/BC3eQFzwbPdGzfmLoCeYiQ/cct0EcR9pd5UZNwORlZHZVJ0+21T2 -FRw4ZB7fRsjMf5XzvTIDzGMsWfiPIr/8vDIYbPBnXzCBkpVEXv0Zu7XNDBlj+86CTAt1X2SpENPF -+OtvIzNmBj4ZIXGlWdzi+qla1hfZn+KegQp1aqLbkNr0QQV+7TKCd78t5QExNjkV8N7uavj8i/VX -Y8R6AKypf4cNwA1j+TtBqxsb2Dh0B3UpEcq20AXCcf/rAQy3lp3vgdfkkbT7ygi1c8tob42knmfz -+XVuD943I+ShjiryZrin+5dX6s+1HnP6OWuXSRZepp7tn69J7Xz1dvxXCW0vEDZp5pRrIcUJMrb3 -gugNesKTDxa4emcxfQgk3ONNQg/oB2Ac3Pt50b+VHZgdsrxI+Y01HSQ37OFAZbxjOlVEBxgPwOhO -hPna8l4csJvoY3Ne5qxD/wJn3eP+IOLuz59nmAJuEUHGM1E6a9gjr0DiUMCohvDmQfhrd5A7Sze2 -77MIVi0W7cLv0N9SYaOetTlMWt7dyhn0FFkKwvmSZgkdaUaUwBsQ51ekPk/VuPfcaUg4IuTFgOpm -1zJ9lJSx2JuILYTc56gfdMZkQoADqMUXS/3dkzeng342loMMv71mseI5PM8iD1DCX8u5uVXycPXC -yrJXss4iewGi8S9RukMXbRJ/XoJw0TdoMcR6/YzcyKpSl+qClWZBY3vXYW2DBUDREdY9qJvCgMAb -++Db2qSLHzyf6uRxmU//QPIAp+L9wpCd3iprPT7LIvFJNgU7B4Hj4SLLBxqVNCyM2iWaFvtzy9Mg -HG2YkC0noMOt4yaGKwccUztGPectz6V8dwL4hI2F+7Z2n2cGueca0OuU2cAqSjSyGY/5ohifJUOc -6sFZ+6yOxZ8MLlCsgSR2Ke7pxQB6aCjP1KFz+cZVMgsSZ502hWSAA6mR/cSRKwd+K7qigZVjvvUA -d9LCn2+QqgcqyDjGCWOQ9ahW9H/uUkzwlLwB/+Y+WUHh8aNJVB5Kwerlue+7D6YeLPME6s0s6Us/ -K6drDUVD6Tjsdh/XRH08TThMx2BiFb2gIMXB9CW1TdeSBBOLCKAaR9+ZIv80CvPVA53yIic53ODm -SdTZmpMkTq3BMOG+tQEafg1GCvL9hdwnxUBxaiDkSnPIt0sQUYgWqKJr0FpvFlEEKVwHT03q8+NZ -4YjZk2WRW6IoQEuUroIJvUxJ7mVYPQHlMULMmhHWlppEmEsSGl2gsH6xekMPhOQFleY6ptHR/RD9 -nIrMgONXy/6u4IAbmTgb9dSxGcYYd3LTxttc31sZbM8+hVZzlo3B15Tgb+ZZcfzfGj/FCOo7I4qn -LElfHshJpjLjeUZ4v9+Kd8mmj3x0pwUWj6do5zR0WgWZXz3FjbQbwZMxZByLA46vzN8eZUoaKXSM -1YZ4L+z7+yHM48mQwuM5sN6sNomZV3UcYfHTvL3A6u6eMenquW/WAIMs2HALFqKI4p6lqMD2orQ+ -sdUUVM0M40JSyGWws+gZ7CecTGx9uJ82TuEwHOxrh2Ay+Rt4uGuBZKaGBNQTuRtiIXwrMTDyIbR/ -uXabGLz4Kt/iFa3X028qJAk7AOJRcPcLqAKr6c6ZUH5DrzT/uFmYiy39leddnmqos7RyEyjsNK+5 -pXsg0ijRcbCTvKzRq6IOu1tZj6gWDxnzCxxWDa/hB9TCllh3P+y2H5LS/RD+IvVoBluGqu35AvrJ -frRwuSWmsue5ZzU1/Sn+rL9TSvgWfiuorkcKdyROYBCJnSi0OsZhKIBFt89Fx+I59fyWzdZAY6EZ -JcBr+C2gI5YWqFhqniLkRNxE15qQf2obqfKk7UinPfwbQYDdaqL/7EcHc+KZnBT6eKKkzjmUEydN -jTzjHyPZJtiNScw6kDbPXbrdHvJDrxSiLeHest3pGaeO78ags+uFK6DZPTBLIyweuaJLsGXhwI7A -yRvBkmuLv/l4AprG9R9No7cZzhxyrA+7jUxpgldeYBi42SlFVycvXEYT2bXz2UVonZ05f+ApqR0E -rVU4xAQTOX9MfZ9WTBeBSlhV18pqb96x6acQ9YHmaZApsFL0Z0vlJtfDMH0UEF3fRj07Tn9f6kBz -xVIXMYTNPCxKccM58JiYJbSFr732mqZtqZsg8yuG0ka/zD3pMZPJOgKAluxRYhbywSwD6Cfb1ZUD -+Rwm1kgE3ooqP8ZK/oQFlPSE2J5Fw1jEJhfAATIdD2GOvEwUzorb+266nYXlPYjS91CwcnPg5QDq -n0otPFovgComCEwkhigDxS2FA6k5aDijuNqW0Yrkq/hF4YL/3XCjhE4Q322IFesEGWeAnVWuixJq -kl2mF9XqJD1G+v8Zaw9HNK6tIQk+n3DxnUEZILmDb/zn7ddlUpTNf18XS3Ba7KVHFRcwteW661rI -TWqiZelDpw+9/zhkjIaIPvqZ0NQBtbsB/HHEu4IdnK0yVETF3TM7GuBOwRIlZpsEnU6bt8J+l37X -8y/zLykFmF9sTAR8dSYS016W27PI9YGU7YboSmR3xXEKnkiLE4k2IHENG4eYrdkHPUMZRvJHymEK -5n4AZiLvFuLE6YANhpq6LIzmnBHgcTLW2TQsJyNF2vhEAX8W5dUVFqzBYOI6RJYwrgWa5VB9qTet -d/tM2sCxth+a74otcM++n8mZBICZxdEXtw2FY2kIOQOJkqqNgMIwD9Wt85b0g68wKCcGVj0SD7sK -bD3twCpsFWpWlSGYwnHyT1gOdCddNhggbyvpXkyyAdxgR596MfEWWtI8jXhEYoZwuCI8kwHRn4vR -XCmcpuWS2ew5abX0w67QMS4m7TZjweE0DZMNyj5RMX691tbF5Wl9Kqirb3ou9hlPuAEUrJsFCbt7 -rBBiGl79GNr1SzE4x0zxF2WXWud/J73S8SLkD8tqbKi+036wXQzR2swDRlCqNJggsORW/AXwtJLL -ZeuLsVajgp88irworkhmZqYAagQ2+Hd4+jOD4bNVVaS7/gVMaZ0q/cj4uN3tZNp11hWO7ZZBSCwr -FeIFeHsLbqnZoCmGOSkbIx6z+wv5CS0gMdrxehgQTPRo+z8zKbYA4n+XelFlH3gTLNKEfTr2eOTq -UI7i8Ah6u6FGKjxx7XYrQN5uo2JSbFn0qt53pgf5w6/JlCejZdgHwMWJ9d0IG7eSHK8q9gNomAGz -byMLGPnmXbPhgUBBUwY6b71fQ5OrIQC63fuYn3QRtNwiSR1/BO5ygOTl5/IHvVrBjiVgnjdM9u4w -A27p7JNwbDcNPK+S1I5XUB2ijBDGUpDLyKoDAlxsqz74Bh8LZPgPC+XorECDqyCIrFPmzOIuTLm5 -V6tUCp8oistA023SusgInNmFOhWSjJDP67t4x2INVrv0Hf0YsnIxyJfZ/mRvfbSL8Mmp2/rh6C/+ -2rPi7uYWjfTcRRch7FCDeMk/S84F3pQnNWaAjS1hgrB5uHqw1QLQNaKNDZk0gcZxXdFSRmhehDqO -0UrD9+DzxyaOOkrkf4bv1ocpL7JXhehfKlXnUWBcmOF0ujCOO51J4m0iOj41F7HkLy7NMlCgPKTe -N+0nVsE3E8og7qhc3sXnuSLf7tSkXdhvBcCp8BTru5CXPfFj/FGUEmULJORvGtG492yF5SWu9AmQ -xbg1JEaeOkMQcLMkfsMAW6fJ/XHwKw5l59WCXQ87pezF5jWIozs99ISk9Nijm8Ok70Ig+HKQ3bBB -CKNpn3p1/u1dinpEUnlFV6Pfjfa3i8CpK8y6zrzMYbThVKRqQKOKPEWNVi0QSVvGoUVl98BXMPVK -6QPvHDuKQpoaUjsqmBH/mSvN6cw+mJJkm4NKII+SP7eSM04YADmhV7urpR2aA2Ten3jyaLxRqaGa -wnu4tzj6iiJWHyNxQQs2BuoqKxh+XjgkI52fKJmFktKHGWs1lQkMYrPcAfQs2nfITO4H1P2Dx8Yo -FvGNqtS2OVBjE3mukTH+lN2HESxPHPbazJ8U45igABE6p4fPNrXLvyiWn5qTkSI8O7byJpxs4pqk -XQ+NnPq35zps5dzl3w8gwn8wIA2etLmbxwkUEkACjuDwC4HzJ9B4kEoE+IV9i66KRTi/YP8Xqnd6 -asmdGI2wOL3bFiVD31Ndc30/j7tHd0V9xbphvrHAo6TfltJNAz7Gjo5PbCskMR3KfjS8Kvgl3o9k -YR4URKlzjSJdwYEGBLznIIVtAQFkHNNTBRwhY3PZuBTFXG6ckNiiAK+m/I96fPdsu2S0PCE3wnGx -jBOzILalL6tkCEkeuF/kzc2T7wdKnoa0KkTqUy+dq++Y90CKttfnhVjhz262jkEKRCdopbvMEkQZ -sViD9dfEDlyQRUYYh6G11NxLFOFpTGr9nH/j7QRoA/hcuCl+PL37ehppYDeAo3dY52nZzqcT7RjD -zybGfIB87Zw3za6f0rTFLep7k5H+IHRIMAEW8SMNvijN3isQgKV/xxzaAHikRQHdKjVCOPM+gq9P -WxF50YMkZV4EBR6q6s/0XFqXqee4DqE7zwS/V7zu6w7fny7nJ4M1/CZwm48tMoMgdh/HB2OlGjU+ -qgAhccPgqINKDTpV8xL/RbzCzAyhi3/S569/sD/GDZzXMLVsl5qdfLHFWkFVZprc6PzJdGu1SG8B -MLOx9JHFd+U8yRy5gqRdsz72GG6p8agjZSmy0Edlzs9gv91I1hQY8OmRXYpIv8xMqIj1JHkU7myy -SKrq9T8P4NdyY4GNKKlplnmUgmVQUamdgAGkQrYf+uefDYOHRjbQCZs6yL/u2Zb07rh+KPEBiHuX -OxQHQQbIII9Xu5YNEpAB2v7d0YxThWZa6OFFWh+IIrmt9UKENGabPe/YM4eaYGSZxajjHxLAdjEW -sAtgXjEG2fdvkCR9u+VcJiAWYnodcv2axq86uln3FjUyt2F/oMIZTvuBeI0fKENulMc9iH9AlK7P -uSde4sf3J2NGfRJKb+dGM8BIkT9CDo7j9mcq3Bry1KrNbkoa9dlNndzCFv/TzHWM/nfiXhwveh/0 -61tjJ6Mgipg/KezafNMHow4IL0OygVhtXKH6HY3Z1G9zlEpM/4fW7WAohH7gUI1o85e1f+2Hajba -xXxRASf5gxWYVG8Gtn+Qdy68bIVgB6wHn5FNE4aW73vCUJAk8tbpQzW+x2Dom/sX1alpmUK2Jcj5 -GIzUvqEeTGYXciIdgE+gEZOhxo5BPg9usy8MnQzus/KbOWLvgLMj+qA33pWkP11kONShrsqMBxJY -yyhq3Izqs6ZIYhk+onbf2qkvd72/in19h0oJayEAmNKsrG46wsGqRkL3rq8iDGM6K+tmwN/rIN+6 -EjVp/63bqjyQ4qoYHlRVIWoZlHHYIRWXv9F+10HHsAKczioUmmKg5J1Bjl+ds0QFj47u4hNmzIBS -vC3yGjdKmsmD3VZFX6TZ3QbtwAJOgafoKEMu9LB3Kaxr2cQqqo/quqbNxJnIHp4Ua06BdIJmzWCq -5eq6j79wrThNwHdsoumIjPn+10WwvTLjXvvC5vi5I1Qhw4QdkW6NIlwQkMPL342AqQh70IPMNpQH -yuOR6wBpVR7/8GaO/sutvKI3ip1uF89+UdwOm4JS6Bzplyk+qHYO1qI9XXoNHaMdq/m04gT6nDTb -3tzZDxeO2leOHGdjK0HL3uEzOqAc9TXGOchED+bLXjv/hGr1RsTEkEr0/RUrSJ6D/AO3GanaPUZ6 -Jj+J8Oq7qSQ3nqkbOLglKpUA3RYGv0rqXTtFTBd0t3VZSTh6v4FwZ22rMQPukHBbFq1KjzWulDCw -07uV8qGcs7ksRPGHVp/T43kScfRhyqYJsNS8rujb2Zd3i9l0+1GfWMz15dL4fbNrMU7QQo0NeMCB -wKmFwmw3SfKZU65d1riyzkV/ZgJvSyjbj53FfYVHW8ItglKvoyGXuSSQ0wenK04nphDIUA3y+36o -0YTy1PjlKR0U2q+PBVVrR3afr/exXsas9BtEYiKr8aOSVMaSAlX91URDvhS73+KYukV5UfwXIq1l -spl7N006PCRhkG6DTDj/MRX2GFmM5SMJpvupAjjN7yxvtdVF14OsCry+Pbl3KbDG9okh94isVoPi -SlS1Rfs7ydbUOKmHYi0zgympTteyMuNDzw6RFapAoE/BWPkkROxlT4z8wH1ESdCWUXeEfELDM0yx -C8wLcz5w7rEc/+A/AsW+Sc90/7T4DdMJx0EcFSVAGDKiJ1WX6Ui5U+LMh6UBMWjA47tD5s3MVs6B -rI2ygHDwmROYSn7ygenDv3Hcz/y+Ecp+mEs0nF1YIsz7O9xTx+biu+IG4p1VpgGYZOToOuOHTsRB -oP/pkiBIeQxBEUdrPuLQJLST2ZkYswL5rd/eb2zWOiaNu9fEgDMgZtGBeWoCvEYAIsbPlnV0zLfC -oauH3Ma+93DRgTGmUbSR/fHwURstLqawOdFrXGZiB6YOalxJeODhq9UR+lpzGxpNMdVWeJukV/Gv -m1QzAzUdjLMyubDRBs1AcSov3ZLITuy00NYAae7ILIzAZMreXmNNCks0Aov17SmJRBlo8K7wnNfU -dTZ5BC6D2CG06x/pdsFm/Vp1r2Hb3LcdXi2hpXzRQgIWJdk9Sdli/9dh6uVgyTWazK4RpQMcHt/b -geQlfFDG3zp63kKwgVu71FSyELQTkG6+8iXiUtO7rEA1Kn2QNmo3k05TlqfFN3njv+8UiGXLwefm -XaA5kvzhX/eoGdneFzkmC4hPQzM5JnHi5/v57tswJkvIueg0zOvEDWJAe6KN1JCZyh2KFuhBKK5d -9Sp8vAHL7AX4Eqvh/fBj1vbsK6edOXyzmPbKC1m/tlnUl+P/8A3ZFKcljSMuG9WMe1Iczk4HJ88c -talHFqf+0dOhVdEQtLVnDSVilMgLcid5wsFL0Cs8cm9LO7q9s9IMS2qbTA2S+BbxwgE3yXxW+h7N -4HbZHHI+k2D+qccv+FeCkTviiArkxfpMhuMXDqmlgsxyrzOqdSdVQOKrFneAeyD9rV4LUXoflDZ9 -wt7zfzWAhNfqL+tLJsO9B9Nt98lWed+QTPXFbUZsOcHAkres2AzZGCEZbhPGFPSYlGeC3Rg1GIf0 -B5K5tApcs64NKFIMlMADrqGFYgNCzXY1wO4ejDFXUzqK6GNbw6U9jAJ5SanwrvJqQgOyZ+hD2Kmg -DD6bKBrve7gHrLO3K0opaw6d+YK4XjZ4RXHdmFXSmm+fgtXtFABiOVwQaH2yaB8sTfUaF2PE5zpd -d5wV+BiEGIM1Vm8cuACofDNUCkxQLri8MUnZrKqYgAZJOy9q0jkCFOhuEz0iSwsRcYU7BQnEZyON -6DRDynZ6n1wLnIn4Td5y9fhwOdcjmg2LY748EYtu1u4b+egSf//Ojh7+0XQ+KD9xyelHUkNnLUr7 -pUNoEj5TRJ9rFcf7tCKDxC9ctSCyAJweGRoG3PnCL1whIYgKNnPiM4oKBXAcGuYsf57K+ekHLw45 -FLGxCFMHhmG8F2mdPObgCI1qwkdmCwgJ8rcLCjj5RjapZDiVah8QCH1ROfjvu/GtwHYsLTheHjqz -d8mOdHYxdYsYlqO+v3WZwSlSmdeSf7m7bcxY+EMSiA1CWBpN3tHJx1Eo9QnnLI7UoxTe/vh6oOPL -FIj/rSdPatbjIJls5xFis66jN+KBXgRNTkmrtZS++Tzqtp6aTJWb5f8drJzBWBNk67bVO5WQ/KP8 -YvpYfzE0iqK+wS6oLntMfuZOSHCZb57FFgJHwoVDObY6DqQTQe9eW5212LybdjuIYndwii6btEfD -jIdkL8C/V+l9+57V3UVclY5KyBaO6FLXUEo688hY/LHhOLAoBL7IHdwqvZnulOKeqRCJWpWLwyJE -e7xVJKi+XVgAQ1E09VPiuIWfHlhwn8XaKVlrqEmGimP+LV3MQnjjCmtac9Sq97GdZUezA6RMl/1G -z4laJYCWWmhrXuBXRoWx2dkkLtC5XMKmbm3MKeVD5rLPl+AZ+FyoJGghrGQmnSPODGPeSBlmJRxx -Dy9ZiPFnVkRKzNvvWuyX6+GOWYOf4jS78UfCkb7eX4SOKmNvg6+B6LwcbEQcmZPvPPdnPmSo0YJE -D0Ehz5tjUO57rY0DXZcdHdbFE/N/7QDI5kbrNCaRVJGHDSoxPr99BBPZKAtghQUdmHgTG0RfFI6h -7iZtpwO9wkFFHFqCGQCsOfbq/98WaRGnXE836dqctXPx4gpe6JuBVnYLLP6+r2W+1fiCfH3w+2Qn -C4ZexjNC+nVVjr7goLns3syWhCId/e1c5Ax6utjICmSJ6bRCHMbMZylL9ReDLw0oT7Gemb3h63RU -le2zzkziEkEy0cuLhZ9nglaTtbrShekHsKdozlKzurs0oGy9vvMhk3N4RZRabylTqcWQehqPClhw -w/bpx8sgFZGRzdjHdsd0xq9YIz4n+V+HcNFhqipBxKFsGBWFVL5TL5q2E2hsrSEMLH89loXL7d+E -z0dfHsU2e2TZzp3iw96ndE75uMCE6EABWBAMJN4y1lYWBWsdeso8Uw2Xt30euevXJ5ov5yVmAJb2 -2v4UhaqMen7r1NTc0VTUdzu0v66qg1OSXdqdVghRmCgY0Dj++6gZETiDEycd/1+POZ0wcGPxGeGY -THQtV8ZJusfp0S9B2d7uMW/TYbkuno2QVuBjN6r2d3h+J9xWap8s0SbpRd4DAfnjfnUJeSMT3XLN -dlaa6JyxM6sn4+9LelZk8QvVYK5eEghxoUbuLLYdVd8kZnNmRle5xJpr/zvpiYFIahB2jHCwrgiH -1Dge+XSWaQX1r1pkAF34Uc92MK8fxi/02hyxTFGGjaVNgxDy+bQ+Y+0z3IgiDIz7iMGtFXDCBKF0 -5b2GLqTrj37T6gWUYxfZhd1gHnhhKNHZI4h/yE+DRbKXSbpw4GDRFFC3+wm6LSP2WlloS/xdGNCv -H2UrjpVvWLj5iWlbaMU3j2MyiIogpGClHHCAmBiYAFKznbBzlnRVjr3334LXqIhHeWgQWvkYwEPE -q8+GWc6HtixFPDOUJ3THDy1GbT3kS2Rtfdx6KDhdDpDamIoqA363fHVcWC/SuDOQHUKvtk7nbSUc -xGWsqhZJi95lBFCD2/eKQyXyG2lqnWy/XmSIqOW6B/aFFlUGb4jDqZQnLjYb6BQ9YCoSxHoZlNhr -cfGibpVkAGe0bsubFkCy0u3UJWRHAvlKPipyjGXiIO++VESFZbS1D5U97a5NR6F1vcMVdhaVA0IW -v0sBrLxSKIFtm9P8U9Ndpp51O6aA1Hi+kCE0dpO17SFJZspF7A2XpDT6QnuuGoFR5tcURpK2819q -Q+zr+TEtClqZvq2WjD7YXmhyxAZNSZ/eY0t/hx2I0agn0KQ/tkwkm72w0eoMZ3c9cZKR2skX4g3e -GAdjEz/jKUrTY9Dt0i5iKRvxHAIzJVsTblPEDnEOn3KSeXISsD7LkgZnNn/ocO7ygLIYyR6RTlMT -BSFkmtqJdLWk3V5bxQ+60pehF7HJYY0U7bjvLZNxNVkhxXH2oWoSNcBfRwUYLJQh9aM9pMk3SK3V -KciM4v+hLHApUiUCnq2pwOUqg3+ZSkCr+zyuMDNQLTU0PLps5WRVZXgft1x7iaFP3SpfcBDyomgG -CINwO7cDKtytN+Xael0CU3PvDyTVdMXLAvbvi/QplOV3svABdJoI3ZGG113MvdGSrvn/ls2ZN2fm -vagIWYIHyGchGiaqrZBloMQQjA6u7C9KwPCKb36q3CCdoYA428DC947kJ8o7VC+DdyIpfQxgL1jr -Ui78W41j0G2MUT0nZjhLDpUJ2YABW2oQL2JX/k3FZhqXN/iPIMfx34ksbNooLP0oc9WkeoYeob1y -Yk1AYSI96NUBFLh4g0u6F94aRoShznZ50F7m9hjSql5opXW9cziWMVdhb902PmXtpmdVpObVVf+e -gfNvTfJvEQBiSa6E94ncVwRRvYVB+j3TbvxNS0w2Gqj3AOdvwt9dluL1uLzz3xP8qEjS68cLFAMf -5uq35NMo+NZ1O10Lx2RWc1qdOmrWYuot/10SNlIuYgYwSXtkRXsGWcFP4pvyN4T5T/O5Vi1TbPq3 -hxHIdrxkBlrwjcnCWZtPXGb4cvui5w4WHkBUnGm1+QR3YUlINET62dQrbQ7y1unalPadqqmRrBrV -zzTFjSmS+q/U8qCsZBpSx42qh6kYIHtm+pK9+FMiRyybN9HF1Jwr63mJQojHrs8Lsy/mS3lLMvIb -szvKLPuJdChlEho6cKS+UEYJX5ui14PzT3g/k8vVwcwAvKeQXQyAFI+CHiAI98Wbcfp7HsqUfTe1 -koY5xq47PpVUt8KsMREa7DGMZdM+AINq3qNaxNX4QrPGcYsOfDNJ59+5df9L4wQngWHKQhc9BZ79 -EKhCbVr0EuzU5+DJHXUrV+pXb5UkjtXYrNg4PN1zCgOyyUSP+ccnfQ+f4N3zP/wfdmRqdWVZ1sez -P1fpVps5nV20t+JBgoULq7UdR8jWRk6AytFWcChLXeAfF/5COyrApbw6SYzRD07CYhIcsb+0mtcN -p2fBEf0pQvWcxJ1emsQikTVqdgwPsYLkbSxPU0BmrrANVhhRZYw2iIbfvYVh8109PYc74j45llPD -lv/xKjWXcXwZ1VCOGKCNxZxEG/1lDizSLoZ1LizBpTr3I3zjaE05+vgEMWN2uyF7pxLluAkG7naW -LVQU6L+dbeBskoX4Zez4ake/FovPKfl4A+ourr6z8UTAphto7bp4uwQJgO9/qJY4Yb+1x/kolFU+ -BUAhxg2aZSvdXmudof9ZgN+KSlEMkCermoY/s1VkBwn8rPGi6fopR+ru6avYlr17gOo4xy441WjS -Fgt80D+CuAecHRimETN+CRy2Ms8v7nR87BvOtZUEwxDlva04V2Au/e6aw2qk7cgmqcR0a224XLGj -r26cxFINyJ+ScVvRjZhc8zxnOJMRRtuM+bKHdWk/xHnX+hMiY58V9t79aB9fhslTczsaY3yO9Tn7 -4x5wqknc+/bXEoZRVg8mrDZpvb9QPXW4LdywJ7eQTA9QYqdOrK+dvmPh/O8HyXMxvtGVOMzWOxj8 -EOSkei5hVtpGrddGXwyCK2JElABQWxZKtue9GR26MFPS5S/JFy3HRE8KSzCDpPy8Ent9yFLaj5Ni -bD6WBTW9laarfO8KyFHz8OhJEHYJxs8fC6kZB/iMsBmvb4z7ymn4Gm9boiuxaDgpTyZ1jxSAxI4D -PjLbfy2nanVW15B9BKdt4HRUNl0KGxJlZz7gtFKwXutyQUyszFXQBLllWjpaHKJyiGmop1e+hHiD -w6xLC1AF2vbBpShK12wIwdNoTe7lJHnsavz2PZTYvT0ASMdEleLy2ZPvqr/HKB3CBPN/yXIDeJIZ -Q48lS/w3SYxti6kOrUdDkZ0FSzn60bZGuXlPG7NclXysVX/JWGUN5F+ljPXj3NFGpanGIo8k5f6y -FZ6HhvxRhUhBhphkHJsLz9bXDkSRlNrgZP98I0BXMPIUakVrZbp3gFw8IzDaH91cEnLwPFIEUQvN -JugOv/VjL2757gh2taOO/VF1YX8Nc4mZv/fqrg3MOWIyYHIrW8VQBpcASlNLKCfVQtvaUekzfUx1 -QWw4HE9/0Ih/uGFJ7RC/HAGe2ZtCxh2ZOseIw9NDXp3OBszpijddbRu3u3tQ/aXXEP+5W/i06eUq -J0Na+Yfq5W3vVyOc3RR/X0LFqwDijoyNbd/ZcAWMrAcREcIwOonGtmxfBX+cWVzaoJrdISp4clCn -z3jH6BwwrOC40ZgTAa8unaDELyFH73uALzz0vnvj2jzh61Ul/jrTkjFFN85eaalFaAZQjoIFTcZp -sol9bgWbsgvSwJifgPuPf/2dV6dtSNqBEcJtmkgiCziFo35mzdi6CBb2DXQsCCx1x5ln+lX3Sfjg -XfROHWKCXFX5oMVt4I216rPO2e7oy8xXWmO2YfovI2bfgFOArXyPlXwM3+piuY/LBvTA8aO9A8HR -mX+EzHyNHUuH5vWHUpHm+tMy0FwLTHQTTa7I2K2IOyd0QP/zq+HZ9Js/4KNbQDOaIRwMlvrq+L0r -fMQ5hpmQgOosbb6/Fzbo923DVA2YmL5n/oh8G8SSdctnpvAmvYmLg3RPVdrcE3UcDdcINmxgWp6Y -Ak+nc7M+/AeZPF056T0mRPju05c4WhrOmW8jgFV++4JDpxNC02C3QPVrIMo+tyY5VT3iJaWrH7M/ -528GgVIDutk1CLxxB0fa1sIRwHgbB6nB+1nlmOkaTiRGMm2ivfR0IqmN9QmtJCjHiWbey6Jql10P -tKIS3ZSYJLnWqnZI8ePZNUGcYsZhw3NODEo9gFWNSplzXcN103VtdwyX5k1jEgrZudqTzrFPFKey -Uce6Ytx6acbRG63aEulE86kJt84td9PZc693gA8k9jr/s8buuXHsm6BfjPDORzdcSNd+kjfA0ApN -OmwgHdq2v2dVtqTFDbr6vR4GohjE5sJkuqZ/Ahpf/koZTpjBG/lD/srPi0hVuC9IVNEiRJZvSj5O -CBdwsoupCf/gKBRwOLFnaw+VG5+sc5RFLLIUCnzyDMfU3wouymaOeMGYR0f5kD7lUc0y71giyywA -xCFpMSurGyQRTV02K3xt550XX8VEZBmFTtcwKQQ7RjUvChHuZFjsKLvqCcBJQ6oWzJSBQFSM0Yu5 -fm1XiwTLX5ERh5Yhc2pagsjAXhiWIg68Mil3JOd7ztLPkCzavar4v+18pCUIihTiG1BL0OlXgUi0 -UxY3dYKjGGe5Ep6VZgs+VuNX/ZBR3sI617RtWfgu+dapIZGHxyM192vI8Ks25yYHaMuBeaGTwutU -JKdWgyMBm4aXEU6cNgKjbhV/FvuNx1oKGKbX7QTJgzotALS5LtfxYMbg/GQJkFzDmKgPCRJIYt73 -Culx+HRKilLc4IWzbPnFSCH3Q9g0WC7hoi0vPd0YYwUUL1d8RNhvg8zhoQC8wyW5egJA//82Ywwv -RW0iKorskmJiuq1LCkrXcovn/xIIEnPVqQcQNln0DSKrYGQGr7WEqKQxTT5VVRrVA6HPgLmUNgC5 -+/Kdgd8vpZZ5YDViWQY5x8qnknv11PZv1TS/qHLD/2Affc6ZFz9+5Txq9Kmo3VGRPqjC+r6b0r2L -f+RhTFr+IPLgPKVLJKOhx8FXpdDnScr/uKvOI/3shUty12BPqv38aYIOgiQnRdA4+8cEpVCR/m2a -uTbJ7ksOXFl9UpBLRAZO5vDsFI6diDoofzM6lwPadMeCibZOdXeEDl6Dk134n5oFszETapmfISaE -EMvQ+40/BAZaYJDJ6iZJOAvzaWlM8+GkSzw7amqyKor0eBnCnLMf5YHKqqukdEo/PA04aB1jTO1Y -UID2IJOShTL7mvw5C5q3uZYKlJ01jCBuiBi0gnzTPXiKrv/lvmJyK34UGa5J+rCa7kjJFW84jx3p -URvBLFa0zp9f/s0XHptwIw45+jLeREkYerLaaOb9QpaQuPtwDLxULI6L0TEHGWhPrWTKa+jGYyS3 -swt+eY/lDhGFAPBonP7KiXflXGUb94ObUwgIwGcjsc+H7eUbk1ZVPKusCL4AXbC7HvddjVkQsyCL -34VJn0SW5n6w3K/VQndNoQYju0Dem1To5SZEeiJScCOYGFJYkLP8tEy+GGP5M7+W5Np8N0PcYu+s -Qwa3lMDtGWnfectupTB98yEzmCV2Y7LYFESOVkwvCaTCiF7NHykymBteNYKua6o8M6pGSfzKf+HV -yQRy8KvT5wc9f0CiW3J8MCyzg+56o/vgQef0A+1hSczqVzlkJ9ihkzsxYHSRZutFoSF1x9v9sdYC -d4AJcHIbKu8MdnbIGUX+1dawGLeOaNGoUU/GT6OGklQbkSc7fu06enFrIc6969PSEaZUhwO/fSSU -L5i/b3/Ux+fNtIgtCQyQZorak07B6sX4Sd97lDxQeidn3AOJfe2xODWfP2fOvPv/zT3X1S9ux0CC -dx+yRsjtqO0PDlkmBL+6Bc506ppvoCBwUTogTgNZYPANAuQahAkXEf1g7BXiliIkecxQa5cfyKwx -lELn0Mvb3K+yTR/TjNaoNo5DJ7EYmAagOA38irA+wBvUQOkje0Jj03Y2do2JhgV9BjevWqOqApYh -6UJUMjWxsjrL9qt6GbNzgnhXL3SDHNsllAqQukfQ0nuI0lDyLO+drEKr99xL8MXnuV5xVjuGTKCV -uukpf/YjspoVkIw2xKWqPRI1pQMLb9cFX0CN8MUD3ynOwFgonxriSywF1mKsA1zvYmG5inKlAYU0 -n2BfeS5/R6xKXSuV1bXphEduIFcYOMa1DL8Zsx9JGIVLZel/nKHISDJYhTnc0IrGjJ9id+f006aL -IdomZ7U4YaFargYmSGq4DtqLldFR7b+x92WtewF5axhz2wYbRWyqmzg1ZXkdtwsMv98DVO3aHr1G -X0qsWHoCett3GZlFtaBZxfsNr3gA55t99QsYwu6sLxX1W70vi8fMmIWwvpuNv64KkfL/m63qBmeU -Nj3RGd9hc7gwLioT8the6jYCPENh3VRoi0ufMEZxmuNIA68knVEsE11Q6ZTrfRl4ujALVPRENxhF -ILKNoYqXaEMk6pSN55GMbMlIz48k+CpKYkhAY8SPOkWHOa/PmTr7aVVSOdYsBayBe6sWcRy2kRMk -jksKn4hcd1NK4xMZ/e9wU5NcwuYHucLnDqb6laaC1iz8/Uo4U06eXm1VA+EL16OB0Yr6RSZ9Yaa7 -rsMDhOO0fwCgC7/Vnom1Gm5VUXL21kAF2XkENXGaIyvlet94R+yi2jXFQt38/L8H2ZNDE8Ubys6h -3HbaATA8isJGelvyHWdYvgy7hjWn3SjcMW6Whk5RiJgdomvOlmADECZNuKLYZxCe0EFPyJNx6mLa -OuY1A40J78smG+/V41YDbXDyDR+Xc3wQq5gqCVa79onoTH2taMY6umKuqcMsBDwNaIOpsxcIUGtG -tqdmp26C/YoGQdcGCGBdRsiYTjBmYf8MPCdvkS4QuuOccSicCxedlogj3n2sVBNhV4vuMqE1be2D -9wCDmHjj1wwjIpWWEVFvHJVR1XYyIOJt9cxl3YXtm4++PbMG6YpwSZ+P1cf6dKKQWJcHiCUU/2wZ -YSds70D5QqnOEuS6PapkCvUOighlb1FZ8KH90wISYcdpcdbiFP55uutEdeWGPmuq7VGJ9FvxLXil -hN+M37pr/X0is1FcrRx/ICKtd2cy+QGZnJPNQBftQpTTBTTFJozjtbmJzREGJjoznpIUC3g8Roku -5gKYyKqAtZ4zYj0HbdTxc08BjAsmMLdmg+DBxh8fTmr/yhr4ipQA+2JoRx69TCIHOppRV8ozrrNu -MG0MqDjSXEXP5mHoVEtUY9gH5p5rGsLSZbyCLld3hmQd91ug1FOBmFTknSgi4JzO7Y8LcgHt+ISQ -wAFO/0Pp86o6VnfTRNtknP5fvprXwd5MkFG2ZKq/hsKAhsfNhVwn6DemxjxYqPaek4Y+9mTJOJPN -u5SRWqk8T4I2BVj4forNNj4mCm5JG6GqdgTJ8ok4+1+iEi/ExpXx/A+n+gRezysvJYgwIMlLSFSH -3bKU0lq7q9mBOZ/MvHQjP4HdT52VU3g+a9RMFaMfb07rMp3/DOjmKKGQhBWGXOviSpTKVmcsYnAv -my5+j7+uqaedh2k7BQ+ATz26nP2AnaZ6l1mHv7/OBajuUCSumoq3vXzhm/9GBgO2UPeLJ0IdWot7 -0Jjoo9yb8I6Ooegpm8RFEk7PbKI0EhZVjOKIUPMNjLzvzycASUxMqA7q9I2jGGYpcsrEB39Tono6 -oRZ0ETy6Quf6Jm5F3I0Q6cZxUa/n3SkhWetOCKFGR5J2f3a+3YvKOe2PPcjdOxYybxdb9YBuYMDE -6mLLOiFWBx2OPwr0VOtmr1YvvsRJXgAJc7YN9FI0cRIW87nVe2HVjJY50ROEspVVYyTC6tYKEkxj -y4WzSUuxvNFbyJq1EiDi4BNAEnRt4Zzeqln48O2cqjDQj274okDdxF8TbuwTral/iW0D8P+XfXtV -0bnLV+aInyNPS8FG2Uxe/MfwMuLTvdxjivSrZ3ijy3z7lcjwg9AtL8z9avp1TR+ijqHbpCX4usyZ -kXs4+p0yD0gKmc2wV3whO4Kl/NPlO+Qw20xyG4AF2TBt8KSMIZxjIcYoiH4lnfGjrWIT0iSIpG/q -Az72eQaKECln9ejg98L0dYRn+v2qAm182GgU2kuVw4Mn6yMHaJ9XO7vq6mqrcbjT/qjEmDiEJPTG -cnsS+yr6vatQvBrGcJSBGbdheTIKrgkZZWvyLi7JZume2047LCobicAH61TM7FhNQ6/y463eHcXx -yThLDEn5WKpg1H3/iowpTUa/ilyEB1bCngNusTktv6LMn6CYOr+c0mB6F3LF6J5TIr+Inv8mEGCC -LfW52cXFGaA3sJPWv70WF4VeN9sunfGqcTJ5UluALVeMN5jrV1Hvq2xEzZ+oLPL7sESngq+VdqoC -MLq8BYssvvlcLh9A9QuGHCeS0IsSLJHgUSeAmx/9W07J4EbNwEsKLkj9rhw2sTadK/T81Bozlqn2 -HSHvztpaJy72rvVP5EMXEdVHoTCmVUfN32eP+5ePcaZ9NumHkippH5dGCjyLExSzmPha5PctfdHs -Hf8o2spjeQvjHlDSW0G+/X6bu4rKJp7O/Yfk4qvaGg/GVDkKCOXFS+qhJ1L2bvNgZA+U7j6tX0+y -vruCCLhsKjyPkT/2pOb+KW9m+N/cQ0sWkNdZ/6AmVIrsQoXtCZUGRH3E+v1BFaozc4ZA1DVt6Rni -gjrL29ThrS/h3lj1950SuCENt8dZbsapNvWjuoeJ1QTH4m0ye/7CsmiaPKSTVyYb5unaAXaD0gGC -GOjL5zhiLLC0N/Uepp8FJRu3bZ2R6BUC+dgo0SHAq79eSQWmm7X4oG3WiNaVtVOW1r7ZDgZdHlRE -LGLGJDMrTZxdqmzt+rpQJ9Z2jBh1ZqN0C2xXkadf+tZXEurV0+/7pPLxVgXYwd+Fqk2D377tjEbG -H6pvwDI2PysQxLARNlHPW7y7XIz6419TBkLkweTx66yi+vc7hkDaCv5RMCnOKKyIYYQIHoo6zuxy -yh7y0/2b2L39hn67V5+ox2N5FsqE6KqfEIHf/H2ogvcp4KngorBIhGm9TEQUPLQc0iwKcb8gu+ST -cqCG8tlPkLlQyp4eu/TAJNAogSyqUfbzCys7/G9pd4zNqTxNJOLM+TxmsfPZ3bLgc+tEatySaoYZ -JFu559mt4+nnA5eL1zBSEJJcQJLMMtDKIFd1f6RSUynVI8ewGUzM85y9efQb3kTCgktrgZ2SdMRd -JDPCTDO15yGDz0UQsJQNutgKZrdg+UUlFjcnjzpNG8qYTrpEjhJD6JtoCSBvbN6r5HMKl956xlln -0TtW4Vh332C90je/vwpfAKh7hrY9g8NJKU0xzyVTjVOAv2mHfcQQb0Bu3mRDInajRG1bC4LIMo1C -BDL5iNnx30sjslqvIXUyrj29ePElFhE5Cl7p4K/t04YuTzMfdXMtZ0+If4/HN3HCPMGnVg7xG9l2 -zJGntoHp22ECLly//BwKx9QnCVGBgQCnMgBSxYI4PM1s7ZOD93H7NVivFOQM7cdjjXOlcIOcaPDK -z/qDRxLop6/70KwtLs33/r9g4A4JtWufzEmWp8AGIHH5L2ueM/mITQ0TrqgFmFP7aNPd5LQDL5+4 -X6Wdol3Vjms8myiFt/5WybShdMfZBI/knYREDK6ycGFqcNdxuVyjsx93Co+OP9Ra2s8e13lTSGwh -2UWJTd76viMEEdmVIZ8tCFtBSZdXDVy/IaJrh/z/By/ybX68pZ44WqnlJIQxVeGGctXvS2NZm1sD -hyt+2mBqgeSwUUL9JS/4Yo0Za0rRo57iMCTAYXMmK6ET5NP5lM13Uijo2Z6Us48iQnwhHwri7Oum -5fxtlTP7md3ruKwl4ikHBsyNz8twxuo5ehFpS3x3Q9svaM7QBpEiVqL9VZjYVziljRAYFvWJXopJ -89goAf97A0e6fCnYVVMMchAIOZ8CByq3Vctg0ssjKmZU5UUJMwyNs/ITERd7CTbuStLcNA/Uq+fk -2UIxQFI7SMqJZRTviJYUc5NR5bvUcrlGoRzR8wD3idGFkmFrgamuohHjh1vjxTE5jClXWOVazP7G -2L3Xw8TQlxi6+CQjXpbIC6HPv4HylgnEm2Ry+r3a3wyy2B3S59kw7JtjOFqI9dak8dEWLgbpZcGO -X3UJHhoPQ2HmyCz843ZHxtJz3m/bEPeaXWbO8UJg9EouMhmFsw2TyeBGX907ycqv4HOkKYloE2WY -KkuxaaOXfjzEEZ6QRf2YN3pPf+4uzEC9Ew2l9gi37nByWbOXgSuRZ+TMDDgg1it+krcUSOjTnOGM -1iLAHJs9PyZNoTmzjKDzBrLgHEwH2WiWAgteDKQEZrt0GQatwGzX5xLVa8IfClTDDXegOew95E3o -tB79BZgsWsgBGMzfw1rfWU9A7mM5THSMeHEfrkqlFFu2/ztZBLldRI2BzVPOH/gwxkCyOlu1IZFJ -8rDHwE5j192o8Sz5NQgcOiSgdJ7ksmvoqISZclSqc68R62IcVHjztqEv8U3sQb72lodKL+XgbiBx -nQe/YruEOFFexAMh1Pm0zVBPnnYFFH8OxxOhzAR3T+Mi1G7l3uc46rokwonZRLIvPVAwL1uFI0Xb -8nZWoAFveHM6NbTCLkD2i0wt3shj3VjxiPhWL7yJBW3hY2XdUVJltscjuwOM/pnfTt03YEm1Lmin -Nr0TsfeTwxKFPq4NQSKvCrthri0RIZWjiXUOvHZSQLWcPwhKZ1Z6SFej9NV14zTAKyhx9ie0+Vsr -+7LhRv084c7Z1nYweHdU5o64iYHjSpeekCz16zq5umf+jrMmpUP5pdQqUvv3bmJof3KGX4me49mw -itgI8kfBrLzqW4ggRVUyTuNJ7wUgE9PSIWt3SjP0biffGZkE7zscd+My2V47cDZQaaj2Rtx1ZvAU -T0Boq5vRtmitcyIdnp/mH20cFWKCsebrRCXkB9o2euRTsciYonZnebwoWgc1y9ipELDYKsOTH12g -1ugx9z0v1wtoPVzR1HU2QUJyVEVbSU5qSVGciKGSG7j3hC2xEL6fpnFr2tynGx0GYSlatYfxEzFt -HLuSYs6+3RDRN8WHfyVU/OqyoJY5iZvCjExP2l3BFPvcuZboyl84VUF5qhy9NqAWQjux3byvHgnz -dqxSUKGq/c5fjJRMAxtFqEBC0/u1MtakZrJd2Ujuu2LM4Zf5SaJfjd308eCZNfxmzVGcCFVNAh3s -5+smbysEyZv+NrdOVFdVkkpxyWVRVvQv2l4GoyKA1eGGdt0RWxhXIoNcn+KscI4flZ5MF6DwXxQk -K2bkFcovNJD+zF4Zt1/H/O19Hi+DznEzzB9vY87DTL+rlLp9aHJuy2QsvwDj27QqBt0INoWArcFc -z8/vpjyrYcNVlV6K3CWHjS/I5jUZNUawL10l0EGQtET2If4DiInyT/LAwCnsu8nfNulGL/bWXCoT -wnmuvrW6yVwu+6aFg9IoWc3nxm5ASJg9G2P66MwiA0iPaBfm4JN5HhcDEAOUshtgIQ5ZNnQ7NEfg -zmfE+64dtjUqwd0T0yZrtpgmDKwqJGtkSlIAEsDYCbInM9H1scsIhlqkrr7Wy6CAVeEIPaTeQ0NQ -m3UtqmB4ROhngP2TwOQxO6n7KaQiDj5+E38cY6qYw0PJ2lrHX/f1JewRg7CpXZSYLSjzEZA2DU+N -Tuo9BDTESzfsOJX1B8wXbxJSDQjKTdtdHKgkXltH1xvVvfW03XGrkwPYAD4USv0RlUbhRGXnOqbC -/6BAVle905AT/nJUUnSAM15M38UhiR2bJipupGq36sH4aaW0Gqt6e7At/PEcmGXDCZkOokBofUDe -pWuTXLQE6hAn8dc/9e4GQiA/F2Y43Vw3NcDMWtNhgEQkY1UbpongnyqOYvdgZdNPugvo7t7A1hSH -K/fviCC5PiOgtlx9CG3oiIMsHyiuU2rJtA60KxIDaTSuUhKBiu9Z1fCjlzuZErwHwruxcMZtK2co -xINEo1km7Ug2Fw2mvlYF7RIpnkpQ6T5vTk5jHtIJ4KtIvI7wGjBhyPaOB++KFdk+vSh6GYLrHr6q -vL6fgl57cQ3QW/T6/TKYZeP2RyqGCImD6rbV7kdA7Sakg9UOS/xH0f+k6thLSV5BCKbdqydVlC3R -KcX4RFGavIwiyf11gkKlbVFsAQ8Yx1xOnfEASuj5GJ0M+r8po/GCuUT2jE1iYpTMM9NIycsXNDsi -tE6tBJ1vILSCqlSYZuU5QU0gMYYf7qpoGDKKv92GckCAQc2a/Kl3LsJykWp7iGu+WCafFKWBxwUl -lIAi+ojUCUSePZZBXpRvx9+EfpHX34B8DJ70uPP9cFxfWyQUTDbXxGGahFYSWlEXoyIgSLKb7ZKd -7blFmKTg1jJGRk5XFMqEDrfjoiqMXHIv35zn+82grLPH+0fnmmc7zR923VbpKsHAdSh0qXfdtBMZ -THodE946PjmZQm/woZHCtxrkXmMhpszm4bsGCVPCoEiDn+VjNVypUVEgFzELqkcL4qkWWi6kKlWp -uvaFm+doM6JTXi2VqU85JYP+zS9ezz7efzXVNNTuIUsuCAaV5IcjnvL3nv5GE1Uns1XrU3DIICU4 -vqUGdfWJPn6HuaZkbUA5t2oKQoTNuW6kCexhKdTqx4foUe4v2cYsoPJ8XqtZS2AjdU38H48PnEea -XRBKSWyLuAGYJf5Wi0+pSPGdPN6Z5yf4ZutZF3rwvH63X4qx2WDz9xoPbUoKSmr3G4M2wYMuEJ0E -NknOPxr7M9qIsS9P7YYJfx7mBjk9o3oJSe5AjJRv3MneKGFzFGxxGpWX68MOB0R+bERIxlrrb5zl -UCLtFIRSGRjHCLLWyyEHVDGQ2NjHRE+4uiNXk5MfVSmC2nPwU9z2Ooq7g6dgo1YVuug0obyb663/ -LvpYLxh2rkVjiIgKLsx3+jlusszNYCX87MxDEtFZTHlH4Ws5CY/6nY++HT8T695EoS+BhpH3Khhv -vV6wh6LBuQwhUgCpXucQCNTqymePkiVpMjEiPejDueYiu1zyQtlkoBclgiEinBjPO172pwzO0eIj -IacHPmRHyTG5wd6h0HQ6nDtiEos1RShtQbkNS/zFXQLt5TFkaICqlBfvFWUpBZyRGRKLjqpYa9OY -Xwt1+R8qp8dQWz6+kp3IB5cDj7vg39zUVMT7+NCYtjVv3m6xCF3bmD5K8tPPSMcriyOjHHNXwEZt -DpMGRnu4OJPKBlAuUJYcsXG+7JNOtXdg7FoKyJxS5sCxEVJa+tnEDBKqBYWdvu21dSpeRtarTSCu -/iJnk3VEzuojeYeQPN+vPAl5l0NMM7ayVVcGZVDJWMjY9L/x0a6Pqtv/z+wlkbAM389Y7+Krk+44 -txx6jO3DU2WcX+w1W3PMd9PCwAW4QLS8hZ7gXRbpPK2F1JE6AhP57EfqWWgYm7kPdeScYBW6HWmh -AcXhZv2NtNdE+VHSpvs6DL7zA9kLwtGJ+T5eAV3ksLCOKEd81AmlOsZzOkVpFsy6XhoMHvJYDQyJ -hH9KYaXyQSfExGYHrQdMhqQIy707ik+42nE4HQfkH8ASd6MZjbfJiTFxy1V6L+URDPHFg3IBMOzs -hfP3Gf9rSIULcdCGRsHECYqTwsCESKGCH7qww3a5prfCWdCIbBlzsSgIq+63CkPx9GQhkugqLUFU -ywi7d1qimXSqkDL0NdUAuBYy5PLuunkRXxI5/C6a2SJXuyNALItZP/wBSCJaJb8DLtSBxc9WtW5W -tq4NDD1ti9B6pdqR/BT989MvIE0Qdco6+Yug+cC/b+myP1vcLbjMZ9OED1Nda/LO8Xiqg0MShnuh -J3eN/BOwECfub2/YiirC3LSqVtuqkMvQnZNENBDV2Zh7/vilUNKvqcF2yboSu2UqYUIQr5lMMran -JSUIvl5p5OeWq8Fy5roLrpx4BUVQS6SCPjHlBhkkLUKKOIIxSW+fdzPaET+/hPCZpNcv/9mGrBvt -5D62NBHaXjTLo6XS2cuHjW7QJDxj1yRZ/Jh7QWv5x7m6yf2aYNTfdYnuIQUcuAYcI7p9bfZEpFw+ -KsCvBzKoJKVDVyh1gQ/0z94VIAhcrtbxIhJ3y6cCz/HluMLO/x2CoA8OTZTicxk/0cY+rHcXNHZ2 -wjHWwjElG3aju6n/fnzq3sUEoArvI84tpEJsYBZLcLLreCjhHBwmyJPv0e5oCHI5P3gCVJRGdyIe -eSjJ5qYoALS4fpgplZQESWT/9udiHUSW++Hm3wE9zsyB40ZUHlZVtdlkDwb6rg/feRBT1Hh5xXuu -tmAVKatAlfdLW+pAIuhD05ILe7SAJPHg0AWl24u0bUKypm97U1hUS2KeUYCv0H/hQvW7sbXgDP5o -0aNbM9FnnpaRvUC5KWKVIhMS/xQ/W/ygM3KIhnXidWgowkDjWia1wB8fpM1UqwQmhc5e2cP6lCvi -ztyKG8/xljW6SMqiAZICJMY06RMrl+Kuj0/bvNPlZ/VBud/2u8pZIQ/ns84sEHg9Mqjc2aLYPHR9 -RMdQ/X7h80u2uBo/zCsPGZAoIE4RvYhBEacRL1KA8pvrmGFo7G4vryTpOpGaA0dBkhV1ZDtN58tA -3mh2sTNzWaoNfLJcrbpupfisvpLe88aoB+ydrAqqkTOleZs2misyx3zuPtbh2v8eWZh72GgD9BCJ -UH9G2ewfN0FUDuju/NVNZJDoT5AXI4tOTAPUh8luYEO17lf+kpd6Yz9X3QUIT1NqV0o+0CilmRar -JWI/U1tiDLQ1RGI5cBwVCL0oP8TDk2wC2BJOP56Pv46hP+2bjt+0UVlWAPXfbo+4/z0nSWaA0EwU -Ju7vExBc+QmRjLAYPUv8EvtXAZ30Sv06WBFHN+IMuPCAesLyjLeucdNYUD8uRKza0bex8uS0ftJt -1zAzrlf2tQrUeTNUOY6LZoi9wSX246QFQd3MNwEEKLv3npKMUynTs3rI+4SBUlwINNwNiRwXVNBP -fyPn7uJlsSJP5WZpx2qRhmifjoBMUN5iz2fJwkETmuLcKiKRf+V/M006mpTJiRjI497WWHJCGiDi -+znvrnmKlHrDtlpRnoLZf1GeW5rvEA8Fe27IQdHFaPDJdEoPb6/YNbh3w2hskT9Chw6aw6cRECv1 -c+vPBMM0bigoOj/2gic1rozkEvSBPk92aDDDOZ5LrUBFjvx0CzPKddhYYKXKgCrGy8585wh4q+0i -rWF4JJD68D+xoIAq8ICAEiQ16goDdrMuZDi3Ij4bJwgNCEA6b339yRBHif9NKBVG63vZKMqYkH/F -bvdUjxLWhdpj+GtTbbSmeeww5IuCEJ6oGUAdPbcxMqTHcd2R7FMMerX94+LzvN5Yrrr4UJt0gh2N -8+N6VIXZ1W31SOAjrYMi6NWopJll72nicWi07xMfa6K4sn5YpXy7B/w6S5gpl2b7xLwYJXnnMcC4 -d5cy956rBsL/vlLDJXV7VPquk9dpdT2RmnHtz84l/V0LRM1lCfkftgmljJrQhc1Ls12r8CNQMk/g -Ji+kF0PfWBIZ6ALnf6PPiXWYfF99ZvzK1HUuDW4uEbXsTUgi2RLsF51hZJ4MOMwn8JPAvI+ONEnA -b7GC51y8N2NDi1GRbg7bqVeqjGwLcKwufRv9DGKT/6zw0kPBVNFNb9TfOa6c1v31hQIIG+yU4IWT -AdN1c5nwiTxzzK93UqOCbcVcImgWzzOYjS5RJYx6nNZPD5fZiv+iPmDnzs8PuH0pnZKjwOGDdkMx -JJeORJLP9/iU/2n1h5Avt0ukbJxdEkNTs5G7pKvGWGIL39gOnh0Bz9ZZIOaKoWcIeZ0UC437hFCA -+ni72o+RNmg2rFAVamHTF8rcLLA1jUx9lEHm2lNydOrWSgCdIdRB91Obww03SLAkyFC/SopSiKTm -YopNaRoG8PJz+uJgeHDdKJHjlhXFk1Jv1gbIW//QIw/Zw1kEvL8NuzaPKW7LNL0qEuN6XiiPY6xZ -STt6CbPoUmEI1a13Hd2gU10vtasX/NIAGcBhpcEkE1oc09IwH0VyXm1OtLyquP7z9OTGNY+/mjix -N8tqQ3IvlhpV8W/gCTLeMfqa50CsVUB12wYGxXocuSjBMcrtL/WUbRGKSMWFn9YU4ZoeA9GTJtlp -APOrt1+SOm4zFOsvDQOaHQuzkPsNo3OQGvL2pavsSaGDPnvp9aUDyKrN327+dSjesbmjLpbEQgDA -/Hny/KGEE23jpDjTgtJz1i/KROU33nZ165s2ASlFhuk5EifOyGjZtKVvSYRVezv8AOCrldB894Po -IwDTyHwbyh5J5nCsu3Enj2DNNipJwsjGun80vtGHCD8kzNhwhb75pm2//g/FHQ6PPhD8UcEOkV4+ -ySl8gFzFtAPnzJuMnEsUlrX3sg17aQ/3znKtDfTXhcE41Kb5i3b/cc2wrkTzSTNV5krXJ+GNrhhf -VCBJgO7simqi9YLMTlEyCtzo4XdxF2A7HTXS2Dv6C6WSK6VQc8PFjIborQcy8Nt2hA20IBIk5TbE -DwZjphD1ikuu+rTx6iteRxuXH1PkkflSwm/NinrCsuKMlrGS6Ayh/+LR0djoxO00aFp9n7HldlBh -dEaqVnfuXhYv9bhrjR3eec0S24EbIUg3kXZHMJqUg36Xmg9HCC7a4yXPf3oQ++EHHI36b/BEhHXy -HHrBq3T7Xu+i/mQ51Lb3XABVcs9fTzU14DdzFyRTfOTC8OIjPNlGkb7d7xeG4Ti4oS44UBhFZ+rm -weRT1aoYTpcBCOHMxaSpEZvE3TmYDQHeQthksxAcVluxsBz9RUiuTW2RF//lKFagPe+t5Vv/sbeF -zQNwhhd47Nx2jQ9QD66ZoqpCeG74AnZDAUxKDY/8KS6dbD1F3gEpPdo2Jgp5WPSCabJi6MLOiX9F -zDmvZCpTUXH/9VmHlQVUa6V1NIYFGfi8Orf5kd8m66TQnAnOoeTrCd5zZMfHB3GzL77zFW6qRKae -Ir06mh5LlExTszrJWYmMdK1+Nd9ccOSkfsuuii2nHAQK+ZtErdGOM6qelWhS6p14q1yzRidI3/qX -Ek/UrYxDxX4b7vRZB/hlglspfcrghtDaYnRf4N5pPrcNAedGpm72Sc+5nOKARngVYBTZFBlK4m70 -JKDcb25qEklai3hsWWv7+AO+FkwZSpXRgSspA2s2xt5HCacb2QTPhVovEyd5lOO8OentpjSDrYF2 -bfki7YV7kHbkGVdzvmhILKdXcOtXsOdJjpfNmjWrfCOy7/4f06Wp8Tf++Q/NeGCnm1U+LyC7xQua -FHGJ219yyvuHVjOcri8Jer4DwLquo7Lp5WTW7pV1dElL+VxVxj1J5rMATOdJDYonvtcqZ/JGhrxq -2Iy75PWiIkSwOAO5RMm60qxtuj8sCcG5BWIf9kcmvqqdgp+qqk6sL8rITRadMA9541NiOB7TuPZA -/Ga1d/TYN2QHbsFtOdZl7cAPSEiV6OzfjabRUVlIwbqzjhXgz5hrrr/BVldoq54Yed2GVx1ZwVjt -SVsTVjfT73oATGEv+I+YJ5F3nUUQpKWQHBoZRrUEZbB0VqVfIkt522goGAcR7MnMy7jqAVKpJM6o -mxaZ90UvHjVxKvp/bYUac2NeDxxWWXVhJoNdngQxiR9E+6kTEewLBWTFEfCo08+53BCN0XOoXJ23 -V4nkwiRv4WpUqhWDna8IwOWQVqUqNPgYKXNVpKTveNFBlpL4o5iSok5/sUVYWXFqdWFWjM46xmMP -d3HBgHiFpQlHEAD1vezWeWIjZpF+sf5CK72YhzzMAm0b1+9w+GOhoups3dgJcUetKNOox1XPlDSy -0l8DEGoUSnMksKWyE3leTSz+JvW1Rnhq/RrFHI+6l9fJji4VNhblL5zX8eday2z1cyB3GhFvC4CX -XyK9Sq8z4gKynji3GiiEr0wlGyUz81ir0XvWxxkBBxYtRiG+ZnxDbHeErV4ahI38WKXN2JiSki1k -iHBFNGg9DcfP8RDJGaEzHbuNnYqSBemqueshBQNTUz8jP5n6bw9TtF/5QqVGoXfkikwdYJF/CtyT -y8l6P145vYHbKTMu8Yolo8ex1bXR7MwomwW6E8n55ciMjguKnfyTnKH1w1GzXrs6XoXyG+ARwuKg -k4q/FAkSpyvtAkhrjJ2Z7qvBIt776Ze6NaCFAnVjtGYoEVRbBrBP/cSq/+3EpW5BB2G21L+L3XEC -YKVaQW3lX9BvJ1odop0KFIsxEhZMFs+r46nqobmvDZNI+x6ASePOV82FPYQhM8xcYvkQAWcUxBcL -gjt10MRfq8HP2wa+1wAIlg3kz5jnuVNIvdJz5iVSyjWAcsDEAkh1jaM0lkygHNC4kcpp47cenGZj -UZLRPK0fHubOKRq3cF05Cmnp5mP94MN/PLnLhLJ5xOSJZBohSgEQMHv7Kw4C2pnnSyKxghsM6nPp -YVTdKRh6u6E5dfW7Xj9jk7cZsc+eTSMcp6o/hDKr2g15aqXs+iA2iBD3hCrP0Q/eoF3/+res8+jO -YK2035pt3ZTRJkGHHUYLhnuEtXKArgMBJgToZhYpeLf9a2NMPDrBXKiS2Mler9mKhfhW5A2ednqE -VTnIqM14/FmEGfEhDYIlskMkXd2TYXjoFH/IVzLBytu9nTOSX8p7LP6CJvcAKFC5Mq+x5zZmggKF -vkxisqAHdvkwWUyLE/MK5e86W+iAOmAD+qLV1MVeGDzV+pAPgJT3Ffgvg4WoHc0gfXodosQ7UnmC -H9qs7ZNSOd4fdJlmOnE/7wx//fpC6FzQWkNc170b//VYRmulZ2BU8cpjzYurYpAl9Bl6pzULt11r -UON86W2whLyl0125iYERidNBI/vekYi6F14KZ3j5A7QkYe9d5k/TlMbFU1O5AKZlCa3AEUHYrs1V -zrTy8NlukjB0HSNtK2SSsdPdxYA5dmHbOFrYBWG2khOOw9FMjNebr8nAkwGPmj16LHFE/ko+UT+J -9BzhKh9hQB1PIVvmmPrOsbs/IkQYLqbnwjEE51U2J8vrxJa72jFN2BrJLG+fqJIbIIM+kRbv/7dr -y9N7qT1t/YMPj6bw3tqZsBI4070JuLN5P5ASCxIU3Y7QIiOVELgc/QG0Txe+7we3f61rUacpF8iY -FvQ2YMc85dXaBz8HLLc2LWl0Qc3sjfI6Oa8Tp82rZBJqiZ6BJ79FkXLUMgG1DIzXOGf827aHW5jZ -XEvdmyJQGmSjP19TMb6ZTnmsVOuGpQq+eoWfWdHeD7DLRqi53TvrIBDHs7J6EYs23tWWxCIRwTPs -Rh5pVY+gjNI2zE6XBMrImlpBLcGQ9d8fiGrYKDVYdGxYY9MGCJvoNCh6iiUKAjexTY57TgQoEExD -r7qTC+MvJeVbq/ZeYRy04361u15GsmhYFPuwwZu5pcF4S1mW1wJbo+TQUE125+4K+JMJ0ksv42j0 -OTYWTGOSSaR5lxqpp7JSIJw32NSPNFa/7yLhU38gAF1gnR22qJuHyr49LS6PFzFiIbA76dZKYA7r -zl8wgyR7zYMR2iiUexVrwSk43CEzGYZmKiuP2DgjpzR5yJIX1+q7dkH8lFcsAb/J3XGB2K7Nh92B -MiftJf039GL/+nowZ9PUpdjguICSwqkggOZl9o2WftSSGK5m+jFXLUmWxsk33RvvTFSMuom/zMHJ -7srWJOWIL5qotvSjlRBpElepGTaDCyfPkbijrOKifOP3eUC2ziNiT8clh5I2OTXOaekUWZhEtGJw -sTYzMKci6X2XQi3TCk+r0PMNRMovIh3nfLg443aA/4Qn71CoxDjqzMi8GLkEt+t4qAbRShpACSNx -JQDx/p6OZK4CJtPBcN+HXGg2SxtVX2Iger+ncpgrhCD8fof8mp7oIsHYb2ULoYWhBTMdNjuvPwIO -cGoKcErvavgEkKrsr4624PXbjvIQ74JgJTGOR/7zPuCvqERrDRSimJ4n8qeNLCQUHBwdBHvZdEWu -BsaPhcQiMEvZVFbfeBz4XdvMZLfeXw2ElDJ9qagXPk5nzmVn1YCTqCC2DNqyukDFt6B+rQmZRDd2 -gwx4ZNyWngn6djc3iAOpWTuEzjZIH5LLJQc0r4aJT6YA+hWMhlvMmg1BhGrwmkP/CxwLq/4Y9+Vh -sKFfj1I18uvtnDhepJYAWzBVkBYlSVaRSXdWOSRjCahyPji8nC94RU9xyI5YEPugbdR54Sy0qMXp -r5VLeOLqGYip91jA5eqcVu/xnCDd/+2XijOSNy9jtXCRpyIZKsHzed6YI9+sWpnjfq6nGJRPV/kg -DFy1Tan/dAVqHctaXDyyoIGFVCtRmn6nhmThXFPPufLt9wtFLTkGK06lENgRbzexJkZifRtakl4V -qqTdO+bGkY5CtR8lD/pTjA3qwWuMyGT0MSHFK73uZTMBh1QXrmGGfMu8I2UhliUSLq9sVGdNouVZ -dkmqMieVrLpfX/UUmo+/KFEteJR4LscZYO6x3flf4CHBX17BlFlqStbpCMUA29u1dJm8gz0a/ORX -JEmsqA+NGoNpyJq/jHsJz0wDOcLR/i/Gt9cTRJP6KM3P7emQ6ZycqvX0NRXXjY34ejI3ukbOT5bi -yvlqhvXvJ2W7l10KW4jKnllWKtI+WZu1mmH+glpAOs1YmGFoURk20766hNC3NONO8tIDeKn9xQ4e -QzOjNflVoqr75M+JjzZkI/GzlwL8HukYPZXagxPx6B2mAKiJXMTx6hMNb7+121kEeqgBqsMzWWs6 -JdcXUY9QKBTzieMLljSyFHALA4/yy3WSxHF7/LlW+coXe2ciq89hFAD+9+U57qhj9qjLXCMR9OyW -PYpzQ9eT8qLvgYErfeyGl9JvHmLzDSMG34sU+525uOqxD847E72DvOvxOU+A1rkhkZy1UFvavA1P -ks+ZKeiILVqg/7MsKC3aziut3KqTJgB67btFPfxvWz+WvO5XxLMdwwV7QWzw7l6AFU55pdn+F4Q5 -nfnKtnJyp16LHpHt1fCbXnM3POfsDs/OAKxdC2vPrEnWy2T5YJZyAkUEDK+lDA8a1lU54OMeyYol -Q4tquXb+oHC5TkcVnCJKJzzDRi8GKTFGwm+7BjrXAnE1G1q+BWxvFq8w/+gzf0QHGX3owtaK8ubP -A5IQktPA1KgvV76IKwvMjPA/SwE+l+CFhNbKJscupsjMQ6o6fNurmed/oKYDL5kIq+lmN9J2vDBM -fAaNLbhljor1zphhiYnxTu5wRyzboqB4xdWkzp8Sic4jPkyvmB3hbT9mgleoXRIUFkWtZnumb0/H -jlp54HprQPtNbd6b0c7LHrdmMLLaXpNbQC2Vh756x4UsWbxZ0EvCGnGcpq52u0n50OCRZmex6JPh -ChTps9xsN6yZHwau7dHUdH7g/qGvcImEGUXmAjWalVDvyuA+fIEx1V5r5EVFnfIiLHOAv/BfdwPc -SIhrZxzXUXmKCPzV3+d5qV3Qm972Qt3pDq/L4v0I8T9QwYwCMqai4v5TqBTXujVr1lU0c6s6ZQCg -dG8dWNK8GrCXvTgnwRmVjtEsh+5Jms0q3IeOFfdymuw37cDS0NsinPIAM8AcCeu4gkfoEc6In+Jw -9pbCo6QEqszkSx79AZPBUOIklFpC7Glf1eMbitOBBYMBHqj69iQsUJf6rUZxth3vl87fjK67bGaJ -JXilKWEmKJ1FKjidqApyXcagWMi73Cb9JPlU4/IVbL/tq5bS5R8dqPtlvG4pXl8idQdVhAQ/aMZe -LvBI/ScnRibb10I01t7wA2v97bjngkHwABHfYfvKF5F+6KSM1S8Sr8HdGSMaZB9EBxHFMNn/rYB/ -DJ9BcebnP68puQ9MuMHNufS/gxdpTNPi+EzLJ1ypwTVDc6wPVrWM5XhXvqYdtSsKcT6GQ4aAXI54 -+T/1P+8YJhIo1Ca4y4nGLcn6xfeviZHnPf0ECS/LOj2A/+EAFBFthz+fRcH9uZ8ofDcczfCKqro6 -9GK8NsuQo8w5O+Iua7sKeecw9L3C429VUbZItJ7VgdoWVkZetLGyJUuYbovwj2Qr/EivRN0408g7 -fbLGoyRj32P8G8PuT1pyQySEKkXoYGh1nl0rNP30hlk6IBZV0eXkR6183J6TfbZWPQ30OhEs6DFY -Yot/jRnfdEzoGYlp6JCUv37D5W+CgzBLr3dlYJhGhaUqQ0R41U1g9YtZzCN6x8KHN/2u4xWVq5BC -8fmtx/KpWeBFogzD1+K33/1ZF+mDzED/8uXB1sOG82n2rp4ySM+RmDkMrRrOluljgJJBK8MjjQhZ -cH2gNppNuL0IhQZUfCEFxDGVZrzweNzUltJZS2a5KLvbsKBjOaynNASaHBGWLrsH8ByfmHDp6Ekn -9FtJe2jx6h4PDxXI0p4LBO5w0QNYe/e2oGIRj3enSM8hXWDsmQ22KPx7qkeuXykkIzLWS4Hd0IlB -WHlKX+puhoHCS5QbAFraQWbE+1XaW8lQXnaB9zrBVrh0+rNgQiQlNfEkLM5WNhWUxoQUfaG9/d8Z -tVK+g/MnNoIBEAsicdNYFVD4eBwzd5nAYNicN27wOYA0XLMqrI6V21V5dieLQyZIfiXfSOxtr06t -CXfMDeuIgv+5iTDwq8nje4QZfwy6xKf0bm4lsSHGG+6hvveDGW1Hn0OLTD4Gy8kuLGHd8J6+PBmG -30XLBQYpOF4ZwFGky77CpDATG3f4pS6k1iHEItAFeqUH57zLj11tPzAOYXQut4sUISbpHQkaUpnU -gXn5x0bFAby2OzxAgw1v71xA/Fx/fdZS+eD7FHaCgwUcuyHqts+qQL7p8FjzEBqzDYh+/5S3/SI8 -e0jePcMIgR+4BSeh9nLZzC7BaMuiWys3CC3ek5II051ICNiyY/k6rBzIJnGMBueMpnO/PLz4nszk -MEUXlfM35SiST3HY2ceMI68Z8y30HIE6TxuayFRJKUZr+VmLixbLCJUR5F7F1KqTYEGy72Em0qfb -1bZ5wtP0xmO9Z7PayNT87Snt3R7jnfB8KwmevQuQDHzYGe8eGzLvsLbLSbCeMF3jb1r2J+sj2FKG -VY0rRzqjLf/2UlLYlaCKuQ2Zd2h3FYIYYvgK53u0X3xsKhK+2Bktqoo/A+FbadzPqmyPdHmgH0Wt -kknIdLTlECmzjVVeBZinWMhCFczeweA7VC+OlTYR3SUMM/73ADM4DpCPGW/3/MGCMuZMD4PGfj3o -7Y3RTcDBk3ok9rbKY04Ld7yaFoBveVAYV+Ze91GVHsh5YwRkIoed/CQNqt9v7uCFEsVGyNMig7vX -d45aU5E/q+0Quz2yIfMVGB7tkDAwcbT0npb+P+9hSdBHbhgsyHkwsfZcQUjnie/OgGBXPAKz6mxs -EjN+P3iCCc4aMrpqQcm8PgWueOCM4jN/05LVcpRXc3AGgyyJReYeeHkWkz4iNbfLG2iVFrnXiMMU -PGRPI/kADMkPI9/VLkU3UnIZvbpD5RvGkJx3UrZl8SnccGwz5zbXPYizjrpAsxCeTeH8Lbt7XKaj -5MsKsYo8kPreaQyrCS+DXQjAcTg/s5RbwaHqZnRPs0RvgCFpxPVUCQUAQ2fLcwXU0mTn//iFI7dn -dt4tVT8qqfCNZ0BOPKK5N5OGctojYRQAYN1kBsM+yy7PcJOehyWxd644EpBUQ6Evr1DqWqupaG5D -kdpE3yvkdy4NTdGdkG0beXapQv8xn3uiROhBg+0V3jjo84xaJFaBsf1a+Sv8DlHWbvczIAVkC0SZ -eKm2TzvDdW5y2H6XGVf2I5KSAyYyr9OFek/12HUpJDd1TGbXpxYPGBeRIw1Tz/PsD0qY6pr0HELs -Xx611wTKMZSa7SUFr0/urycc+fal0ln8dp/16FSjV7vVmgWAt3/fjvWz82vh8JUVE92y2mE1BRhk -IFn80SDlZrg6o19iQdXey+OuA9piNFXRsu5pLQwft2iOc5VKomAFA4VQUgWVgYvs2yYs9jdRUXUb -UY/BoaADf2TmndbCG9nwsWMqjp5Glw9vqM35OtF5M5awRywP0gKaJ5d3zCRUQU4zqxcbKufQwKlg -WqBLPESgqVsFx4sVmCW9avONWq0HFqThreQjzYSbdiAL2hheSyxmeuuXvYXs5AVz1UFwEJWqWee6 -IIW1jO57qTo4d9gKM7Fe2I+5kVWog8T95p88CsJChrusmdbOFg1SdNBax2ar9VemOW8WhVoB3cah -M9zOzsMU2lZqj3kreU01QfU8+A0L914ODsZyLM7xi9gSFqjeOqxEj7bCUuRqmOJpLUVM7iFz4jxq -lWc129QoeNz0QO9SDwcqOjTykA4UsTeqew5hlpU7G5ZmN3HaraPY39pGBZvNwqDwHwqJ9N9dRJ5i -6KMDkfCWKV7X6tZ7RYg+gpJslemkaAfy9jveOvClXMB3zoHDWn4JSBt9iA4mKkHL+zydEWn5wwcz -fNFM84RoV8b7vBwF0Hss/JaZXBJ0AY5ZAwND9IVuIPCAWAebtkYXzN7UH0cnC2Q3d/7HjK5hEnky -/4a7r3hknzZhf7FUStGwdQp8q++d9lAgUlamr1cnf1RqivNs4bFCj2SEHHtPPRXsoXCIE+TY0nCc -O+4GKczEeNHg/anYx5jklpaL9VJogy8ASuQBAmI+L11+xFPtZ5rPZGOElVA88q2cKyBcWfoStUQf -J8m6Ze6kD8foB+ZZdzjYnbTGreaUeJqOf1QdRAorxw6cPniP7+t0PGn2ZcQ/TeaP18ef9EA+DSg+ -UnwVPbjsXtMhyFXv7DxFRp4ZP+kuWtF65+0g9nOxrV+kkNApqWal8I4oAjj+XK61irK/INHgqmRP -hejYN9YJf0fnq5voKJ1pFhJDwxkjUJ92eXGr2rKimkD/AoSUu7HLiCRP7hqo2NN2Fm3qQEeis3b6 -UlOAjERRiyNSeyn2ibEm1YOe5zdTdVtNJd+xZu28djaey549XbrNwVBGeahMjcyVaTIW+xsmdmem -7mJ1ptrBSRYt5us6CqWT7EUz6MVlWXYkFZOILr93XA2qlrJRLURN5NLq7ttqXS+ItMB/jVVm2CmO -yAlapYI1sY0MTVZRAQyQNujCgmLIHbz5ruzjMe4ZAfHtKQdRDtqgYjgOgqpeDQXDW7t49UFHmWoi -szevBYY8gsup/CPDTYlpvQ0aLnm4A3am7Q4YeLLE5S7qld2+AIauiSbLa2Cp9gbcHmLSjDOX5yJN -yPPu3+RGQz3OfbslYYuc2If4IqJwITuogXkh14klVtSBH2Z8u6OwASEU1t9oOjncavAjPzw3SZyk -1/2Z1xHAmubxFJGwl/MgwOBmt0Mt31S4h8wqK3FBsEoweYV+S52bS1mcUAAI+H8jvccmLw6INOD8 -Sq03hD8V4VhOsmEYqaWwYNPR3LhYw7gFUUbLFz+QQ+eTamttEO08ZOyZvRZpiiqiDbfXupL163w3 -K2sGfx9HrcdnvKSS9wVKFz3cyLriWfrMQQjgqxsZ5xY7eMYcICMPbQVEnK6anQGMn2JqSLCid+5+ -4noRp2/eqecKiaiV04YPj92XYpHmWnHCM4pbb3a9u6biUTZgEMwgvTwEyTXIGAhCt2vz/h/R4Q67 -23WKgJM800xhPhkCpJO7lD49PpJNdweCkj0tLMoffQ6yPN4UxEkRx+3Tf/wU9x1wxGSBX27lghPQ -XyeJ3rXkQ2FwjWAXeOYbt/0GFPd/Zv/JLDwGcNDTaa21+x/xtkN53wEXJi4QSsaPmlT51vdB32xN -TuUPzLhHIETZEC2bIHFxYms+Xj4LKD3JFkPqR7klTZDCfk2norOL7ipEUdlwkDRCgjgIbsTevcRu -wyVp2tFN4H5IAIfQm4W3Qe2K6Djgqp1RwVH/33S6O8raVTMmES2lR8cfW75+mgkt5DX5uMfDnZNl -5Dz7snalYuJwseAHEASga446wxC/1uzQmXpsWWh9R/iqfqEa82y2AV9aBh6sVFKOQkbFU268VyVD -X8G2qbwCxr8WO+jQrq6Ihvzjr69PLp65LSh9VAlzc5HhU5bFXiWkwrJlxln/y6BYe3GC3rEoQg14 -gS5M0A0gJacDJW59GETNMIz5s19QB21DYKdqh0vos0eVhAhcwdCaJCUXwyQyd0sa4qZ0tEKCeThS -38L058CUh1+SGtmcFZRzMeIZnZb6YjPx6EloinjS4ddM++V0aCt6lJ3ODvSRKq6t1BYxpFjhrxoD -0WB7Vs9dtA6vw+EOfiBnkMV9WaHc5sufDwMsanu8UjaeBs41TdyWR2xLIdkiKSpwNEpMqkwpaOdD -Qedj/NNpYOcLxDkHXlfsvVriPiJF2+yKu/Rp9PEaqhqjUb0nHO0h8phjipu2/H860LdKz9k9hNWn -KUhB2fz/w17aKyefhTVtohR38qntVn2JF6kWCPy05o+j7GoRAoN/hIsMU0UN9f4adp99f8L44ntd -4+ecIrpQtyvjqNfJQi1/H8TbeDSUQXismG7eQ1RDQLadGL6ytPBsdzOiriMCmV/QhC/iFQSTyo57 -wHJLA9GwA8avqETt4esU4/o11tBfBVcFitHVCzecKTnLVUHpP83YlcUXglEjf0Ajq+oZ0mR4B1ND -rCosy6RFYVoIXuPdIkD6L8VdKNg96Y7kYBTsc4TJmVAlaTxjWZbc/z6SCW4uu2WUMWU8R2qtA/qV -X6m1jM8RQVdKVdmq4PmmqjHkhmnXRKMx9LLQNdkgUYT0ALiA9lbAETtnDH8d2bg8M9+YxWL0E6iB -qmAryu/jPd//JDRFpiDCUPTec5e7Ter9Y2FYL3556UQC8ZUxD6p+9tBl73NN2QuGRlsAEsov/eBp -K+h9jhIbipkghSSFU2xTxXuToGdqKHrIZPtwtRdqGABgLph9iQemXp0Uhm6jYCFh97TV3COEDr4Y -P1MbQFmdBLkchcWvxd6JZXl+sUbkIghvxeeU8jMDuou9qTtkinUcwobJejptXIfPSF2fjgDIJPi6 -vYm5+Q84WyNHI1Z10iOm55MdNSuaYm8QbihSBPLJkzZPs/KNjvVUd0ZMwQJj1IVh20KWkwsMSAwl -GGlVOUYqi54coL8gAd2GdKx/hp6uDHQaOhT2+zBgNzBq/hAKtrE69IL/MTi+IUZH5AK/6JcYD7SX -lULj9AUK+4X+d0aMTnGPMq3FmNN/TgI5SVZKs45u1Y8dT+xdAbZxMWjL8TWhSanFC/vfYXesomwV -s6xJMCVNPnhPFlti0cmRbNURwa1lat0+c4Kzgd3fLCQFSIC74iWwJJAiQ7GzvUSPgIURPePT0/FR -CfRRjFhWmvDBZkCyH8rqFYmfeY7dS4gkMXW5DW0UO6RlBwz/5AU69SQTeQyYbiNiCrWS6hxonv0m -oKah+S/ilt1VzRBOgrVAsq9seGp8Xz275HnvawIE328vl6REvnpuLG6KfU0ZDfwiwFmAPNqVfNtX -vzOdcrgO5EEVCBRviUZcKCMVU5FUoevZ91aB9tFB8N7vasAGMj7k8qQV/cw35xyojsrPBfXqq2h5 -rdRzsfka1jRS7QtsdChpe2M/g5BtfZj2Fu1c0QlTZtT4kmhSa+gxwzRw/NS26H7CleeCOt7Po20v -u1AnuTILVYueNVK6LaAo61Fu3t2lqe+Gb43EHZE+91IOZ+HVFwT0oZewEs3veXWJzywWCLdDD6gH -I5MKdW2RFktnsddz5i3pocionX0lYCIpnmBxg1ma5pg860qWVt+oCf28QQ4gegS0+MVL9c+x86FS -MwnsefZQp8Q7zsLB2X0MMtcaoUSXNyWfSWnPUKpmuLz5V8JJfxTe+L+/+plju7yf7tB2B2FKgDZo -xSmbVAftKQYCdvCHQU8nU6BxkW/vWCNhwPhGtDRKqscoQ7CJCC1NvUvM1owWjwQnIygSOMdg+NXS -tNGjl7/ebmPCEdPkhZNI46/NJP35x4uCwrPjJUDWdWUwTp0Mhp2z4yJuF3IJw8Eq+0mFv2WtZS7M -OWL061JJoDmnt8mBf8uimZhQN4VAD3oIyi0HPFXXBybbcUfyGf9ittCxDqa2t/qRTXBzigMCrr/Y -rpiPJLOzQyFkZmnujEVKpEsGTgHSxKklfHiO96QP5xt0VoqILoPT+i0KVO/pVe6MJJB2vxRZSG21 -WO3u7Tp/vOST4nmi6XbrAFvmNIsJLtbhzExAw3Tg7+d+DAZilMp2yzcL0nV3aV2nJX0qMzRGGC90 -exFICM8YlnbBCiKQHCg8yIUlY6k62IpIgNtbrNwzLLnH6Mz6pdI+6WS+heaJmRMLwNksKcNOuxs3 -ePxXaDFnt9/MlgeV5/cREavozpBn6sDBU6w0xdGBBi6sP/7ou8ZtEaj58Vz/6W0AN0crXf/h9yJZ -Ujg3RE697BQyvp4V4K0JXKPbQSS04agVDVHCWdA/+cE64N7lx5iBjS7zefzME3FP+E5+B6R05uoz -ef+tgSH0VyEMMnPiLsFHHuDEOWk9A6WCpSGaQZX/GuwymfyhBDOqGxiMtnyhBsCX0fcbLoSv2Aw9 -NrUwxDXkwgO4SHx9NDFIG8LKMElcrL/M9WM9E/c+9JoqTyI2aC8CxAvsk2wDObBkm1bhA8ahx8o1 -9M2mDXyYhX7+wn7Vrqn7eThchnnF5y7n3I5nwBrUSj/Dh4sCzhL14KU/dvidnczR33OjHSvWbeba -Z8c1bmIoXzmWjt3msZPXR2tWJ7ChNd8w3cugQ8yvEconTw8NKIjL5NhKMw2bDLqPr+uVZVUA5gjB -Pr27O9vq/QVX2qCXEktajKY+LyblG3iInTiiuTeXI4Eoj1qVeZXI6ZXxq/FeBAxDMgHJssO1R9ou -02uQOVDFicOX6VhXa91NiO7FMYmqVP1PGs8+36+AAh+lP8hl5nFsZmuLanPscphSdoGInWelYHs0 -3+7yGqtX5mlYtCVinzAIcXflvhEgRKSZ6wITwEpYfN2HTh+bsUD+QX9gwtWNPViwmrwg8Tppy7cA -QIspg7+Z5KZ4I87/vAflwRYYOzdApEpMdCSK43yw7Cun/hFoUu7d0I6zcJq2SERpMoDto7Nlkblo -ihh84owwAJxqJn9vaz9VZMVqQhmyOun1Aytgox07LtAuGXRhKhyojNLzWLdR4F3wZeqpkCnbSGBG -t8gjJ9z598Vk/VccaOSaseWVbcye9CUL+BeEZB21U6CHm2sjMoe7eulrH+Ywj1kcMNp+ZppcfC3B -MU17WYYT/ZP3sAQCaXI0BsGEuYKjimrJFYPm6/0zMLCOK/BSbfOGwxQoi4Q7HzaIqE5PDRIOP330 -9eissFxVOZfE5Iwda9o/WQ6WM0uXIVj0LVf3MCFa7xBUZPEoBW8WEgr7m6dY8VKRpRDgSBrk8tdk -PVw0pUY9CDoZXX9gWdd3hNs9gKwsUQlc4sRzYR49viwNuHgRPwYbAWMO1YL5OzV3E41Bmme4fBCo -joI+onvkYTr+SyhxLll2DSs2fI4erIcyS0PtmPTc4A8cYSvjfU31r+s3RqI7etFIWXMH4hz0B+vf -qA/EYXZLvhQp1kBiQmpo4zmqmHbYRKSEeYpwPscFAqB+LjxboSz1SAe8PGSkps1SpMN66smQV5sm -So5RyDHZ1iVE4ztqB7Kxs41KXrw3RX3SNSF7jKTF/ubmfRh/iI/gxIUc4LPGHSlIpYEIwjVbgfyp -J+upRGiI9tePaP601LrjMgcCpSle2HeNfyNAcmQLwTC4Upi1BhxfNeKTnXoNVsslGQ6ALk3SMUZl -cs7N+mBjotbrO8TB3w1fzWntqS+1+Ld8Xf1IMFDHsekE9rXjsn51NX8MoAa1UDCayySvRB4BHI/Q -hszSHhju2A6xbYB0Okox1ddnw6CG1Emfx72uBNYUUD9QwuOcYR3ipldkCszIy8Nb6CeY4K/mbhlC -yPBN/7SvGZ60KrGtPeRhn4g3Fspennyelapqf4qbftkgbQgbd2gXDLPo3Si9+/Iu4GN+uCCU/yjw -dPuIujiYTxF76T+oCI34iQvabYEJZIHbpSgoQAA1N3vUeztU2+gGGc8ayKiau1DFXAYqDH6pX4ED -XJ4/Td6Qj8Vh+hFbWvoWB8ImoBE43gv8OJxms2mbHidyi1+SN6kcJ0Gqve3kfBwvrKpLlmAuMf6k -fkK9FvM085sSMkojBkkuR7xqv2oz9pNG+ClyJ5SqKj3HoB0x2A3Q32gm6czbsNtOA8H7YEbTW3TG -Cp0BZrt6GsxKtnguAI/ga4g4IQ/8wp5GM8IIT1ZlGlLmN4eDQL6pDlq4syJtI109qA364UKcf+Ps -efrvqkRy2hu5fFGktBVZPT6uWbwQKA/cIkKyeJoklda59UvXaSRlo9BfxvK8c1iGVgPjApWrlzwI -5U72cgVUKMo1JZRdiUaBUPhOuBOcK9vPYhnL+1XGpRv5OKujA0p8OW62lHt8RV0H9kV7zAlpXdJM -1FD4Bg6+H1J7sIBSZj1/1ZQdTpAF0scDjzcBEjOcuBNLI8wWMrpWZWkZK6+FwMROlKncM36naxsG -LC8DV4pJtuzJZHoAPSlGQ+SD3gErBzG+lM65YbtGH39vxsmzNFQtsIPsKuKU9/8fNr3nygNK4tK+ -25I8lxUicw7a5KoXUNtgMe0XQqlwYdV8ua8sWYotTcTz2H3YU55N8KZwH3KjDVd3R6RD7sHzCA8Q -1SPij8w+l+TMLIIzmpiOdSEzQpdvy9K6oyXawbkLr10adS/tXX+LQnyeKgSNUjLUGYEChMygJNbi -BrC3i4LSX3UpkPB+g0P6STeqy2raLqHHNbyemHoR6IobPwxFvFyvFhHdl6nxO4CnxliZ6hI+3TPg -SWWkVFbS1W5ztE0dA9XMJdcVHGThqFTlrfrS8Xh3B5+asFWGsj4vu9oRGb3P1y2yLide4FY3aLdc -UmoKPEmD05E+LHpg+7KL35WKqJ/sgvt5wWETV6MPYWZxZ+Fet4mdIrJYYt5kfYYwns+QPQ6okbNU -/ubGAS+0GZ/5EjJ4nthW6ACCmcEl1wbG2o9JFegNKNQajCccjtlbaJeJzHH950e9DFGy6mEeFbmB -TcJaQ/+Qu1/w5+CdH6iX8DAZGDqxrxgjHywIOPavvmxlMIxwIIJrlOqHx+cDJk7Cf+hEuyyobRsN -cyVyn1qaEOAl0Ts0Lpj/9K0baG0i9A1yU2Sj+dAdX2M0NeWAIAjoU7MMQv1Pzoxf6kmzFG9oM7OV -lLU78rz+0NA07gM83H7aYmdC/UGJuFI92yp8h22x8zrnN+Gqd6Qbane9jmPpYnC1OvcNuQed+yvq -BodOG/7pWtMbyLd39JBqOEQ4Ag9FbpxVbB7q6hfGwDrhIDTXMMCPoaVX7asaAprxSzfUKIlxXX+J -2v5UJ/4pR/roNcZLzWknNcwjEMT7mVEqPwPb/EBgda6ed64SJBNd5v4a4buc8573yRFpVmJtXfiz -A/5JxUwFbXq+a3z2u/ngH9BIxIrfU6lC7LqefwYmZBpRBKMOfEkhxDi5n+y9FzDkCj+rH3ei5NGb -MNu2+VPuQpN8rqmLTs6JOZxo242fEMPczvioRy8KHXCatelOrlUiFpEAvKsc/fKc8VJo9vO+Aw2E -SKnDrm2sc8ruj+m/mbaWAqKh5Qg8eZgCKVHSyAhDaR19tTPGZc5+BpuV3zikgTpjGOppLDGWOEoc -VvYOtIdjcRrtBPxpW5SbSL7AQG85SPhF+eAFvhwkKMb9kzeBZ69YNCcKxEi74pNOUNnHXh+4qlxo -JSuuAcwy0O0vQboviFToTbY7kiNOV0k/pVHSLlT6AlRCRSqroDNJj7hzBfEWkWpmADZtLR9xUvO7 -9FGyM3qKhA/p3Px1EgUi8mBtvsAID1Nn/Co9NbnmW9Xdar7oi24c6A94IGTG6/471R7KucDWZmdO -QfjiyvdOTju64ICvbQFb58ApSRImvAjFvIlyUT43JoEBMc91iZv7VMvIL2QLrXcBpjr0iDnEMV5S -mjAmTr6sbbZ+EV0/F98SCUjoddgh+Z4KOr+ojHi5JifvGpGNufVKasgPbjsCm7ftAZuRPWoQN8Bw -gVEpVzTciR13M5qWtVmBsWnuI1TrJRtFPgf34rsQ8Hc0T+nKKxmW8n3f0dlAcVWX4pTcA0uhXOgB -xhN+UzyAmt522im2oIahR043WfFWDbKtT6bfVnSwZlmWiBCqONl4vTz0ASfycSppo8yqzDYJYdnQ -NyJJ8O93egmIawckv1cOIqX3J7rkiUMmnhIkdFYyrUFzn4iUELaVkDQdoNcTI2Qb47WttYum6rnA -/KIewrXQe5lI3TeHsiF0Ezb1KorxVy4qp3kwyDL4i/88hqpZwwiIjYQAg+AAvn+EPzuRXJ27avi3 -Pqn975+pYF6nGC5MsWM6wK/xcUuIjsMeinFP6mMpB1tNgcfi8pwakUV6fZ79c1QkOCZnz0dSXaPv -wWYUMVt+ZwYCSbhRa4rm3Irbm5yieT76sjTyaxBSw2y5hY4Znx6hrpEILWP9CtNZGHPIk9gjdOeB -ZrYcywVxTikcdbZTxk7CBNtbrqQCXs+h1d7RvHuaw3WncunIb66XxMudZsrzNEo219SBiluVP2cz -Zvlgk78u2E96jAurkgtis0nVKJxfbQdSIhtXW/G1ZvSwBq1/VEdMZHjNe3f9DZVtphBxYeKzd/Rw -UubAeOrKaQ1dVP/O6On1wEhtAAwBmgjSCVwb4UGz+5EgEHBFLZBieMbptgAsLEDswpCI3x5mPL0V -/yj/FeXVXHkMOiWNbmdnxLgmhb0iqMndxqadXpw0+HBdwTVhZBgP3RarKSAtpHtqW/y3Xy5mRKMX -1cFgZSDs8465Sf0xkq7Rf1tZkVFA6P35v7enO+66Np+US4j6kBv0ScuApzYxy1UEY9mCaX0cqVU+ -JcfjjSPprKQ9KXgVc5q/a0gRYPP9K8vo9r8Jl+6lYyKRvTpEmJZu3yGy2QOe4WFzZujMmWsqFDyn -a7kRR0aIM+aa7cC6k80aohs4/T/RzkUfpqtnT8rzGlUerRvwn9j9L04Zfxvjx8N2SJQu5lg0Te+o -qQjLlBK7iyOfIJRH8EwkeeBqjomfxcsEaXNNv4SVGlbysPbggQ72Y46bUYo9Xtz8fM4tM5eFH5p6 -z20EPHEIGTdDWvMSrIWApW366KWwAogt9w10cbQePPm4UWKNg3NHVW1wDDGL9g8ESRtxQF7ZycGG -ByjCSEYp1FahzRt8ZYQ08IxPgg5KslEaCjXr3kc7nG2GFqqhemNR0Y/BDco6j7gD8zx6IerpXjUC -4jicRJlPF0Z3ak1pQbtW2L9PT4MIQWCmSYFqTldosymOHK5SltmxkX01VWpFc+y9DzFklwRynxvr -4+820ARTTusSDl2AHebAZX14AhVboqrMcCl8bO0cL2dlTS3Xi2Uysy/GDzXDS+64d+zP0fTZti7l -i1i/dYMTNLSM0FBe2+N4T129zQx9BCcZT5m/v7oe0BZPc3K0xa0807mue15jJQzv2sjWSD8WoZPj -JjfwY2uoaO0fjZutE2go4BIPbyoNnB5PDho5LrXZu8TNAFshezDxVQPmAL0kOXyFavddcCatMVzw -ohiGB1H3p35T1gX9KmgMs7yp88eipHzk/Mi+GUJG8vSqGCoMevEyI9C2z7tW0q/FrCvZIKCRerYK -ntTyHdtgm4JBKR7NVv91nq716ILg20ies9xfXq9vid3+M5bK6OhReEtrtkY46CmKbV3t+lAmMxBx -hD/uIB9U0DUFgniYdSZIcHpNb723fskH0MVp6C9DhoKK8LNZqAqxVsRegANzc0P+XLH1p99Misph -gH0Tv2YEw3R4F7khVsVGSitvT969vx7VKDQX+iBRzDXkCQlBmf2yhqyzGVut7VQVIQhU2763//Tl -+Ka9xTTuDAtJRlHKQlQs13RK3MoPEZl2xAky71ZKzt86ubGwgcOjCKiy4cptE+JE0J/F6mMgA9UC -X+x8vfqGEubRzaC5fOwLVbHNRs5H66aQGprH2H3ciCRdPGnMVpOJ5hEBzmeoFRCl9Wzg6NQS/P1R -QCG/2juta27wM/GfrdzmpsVbtnvOcwIGQe0NDjUK0kfNkHz6vqUwMMNzwXkr3bCWK/2Qr2XrXyke -tkLXl5LX5CTRdEzLTnJVzbVizMJvWDyTT0mhh4Lm8c0F6mf1zYGKM79OR5zSaH9KASKPXQN6rhYp -DiuA/SKrmNuRT5MJ5zNpT/hMwiw6rdj6LFH1dh9jI/Ia8SSagJipEVPBjPJW+spJZQMd+CYCAojw -cYU4WFKaV7XnktUILVbkAI5yJMXQrOshssoH9vFj5v1tbvkshgqQqbGCsrFy6ZyWNVvxDmLlEicE -CXqmXzCEtYDkE417UN8z3A7ISpLzN6sBUoABvcHcRY4NU9PBcj1ym7Evd7oot0SQHDO94Fc8u5vM -jjdFEXX+yMJVeJfVkuItXzjLw4Z4lCc7XecXjSPwwr+ysA1KhAfzy7qnhW7TNuUsKY8cc82puAvE -OwAeQkDiqkhx/SfWXzSq9EcbwtXfMCDuKIYZoa1RwnpenTSoarcfawHoSGL2WrBRsPtq73AY2qnn -DOrOFDCG+wY8RV3O/8eqbSYaG+oaU5bmjoAQv3Wg7YnhAfKrs/PwzVzhnqolRi/OnPg00AyFgV5r -xlgzXM4MTvcmLlmWn/uU8NGERv+v4SSVj7ZKjm7O+GrhQZSiKhLWaGex6G/3ecowLfs/AHLCUzWb -0em7/5Uxc7cf6V/DyB00k6xjjSIyspccvwE2OMveEjsL5yjDYD1f8ZwOhbpcUMtOJk0upMfUbUQA -CenjJOsOfrWEuM8y87AIiaMcZ7sy/gi46vW3CY1NtD6RbAlgA+XxBXgW8wCYuqAfbPcbJIZAKQ+e -hQ5nQy64WeokT89EBo5yId09XdwrCA/dG9zk1ifVqbDVthEDYiFMBACZF1MzETyqz0dvAZjYEaLS -dgp512U9p/C5B4xQ3P0tPyRujVvUTQbcp4M/S5hux14ZnCyC42Nlucnl5RkQCHyRmBxm5OBltHUI -xlLcegsqvgyHtCl6JJ37l9S2yn1il6vFX5ctT+ElhGj/L1kkAMnMwO3AEuTuU5gcyVCIn5KbbA0y -yVIQAt5S9djj//VTUttVwm4KGYoT1yG7FxB5vISvPHf1itfR3to8PovLad9/zNUzxILR9oWdhckO -T7lxFOPpy3ltrqppkWvAinrK1EUvYj/T7YhohgKAuGtTZB0MFos/Crq71Uo2js/vtLXgBdlZetPJ -uXsm37fJ8+qzY96uLuXrFuDGMaLJyTfjDsSBqt+Qsnn7KJyGdMNsg4NRVG+EWZ3Th0SR0dBE8KNM -eMXl6yFI1sEynjHKP8IyUugXr+/zJ5TAnDafU4LgH+XtPE+goGioXciITNIk7g5GlukRhtLOj2Oj -KZriZHfmsR1elYYUWwoqszvDmAKNOHDEnXW6OqcKKDLmq9np9RLrgYrQ0znWttkwoa1L86f67pv8 -l5XRR/Pq/qJaMrXDs83vUMUBjOg/VpR6urmnp0/wR8KdcOtBMPnVpQb/c4LSLXbtmoBFxrQq5X7/ -GYLflBb/LI+uUJP6OaVhPjmSYpD5dUQFiO3g95kyUju4AmQogWEYxcEhnF1fK3Flz8PkPS0Tu61H -f/bOfojysu+yEknJ4/2FxqoBT6LemxTjxt78lOPqaLc7yxIxxnaRU61D/EbEMfgSD9evfFxQRi9i -jNGh4u7LqrvUpLuSghU4cyKaxX2WdknedIIZ7Cn/xgP9tGF9dxhbYlyWOLi+j8fFr8JXkukPIqKR -0Q7T9g7PavKZ3RrYJVO9XeFDo3BtVAgkG4wasUor3JdEwS5j3kPsxxNnEG3IZDknUmBMsHnLlKXr -amqAhuUZe+evcrbXrR31OjXeRY1wWqqT9W5q192ZUBR+rzk3PJahj12ATNx9YpxgompvRm9Cd7zT -c+1uC9uI8fi/D9FLRPmhkEbZJ3ggUVwcgdFfLrbKDTH3fT2BgoSGGXRyKPjWJaRvU7nSepZcSrc4 -xSzqkJ4xcwwkY1bicANPWcFLmkIyFPHGqNHHCGdIDu16LtfnWxwgyJsMtjy4SMwjtiovwCLMbWW0 -PwpFwcOwRbILqqRP9ikw/vBYUZb+LrjDLyqmplXx96WzAUb1akmKFncuInlg85BkW0kiqwiPKl2W -xTxTo+H6ZU4UoGDrRUmFIeulP2BOnqaSkWMwpJy7zVBjmmxys9I2oxIFC6mk1wv9h5GpbcOa/BUL -7lOnZWy56JQ3Qw0Cj9XMpmZs9pZzpcGAQYGnXtyYpfAwllP8Op5VNlcyMwKiOtdLbSWRskpAjinJ -geJ/iMWVULey2bHHN2GqoBpgKHYCP/bl+z5LgJSL5ltffv8wpfynqbHfp9FOTjnT+c6JvTyI7tIj -m2YXx0bjE1Lbe4D4A9mqIY3pg/dfhSbec3mneoy9z+qopEhHyKOL+3yuFOcFJBa7FJ0le+sbIAW/ -FopQ1YiCnX0ECZpE98Q8/6kF9Uk45bhRwu1NPgXqwb7d8oYWXl/B77Vt/1xgJPY0naMOC0SXYVff -448r8LoDel86Ka5GlCrmzR6W62JsEO8gJKziJ6q7p13erz4d0z++XIdKH69uh9o1xJxxbn9JVV5g -cr1Rte2NIxLLiEyZho69fiPvx5rGujb6x95flER4K/eyZa9bXUvsnHA1JnQA6N52IJl9fgockvO2 -oIXRbtmeXDZmd9MSpdBLP0R/1GJ/X/WKOgZjIYBL5oYTkDJExVFpPg7DIZiGMCiE2AnE8GQKJqLC -Q7IPNoO3OuKgl2qLe+CO1wyjr2GTeCMWWqxu3eoJgZVppv3pZGTyD3KY33iEanFKGVeF3FRjCU1o -ITlw7ckricG6pMQvurni+NX6xzJVO4eglsVWiJK6fPe1OPUUe35OswKq3vcHOt0fwv+cX2JalEVJ -uSLYwfs0AZmE3Lm8IcmHMbD0vIFTNAiNuyh4WPzj3devnycj4+74fCBxCx+zcuikJbhDC6Pufr2p -ulJ7m1hCIr/3O+F2ROVuE7+Gfh5kPh57ZkgyjKtwD81vU7I/t9M1VF1nIbZVvO8LealT9P7/A0YF -0/quxe7bJBarfpi3TrKXQJPXg3RG0TNkh6DBdlgiLqkooYc4UDyf/y/XO6LHAXtdn3FjY1tiuZv/ -HYHTPNAbMsjFw4XCQQhGviPwD2qmvsXiMjHsdrxkJnswWN2Mw2cqp3Fvd+9wXlS9Ei3qHuu2HLF4 -vBXmencyvVqMXEwdDmIUDQC1r0q3z+8Sh9uRZGLYlorD9WRrKwRNMjVbClXHWTsxLiSoRbmZzk+q -VRQEZadO9pANJ9OYiWuX9johFwQWwB08w4lqufy/lLu3JbLjwq76sCvX14itZCEATVuneRqr8ehm -Do+HPZnGmhlVSd514vUPUw5AAKSycfhjLEMqIFF4MOby/2gNfBFjybdDSSHjpfZ9EoztXN5xP8Px -EaJ9DaxDIUoJgudl7YOEwPD+H94xvF565nX+jtJcdmC3PiurR+RRKRzzxj9szieI+WCQfLcxCyZC -tWTPXgtttOtW7WmBWZDWWpwFRimVT4rSkklyd9HLqsN8lEaJ2Iq5eUPMC5WfTLEbpo0hVN5sbFne -590DvCdLc2Fd7i3G56LMofySsfIRU8wrNQCIQ6qeeZwQQQ68kR4uquPPCMpH2G7Ue0hhqmkoSx+J -5nT313a993gT4aCM2igHyu59udr/AhB+6slliKOoO13KoZMXVekb7jbiPrAaaxtl/uWXSzk1uSet -PNTb7nU8222dAI9fucrESE2v59xcZ5DNWWuIZ8CsuF+5tpFqYLhetsF7Z8GakqDUtWuZogQ/XZEK -8dSfzkpTeXhuDwyqi8CYG5zX5ywh9SP7pvg1s6vA6iiE8m+I6vVN93RvMwWVNzGBVZklgwj0qQiE -STndzUQBcu1nvDESAGUUlE2LWqZAS+eUBjuR5vOYqoAW8xafzWDaZOvBQP5QxBjKM+nxPCtcz+Fl -spoOi7zuPRdDH/+KZR9nKRunwUY2W8r8JO8Cr5lprEVeyDLWJ9o4pogmo7HZpSCq8Hb0iTTgNwqH -iuqzrbMyjbWHLQKqk8R8RaY1Ee7lquOF1fE0Rns2z2qFj7KrRtJYYzePTSaWBUbQEh4jvhURygRJ -yEVwuAr40v13fGqVN54887DlitvrPptq7+XKPgNDwLyszjypUnXuvye5AhzdfArhka9idpf6Ct0e -ijM4Qbjt+jvPX1esZB1mBOe5a0AsQzviZWrYDxgX1VWcb2JxYeKdncTb+EI90aGxFuzaZ8YOMGjg -0mfHFy9oJQ74pZwTN3Pc+hfyk20IjDIY4aIDfODjrC21EYmHyVp1drmvQp1om1Pe87KOo/3LPm/r -z01X7FDiVnzCihCF8dJ55eA3RfoS5BYXPLjKnhi0jD0qhuZZMrWYCkeUmquX9waYd/BoJFC9YyNd -FrMWbjeeq5WMPwCBdDp5O844Z1Hg/pGrsHUY8jiIpIsduISW0Yn5v46aE2qW6GcLBIwJX3dL1ICw -F/f7XMa82GE0pLycLqxa3n3TsIgiHtvSaFwolsJP4i+bCYRbfpcEBS4F/9e1m3iMt/pdsGMJXOVN -H4dqxYWPgF2qy7GUAsQfvw/ZBXGlR+9tUrt8pnhH8gnBJzL/IBShLLT+zuwEBBdsHEG3KdFUkFBt -CM4vHgwfgvHDqTQAqOVs7eZUn+z7BAAse8iU9OCje5IcQFrg2n3eQ3uOEJdOuPvUheafckWKX+SO -FlFlQxVWU3sO1vMEy0vwR9d+ZWp3SXhcAGO22VLa87KWH6TZ7OsOZ81iAu323kaJ0fFlC/a4TQWH -+c0dpfvMdkj4zkf++II2U6HQ5NAv8gITZIhh8NT0UeBKgh69czLoz4XEpzEonieLZipeRlFGG+qz -F32EeoZiZA/JH/pQZiazF++rTX2BTb0lZATiZtFABUa6Q3ApuPtxG0GKP5em9uNIpJsyrG0d9c1d -Tid2cb3Ewy6Gf8FaFcfPTFO3fJfIEbGMayVjSKnHwr6w3nBOSJ37apCdF+PbmJo13ThhiJRSLKQq -sVqpBiqibdBEerP8QeRo6gYImOmNIChm18E0uUlJ1aMEr/fNXhzvgjjSZPe+AiJfjOwfYeip2nvx -DZjwEgwhY6CEdz1W1lEZbiOrCvxjWk5bfPcJFoNxG/Z2QikS6U4MznPSnu3lwHEznCkHTw7yr/Cu -d/WHE1mGcioTwnEUnLpWTc0aZvQyOWCc/cSbnUQTXZeKmZeQqMwLajuZBNMTk298nPUcteUJkNAf -9D0CXSohinqVkeWR9KaN0yaGN/t/AgQ4p5+anb4affkcmMqpksqCr9IES0bE9SeNR5ocK2HrAkJi -sIkC9go0ZkW5GCWqWEJhvlEEOTSNsoEYqTJEcoQ7VqgVB+D8ryp79Dv6FqcME6VA2eZALAGTypU8 -z2C4copd49oMRoded8t3FUFGlOZWPMp8BdJ54tawDYAjlw17y+wD3hTx426HDZ7VsmezmL50YEU/ -sCfSnT+/lbuSbkUSBysh2J+izQNMgjFzCQmoiDXeHzRSJBdo2Ldt33P9n4/W54BIMjPNwOOtykxn -oecAHBBGoEvIjIHdG3meCv/V79gBRZFShT35M8vGGrY8whQJTI1UUQk7gP942170+i0xrUfug5hH -/kl6pSiLfLFCS1nFdSieY9hCwyEXmponNTswIadjTFpk9jjMuD8lQ+PgyhavG4skyHCuAzNFxtBz -0KsafMHFG1PhqyuGfxbymhcU5u3LWeLFRVMmjHKBIk33YiDvLquhTPnPIaik0VNNrDI0nRp1f0L0 -VB/MjBk206oY+cQx36fOuC0xf25lPhAJFULwVpao/d+ruFC9Tm9iJHdqCswSRHTaSaGWA3tAHF03 -B7WhGlHGm3083WiDoNGtMwDjwwiY8UN4KYZWZuK3UqXDR4ZN7L2A0lxZDJs1LW9HzhH9FDzDl+KK -iqzgmY9p4tcEStx/R7G7c3Tti0JyulOZeJO99eKimWbGjCaCVfpMLVFA+b8fu7bhgc08yo8+cjFT -YtlrJNVJohGrRsYD/ms4QA+X9Ab3ZLdMVII/Ll0ESDhUiRxv7zxZc8qjqMKrZTFKnmlBDsy5h1t/ -+KVeohXfoZZO3IlJkgABea3caVCZx5Jun1mne4x8IaUmWBBR6FtSlGoOhiILn92x6MtHoDDwAcNp -BdPfIdpKQ4wMX4y30g2GX2XsCV2fAzz5FWzPdLIe7OM+YaFxREsrOB191ly0aWSSNuXzEyqRBIzt -GfUZveiCK8ztpdQOrAauor5g7p9t3+pztqEHGo26MhdyQKf/hecc4c/lPySEGOrGMVT+PYX6H68y -voTJ4taTIWPG27QOFDRBQtaYDexErGr+r/lyxHg9wWmXSEXkvSmMTjOcECtW9VArL5RFVochEsf+ -Q4UxP3NbS9SbrD1/VKNNwobruNrQ1ar5LqDSb4THxs/EuHPv2pimZvTBDLrfLUAf3ZUb16W/wtbP -7CT3deeZrRG/DfLWUm+ZPehP7jVIL+BHDEy1WR8dZ8LkzwcjtGeR/49lNthccjiKjA2W09xqoVJE -ugsmsoYJeWor9i11C71LEtE+WqJGOvBMVNBKhdJc0eqivgCfHYbBxsyG5e81OYSZmlqBtH/gI9ty -YsePLl9ILIwb/zZqqmPYWKxSEmzVgi/uc3yJLHaKJkGx5vEthkt9E0D4IJpCOi+2pqDXr2xgaUu7 -U8kuY0v5IOqhY3M0MTIwRwyrLZ59nQClHZEulw1raLbmkwfGkgew9NgyTM82i6A6qj/UM/ZsCAGZ -LqbC4bECguSozoIet6iqFC4Z6YACdMCNGwVT5LFT4y62jlPUTImRpXaFB0DQx+sb5U7ijZL5a8BE -EWDEHAbazgWjAd+/MbJR9CdqR0zIop+zpkztCFfkqRa5kc2SlhVdVD8YTi8VFofdBcdvAnnHB8Mh -hTOgghq7Qr7Cl14v88a5w5ZQ1sRoDfRN6J8jCYQNlCOOksxKek0JIc+Hx1LXUAzmV21RA0CZog4Q -LkhBrZPYaITY0bJYy777IYre9LW+Jy7VwJ35aF1/uien/0yuXZVpJY7KzErC7TUUfnsF0Uz8kDAi -Vs+Nax4+15b6hHXeVfhnwB82TjUpdG1pu4aZhyG2iPAkHaFTS30Wgi+He/0TsSotnlODoyUyF1zz -JIv55/R2Fc5mdQFYG47RoOa/vKvMxq/Gd5nxWfWruNhAYh9OvQjWPJolVB4ZKV6ZBwGaIDNe6poG -6M5Hr8VBUbZ3yWsAl5eV4fT7nsWory92xOfdxyovQnFhWfmcREayhnEGyxZNlFiJreVZjEyz6Nqg -A+JdbdfUn7jtaAMRJ4gJ/25yZlej02b9F/9fv69ZBz9hq9rMOd7lzYSp8nwr3dNLupN669YWlefg -j6eRPtmbh9yC/mZsqfqKqOjzjWk9Frcky/cOr6M83lEDkg9NwOhzV6udxDjBD6147JTsTUABI6RG -oZYEjxEHQX6DsOe2GEleFWv3flKu3ALuDGkcKVp0xMA9ixy5mZS8flc5CELC9EZyau07Q7l4Ks1e -NQ2JzALXvCeUr24dt+aDRQu2l2LOTIuD2AiLx994XtVgcRUH1tMBg+i1feIhurPmHAHAP55Tbk4K -GmHsbeUXtFrsLXepuVYQ+Z5rXw87zPYKVcH7vqeMhosqo8F63oUGGKMdShk9k1Szq6RIL+gI+Q13 -AhDlnb1N9XhuLBXNHqN3qoF8NkaM+M6pd5LS/dbsrAfVQOXK2k7TbihrpcFpTXyNCkKaLTxX3sjO -JChId2UaXgnXPQGZI3JS96unPLAW2KlUbfDALgUWbKH08YVfFQyNLEh5mPacnpyZIwpucvvojPmH -lALExL1iCgAIaNpU+zgHGAXKPzfLMU3WXF/PSfgSB7B03Fv1JI4T8g13kZRB7avgjdQzF4w4yJjH -z9Bnizk+7tkk86hUutEOI8DNrIqhAC7jRRiNdhDSK90/9/Rw/pJVmZZ8gSCAKwkReC1cvTWoN3bu -cEeqgAdmZnktJ2/eVG4XuToWCIP07rOfRHo2dJs55whAqemsunBK81wBPUjPp/MuzvsW3Ne4sxXh -2MddwLxiFdiIxUC1L6QIAd39ExyHT1cCuIe1DlzRIefO0YVh9z357FFQaKCIFKz7sKBPkxHxFO0R -u6N7OpLORltsL8T8zZveD14kAPKUNi+08zywnrwNhSpZsxW/kKk2iQyWOktYqevjFX5BinzP49KO -e6PPf/ibRO4z5WVhQ7qtiqAhoPuXIlgXD4ytwCSTeq+jyfoJmU6x2yaMQmpOqoI75pYbgwjs4UPI -fRtyi1CkRzbKNtJwUuK0IsvtcCLXB4FzLg2JiuiAJugevynURzIpkliP5v1lgZeHWOlKPrFkfQln -DA95lpq6c3nlXchHTi7adRdD1gGqS+CeiNIU/I7UIulC71MJlOvaF+IdeyiAwaZ5olFJylgO7GR+ -NdpR2qsb9u6I41EF0/HvFWGOlLSI2E6qeiFnuMDJYQuOw/M8zyAHHlRAKKyAwucLJO5/0KtcepWP -MMWke3vuvrexepZP+EvM2Ed9MsommUZQBQ8nj95FgtkarA9B1B8MLFQFE58Qi6nfpcPOvvtER710 -V1HExChEdSIiLY8qUfwIwVDcDPbaYHUoWxK9ssm2RcTaC2v3YQUVQwZ/Iz1wUBUmrNzVwIJH0lsy -vUY3r3nGVHDtcwoYUdUvCbsZkgeeJTq4uoSXl5fXxaArtnxv4OkUUfijPqLHGb3uUtKigKE8TT7l -Pf0BbGheJrylMH4DxyDd2X/OUSyE2dXH7LioFFMZn5gTBFDLklc3TIBYqNdXJtJmFMPBnVEZYtc4 -y0E8p7fZOX7XChSTcXU/juTf7LrRDjIdXbqg8PA/XJFDkrjB8h2LWLSUC6hSj/YWJepyOfP5tmrE -PjE8QOE7ADz13P2gfg/X4ddzqwPpLm8PUghQbFD/Ynuy2lvf5Ni4DnamLXI2x2HnOEq2ClOTvHLB -iWXYTTUQ+DxcTlQu0arpqukzr7LUygwKgL44fMZUKS/nEg7odH6hmqti2FzgRLEUYXYHgLVRrcn0 -EZEBNnPBGXIStBRcDzfU6l+XSVIK1c3T6kQXd8PveY4tBwE8eZpRi7cK5uUXSdMz14qpMYwx4mV6 -58miGzBSk2a7wwEbYbL2ExVJAE1Ss5N0IkWIsxxp4dy+uePWlU0g4Uas+RMtD88QRL6KWYaCrJ9L -sW3hMuzCotooRSMs5vGx1ix7HkVb2koJ8hHXY1I6WzYZA6lp1K2PafQMupyRYlhvcgm6hKIK3TCx -H9f/hp5QaP+CaBLudEEQx52aet/8C6fyrbMHynKiuXCiLi1riO4QibEhPbcACpCGJxV8xIHkvXAy -Cn8Y+lQ4s7LSoKkOwOioqHt+/Pp2l34Ns5jxc/My3wEYHAmlaNiHcFiRjp260N7bnLmF1O4ZpwzE -YEYGSfsGBcFPF2Yjfmwa4Xy2LHAtCQFA0P0AsuFvFbxXqHdzu23efWGKs3n3FRXABTDwudGn3+Is -WvOxnqnh8i9rukrMDDZ3L+Fs9sKlL4tx0kQEZ9QIoAZipJlemjLjNzjtdEcCmf1GmgXSoEnqNx++ -NrCri52I5cnHYFJqSNibbjT9rnNVzlZqVxGh -`pragma protect end_protected -module DVI_TX_Top ( - I_rst_n, - I_serial_clk, - I_rgb_clk, - I_rgb_vs, - I_rgb_hs, - I_rgb_de, - I_rgb_r, - I_rgb_g, - I_rgb_b, - O_tmds_clk_p, - O_tmds_clk_n, - O_tmds_data_p, - O_tmds_data_n -) -; -input I_rst_n; -input I_serial_clk; -input I_rgb_clk; -input I_rgb_vs; -input I_rgb_hs; -input I_rgb_de; -input [7:0] I_rgb_r; -input [7:0] I_rgb_g; -input [7:0] I_rgb_b; -output O_tmds_clk_p; -output O_tmds_clk_n; -output [2:0] O_tmds_data_p; -output [2:0] O_tmds_data_n; -wire VCC; -wire GND; - \~rgb2dvi.DVI_TX_Top rgb2dvi_inst ( - .I_rgb_clk(I_rgb_clk), - .I_serial_clk(I_serial_clk), - .I_rst_n(I_rst_n), - .I_rgb_de(I_rgb_de), - .I_rgb_vs(I_rgb_vs), - .I_rgb_hs(I_rgb_hs), - .I_rgb_r(I_rgb_r[7:0]), - .I_rgb_g(I_rgb_g[7:0]), - .I_rgb_b(I_rgb_b[7:0]), - .O_tmds_clk_p(O_tmds_clk_p), - .O_tmds_clk_n(O_tmds_clk_n), - .O_tmds_data_p(O_tmds_data_p[2:0]), - .O_tmds_data_n(O_tmds_data_n[2:0]) -); - VCC VCC_cZ ( - .V(VCC) -); - GND GND_cZ ( - .G(GND) -); - GSR GSR ( - .GSRI(VCC) -); -endmodule /* DVI_TX_Top */ +// +//Written by GowinSynthesis +//Tool Version "V1.9.9.03 (64-bit)" +//Sun Jun 2 18:05:56 2024 + +//Source file index table: +//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/DVI_TX/data/dvi_tx_top.v" +//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/DVI_TX/data/rgb2dvi.v" +`timescale 100 ps/100 ps +`pragma protect begin_protected +`pragma protect version="2.3" +`pragma protect author="default" +`pragma protect author_info="default" +`pragma protect encrypt_agent="GOWIN" +`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3" + +`pragma protect encoding=(enctype="base64", line_length=76, bytes=256) +`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa" +`pragma protect key_block +al6vro4MZ1BEEUNKHyex8TrSQas6QVBVJhpXhBzRnuZuJ7JEmoYoEOcD8cbwqnxILAMligQh8clz +2kiaBde0ZVKCbjqACyNEd4iWaSBHjcT71leNC8k2hdxWGqdY4iaMTueebLuGJ5M+Viob6yxFbSy9 +KGCeEveTSZKM1/Gb9ek+8QKTcMAKRtcMBKMPQHjVqo/yjDY9NpcOXHSfI31n+TDaXM6hydDiqGAJ +W97xt0kpzA2DkVaMBPMUgPLfN4gKjQg9N1bbKmErZlJb4whyOHJ54/yQ73zzPg0eIh4+AKMVsJPJ +sWLq4+YqxepTedSeZ970LDAZOjW6eBcboG6lrQ== + +`pragma protect encoding=(enctype="base64", line_length=76, bytes=59136) +`pragma protect data_keyowner="default-ip-vendor" +`pragma protect data_keyname="default-ip-key" +`pragma protect data_method="aes128-cfb" +`pragma protect data_block +7mTxKdQOH2ImYodBh4aGPvmLSPzEmKXRBXSYQ9zPW6+7Z2k2FXkL+shomy8FZ7P+pc2JOHqB9uWz +AcQ3dC0ecQBG62bHoiZNBGta1FYuLUprDVdvx0TfDkMmOmGQbSYH97knQTkP1SIf9mnplrAaA3Q7 +qEDggvlp4CgAxLc3ggXlcgykaKEWcSNJDtIlU8OQVbuzkFN5pVUmTtyLrjJAI5FVglcLoZb3iZuw +/So1tdvJBe2id2j+7zozWMr+j7PFFPrgVMQELSvE2RAzWosz3RFZ21p/D9fyiux2+YpykSeaEG+C +fkSsx7jvN7PV9aOWYNotDszh9b9VbRovfEZ4jGyRQA/6yVnGzZF/SEmiwnzEeiyzGdCalIeVw6S1 +zDaM4U2mPvfRdBMI+tB0GtvwBKcHKbL5NXg0Z6NIDnUaHv1jxY9zMGH2Tly9Fp3sczrLmezbPlNw +wWutlIbbaPxFR6/Cc6//2SSgJ7EBNp0TWoTsMKPX+fHJV368kV9qCMLZuCtkwIn9gQhNLKhw3Fnf +A9TQgcD7ZevV5PL27J4uiDoyF3OoczHx0aaIHCeoTWPx19eBqsv8TkeLh3a8+p630YFcJ+65Pvi0 +exAExkq2NiQQg3ZpkvvDJv6wKTx5y2nF5cJ2KFI7tGgA9qSJFiOqC1LqBSzmhMyMFIokhFoykfKR +tVCmaatxqCc+FgA3HECIW9m0biw5H03JnmIH+/Cy6zGnX6I9iGnI1ojfhTUHd01t3KneYLqKsHiB +KcQcCp9797V91087gHI7JclOY77kVPV23+u6eD69foRehFp6ag4RPEnGDOGrqZiy/e4s+pSrRQxQ +L0joJ/bUnZJfB/HjapZtTlpez7UjIYIvtC8vfWNmTMDsUZ45Mh8tZdpQMbUFgIkCkJq0WEGpauc0 +9xBMmmiV4L9B2v3Ay31b+R1dUngbs0T/GxvCJPclMo7oM2FwDvYo8LQ463o2QSWFxGfPPPvBTy6T +lXlBBKh3ExOO00nFWjmnF9YurT1qM6Sne5MYVeOhY5X48ATc8LyFcHIbf1LqNJfknWTQJ/wsGGMQ +rI/Q02iDf7uMk4Ed5l3WHQop9xq8q9Jyf5slslTKjGl2XGVv+fBFWgdgitNVSIWhhnscU2NdMtpG +960eJ2o1HFgiNWtdScrWtT2NV2PAAuTvBjy4YM1b1fGYSzeufJy8fBFeaHsgd2WwJUQsnSKFlfzW +dNzYjof0YzCm+SvmsDwu0d8zLhR68xnS56DHR0e/IoP+rT9f3XZZroSJGngbKQJQ+MOlMxKZL3+I +Q2wndY1vrO6fNFBL0kFbqRude3cd9ak+W7L8pY3wD5yyGeXkXuNeyzwDKLz59LUlyBTm4YUGt5+m +6Dls8748NqyscIYlZmd2RFEy+Y1UaqoyknS+45ZEKOqJ1ZoOmbcQDbiLguEFAhMcHB+Djxih4itx +9MTy7SQBNfqbLM3ohwJhpBCHBM9mtI20uIiMXBtd2gMBOnyRqvaum44zPH+4mz8nCMVUoAS23w1R +OqLWNKMWak9McYexncpz94Dd9esSPiTcMPILiRI6kDVWZZ9AEus9yVi19xyHWr8WXuPTMESWhp0w +mIOxvA0dFoJwc4Cv4vkTfyTWWWE0TIWgICAy32RLyPvLytOSTMTZwX5IuuYdRBsayIsHO385zanU +zNjrbDOryAsFWKUT1LS6dsA0zZuTxJTjtNdcSAfkTtQa9bYNcMV0bcmGhQqD6giF9Qxkle3VFSqr +5CxNTPNpFJLLyydKd9pbT7TO0HNpW4oLpd1qZFN/WFk+IxaNU/ZGRU3F9VbUmClp8zx5LdhTDiKs ++K+cmVKBI8B/qms+hRzGCz1FrnR1vMUa60BFDNbBZt2QelTtd62yDFKUAR2atlGL+tDXTd+9yBOl +zl513F3Q+1mWu7NV50zRi7jQf6l841QYhyY+h4cs76kZsosHR6U+tDnQfG3l23aTkjp1zj78uZIs +Xk/D947932glq3Dr7lQkFCmz9Pqfj5nXJy01JnUAC3WekB2KGmbqsNkE2T69rDx9jM+4f71UnG/v +jALu+jxf+78qdoKfJYUZmel8q33ZnylfvmH2LQTjoFufd9OWlKgI2Vp9+L2kWEzYtmwT4nmLOs/m +ML8vIaljUha5YRwVpxdeseOvp3Blgz/MivHlvONCcrMNesQ2K2gHnPw55pNCq19CMXx4K6o7/zSu +sgcRRAxaFgIyEcqe9RdoqPu3KmqO5EyrHV5b3BlFYuPTaUS4JvKHeWXnERMn+Wd9/WMByiwl1Pn5 +n4oJWBL6sDG/+M0qbwXMFoUr1HzuXO2bnUGbCKusMEOVqG1ahKreWaKYcKLcj3RFXUe4QOBUSp10 +5G9ol/56ZeYN5VTkcBxSNRptd1HenUyOonT8LBdggvlg6o9qciYt9BI7foCYmHRXE1wjgGTeGFgv +EhoU156BOj+d4UvKnAuBv2YVloK13vzbyyD/KD9GaVbKYkx8KmJ8fm4B4HD3kprGubDQTy0JHQmE ++C4mikjgEv0tYPFpRqDHFEyuNdAm50ISxxuQJw5Wk1c+GRRFU9UWMk3GVwy//vtAuAKm4jzsZsnD +qFtaAQzCOavyerJQ+ky0CHdIXCAeOd+MDtxn8h+KE/5klx0aaVBjtkFbzIPKwbCT9eBwHhGsZXVH +JrL7j164xIh8pw6Rux1lY8xzwY6jZGFSuxzmXm+jpfKr5+X0P+W5EkbYl88F2aTuzp7mJiZBifz/ +VCN3lpiuq60kiVDFlf1/0WGI1apNJUcgnjURMUmthbBfdtfHfBmkDahzkWW0fSFJ0lHr8UFN9XD8 +T5LOZVttnDrYKghGmBGMRDjGsg9XN74GrF3fWFjbQyDTM/WYH6iGNq/0TMAutCdqkKdZk0qcMIc1 +qgwEzXbEbFpYiadC7q9dJzcFLFybU7BBf9WLaedNE5AOX2N7KxmKMSbPEBdg4p2Ze0Er1MgsQT/j +ZgUvua+QQ+s2T58xb7U71LQHykpK9zV0TdtM2vkVclVSQcvdABrW/MSe9w3+BdYZnAwUcPO+/uRx +AR3SkY5szH964oUXuH7M8iHV9/PnMyKq2peDviwcf5yzZyQ3YdzrtHblPa+rQJBoX7Bpv225SOD8 +qBzOhZ65cocLASIuJTArT6kJRulxXC+9FQqkrFQ2LCS/VjLcak4W9CtjJtsyHwyS7vn5SgS4YN9a +cG5VUYn3XpkYCHROkmjaRqUDogw0WQDsRnQDJJPQU1TcT4pkRQlb5TDDfYbVcUvtXGvaUdzaEhII +0VF5o7pN+6IVsoZW25io3YY8attfwa+/FxpgQ4MXEkMHiI75lCfI5ft08trwYTsuGF3tjPFyJbwP +pCPP5lxlGTOjjLyNS795cf4xBILjBM9fdLBRGSTiqOkabQc/dbuzygPZ6orCUVy16cupzgvNkCwr +ZgHre2j+b8ioLyrBLrT56xtmgXmo2C4uG0UTtVE5AWMl+IMDLW59t1gOG3+1SZCySN0J/gRxPy6Q +mHcdqysNU/0/uhrm3Zn1H6aMwqcMgv09si/vCN/v2zQWhGMwlHRnqWSVEE0kyUABaAMOjgi8n3xa +/y9TSDwJAurQ4Q6hEk6T8B/IHANYYPPbSSsVjvBRC4JFwbuyuBLTDdCyWEK1Tay9rB207Rpe60RK +CJLTRrqQuFfdE7gBpvsXcHiQ3uO6hE9Y4png+NWfPSovayUotF5K9UwPBQ/5EbLaky/DcH3E8vtN +gGVWq6ciafr3mY16/ssq/eiFz3Ynyz9Cc0apMHM0kTGLj2lLuIwrtJ8wjis1ie4gIia0u/c1w251 +AT+q9YSoKsI1bKlQHt+81NH0wifDU3zdUCp0Wn+zInyeFefg5f0qbb2fTvoDABs50EykaoYQ1Pwh +5poUmY4TB0GHSUN36b198HCcM8R/E/kZS9nXIozgMFafevBuEIUmBl1TIG7DlqP/W/h3k22UkVNK +CnQmQRdX+d/X2fOKVxv7OoUBMTBYPHkqg3vOVApFhM2eRt2ILTw8GbvSFikyycL5NOCJGNXRMMs/ +HQYFe2pcOLEo1yZjot/evruLUFKk9+YLkoyrJQil5S9Uvf8qubYvfRIOiebotQxPymy3z9BkFdpy +IAmGtI/vyVRXggRLOpzrAMAAQA7L1glN1hyAgBN7QKQV4wCg2Xrts5YS29MCpbgrdnTwIbBKxgEp +Yjhk1jgNzVE8nntrbUZFIx/uIp4xVOooCJwWS8fRc9eElFZhKfPhWD6gBRll9KK/KKVz0bIyryRz +m4aVhnBokZMvxzNkR+z/2WP10c+jgA43wc+qaX3bleVoZ5j55ELJcGAQYs2mNzMWiPK3zPTw5mpT +l3Uh2mILA3vJj38Htw0cvrTIRYsG9uAQvIMkj55QvW8HKHLHIu2Czd9095fkrOdi4E1Fazms/ocy +nd5aBEt2TSnv1VcXkzwqm2ihKkKl7ON4uevAUrQHhvVQ/62FFuQBvFBrj0z83MtYXpCh85jOoUhX +SXc/dZU+cQHDj/iGSigQqo1pkxmDQ1/b+zsL3YCQR6nmy3dczt5kESII4+iDchk0TaYT8Ms3sal1 +B7G5XtmO3v/bB0i4hJIeoDjjDHiNnqyPL6NRsuA6Hq3z4JkvSy9tG0kngXrdT03Ynh1YUaWEqDml +PXIV6r064G8fv9iJAy+0DcYXF6SvRZAzg4RsxydV1YUAdMSrEdHYB2ZzpeOXq0DQH5uh6wqddjBq +BOkNWOREj1N7uagViq1cHmYni/O+6ZlHsNT7puQemfNXcEPDgNlhGHMa3rq/UOncSPXu+0/R5Vs+ +19r+DKbuR7GX4Zu/xc0cmk9XwfumcsqWRPmoqFHap8HiRRAH2rL4SCvIEF7kY42AHFjRD20+p4ho +mqbHQr19OnLDpOVwDXq7wIxh2idsH/Da3FExh8z9ZbvF/L5TijHwQPGWr32MU+87yWzVLvHNCajc +LJSNesMPYeI/GdMbeJtARLppOtqfkHYUtEjNyzDA/QWOhEX9WpTdxlAxRnTNdYMKB4mam98+5y+X +locU9QtYWwUvK5PjMLJ96/vhNIZ9nz3ORrDYaqbbJ7NB50/mGhMr+oyUOpg8kBDiW7GogM75p0U9 +b+hee1LrXsUrtQ1THRx5gabiayUFpe1+Sy+C8AtqWekB//kJELFK/AoKhTuBYtMsn9C6W8HJZqLG +H6+EUW7AvCPyyRTMLtAQfyM3GP+r+hEVNKjH/XwDBYCDuevAIAs7yRHizV/tTBvHFy7cF30RG6ix +WzKjwud5QD5bVDChA4V4bp7JsgNxJM12tydAGwm/1k73ztsGPq6qSwISIy0l7XAnjyhizbnykW8b +1GTuZEM06A9cPl7UBgmcbawtIrNZDBL2Jvn6KVtQCiHWHD5QMy/LYMEuDUoXwSiD9LKsZ2anotDz +0oBp3QTrcsto0KDUVMQ7rnXfeVFbhIr5zh7/6nR8y6Bl8OcCuFQ78Nxv048X35kVEle6uR9AHZNu +8TkU16ePZUWEwG6qDaRmE5+oDIR0c1scn9S9lxoKVF5cl8Zw8bZR1fRXEgApnwBVuMGVxWrpHtS7 +WNBZRse+fjE10dgaJ4CWWrAur5uYShSjFQkvh0WjU75xJBrvNMNqNAQiNSR1fmpzx580TA+VOCaC +vZ1c16yQTUlXwnVoW84aa3UcGsoU3LwGJ23XFSQ+HBaprUf9UWJ540nsKdiMDlvpsXqLqhGCnGJu +O3bR0gdB5pVP5TIP54DOiqYgB9TXuOqgEvPx3cREcpYYmZyiDlYOnejTH4HVjiCfwnrWbqlDZnrt +pPmW2VR3IWNDe7wvjIQkepNRt72sgInUmhrFpzMuRewIQ9FyHBp2X4Hu7DO640zv17tWqejpUQUH +U/12z1MDJ52DcD1sovsN8avv3QLdz7ZZ35eJon+TBxfi0T++7CXo0AdIgiSSZoyVNNu4hbzA2pmo +HjuSk4MldB+Sle+lNq/ZuwES/dQXPx4EK4XHhrNC6lPAz+gHCkxNw2LIb2PCy0Oq45K+rMHccWpb +lPhKaWhlZxb0wcDMFZAQbvM6He+9x1aLmATmej/tQhXNry3Wu4LHaWkBSIwl7SWQzg+K9+wS5v10 +szo5YJlim3WLcMHQSxMerhiYLGt8ChDdfabe92aSQXuNhntCPJWI5z42HDdzyzDEUGuDbtVS9pX5 +RgfcPjxJnMUOBH5hNGPBVDFrkY9o+8/LGxg5NKEBSbbD5bUSc+HbJovnrxMLo848xIzIgY4onZGN +6e2ikPXJL6zkHRJQWOwHV4krC8DF8hTk2mRzaDfliQRCB8PNnarpbfTx2e0n7WKjqShLo/odnqz3 +hLm8iM7yNynQO6BZtoMBEZNzOjpiCJ6XjpC4jeDdc27QePbPfDeQEXk2cUx8ZZxeJotWMIw/rTyt +O5rtzuA5B5rZJTcszoE/eQLj+9xovVUwEzgUa4IFUOFnNHzNaOZqHrIRuy+DxJQ64CRlSGraSpP4 +DJ/QWSlcTDcaDc90e0omKfFkz8VlMu8UxGwVFLGeL9WMyRikQkwIdkh5hg01RAL1I0B03xyZd+xr +aFAaDwMjZJ0LaKzgNus0kk1riV5XEgIzdNzuI2X6nRhdXNtP+Z4TqR1DPYBL3Q46mzC8/cFkqBUd +vuaMvbMamWqtbcT6Ivb+5Gl3PzpczmgwlAjBUnrfsw/zCLp340JJ+xtd2dvUixW6FzlYwxoCLYRK +lHKAFnfwqV9k1+GRp4fUnLwisRBCYeNyAsM1i0Nhi1w4SAChjyNwQ3W00MswZbuJy/H2NPhTcoDs +xN7ZQAbdqSLO80RYWJSizkSLMOxvl/cFt5oOVWieU/Gv9r3okzSwhU8BfzvGyPimQF1cHgWvAL3p +AYZAYDFDBLu0GCl6nIemMxLrHoWYqEzSVGN+G4AjKSVnkVXT3jh47sv2J2TJMFYCPbOqwmW3q3bz +ZuYYlOO53ifQsOUcdgMdzjvI1j4tc0yPhWQZhZ34oa52F2TfvJrSXACqyqt5w4n85lqN+FZARi6a +N5Cz2ttHBnEn56FjBw5HkKnRc5I1z3WtRSBwYyy+J7XVk5GX9UEx5E8/5XoT3aeSxd8no/1oOtKD +0Wbo+uBaXjlCNXK/6pJchrbubRj5vOvrW79QY3dPvLYQlwLv4MlPI6cK/28J4eMRpLCOKQIQF0KM +T3RIRBfUrmO7n7e0jluFf2hcGLcWAsuKC8xAMnyEzfskjYJZtUhmAIbKwcOKQvSq7ZrLJV8z9RZy +aIr/4axyBwTja/+Qg6B+tiu4L32xgvnLI7T+KwgWXHkUtXx9bVGqH8vr9O9yY+cGLvOVx/ciXdC3 +WBkAKaQIdt/CVg84QgFrWoC72lWoN0MOaXK3SQRSa5vf2Ja3fXLva6Dnq/wa9MTZiZ22qs+kCHG5 +6BO3avj+D/2GzgcNorJGpXlx4FgLi9yNVdSHEobf5u76KXkXiRlYNs0AlRK9HF2aotDdcawYBokN +Y7mc6pTwVHjWy3egE1WcR28mL/BhfKoAABCxO3yOqTJNyZuZIuha+hQRNRPjySyId9OocRl0Tebj +atSoFHwO8VOIRzSHd9ufvvyNIxzi1B9wkEMMelG5Rv6P6b3Qiduv8MvgMrEYKinm9v/ZY4u9Qc/N +RKMeWoMZanJcrGKh1FHXvvGf8nfp1z+an/+GVAXIt39ZY8tphVHQujRw+5xtcUsS11hlTyjaei2w +Ts0kxurh3wZ5uS18e6wvln8b0uy2T5f4UKavSXb/EkHol9IBfKDUT16dM+95rd09JQj7jYffRHTA +NLG+kLdkK1DudenymWRvyEQFjV+JvsU7KAcBdjjjGJi9LipNwBydCrDbHITq/PfKVvvUnsP8dqvi +NSBseN+hnVdufZrOCixi5bIkY6xPvTIWmVkSzSjniE3dK7f3gNQPS6zKBDABvAzqJuHgsUCZ4jEk +DCCvCocWC8LXbEkpr3mmO1hitvPXN0GZbhI9H9D2U3226SUiBAZCm6KQEr1AhLUJfyRM+HCAHmlm +zjkzW8t10VfFBDLNtk0haUZHJFA9wOcJ1Imla5UEWVtUkzdN2X7bW1QXXxSjb9Ug6EAz9zZziQE2 +YRXHwqW7vOTRNlnHMtSTJ7ppVJ5kFgrg3QOrxYyk37voxph3Sv2s2OHXHJj0yK0N0VrJefaQpuvN +wyTygLA9PAWUvdjdrMZJ4XUJdcAS2fiDmx2QMrI2osY7dSn/ReldejaMH3FerM6wWHlCznchs98w +ovC4qkDugeehwXIDOpYXEfofcOEaWR5goqTkqUV22KOHdPdh05aHdCNguN9HFy+ApYBplL737N40 +rkJt5f/5SfsGuz86GwXSCrqh/V5Q9PRMzVR4+L6LtoYKebrLHeFm1Qo3lb7OwgBKL4FJc03mwW1y +nPNZdH2OIODEHz5QPt0uM96yOD+Os82ghAO2Bs6Y1TUtZ2vsOSvuw3r5kd/Ds6C2PVYMIOk9x4Ku +L9zXcylBTcRoxAnXNrZFF/VxzviWNJcDYnfBN/KOwUcLzLaLucpP+tUWx+d0lji1Be94OTv5WneI +5rEjz9Ram/PpYDSbVMujyWEXwfadd1tvd9w4XGKGPlCgMh0cvHuTsWh9n6oSP06TByO7OH3BIa3D +yui21+j2tesZvyCSUuweaO6RC/cm36pXIP7sEsq8hif1x1AADVOdb16SPyM+xc86eHRTaFuWWEIm +ByLEItrUkAkeadujlv/S/PAAxwNrknJuPtnmfGnsqVMTEBOypTU+QtQpO+pWVcXRTB6V4Ng06uVm +OW0wzWOuITOo8QFuedW1qZ409QgKMfb4wktLZESvRBS2Lv0HFze2nbPsy1R+Lm2bUjn7yEDxbFqi +uRCnYBJD1a8ZKFXQtoXPNZbCBu/5wGdPo/MKm+JXJse/WZN3Ck9KnszV6VJ+k2VDsbzLmuHcJOAb +V8bu1C068jftH+LPwhplE3qL8sTP67IjzjajevtstWkah4lAzEDNcHugjE2uIDxIEGVZ7rmeYivh +phEx6/WUAp7gSaFmSFY1oBf+QhT9IjZ1ogmwiI5ECH65C1HMCwh9hy5kq48Ovw++VP/doW7SMvMS +F3mWg3XL651uGE1reLPBUBXhKLSf8oUODjHudG9PjQENb63HUr9TbNQEAZd15zJa0EvXxx48htk3 +wJRGCo/1qeMIroaR5VSg3nohiZ0h2EPmzeV+171ZKzyG6EFmY3RlfZvF3B8QVkcj4AUp8b+ddSlD +cpnVkdeYO/edsBKi6iKqTfWPdLv/qht4+fRwlFSjPbW9QPkUjhDMnMePSc/U14E8sXO5wyEbsFMs +Tw7V/jj3hVa9TWWXynEX2YIVPjLPvvpSZnFhczYHXF47IR1w/r5U1t1M6QCKW0P75zob9usSDo6X +hvxQ/1VKbGcxxG0Q29hOn5cCCBeHOJ73zws/64VdAbaOfqx6XnT9AMZxnfvG1j1jPifzpgSG8yzW +OflAGy6jyoLwJRQH0604gz+paQLwa3O5MNRZS52tpmxJPmmXFhiISkpcrzGBCJ7GpTvrV/gS8N9J +mX6c+u+bQD8GjyEvbmlSzJ9Gvngbvdjzs0lJ3NaPLKE7J4VszBoHjhk6xktTik19H0R+mSTvHNBx +XAiCeCGAKpm9tqKduxxMgrz5TJu+Dl/maorTde6bNGNtvXuVLzHWWlnt1IRJZcYCoDKPfYW5b1VX +l5sg5ATF9WSJQcu2Qo1AOLIggb9f/2srlR14JF7Ium6ZHFUw2Dqw2JyHXJDz69AHBkS80hGRU8YF +Mv4eE95E7Y0eTpTGmo28wdjKG3yZfdOz9bOxcEJd8/Otyb0Y8NoXr1W7aE4BpgzL6U2J79iKaEhK +8KkYVt/lfVS8dSrs8P1F53+WGsn80XEOqRHTYpifvhLWVDAYlPMxG1MNJxATyyCt8FO4AEE4ocA2 +ZFEMl8hbr7xWGkuPp24Y0hZJVO/1GivCbEv71PSUhMyGlXN+uTFmF37T6svbVQp8OnNiZMwsQcbt +UTlgQB985NKxw+hpZWg57GQrcoFzkFnv319iBYfiJUolgZK1NogDyUaZX4lo/xwkJlzaeMwYMRLv +PbI+dL8ODBp8qXaya/k0BP2ZcU4X6zbBTgKrCMdG9IxoAgTd91thCbQpHUKDO+oeHMO+7E7BRF1o +eZYrgueEXc30oEBEvcH9mWyg7s4+SYHjnuA0OQ6vq+fDIeo+MOiOuueHJbfOeABVb+g41FPVDxta +jMgxLefIWMx7h3vXMwsrq6SLpDAzcrjxxvaGEB9b1zb2MCYAH1s/l2uRDCZ0gFZwd2epHx+/A9HC +duOxSR0qn72cnJI6VwTBZkuOX2zJNKqjrkzZCLK8MPRaqHsnXfjkdeTCQ9BeYp/qbZtmgsUEm1V9 +7uyqzeTfAwjT1FsJCtlA5F2YECEgIXumnSkmkvk3KYFSNKEbljQJvb2tcR7jpiaDnnZzUA39jLHu +3kWotuuzdVvuFhrrszyay+BM3F8FVJKCU0fhYTGthIREEX1hyV+tol4kK9MLlR6rYJTegdkirDds +2mWWAS5V7i9XSHTCR/AtvkR3ZzGwUUYoZzlobnmNaJooknZ1sBqrViSMjZGrMt7kgE+NLl3Np9ZJ +dp+L31R97ydoUo4cRAiTqTxuNAS6CWgNUKkvHSr/ViqhMqysYS1FvZJaO44n6LeXiWGdsEYPBRPq +JG4Klge9JntjaTseS3FT/8EfzuBhNUwnanhmhMoEybJODYpot7rthRGl5o83xcrdYOmE6CCrlQQc +8JMiB81aIIDJQVcnt+SvUb8c6n1rIq5fdObn0hTo2wAkW8e0EMkUgXSg8TWHvYA2VY3ZE8yo0pmB +JsABxradGN1Tc4D6FvPlSGFx7FaGL4zlLCu/iTIGwAV2VwSVjb91Nh3JFzaVR1JkBEPFZi3pZyMD +9FhfksUhOPlUmJ4wqHerQxKbDxbF6Y+M80IMPDMOX8NnNqCmJch4kWmR8QHkeBpKlFPB4HKW1Gbw +Zl00+KjWQBrh8Q/PEKRlzspzf5/QuxBm8GpZp6khtjjjTJKRUw3zQBoma9zPIbXpR7kEclF8SB6U +Z0pE9hMsCXHl5Os6JDlcUwPGr2GXt2/cZRf2lKk9TgUGpIJVr9hFzwe51GbL7YB9Sf84DnpRI7ki +eCTEdKXMiUVIrUzGUz21szCFx8ayKJKfiFM++mT8kb34eqsX7D/uC4l14F4H4rXJVtpCBMTgaLRJ +EDjwjtwBN4hwLvOKLxoYk6qP3D9zYX2voCH9galXXDRB9S/RrxFkvRL/xsmueg8G6ETxSkzPA41/ +E19qS/gkKFO59dCVRzmeOKznmEF/k+NxGLLpkgMt6hqctt4rVVRXHvlcmupX84qGYriXoA+GjxEK +K5IXyl8MIk8lD0Sfa4dIlwl3s0eM5t1PxNNkISQizM+n3k7InqAsk9jSKHKvpJDugsxRDYBVyA/j +S4GVXJ5VXqI0K4dRhhLV2bFTU47ASmkXsfLxZI5pptuj50P1GhQV43aZXmCUPqyV6MYgZZhhHAvx +HUpDQWYbieZQ+ok1sZf7A9B7b1PCjZqvk4ql4zgjGDKbCO8yunVqFgyL2D6GNYvo4DV/ekwNnEHH +HrdxqQHSyGW/yKraZ73SgpJ93wGcL3vL5tmR59uDeoaPHXOwfP6ChsHW5XlozwoKQHpJ+CgnBclk +9XWPMQc0C//4vsv4bRqgQ26LnWPHQ5JP9tkK+CQImtlJD5hd3UhFdo4RkqFGfK7JjJjDwX2OJhxU +wE/0Drbe5Vhtk96EqRRKPiVBOICOEF5V622SbKh8tAqKixuGnXdHc5sswu1G1H+MTB5WM9j3Uvpu +HiPKKkgDH2yDXoum73dl+OE5LAg0uxYw1fH+RqV4qeJWeuv9OzdfPTGlpUnptOGXA3gDRoTGn529 +dhyp0g9q+xIiP2pGWsMOVF9QsWL82MZ6Sh30CDjcIGl0cM9uNCWBHaKLEJKViQwWaZemhRByccx8 +ZKDab8QCWfDafD4GLFx6zUvmCzVw3uaz5+Uhl7MszaatKTCVp8WDsb+g5RwO/nTfKBrFcG2VLlrF +SVSt/AW/Y8P4jCBbgyeuIz9gv9m8RJ0l5kmgg5c6f0n2ao8X7Hfk3UcE02aIy9YzUyOsVi2dJ6B4 +BYec43INL3jDcje+oo7CjG2MLW/uWPNABBXcTBvIcFUH00acNvGIee2m62uRRCsZm5I5mW8Q9q2i +Z94BF4OvXbHXZzJxCo5VEGcA2twk4rLhc1xD/T3HRg2RmYsxf8dsYPs0y1QNRF8GbxFn9Q1nHgJT +Z5cdoFL5eIqZh9se02XI7GeYU5eSMzUGxEZC07pSQdmVDtsc0h0695vyYkI2J7wE/mkqeQm8MEGt +IHocy/EYp2i87M0aDq0qn3yXKxyUJMYhq4B3z8CRJrMl6tn4/ZfbCknLle1WMY6kHrB4Ta6epM8T +jrVuPrWfCHYIun5FUCA6tU1o65Kg7hbfvoiTo/XpL/by7XyABOh3ZxXuqk+RSrMHYCGYjM/zgR2Z +JLW4oBFH+jSgnecjJea5Grrl+S74W+xithohgB/eIQfLlpxVqs335PkgZEpBi6+ZNj/KunmtRVeC +a57t3CMSINiNpVwigJre/gUrhAlJd6pH4YKlQRDMrfCFH3d4SUWpBfps8dMlsANJObaZAvZGZ1z0 +f8c6jRXlCeUTQ4ftR5uRC6u96GqKISjlAK3S5RQwgIirqImwjAJlfL0DGSkCthBLEJDgxeCCa9BZ +qCLXIePa3hfP03Pv8PSV+A0lNkQAZK3wTp+xIhh/wMjufb/R063yqR3slApIV6PcG3viwnMJHhA2 +KztVfauANYpyZiFF7Sl4WFmB1NfnC/DT61TJ1sqJOZ9ywn1WkRl58hZiCUA89rMwyoyTtNWXUpQA +APJ3bbXkITgbCuiHN5mdnNgu31sb7d7rpxRaymILLk4OXovH2vVslQecJn+8nuG2nH8GOVBzJCHK +xISndEeRCDl5RI36zFjzJI8FgwcygByxYzYjqr9Zg5DO5LLxZf5ETfIVc+UY062FUqb1nv+S4N7b +DGzpMqUfLSPu29gn4Q4t/wD2CphezCK4y2rG0oaH8nEVnLsHxqiuZI77Q5ALRpBfvJ9piOyDj4yj +egNcfKWMU96Jd64ODD06Gb8GOv/m8UQegW1q9iOtfATgFvk5ttjj97BxLh+FPIZHkLIe5hgfluU5 +2wSdpdjzpGTyngqY33/tZ6jmxfoZBA2c6KE/RTXHW+koDRik5uBuZYkNsnkau+WP6urOgXGstkVG +HK4xeWf0JEmXRl8Fatfw8wAOs2zuDH3VfAuHtS8R8gGwoXwq/bK+0OwRBfEcOVNA8L+sSNoym/Dz +1CBI4BqXN5t3iBD1sf+V0+xc19MXxcpCiY7Jo/qTgY0VnNweuQJcaOg4rs0VwYwYMeVb3jPQFtor +F0qzdk1tVRLlryq6j+O/c1nBoedT1NWcXZwDClPJ/Hb1+qryDQjOL2eG2Lyi+DKELD6DikLSV8SS +0W6lpUUvcN9b6uLbOpuI0biPOttjy66GHOUycYbT5YTYokrhF6qbL772CicjXcby9JUhNHDobwla +UMAODqfatfO8+Rm8bxMZ+WXCPSbzC9Xr7bWjqcqXIbrEe9jKkl1nB2POsTOouzTgMLLYqZVbtqbM +Yo1Vq+63pw4nG0MPNW5gPiqMZ51+I+6niuZHB4IvggMiat7vaY58SicfoDZ17hG4pYGT1fu/RuXJ +Zg0EKz+gmUfXzIH8jEh8YUwTbk7p9vZQ4R/Ww5pY1gHd+Zt+aEzBQEC/scnKU+aQvUsqUY9VZ2I6 +hZ0qvsxBan/mNMDi44IaorV+haKLfbkGNHMIV4hm2RGKdJRLryHfjG6c2VljHclxW+R2jNUpKJhd +joH+4OqMcgJJVgbGXCgAxBOhuiZeiEV0MCAy15YICBiy1IanUT+DKb2FF6iUeh/IwXSx3O95MKYb +9dGhTp7Wj2jaihz8OjdSu3x0e5z8ztYSvFam4/FbjVhfBC1iIZhUBVhtvYL8And+Gk+FuObz4N6F +l1adoF0bTQjyTCRINBqMa+dK/ALhwvbfLBxvqEP8b9Pe80QNd9YA5/2Ajh1J/r/dMoth/1H89b2y +fFoBTxsJNbnEVNOd7yWvP2Bec2eekO8gCw/tU62cxX0F85XChfVohHn986EY5JIj8KYGDtYXAtka +XVfdfTGON1mzhiqE8JftiiPrkgXwY8+C8Gu+IURODl0tDTyWmaBoDuVDlhRYwyHs3ZKo3g3J/tgt +3GCZh2gxhG6N9knuTxn9sh/7c1Q2uRerHbE+C9WaJmAytWK9pw5CUEocwaBH3zmJ5uUEYklBLC27 +D8Q/6x+XUOBQbHMGO5FnIrXP6cSMLTsf1/QX0N944y+zhytgfAec+9iNXwx/X7z4yEQEd1rHTyKd +b0922T5fnEL0LFrr5aaCRn2Avt4xi6z7pdJIbVAZ/z250fW3kDIXTIUQVmThNpFyNyGGnbupsEMs +alRBcMa7dXP+gH3sgaUvPQJ0PFEKdNyZki1OV73zU6/hHkr1bVcCWCYLXS5CnWVjawNA366708VG +tW5ukuRyNmyyg664OAqqv52yyFpVTRUHFEL9JCwM2FgGlIouZxk+sb6wM1XBx8Ml3t7h/TWj3yR0 +ksCsXqv+Myj0BnzWOE5hzYwIvweEzDlddBAqm99biQr61W1LrJdq3wz8YqqpxazsLpcUuaSAMEMD +pZu/eHQ65Vt2S2fmNKC1tnCeno+W46juh3IU8PVOTjRC2/eBezUVkfd0pA/Lg9Mn2CPvGAaZ82mt +mI2L2whK4jZmCxE9uvyDxqMmIQ9ttxBCSWZZFEpkePrCJr/KSjVZqYCYYNmTJ+C8zpqYxrCgCdjd +/O7Hc4W2diivmgbrmaR4sOSoBijZvdZu55UD2gsa5b3PYCKCFOcMTE7CLEYuL+pC2kNn1Gg8fiNn +qDXDfHnuvTZ9uIQ0OFclyXGS3D/1FKy1Z6tyN4YHu5w18bFNjb8+F+Y+HgezDMWHiqqLU+zeq2l/ +EHnV4o64rc5rIcD0t8JDk8GRafCD4ghxaV0E6JKFa+bysZhnyCQ/c4q96/g5PXNwI/25gNY6Pf+k +7gUV8xD++rmYBsWtIPDpnUj37sW5MtaFbTvRi6qU34Cpp0byDwvm8VKtrMCHJtvk4EQwea2TgybP +8+dMYDAWQyxBoH8QmIVT2i1n5SxTLYMjq/AFfqdJeluYogQ7+tUTubu74Z9yA8Ls/u8v3LaFys/T +3sTiJJuM19bYW5Ftc/Bn1gnwTq9/y6yegDCGfX0srdCc6/6DFa5EqqqYL8TjSgsL1UQIu+Fu2c/1 +5Y0NvBIskiQC8UFomEdG2zcJmlsiAR/O11+yBkd006ZgpBX3pF/HFDvN851+QawJaezgO2CHnVkL +cR8EZxKRDl4MlHqX7cRvPDLwsToNpM64WtzQFwZNK37ed1PhIVsy5wNzkei/9fwGaFOmlKHM2WFU +23TOpr4/WBBaI+Uq5APVnQQcnlK/iK2iB2LpCUTjq/cd+qt5mLqIeawAwD9X+noWOIHUluRutCLM +C6hfG/b6+0VPGb7XRAmQSx3phvpw+Yy2sIo1AlzX7IXigxaXSjFMyKBP/JqXurVVCPWeyZJHxxAr +lLlSmyxl6j8JrdKwVSMabi4xg8FnhOTF+tSoDw6Dq1UbN8s4WMyy+owZ2m5irnf9wu/5IOAt6c0L +rHC8/iq7oFudzNCAUW/HOMHnrNxXTEcauXykeaXuTWiuERPUWUeR3TYX5gxH/FyE3jXm/Uav3k3j +a4BfEP2/wfzMAWtE83AMbLjLHNFVGtfR5H8QnjorPvPOXQsYb5B03sTkGS27PpmB1Bl7Iqbb4luB +B2U9fU+OEWhN+h+UChkz1RXC8DiATxShwaLj9glJJKFRM+gQS6qzUZr9ebTFZkzgh8hc9npk0shm +zBOThc2t2KGFGXc69bNTD6zYvTc9WO1jXO+0bNorokLp/82+PU4xxnULEUpuRWBg+QxW3t9we2qV +7J60yvMNQARTKTV5EbKUYcUKwmqj0fAn0Qdtobe/8jFN5julB8k+GCh9PiPeXtPI7vNL7/ZZIFwc +3AL2+SzpE7gXssHLYL0O4bRobyUan44kTZCze/bGqoUY1abW7lOxtqgYcBQ7MlEDBB5PsSwU6kb3 +qUu06SzBrxDwUuENbT4bdtVGK7oJt9CHSzzRDx0v4oFm9yswQAZPTqXvCGyHlOAG4JlQ8EkrREnW ++aYN6/mR3ENAjE7qHc34WPN47GAhUwXGwZp15ZJwYsqOugDSEYLpVZuNKCihWNEZt4/aLqRVqzgV +BAXRuVPR4W7xI/SWem/UHYQCHUQvXtyNJyLEDq47PRtq02V6qv1T4cqPMMI4RBIBqbv0PUpTAxUN +7ImiZI1ABHvio+DbsznE+SkVaBdPjYvJgJkiwQfB+bhe9707KMSmtTNTGjri2ctnBzXC3sb0DKBn +LC31xxU9cAhGpiRwH+lxP103EtIkHSB1D3QGTRTPkQIzDSusQ0PttAV2PHawBxxQec67fh07J8Gm +JPJubMsdvzoFle+a/BzJKqn2lS1hdWIvTILuJqiEBN2gcSVNoHQoaz90eFx4x+bQCAoW+hJ/Btla +wZdHcA+ZTfsfo45rj8lyapoQ5IP98US7cFR5A5vm+TSL+TdHjQuZdKAUP+biBNVWTqbmTPzwDOjw +5B2N37w8sFc2gAATWKybuHrnQGqRgZv20KIV1BDSesYWVrJMgzc5hfvpMlHX0yOy+bSTPJoziktb +YsfpvPSTxPRWjWEnW/yVZJcSWA/No0dVii5buA1WxWNLIYyXxwKigodHTn0J2LnQEWCSTEXesjNn +MxfHo/4wYNwnzsfmNdQZn0H53YpJnIPQfAzxOqw1xq6g1KMrJXF0Du/6VnqXnIpqJNowBf0oRk81 +a0AcgE/ISDHMyb1wzhhVjkyqitH7HrY2KCC2xWWaYOf+zpM4Sh1XC2sqWv9xga5ngK6NSPS8m3Ue ++Jacj5tJyxZZGzxvpeFyUoa0h+EW1WwWNzvfsHlgLnxe5YDxdeKOxKvZiy/XIf9RgH707ffoqRjm +4/FiM0TLr56s1gEErbdHXqKE8y/MHRj+8+yJi83sGVOQqMt0LMLCh+gF+epmDtdj4u1rmgyyQcnu +nk48CVfBMZrwsPo5aUoW7wE60XGfcghCtoY8bKL/x3slpN/2aifAh3cSDMdbFNrvVmgnirCYVa1h ++MxKVJp+eo0RFHM+njRfSPjfMICDXe3R12NCQpfTeqSgArUoFhwO53x0TRvQdiBAX40d/Sk+P1wd +BnpxcjuJ/0BnDL6IF09heN93TaJaC0NOAXqF55MHDT2sPYIRj9+QmJMO/QD/pTYdbWuTcI8ke/C+ +Y1fpL8J9SGLa6Re9dsS1Fzwo3ceVNc4Ok7hQMymQ9YF0//A6NCUR6FaROGhBe602vxN7NUtbx4en +G6PzSZ8tNcvAFQOkW5PeCld2UCnbcmg+wXEiQZLLqNEWDNVTGTJKuRT4KoE8He833lH4uN2lEyo9 +l3XVGlSS0WjAfrw2StaiHRabFlpRD8OpxWLkrfUC29KuTUFeaL4XM5ifhEbSDTj60oqwYVoj5QvR +HLwNX3eE4qlC+9ed3ksTOgD0o4uV0MgCmuvD1kJo+YEfynJxr9IpRNfZYt+PsxN6KCracEswPNN2 +JhlPbpy5ObVCoNsmHiyx1ub9GFZNXTM4buYuTiwqmXx4+i5EH/R7eBSiO7/0Bmb0JorCr6pAJCON +QAz0PfGgiijvpVvok/EBUgARaz3XjwaM3Cmq17Bff4wQt/hSXWkSNUuXChWucI7/YY7QbIbwkGkm +z0DH0YUXekLLJ1uA5eDF2fZCQXM0l1ERGdjIOgA0irSBqrI7e7zCFfJBZdr7gE7A6oCOECHNj1x1 +SqzfBwO1xicjG1l2ZPGr+WhR6u2hqNjFOOeU3bLTENOX8A0c8XH/G7tsbZD1mLSmd0LoVlUDfKAf +QMeEKuPi9bJoAw32cQx3Zqcq2NnvwRBiR4b6x/JqwuZf6Yk1JtANanhJPqwEujBsskVtA5G6R2qs +t5wT0axG+T3OvYiFKg2OVpXsExqpesoA1aimQrQrL6MEEOaz5kWPB5rbZEINxghXbIj27vAyhrKY +ECf3SLDy+2fZnetOxKaSEzHEK3TXxNs+vNBRcuzP4xSBsSERFPLmOdF5AqL5KhZ6vsxYCEWkgyHf +se5EYO5HyHBac7vQtnJshuzrmXlUzNOzu12pupi9GvH304s7X48XKjeir4PVz0yHYQG6P/SIBvso +vjSbb+9dRrCGJZpXai7H4025TyawbGPN0P8L178Xe1KVzjD2lmjgwHe9Ojbs5HwG4PaAxlxUYOSq +xjGLYYAi6fFZ91z+BoA+MGlpXXRW2V5Y2qsWQjKUK7jTEoEHhZRTmI6NYaxMEgYZQTje2m46SQ4C +044O366H5oD9ABpcbqap4lKg1rKeGS4kPHv86KgMRQ3BUS2XY6v2YTQFy8vXQUNETtbMopnLD1V5 +xFhKNdaC5wBXc5Ky+QFT8sfY8INRZQnG5sOUV8YlnpD3AzQv3KD9V4x860Tvqd8B6vjIF0PV3ezx +p8kGQIhx9EDmXc/i8D0sjtmOwlmftxkX7zFe83M0EHunBzRK+E/EMyb8DvfzZvvMEZtueyEOqmVn +ZJV+6tWFNsgQ/YhR9a6k8tvepSMYYjuqtAKwzDEMK6RRb0NSKX077q9h9Pxv4BNUkJaYjvAWBGpC +/+G0ByBG99f2MsSnnP+XCX5Z6lPWeYzuENRwR8A3r0XbdEc5WxAuBJUAx2bt7GQKP2a9xMNan81p +Aez4a4Q4Np4kACKDTpi6Ck4WsF4hp7DwWxJdpv1HRfuWTZ6Z0fHYd8Xt4FDsGvgNg6a45gIx/2Ph +weDIcFBZejbTnofz1eAx3FMPy87MzwDciIt56RxckrnYiZkJ3iPR8Dpy2rqgw/s0FA/zlWQdwdBI +qSG642aq+70nIj/38sOeMnPKK3xyagyAra0oHCnYqo/FvboXwFw1Vw8B2idYpyrEIqzZJIRIAj4q +DcavuIO29IMU0z5XmulYgrjH96uqZzCeOvP4KIfFsDJChuvCEeyc2yKX1YK4iBAfCOgOckcMX8XU +snZt3lVmZOxe2K6aJ2m+QmwWFot8Bigwu1+utrx8Qo80/VBADn3KXKWe13RuRCRBTyESk/6d5CBC +qC4e8tkgzxv7c3Vhh/xq5CGPuLzRZNJdaUZ2JAdbWICYew/S0jxnP9MI+64RL5Xpdv4AN6/oLoHH +swDnWD3PO87LC5ZzOmypTDGVo4m09kWLhbhDI6N2CkJ3WWNAvv4TVn6BvrwxiFLumerCYjglO2Fv +bhPGu5+S8av0RFCb1zV6EA8/T6PiKD31XxURqkv8V7OVpv+aOuNRItSLiBNybcuiWk+2Hk4QZ5Hv +ra/GTtC2qYXBt6Gn4lmkw8J2zGyouuUKezMilCHCA1ivl6eCq4v82bk2aLxY9+kA8zQeuZmsC/N6 +m4wtxXmoBd7m/hSX4XVRKtoDThckdBNPWzGbewxNnxqgs1Xhqo2Jz9MiSRCBG3XESOxWxJZK0Dzf +sdFMwTDWUXtiY+bvxz25VVXm/wwjTLjSczHnvvAoH9+fc5CFZlG5s+ah8spRQuQ1OpcvSG8bwUJS +sl2KyFzBTA9zRcU6qHAsd7kaZcZueshFWh4Qrrf2lZakRWxwpMsE3fHaUA35tGa03MFDohFiyxoO +V593MjjfsNWaypAbjzfLAAivwFlPhW3LbPEwZUqWQ/djkDeLShD9B3ouC5AhCZTmwxXu2tSB2RMD +E3u2fFu4p+UNgC5srRSnZaW+B1+ssZQK6CW4S5jG9JCYtEob8n3m7zwWaq4c3DWxEF4Q44HZziny +UTsMB9ExdHm7N9TzdB0jzf+DfbkLCLzlGe1NJlwNu7ix9wTi+2cHH8Rl12HYpaW2cWXLMmQAFK2V +imf15Mvoz7TYBy6BtXhiTHobqpWgkyUNMXwDd9iHbap/sTUTUu9q6FDazY/fr2NNsUCc80j9Nrq8 +xxcIEX7jrkHRPF4JdJw6CMJwufqwWZ3yhsSWskOAsqZvaggdifbRGzplSX5KMrUapC4r3N11eVAI +4Jm9pPFYOEXuj+A+avxwJz3kq4s0+TDFlO2NepVm3SZwpCVbHjeWAtaFTV7LVF8lHtIRunmAM0DH +HjrkRRnei5Iejnp3QN0VSd0CF7W5oeFuo/WfNBDGlVWYkNr1I9enonQgjU+qMr/sK1UOjBZlykzC +VuoAwgInuSBuNaHX8IF8zNOXrgOgg8pZYK7yFAR5primmGsuJZNDUYXagpFcdP0k0UBL17VvVx69 +FgTMnO2QXVF+0paghsxS0FnJPfw6PzufpS6P5WaQHBiw5bt53/PMvfXmNcsHGF6clZUHqKMFnbg5 +HuUehghW95DqRD7EHxmOzFt8txonkG+nWbvSz/e0m18qKV5RbZ9+1xynWrDpllwO/4Wfk4vcINIj +usT3CiIWhy/cD8jSyFnQqtOWgg/BPi39+P7tHKDwimtXY2wiHFLAlnjyrM0xv4hs3pP+lJotQNjY +rYDmqvWCW33ay4k2ashIWgciowYbQO9PcJwpMl+hhv2Zivl4iOJZ/M+avFFCmdubUE9sUylxwrHl +0at6G7W/Ly+sxAm4q7kWTQR+Ve9Tfj/qX5Ty6jrqi2vYIx/0n/cyZDOu1eWQMmrjJZO9Tzp+p/9r +8Ekh3S9AZPIfXhvIViUKakiMGXGqF6lat4gTIlS8pXDX8is78NXnYSRvIx+rsPp2WX5mLeuF7XvF +B3dDcmvYwKBhcm/75PiUJtPniah107wsWbLtpj2rSUIi3FKamIGq1an9op5/0Py/JkXJYgkOREf+ +uyzuka2w41iX6ZE6Yl+1clHLLh+066Xmy6O+Rt9mufJIYArp/bdYvpUyf6om9zfaLIw7kzxrXafn +OOM9B6blGNcSuI8fQJxjABiX/zAG9Pz7uK20ZhksZjnz67GHhSGICZayNwJzc8BVbDHFHSYcO4pu +VmYoRz+5MP1J0TcvUfnJNlnNApvQdeovWSV9VEPTuAvECIcGAPu8hyYpalK148Y2UoJfoJyomFLC +fkE8cTy91mClvrqtjGFDFq0pvsmnM4h3/K365ikn+vhySiEHhJJfjbSUEd5sn+lw6BqZxUqiqfwM +A0ZXH4m3Lav//hIeJRRhHJ7Zs7sFS+ed/kc6l8rUEIkla9i8dTtwjviqfHIamuRXAhsWdBMjpmeR +OOEA4vcKHYhHCsHP21DK1n5XAmeYLe554+p/tFu1yDFKqgBpf2f8qh3Y+OcHK2HNA/jHGyH6BEdl +13mEEeWf5tLXiyBhAUvNOkFeiZe7ApUxlU9EPnzcoro+F3OZEMbF1HXNeT6i5Mb/mCBT8hXLk+pj +1yDHNuYFDoFdIW6m3W7/mjBVhnegIcHylHNMpkjUN3dT9UWMMYS2yl7b1PdJFdoBaPHXZgTF0gZJ +0mDZJ4k+TDYfL+7x/2btKp6Ke0uPNdWKfkVX7dyilN3lDfC5B8oMnlyLcehdELQRKfq4QrHh7GcT +E+8T+WpdOZXC3M99FlP0KT1pDRupCIAm+lZ+Ffw7Gf4Byot5r/aK/q4gC8omOqk+qgQwlIVNdpnw +XUkmfPfrK7rdEx1mkNZ4XWBmA8zjimo+KGZBmwMaJHk7hIf6J3/K2QZpfLdTwJaoSWgjsVfojhl8 ++Giodiq1x7wUExLDHouicRTnjAMdGfV7772ZhEmyK5Cpeg5weP10Pw6EQ+nb9rguS869oHeVfg9I +XBODmf0C1jGMaqlGixTpOu8f6yJ79oZpsJtxoxsbp3jaiLvNSWEL1hqQRLDTcqlVQIAtpq0D7LTF +880OfyNXm/uz4kT3RdLk5Cs+y/QShTZgAQqH7MmH6jiwVI814PB9Js5rPmLR2QN8ysyrqeStDG/9 +JwAup3jBtjHjcl2X/GWhRbmwhZ1/2iyMhM5uAz4Vn9gggY4rMeIVV/42hpvkeTRdbk9Vs3bCaNyt +rRK37CqteMFx4JhD47avU+AGd18TqY8MiTyXGPlNZ89U6sgZ1zyEqemdHVbdKLGdxU1umWiD5ee3 +HH+YUu84aHfIC4u53uysNx958Rf8fTdAdi2vvubFfd3QWA014M06/HZuVFe8iAvB0KxcPlhcuSfv +Rauc0ii1LWrDq5HomoTxk1oX9Tx1CPrzJjabz/rw1yt6vbvZj65nhYl9G9G54krJHeyZdsDSeAkL +dZXeKh8dYKIHFFwFxMzJk7aTz6FOzlNoV31Nu4XKrWb4r/zIHBX4KlQBSRoiDICeA3nDTkiSFM2Q +ce+Qew4UWn0axANif43PBgc/pbNYJ4itZmuoIFVebqgWNV1sid6CivT3QR3tKP1YCjq4P/nTprXo +Jgw5oBsxQ5dd+HHQQ8Bnnkd54OcmnAl4DpuMrSzwYzealgcyS84XmCo2dOkTNteoG3c5umQJyU76 +fvH1OJdRIgnoPOJanexMKrJvsWP75RwD5pKbBRyNRy4UM2MDGSsTSBvqTMx8fD0Fqq99ASeC1/ZU +UdllEFe0CNG8L6ye2oAwCKtg9gIfmzt4PYGsbflRRj5xpaRBwvFlp/FKLNt/KOQ1CXokLYdCy1mT +k37wt7nHtVxcjGXlTkHKl25uYiyelXRjX2zcgESq1UDiWL3XLVIzF1sb4An646BB6oizxTQl2LpL +S5vFxU1LQgk0hk+RN6V6zGYItUlm/8b4O45j3nziHb7wEcJa0+L4ERl/5oAT2R4KLuHLVMJARnaT +SIGo4PfKDKJ3QBRnf2VEcE6KTNFeYlb4mNRdFfj9GmPqzwfWvwR5n4/7G9xjwveGvoLCYHwr9nnz +BXVdGWqW3yRYv/IhdbMBSpkikYRP2rErmKW/fMX0W/jyZWJ/xhKxWsz5ilQtPS1LkIj2nXzbe+1g +VVGCyekDjZjknUzLVngixRl36wBsbNpYzRJ+RtAU0N8Eh0vIRf4gBZZawdzXOKjvRVZXDaozZfYr +NRl5PgtgSZrLHSJnk8oTzkZfVSB92z8yi6bO+84hcIxsJGKkY7YHudDoZ88vRT+Z0uM6XvdpuXIb ++WHb8U+9fBxYYDmFxHiNuteKicNJfiDJL9OCUyzM1fcXTBDKgEpN3F3agkMnGzwhzgObsIa2290W +GLvWJyKor93U2MEpoQQs75/hXq0t64mwF5YhSYnWVFG0g9JN1QXZxK8aMY6CUZz0ajy85riF/6N5 +tkRDWkGHB93fM1Mu/pfsXUuY+tHWxhrN5dpc2VJCewUgzmkvsGoGrkIHOmslsBCaR6Ng26jtk+Df +WmAYjbeAvaX/yl0cM40XDVvPLdM/jwVBfiVHGP/l1sF+YZcK3UP8CMV7VvMVW56Uw1azTp9+Gu6l +/UrDR3aaY6cyk+QbjK6K/p9jyhj0aV+4O7QnFfG97LLH/5YrSpUVhVDNXCS7VzSQiqOiK6Intc0/ +eK+vzMTSNYNy1Q/j6uJzx89QpRKDEjWWFdNcVxXZe2Uit8Z1n3sl9EWvEQv67XxaKwbfCcQm1OBV +Y+NDnjrsPcpoRGK2YBRazmZJt0TrpRo3I1PeFE+hwmwSvsCFgkC0P3Owc1QomodUuHxNvCKwogUR +Vfx6+rqytgxPDsuwVpO/U0JswwYIB564gxYityWse9fyS914AFpyFWcswky6Le9Ax0yyVy0Mm2bY +0JMsv0hwM2vYc2hLxskjvhxXixd2D+1VoYkCEATHmUltXrL+qdBaVLWC0luTai+OBnC1K08G0w4Y +zq6oVBQEzQgmF7qIUHvtd34ZwxpAbtjPB6l6f3sL3od6ywWhInHnomlj2ct46+Il99hFfFwFhhxR +uYJCigO7Wlzmrxldm3FLlg/Oh5xRCuYXzrf+GphdEtnylV/oqVViv1zOLxwTuBO2doSGCB4xGQZz +4BqbwqiuI9cvQSFSsj0a+dyWczN7HMbsd+ZhgYuRVePpG4mzXcMCVGt2kE889JJX+NwI3q2j80+X +48rhnvKmgXnGRpOgbwhKwhT2Xm7M2pIXYgtOPLP2trp3TTwc5wFDxvtdd54Eb7tcFVYtYEmqQM2f +g1b8UQ34Md6mOLc/CVwEbvjB19rwdjHgIoIfZHjb7vpGUfHqR6SNB82ZdCfXJWAWriLAHagA7oHj +Hc141eW6pmkzNV8bQd2tXcFwNGRhpd2NL4B00aFlzKCs3yozO9GyEkaUrj8+9BVNsp4Zywug/FoC +7vq9oIYEE/KAjYRTtGLgjOX2HKoeJYEm2Z7fi2dX7fOJGDMTz0aaDc+tdRc7LKCNZT0LrbQe0D1+ +3r7doNqBmo6d6GsbbFmePvCNDgdubb0NmXJCBezoHQW3OBV2+fGh1+mll/3Bq6P3hn9efEpUno7N +s39oGbYg1frKGDTRe2sIfjCl+/jXH65mzo/0zpUP36aedirWoTYJpmHMpINnOeGPUZrYI1DaMds3 +aNQ0GVH759z28JMhAbbO251jLnEoa4kZRVI8SXT9q7QCQei63HYoh2lQ0GHEsYf9e3u70VCuchps +U/99DYvdGg4ZXt8Tc4rq1a8gy0SgSKAfcHCLHhacvUKl+WBZnJ9jOOUsKW0GNm2P+AHLD0WrWSFQ +TzYcjXEF8Fd6BQx61JcLQTWiQOEBGLYYeGVeFmR4xFIB96+MC+GhVKaBOJv/LOk5N7r4OzjfAjWW +3YvMP5nSNtpkheMNFejRAMZNfKJLWeVoNgYVs+lqC17qKktNoHNKBAQFqc2iopfdnvajnFVwugng +bQ0y59H287MmPNNTxdDzPPkW6osD8r3SKIxIG5FZwnFXrzFQx3QyJ3ZyrobJiZuE0HanWWzjwjzP +yQlCTWif61tUllrpuSFwGMh23Kb0skIVIwru6rCSVUxL87C+9D+xWsYBLWLQadt7oL2viUiwoJPW +gzDeTL4T4hc65mEfPugGgcG2yCg5iMW/sLaEm7RxI1ycuue9ZBVtmiGyJwBDM44sOi/bpyGEfBqN +n21zQwKDODSyXYCvoohmGSl+qSWc2OVwXG28PUgDRNCHx9T5J5TS8eAsWHWa2iMj5IhcBrfVjfGk +2pkFSazUNx4pgw4mW6iEkTPveUyPvhDIjoj6T24nbOiLBDQyZCYZZrLrt+6aj+uMvfubuUf336KK +vPfRlO/kJDYxkR2nWaOU2MguTPBFvOK0ZDbsrP75iccLSdq5OcytSXMXzatwODr2drkozWuRpGBy +Uu6RgyvJxdaLW5vzh5WwL3UdnmBE3OhjbdbrJLgmjZRd8bvLSSlohl4aLZ9RZPTYPACFvjinoMVu +3lbEHb53TleteCnWlburzwQ/SR1j96GzTrp8epF4ZiNicGockkk1KQs8s3qrJxMyB4vWnhgZlmcW +jytYTdwZG+sORIAg4Ulbih1n+kVzwee+99cz1ZGPcih1LFmDVaWlXTQjdzLbu0QAnWtBcZcR8JY5 +VywuvrzfnEhxwF/WbpqI5iel4vnsZjFU1Oqn1Ews0BsrgAnOiyFj2gqrSGJcmz/bKGDWYN4T7ZHm +tQPP5F3l7GRUOS+c5YjiJwjd7OFStPa/5toRAxUFythWvrSa4SRNHQuuX9iz9ig33GrUUVRDYGa0 +iikbkK/EtMkw4GnED8+Z1WjK0Pv2EI2OaRRMz+qW+1TgBFqi3feWxFADAHuXSh1BFujERfVKEggr +qdQO1CHQAsvoZRKhNPkTJ6zB3c/DzXT65yIVTGmrbhrGQcXay/xs10f0NqQ0vZb35O6wyHRJVPik +cjXPwSeNXdB6zrg0AhfsPJwM2POC/FM8A78fmUzBDOYzTH8Xm7I70uwX+mQPHXiIvLvk+ky3YmQd +NTxwKnu4KU7DaD84gRgkp4hPbqa475RpNOrAGPeQJLY7XHzwKf9Z9wUVAM4kqm5vxtHTlZ3loEkd +QqzAAwfnVk2GuRRhkTQiX4GpAK6dIX9+f5iGCTOE6/A2zdKc/WC8RbUCFmVPpef98PQjPyGlN7fm +Wf5mtPMtmp6ZrbTzlI5W4PG4BRVdXLo5YtRkxAFhIyXxL1N+BhUmTjrCBB19WwZPzdwXIwsDLvqV +qQK+uc0sxY+PIsKuZ4iZ17mci3rJ/xNog9PC7ArEOOHPWTtLDqHFhpFEO4h0PVQmR8QHZUril9TQ +vKciodvRTIKZ94WxqgePf129KM9gAiy/maA0A+6M/+AoHvkrxZumhLn4mXkdnh9E0oe62gYHgWmW +KpkkixIm9kSciDWE1rgoUjeirV4owho6EEMKusrOgvRWYSsP1mtErIIE1KxEyP5+VaLG35C9xrpT +Vw0JSijCMrx21vhI25v0hSlC9wVJpi2sa/xs8NcAe6kIcXUr4AtjFz24wFF05WYtFQ4xOdIU54Mj +MIJOETUpgaGj8wD+O5JWJF/IViiyesfIJkBpnghqDmb97hLSqfcgXXcuUtG6oaj6HH8mzN3aR6qp +jXQflccOZ4KQedD6RPM2ziSTJTPt/wlQmbJQky28bZfJM+qi/4vqxIvXAuBq/BTZL+urp3i0hYdF +Rz5nXQtSXjPiiQNsc5KbbDv9XsChTNrn6tmbF1EhCB+Xb2NR1xk+B53opwPdcQ6hEIPtJz52RLGF +VbdMczoTHUG54C6Ubwwt6egVHS+BkkL3xzFWFrqR6XwQAi6HEx4Qi0kLlobJeltevm4EL66qAyth +FVWvJ5dexnOaALVk/NpnzSyim0kT67S7HMxf7v+R5FrIRo77afu0+qL/gVlSvWsZY9eaXnHe2NjH +zGVZ7KuQ51cKuDzD7XyBKDJntLURTbwxVHlXHHQRAaDQc+Sz8i+N41d0quqCBI8JjS6gxx65jP/O +Z5sj8OMXfUAJtDsmMoY8QBv8oKa+r6BoRm6iMmaRbIFhWdull9lglflm9Y8xeFymgmpSiWLuIyhg ++G9c5xrjTJYdDW9XeYhskEdpvPf2pSg4PFFTKz8tOl1IZ+ruso9VHhl1oiBryI4e9+Bt7WyLjZKp +QGsYAPrReSJhxH+pb8HVtHDEZ3FBdmKepe0IN+as28fsvtgNVbx0otMrfrNtv3J1/mo3sRs9ediL +AD9BwjAAZ+DNZdsWy/HnK63Ia+JL+NBwf6IY4IDGZmst15/qXR2tZZEO0qaoF8FlG6nNnfiz5Qvw +bY+ZxLI1KC2OKtIQkq3Tg1bcOhrNnm/S4es8CkhzQZ8fbMWEi9w4Vgh6IzOqi5wiSGd2vJYDPQj9 +yh7QvvkRmYZs5AU+NaVcnYox4Err1CQw1K543KeO2OuSrmcF+oZmrQqH9L560iVKMD5Y+KMAZ+1y +nEeiBF5SJ9Gz8HNtxSFI+j3QxzO6VIZx0ycDDnLaUK9M2Z7f8YaWfFU+X1qh3gecGZGuT1ePDwJs +NWp+eD2XoqkGovqNiPMTHRls4iWQwSTVSYNKpT6uLEYLPpRZbKDZHWqXJYWUl1syy/qG0wkYAI6b +7wnNsm4rF6svYB84wmQCrY6ohhV5o07JL77XmyeRqWTz9OAXWTkjFOLithbgMEZ+Bflo8KU54IaD +3htdArNQmX2ELJBxLu/DoB0/BC3eQFzwbPdGzfmLoCeYiQ/cct0EcR9pd5UZNwORlZHZVJ0+21T2 +FRw4ZB7fRsjMf5XzvTIDzGMsWfiPIr/8vDIYbPBnXzCBkpVEXv0Zu7XNDBlj+86CTAt1X2SpENPF ++OtvIzNmBj4ZIXGlWdzi+qla1hfZn+KegQp1aqLbkNr0QQV+7TKCd78t5QExNjkV8N7uavj8i/VX +Y8R6AKypf4cNwA1j+TtBqxsb2Dh0B3UpEcq20AXCcf/rAQy3lp3vgdfkkbT7ygi1c8tob42knmfz ++XVuD943I+ShjiryZrin+5dX6s+1HnP6OWuXSRZepp7tn69J7Xz1dvxXCW0vEDZp5pRrIcUJMrb3 +gugNesKTDxa4emcxfQgk3ONNQg/oB2Ac3Pt50b+VHZgdsrxI+Y01HSQ37OFAZbxjOlVEBxgPwOhO +hPna8l4csJvoY3Ne5qxD/wJn3eP+IOLuz59nmAJuEUHGM1E6a9gjr0DiUMCohvDmQfhrd5A7Sze2 +77MIVi0W7cLv0N9SYaOetTlMWt7dyhn0FFkKwvmSZgkdaUaUwBsQ51ekPk/VuPfcaUg4IuTFgOpm +1zJ9lJSx2JuILYTc56gfdMZkQoADqMUXS/3dkzeng342loMMv71mseI5PM8iD1DCX8u5uVXycPXC +yrJXss4iewGi8S9RukMXbRJ/XoJw0TdoMcR6/YzcyKpSl+qClWZBY3vXYW2DBUDREdY9qJvCgMAb +++Db2qSLHzyf6uRxmU//QPIAp+L9wpCd3iprPT7LIvFJNgU7B4Hj4SLLBxqVNCyM2iWaFvtzy9Mg +HG2YkC0noMOt4yaGKwccUztGPectz6V8dwL4hI2F+7Z2n2cGueca0OuU2cAqSjSyGY/5ohifJUOc +6sFZ+6yOxZ8MLlCsgSR2Ke7pxQB6aCjP1KFz+cZVMgsSZ502hWSAA6mR/cSRKwd+K7qigZVjvvUA +d9LCn2+QqgcqyDjGCWOQ9ahW9H/uUkzwlLwB/+Y+WUHh8aNJVB5Kwerlue+7D6YeLPME6s0s6Us/ +K6drDUVD6Tjsdh/XRH08TThMx2BiFb2gIMXB9CW1TdeSBBOLCKAaR9+ZIv80CvPVA53yIic53ODm +SdTZmpMkTq3BMOG+tQEafg1GCvL9hdwnxUBxaiDkSnPIt0sQUYgWqKJr0FpvFlEEKVwHT03q8+NZ +4YjZk2WRW6IoQEuUroIJvUxJ7mVYPQHlMULMmhHWlppEmEsSGl2gsH6xekMPhOQFleY6ptHR/RD9 +nIrMgONXy/6u4IAbmTgb9dSxGcYYd3LTxttc31sZbM8+hVZzlo3B15Tgb+ZZcfzfGj/FCOo7I4qn +LElfHshJpjLjeUZ4v9+Kd8mmj3x0pwUWj6do5zR0WgWZXz3FjbQbwZMxZByLA46vzN8eZUoaKXSM +1YZ4L+z7+yHM48mQwuM5sN6sNomZV3UcYfHTvL3A6u6eMenquW/WAIMs2HALFqKI4p6lqMD2orQ+ +sdUUVM0M40JSyGWws+gZ7CecTGx9uJ82TuEwHOxrh2Ay+Rt4uGuBZKaGBNQTuRtiIXwrMTDyIbR/ +uXabGLz4Kt/iFa3X028qJAk7AOJRcPcLqAKr6c6ZUH5DrzT/uFmYiy39leddnmqos7RyEyjsNK+5 +pXsg0ijRcbCTvKzRq6IOu1tZj6gWDxnzCxxWDa/hB9TCllh3P+y2H5LS/RD+IvVoBluGqu35AvrJ +frRwuSWmsue5ZzU1/Sn+rL9TSvgWfiuorkcKdyROYBCJnSi0OsZhKIBFt89Fx+I59fyWzdZAY6EZ +JcBr+C2gI5YWqFhqniLkRNxE15qQf2obqfKk7UinPfwbQYDdaqL/7EcHc+KZnBT6eKKkzjmUEydN +jTzjHyPZJtiNScw6kDbPXbrdHvJDrxSiLeHest3pGaeO78ags+uFK6DZPTBLIyweuaJLsGXhwI7A +yRvBkmuLv/l4AprG9R9No7cZzhxyrA+7jUxpgldeYBi42SlFVycvXEYT2bXz2UVonZ05f+ApqR0E +rVU4xAQTOX9MfZ9WTBeBSlhV18pqb96x6acQ9YHmaZApsFL0Z0vlJtfDMH0UEF3fRj07Tn9f6kBz +xVIXMYTNPCxKccM58JiYJbSFr732mqZtqZsg8yuG0ka/zD3pMZPJOgKAluxRYhbywSwD6Cfb1ZUD ++Rwm1kgE3ooqP8ZK/oQFlPSE2J5Fw1jEJhfAATIdD2GOvEwUzorb+266nYXlPYjS91CwcnPg5QDq +n0otPFovgComCEwkhigDxS2FA6k5aDijuNqW0Yrkq/hF4YL/3XCjhE4Q322IFesEGWeAnVWuixJq +kl2mF9XqJD1G+v8Zaw9HNK6tIQk+n3DxnUEZILmDb/zn7ddlUpTNf18XS3Ba7KVHFRcwteW661rI +TWqiZelDpw+9/zhkjIaIPvqZ0NQBtbsB/HHEu4IdnK0yVETF3TM7GuBOwRIlZpsEnU6bt8J+l37X +8y/zLykFmF9sTAR8dSYS016W27PI9YGU7YboSmR3xXEKnkiLE4k2IHENG4eYrdkHPUMZRvJHymEK +5n4AZiLvFuLE6YANhpq6LIzmnBHgcTLW2TQsJyNF2vhEAX8W5dUVFqzBYOI6RJYwrgWa5VB9qTet +d/tM2sCxth+a74otcM++n8mZBICZxdEXtw2FY2kIOQOJkqqNgMIwD9Wt85b0g68wKCcGVj0SD7sK +bD3twCpsFWpWlSGYwnHyT1gOdCddNhggbyvpXkyyAdxgR596MfEWWtI8jXhEYoZwuCI8kwHRn4vR +XCmcpuWS2ew5abX0w67QMS4m7TZjweE0DZMNyj5RMX691tbF5Wl9Kqirb3ou9hlPuAEUrJsFCbt7 +rBBiGl79GNr1SzE4x0zxF2WXWud/J73S8SLkD8tqbKi+036wXQzR2swDRlCqNJggsORW/AXwtJLL +ZeuLsVajgp88irworkhmZqYAagQ2+Hd4+jOD4bNVVaS7/gVMaZ0q/cj4uN3tZNp11hWO7ZZBSCwr +FeIFeHsLbqnZoCmGOSkbIx6z+wv5CS0gMdrxehgQTPRo+z8zKbYA4n+XelFlH3gTLNKEfTr2eOTq +UI7i8Ah6u6FGKjxx7XYrQN5uo2JSbFn0qt53pgf5w6/JlCejZdgHwMWJ9d0IG7eSHK8q9gNomAGz +byMLGPnmXbPhgUBBUwY6b71fQ5OrIQC63fuYn3QRtNwiSR1/BO5ygOTl5/IHvVrBjiVgnjdM9u4w +A27p7JNwbDcNPK+S1I5XUB2ijBDGUpDLyKoDAlxsqz74Bh8LZPgPC+XorECDqyCIrFPmzOIuTLm5 +V6tUCp8oistA023SusgInNmFOhWSjJDP67t4x2INVrv0Hf0YsnIxyJfZ/mRvfbSL8Mmp2/rh6C/+ +2rPi7uYWjfTcRRch7FCDeMk/S84F3pQnNWaAjS1hgrB5uHqw1QLQNaKNDZk0gcZxXdFSRmhehDqO +0UrD9+DzxyaOOkrkf4bv1ocpL7JXhehfKlXnUWBcmOF0ujCOO51J4m0iOj41F7HkLy7NMlCgPKTe +N+0nVsE3E8og7qhc3sXnuSLf7tSkXdhvBcCp8BTru5CXPfFj/FGUEmULJORvGtG492yF5SWu9AmQ +xbg1JEaeOkMQcLMkfsMAW6fJ/XHwKw5l59WCXQ87pezF5jWIozs99ISk9Nijm8Ok70Ig+HKQ3bBB +CKNpn3p1/u1dinpEUnlFV6Pfjfa3i8CpK8y6zrzMYbThVKRqQKOKPEWNVi0QSVvGoUVl98BXMPVK +6QPvHDuKQpoaUjsqmBH/mSvN6cw+mJJkm4NKII+SP7eSM04YADmhV7urpR2aA2Ten3jyaLxRqaGa +wnu4tzj6iiJWHyNxQQs2BuoqKxh+XjgkI52fKJmFktKHGWs1lQkMYrPcAfQs2nfITO4H1P2Dx8Yo +FvGNqtS2OVBjE3mukTH+lN2HESxPHPbazJ8U45igABE6p4fPNrXLvyiWn5qTkSI8O7byJpxs4pqk +XQ+NnPq35zps5dzl3w8gwn8wIA2etLmbxwkUEkACjuDwC4HzJ9B4kEoE+IV9i66KRTi/YP8Xqnd6 +asmdGI2wOL3bFiVD31Ndc30/j7tHd0V9xbphvrHAo6TfltJNAz7Gjo5PbCskMR3KfjS8Kvgl3o9k +YR4URKlzjSJdwYEGBLznIIVtAQFkHNNTBRwhY3PZuBTFXG6ckNiiAK+m/I96fPdsu2S0PCE3wnGx +jBOzILalL6tkCEkeuF/kzc2T7wdKnoa0KkTqUy+dq++Y90CKttfnhVjhz262jkEKRCdopbvMEkQZ +sViD9dfEDlyQRUYYh6G11NxLFOFpTGr9nH/j7QRoA/hcuCl+PL37ehppYDeAo3dY52nZzqcT7RjD +zybGfIB87Zw3za6f0rTFLep7k5H+IHRIMAEW8SMNvijN3isQgKV/xxzaAHikRQHdKjVCOPM+gq9P +WxF50YMkZV4EBR6q6s/0XFqXqee4DqE7zwS/V7zu6w7fny7nJ4M1/CZwm48tMoMgdh/HB2OlGjU+ +qgAhccPgqINKDTpV8xL/RbzCzAyhi3/S569/sD/GDZzXMLVsl5qdfLHFWkFVZprc6PzJdGu1SG8B +MLOx9JHFd+U8yRy5gqRdsz72GG6p8agjZSmy0Edlzs9gv91I1hQY8OmRXYpIv8xMqIj1JHkU7myy +SKrq9T8P4NdyY4GNKKlplnmUgmVQUamdgAGkQrYf+uefDYOHRjbQCZs6yL/u2Zb07rh+KPEBiHuX +OxQHQQbIII9Xu5YNEpAB2v7d0YxThWZa6OFFWh+IIrmt9UKENGabPe/YM4eaYGSZxajjHxLAdjEW +sAtgXjEG2fdvkCR9u+VcJiAWYnodcv2axq86uln3FjUyt2F/oMIZTvuBeI0fKENulMc9iH9AlK7P +uSde4sf3J2NGfRJKb+dGM8BIkT9CDo7j9mcq3Bry1KrNbkoa9dlNndzCFv/TzHWM/nfiXhwveh/0 +61tjJ6Mgipg/KezafNMHow4IL0OygVhtXKH6HY3Z1G9zlEpM/4fW7WAohH7gUI1o85e1f+2Hajba +xXxRASf5gxWYVG8Gtn+Qdy68bIVgB6wHn5FNE4aW73vCUJAk8tbpQzW+x2Dom/sX1alpmUK2Jcj5 +GIzUvqEeTGYXciIdgE+gEZOhxo5BPg9usy8MnQzus/KbOWLvgLMj+qA33pWkP11kONShrsqMBxJY +yyhq3Izqs6ZIYhk+onbf2qkvd72/in19h0oJayEAmNKsrG46wsGqRkL3rq8iDGM6K+tmwN/rIN+6 +EjVp/63bqjyQ4qoYHlRVIWoZlHHYIRWXv9F+10HHsAKczioUmmKg5J1Bjl+ds0QFj47u4hNmzIBS +vC3yGjdKmsmD3VZFX6TZ3QbtwAJOgafoKEMu9LB3Kaxr2cQqqo/quqbNxJnIHp4Ua06BdIJmzWCq +5eq6j79wrThNwHdsoumIjPn+10WwvTLjXvvC5vi5I1Qhw4QdkW6NIlwQkMPL342AqQh70IPMNpQH +yuOR6wBpVR7/8GaO/sutvKI3ip1uF89+UdwOm4JS6Bzplyk+qHYO1qI9XXoNHaMdq/m04gT6nDTb +3tzZDxeO2leOHGdjK0HL3uEzOqAc9TXGOchED+bLXjv/hGr1RsTEkEr0/RUrSJ6D/AO3GanaPUZ6 +Jj+J8Oq7qSQ3nqkbOLglKpUA3RYGv0rqXTtFTBd0t3VZSTh6v4FwZ22rMQPukHBbFq1KjzWulDCw +07uV8qGcs7ksRPGHVp/T43kScfRhyqYJsNS8rujb2Zd3i9l0+1GfWMz15dL4fbNrMU7QQo0NeMCB +wKmFwmw3SfKZU65d1riyzkV/ZgJvSyjbj53FfYVHW8ItglKvoyGXuSSQ0wenK04nphDIUA3y+36o +0YTy1PjlKR0U2q+PBVVrR3afr/exXsas9BtEYiKr8aOSVMaSAlX91URDvhS73+KYukV5UfwXIq1l +spl7N006PCRhkG6DTDj/MRX2GFmM5SMJpvupAjjN7yxvtdVF14OsCry+Pbl3KbDG9okh94isVoPi +SlS1Rfs7ydbUOKmHYi0zgympTteyMuNDzw6RFapAoE/BWPkkROxlT4z8wH1ESdCWUXeEfELDM0yx +C8wLcz5w7rEc/+A/AsW+Sc90/7T4DdMJx0EcFSVAGDKiJ1WX6Ui5U+LMh6UBMWjA47tD5s3MVs6B +rI2ygHDwmROYSn7ygenDv3Hcz/y+Ecp+mEs0nF1YIsz7O9xTx+biu+IG4p1VpgGYZOToOuOHTsRB +oP/pkiBIeQxBEUdrPuLQJLST2ZkYswL5rd/eb2zWOiaNu9fEgDMgZtGBeWoCvEYAIsbPlnV0zLfC +oauH3Ma+93DRgTGmUbSR/fHwURstLqawOdFrXGZiB6YOalxJeODhq9UR+lpzGxpNMdVWeJukV/Gv +m1QzAzUdjLMyubDRBs1AcSov3ZLITuy00NYAae7ILIzAZMreXmNNCks0Aov17SmJRBlo8K7wnNfU +dTZ5BC6D2CG06x/pdsFm/Vp1r2Hb3LcdXi2hpXzRQgIWJdk9Sdli/9dh6uVgyTWazK4RpQMcHt/b +geQlfFDG3zp63kKwgVu71FSyELQTkG6+8iXiUtO7rEA1Kn2QNmo3k05TlqfFN3njv+8UiGXLwefm +XaA5kvzhX/eoGdneFzkmC4hPQzM5JnHi5/v57tswJkvIueg0zOvEDWJAe6KN1JCZyh2KFuhBKK5d +9Sp8vAHL7AX4Eqvh/fBj1vbsK6edOXyzmPbKC1m/tlnUl+P/8A3ZFKcljSMuG9WMe1Iczk4HJ88c +talHFqf+0dOhVdEQtLVnDSVilMgLcid5wsFL0Cs8cm9LO7q9s9IMS2qbTA2S+BbxwgE3yXxW+h7N +4HbZHHI+k2D+qccv+FeCkTviiArkxfpMhuMXDqmlgsxyrzOqdSdVQOKrFneAeyD9rV4LUXoflDZ9 +wt7zfzWAhNfqL+tLJsO9B9Nt98lWed+QTPXFbUZsOcHAkres2AzZGCEZbhPGFPSYlGeC3Rg1GIf0 +B5K5tApcs64NKFIMlMADrqGFYgNCzXY1wO4ejDFXUzqK6GNbw6U9jAJ5SanwrvJqQgOyZ+hD2Kmg +DD6bKBrve7gHrLO3K0opaw6d+YK4XjZ4RXHdmFXSmm+fgtXtFABiOVwQaH2yaB8sTfUaF2PE5zpd +d5wV+BiEGIM1Vm8cuACofDNUCkxQLri8MUnZrKqYgAZJOy9q0jkCFOhuEz0iSwsRcYU7BQnEZyON +6DRDynZ6n1wLnIn4Td5y9fhwOdcjmg2LY748EYtu1u4b+egSf//Ojh7+0XQ+KD9xyelHUkNnLUr7 +pUNoEj5TRJ9rFcf7tCKDxC9ctSCyAJweGRoG3PnCL1whIYgKNnPiM4oKBXAcGuYsf57K+ekHLw45 +FLGxCFMHhmG8F2mdPObgCI1qwkdmCwgJ8rcLCjj5RjapZDiVah8QCH1ROfjvu/GtwHYsLTheHjqz +d8mOdHYxdYsYlqO+v3WZwSlSmdeSf7m7bcxY+EMSiA1CWBpN3tHJx1Eo9QnnLI7UoxTe/vh6oOPL +FIj/rSdPatbjIJls5xFis66jN+KBXgRNTkmrtZS++Tzqtp6aTJWb5f8drJzBWBNk67bVO5WQ/KP8 +YvpYfzE0iqK+wS6oLntMfuZOSHCZb57FFgJHwoVDObY6DqQTQe9eW5212LybdjuIYndwii6btEfD +jIdkL8C/V+l9+57V3UVclY5KyBaO6FLXUEo688hY/LHhOLAoBL7IHdwqvZnulOKeqRCJWpWLwyJE +e7xVJKi+XVgAQ1E09VPiuIWfHlhwn8XaKVlrqEmGimP+LV3MQnjjCmtac9Sq97GdZUezA6RMl/1G +z4laJYCWWmhrXuBXRoWx2dkkLtC5XMKmbm3MKeVD5rLPl+AZ+FyoJGghrGQmnSPODGPeSBlmJRxx +Dy9ZiPFnVkRKzNvvWuyX6+GOWYOf4jS78UfCkb7eX4SOKmNvg6+B6LwcbEQcmZPvPPdnPmSo0YJE +D0Ehz5tjUO57rY0DXZcdHdbFE/N/7QDI5kbrNCaRVJGHDSoxPr99BBPZKAtghQUdmHgTG0RfFI6h +7iZtpwO9wkFFHFqCGQCsOfbq/98WaRGnXE836dqctXPx4gpe6JuBVnYLLP6+r2W+1fiCfH3w+2Qn +C4ZexjNC+nVVjr7goLns3syWhCId/e1c5Ax6utjICmSJ6bRCHMbMZylL9ReDLw0oT7Gemb3h63RU +le2zzkziEkEy0cuLhZ9nglaTtbrShekHsKdozlKzurs0oGy9vvMhk3N4RZRabylTqcWQehqPClhw +w/bpx8sgFZGRzdjHdsd0xq9YIz4n+V+HcNFhqipBxKFsGBWFVL5TL5q2E2hsrSEMLH89loXL7d+E +z0dfHsU2e2TZzp3iw96ndE75uMCE6EABWBAMJN4y1lYWBWsdeso8Uw2Xt30euevXJ5ov5yVmAJb2 +2v4UhaqMen7r1NTc0VTUdzu0v66qg1OSXdqdVghRmCgY0Dj++6gZETiDEycd/1+POZ0wcGPxGeGY +THQtV8ZJusfp0S9B2d7uMW/TYbkuno2QVuBjN6r2d3h+J9xWap8s0SbpRd4DAfnjfnUJeSMT3XLN +dlaa6JyxM6sn4+9LelZk8QvVYK5eEghxoUbuLLYdVd8kZnNmRle5xJpr/zvpiYFIahB2jHCwrgiH +1Dge+XSWaQX1r1pkAF34Uc92MK8fxi/02hyxTFGGjaVNgxDy+bQ+Y+0z3IgiDIz7iMGtFXDCBKF0 +5b2GLqTrj37T6gWUYxfZhd1gHnhhKNHZI4h/yE+DRbKXSbpw4GDRFFC3+wm6LSP2WlloS/xdGNCv +H2UrjpVvWLj5iWlbaMU3j2MyiIogpGClHHCAmBiYAFKznbBzlnRVjr3334LXqIhHeWgQWvkYwEPE +q8+GWc6HtixFPDOUJ3THDy1GbT3kS2Rtfdx6KDhdDpDamIoqA363fHVcWC/SuDOQHUKvtk7nbSUc +xGWsqhZJi95lBFCD2/eKQyXyG2lqnWy/XmSIqOW6B/aFFlUGb4jDqZQnLjYb6BQ9YCoSxHoZlNhr +cfGibpVkAGe0bsubFkCy0u3UJWRHAvlKPipyjGXiIO++VESFZbS1D5U97a5NR6F1vcMVdhaVA0IW +v0sBrLxSKIFtm9P8U9Ndpp51O6aA1Hi+kCE0dpO17SFJZspF7A2XpDT6QnuuGoFR5tcURpK2819q +Q+zr+TEtClqZvq2WjD7YXmhyxAZNSZ/eY0t/hx2I0agn0KQ/tkwkm72w0eoMZ3c9cZKR2skX4g3e +GAdjEz/jKUrTY9Dt0i5iKRvxHAIzJVsTblPEDnEOn3KSeXISsD7LkgZnNn/ocO7ygLIYyR6RTlMT +BSFkmtqJdLWk3V5bxQ+60pehF7HJYY0U7bjvLZNxNVkhxXH2oWoSNcBfRwUYLJQh9aM9pMk3SK3V +KciM4v+hLHApUiUCnq2pwOUqg3+ZSkCr+zyuMDNQLTU0PLps5WRVZXgft1x7iaFP3SpfcBDyomgG +CINwO7cDKtytN+Xael0CU3PvDyTVdMXLAvbvi/QplOV3svABdJoI3ZGG113MvdGSrvn/ls2ZN2fm +vagIWYIHyGchGiaqrZBloMQQjA6u7C9KwPCKb36q3CCdoYA428DC947kJ8o7VC+DdyIpfQxgL1jr +Ui78W41j0G2MUT0nZjhLDpUJ2YABW2oQL2JX/k3FZhqXN/iPIMfx34ksbNooLP0oc9WkeoYeob1y +Yk1AYSI96NUBFLh4g0u6F94aRoShznZ50F7m9hjSql5opXW9cziWMVdhb902PmXtpmdVpObVVf+e +gfNvTfJvEQBiSa6E94ncVwRRvYVB+j3TbvxNS0w2Gqj3AOdvwt9dluL1uLzz3xP8qEjS68cLFAMf +5uq35NMo+NZ1O10Lx2RWc1qdOmrWYuot/10SNlIuYgYwSXtkRXsGWcFP4pvyN4T5T/O5Vi1TbPq3 +hxHIdrxkBlrwjcnCWZtPXGb4cvui5w4WHkBUnGm1+QR3YUlINET62dQrbQ7y1unalPadqqmRrBrV +zzTFjSmS+q/U8qCsZBpSx42qh6kYIHtm+pK9+FMiRyybN9HF1Jwr63mJQojHrs8Lsy/mS3lLMvIb +szvKLPuJdChlEho6cKS+UEYJX5ui14PzT3g/k8vVwcwAvKeQXQyAFI+CHiAI98Wbcfp7HsqUfTe1 +koY5xq47PpVUt8KsMREa7DGMZdM+AINq3qNaxNX4QrPGcYsOfDNJ59+5df9L4wQngWHKQhc9BZ79 +EKhCbVr0EuzU5+DJHXUrV+pXb5UkjtXYrNg4PN1zCgOyyUSP+ccnfQ+f4N3zP/wfdmRqdWVZ1sez +P1fpVps5nV20t+JBgoULq7UdR8jWRk6AytFWcChLXeAfF/5COyrApbw6SYzRD07CYhIcsb+0mtcN +p2fBEf0pQvWcxJ1emsQikTVqdgwPsYLkbSxPU0BmrrANVhhRZYw2iIbfvYVh8109PYc74j45llPD +lv/xKjWXcXwZ1VCOGKCNxZxEG/1lDizSLoZ1LizBpTr3I3zjaE05+vgEMWN2uyF7pxLluAkG7naW +LVQU6L+dbeBskoX4Zez4ake/FovPKfl4A+ourr6z8UTAphto7bp4uwQJgO9/qJY4Yb+1x/kolFU+ +BUAhxg2aZSvdXmudof9ZgN+KSlEMkCermoY/s1VkBwn8rPGi6fopR+ru6avYlr17gOo4xy441WjS +Fgt80D+CuAecHRimETN+CRy2Ms8v7nR87BvOtZUEwxDlva04V2Au/e6aw2qk7cgmqcR0a224XLGj +r26cxFINyJ+ScVvRjZhc8zxnOJMRRtuM+bKHdWk/xHnX+hMiY58V9t79aB9fhslTczsaY3yO9Tn7 +4x5wqknc+/bXEoZRVg8mrDZpvb9QPXW4LdywJ7eQTA9QYqdOrK+dvmPh/O8HyXMxvtGVOMzWOxj8 +EOSkei5hVtpGrddGXwyCK2JElABQWxZKtue9GR26MFPS5S/JFy3HRE8KSzCDpPy8Ent9yFLaj5Ni +bD6WBTW9laarfO8KyFHz8OhJEHYJxs8fC6kZB/iMsBmvb4z7ymn4Gm9boiuxaDgpTyZ1jxSAxI4D +PjLbfy2nanVW15B9BKdt4HRUNl0KGxJlZz7gtFKwXutyQUyszFXQBLllWjpaHKJyiGmop1e+hHiD +w6xLC1AF2vbBpShK12wIwdNoTe7lJHnsavz2PZTYvT0ASMdEleLy2ZPvqr/HKB3CBPN/yXIDeJIZ +Q48lS/w3SYxti6kOrUdDkZ0FSzn60bZGuXlPG7NclXysVX/JWGUN5F+ljPXj3NFGpanGIo8k5f6y +FZ6HhvxRhUhBhphkHJsLz9bXDkSRlNrgZP98I0BXMPIUakVrZbp3gFw8IzDaH91cEnLwPFIEUQvN +JugOv/VjL2757gh2taOO/VF1YX8Nc4mZv/fqrg3MOWIyYHIrW8VQBpcASlNLKCfVQtvaUekzfUx1 +QWw4HE9/0Ih/uGFJ7RC/HAGe2ZtCxh2ZOseIw9NDXp3OBszpijddbRu3u3tQ/aXXEP+5W/i06eUq +J0Na+Yfq5W3vVyOc3RR/X0LFqwDijoyNbd/ZcAWMrAcREcIwOonGtmxfBX+cWVzaoJrdISp4clCn +z3jH6BwwrOC40ZgTAa8unaDELyFH73uALzz0vnvj2jzh61Ul/jrTkjFFN85eaalFaAZQjoIFTcZp +sol9bgWbsgvSwJifgPuPf/2dV6dtSNqBEcJtmkgiCziFo35mzdi6CBb2DXQsCCx1x5ln+lX3Sfjg +XfROHWKCXFX5oMVt4I216rPO2e7oy8xXWmO2YfovI2bfgFOArXyPlXwM3+piuY/LBvTA8aO9A8HR +mX+EzHyNHUuH5vWHUpHm+tMy0FwLTHQTTa7I2K2IOyd0QP/zq+HZ9Js/4KNbQDOaIRwMlvrq+L0r +fMQ5hpmQgOosbb6/Fzbo923DVA2YmL5n/oh8G8SSdctnpvAmvYmLg3RPVdrcE3UcDdcINmxgWp6Y +Ak+nc7M+/AeZPF056T0mRPju05c4WhrOmW8jgFV++4JDpxNC02C3QPVrIMo+tyY5VT3iJaWrH7M/ +528GgVIDutk1CLxxB0fa1sIRwHgbB6nB+1nlmOkaTiRGMm2ivfR0IqmN9QmtJCjHiWbey6Jql10P +tKIS3ZSYJLnWqnZI8ePZNUGcYsZhw3NODEo9gFWNSplzXcN103VtdwyX5k1jEgrZudqTzrFPFKey +Uce6Ytx6acbRG63aEulE86kJt84td9PZc693gA8k9jr/s8buuXHsm6BfjPDORzdcSNd+kjfA0ApN +OmwgHdq2v2dVtqTFDbr6vR4GohjE5sJkuqZ/Ahpf/koZTpjBG/lD/srPi0hVuC9IVNEiRJZvSj5O +CBdwsoupCf/gKBRwOLFnaw+VG5+sc5RFLLIUCnzyDMfU3wouymaOeMGYR0f5kD7lUc0y71giyywA +xCFpMSurGyQRTV02K3xt550XX8VEZBmFTtcwKQQ7RjUvChHuZFjsKLvqCcBJQ6oWzJSBQFSM0Yu5 +fm1XiwTLX5ERh5Yhc2pagsjAXhiWIg68Mil3JOd7ztLPkCzavar4v+18pCUIihTiG1BL0OlXgUi0 +UxY3dYKjGGe5Ep6VZgs+VuNX/ZBR3sI617RtWfgu+dapIZGHxyM192vI8Ks25yYHaMuBeaGTwutU +JKdWgyMBm4aXEU6cNgKjbhV/FvuNx1oKGKbX7QTJgzotALS5LtfxYMbg/GQJkFzDmKgPCRJIYt73 +Culx+HRKilLc4IWzbPnFSCH3Q9g0WC7hoi0vPd0YYwUUL1d8RNhvg8zhoQC8wyW5egJA//82Ywwv +RW0iKorskmJiuq1LCkrXcovn/xIIEnPVqQcQNln0DSKrYGQGr7WEqKQxTT5VVRrVA6HPgLmUNgC5 ++/Kdgd8vpZZ5YDViWQY5x8qnknv11PZv1TS/qHLD/2Affc6ZFz9+5Txq9Kmo3VGRPqjC+r6b0r2L +f+RhTFr+IPLgPKVLJKOhx8FXpdDnScr/uKvOI/3shUty12BPqv38aYIOgiQnRdA4+8cEpVCR/m2a +uTbJ7ksOXFl9UpBLRAZO5vDsFI6diDoofzM6lwPadMeCibZOdXeEDl6Dk134n5oFszETapmfISaE +EMvQ+40/BAZaYJDJ6iZJOAvzaWlM8+GkSzw7amqyKor0eBnCnLMf5YHKqqukdEo/PA04aB1jTO1Y +UID2IJOShTL7mvw5C5q3uZYKlJ01jCBuiBi0gnzTPXiKrv/lvmJyK34UGa5J+rCa7kjJFW84jx3p +URvBLFa0zp9f/s0XHptwIw45+jLeREkYerLaaOb9QpaQuPtwDLxULI6L0TEHGWhPrWTKa+jGYyS3 +swt+eY/lDhGFAPBonP7KiXflXGUb94ObUwgIwGcjsc+H7eUbk1ZVPKusCL4AXbC7HvddjVkQsyCL +34VJn0SW5n6w3K/VQndNoQYju0Dem1To5SZEeiJScCOYGFJYkLP8tEy+GGP5M7+W5Np8N0PcYu+s +Qwa3lMDtGWnfectupTB98yEzmCV2Y7LYFESOVkwvCaTCiF7NHykymBteNYKua6o8M6pGSfzKf+HV +yQRy8KvT5wc9f0CiW3J8MCyzg+56o/vgQef0A+1hSczqVzlkJ9ihkzsxYHSRZutFoSF1x9v9sdYC +d4AJcHIbKu8MdnbIGUX+1dawGLeOaNGoUU/GT6OGklQbkSc7fu06enFrIc6969PSEaZUhwO/fSSU +L5i/b3/Ux+fNtIgtCQyQZorak07B6sX4Sd97lDxQeidn3AOJfe2xODWfP2fOvPv/zT3X1S9ux0CC +dx+yRsjtqO0PDlkmBL+6Bc506ppvoCBwUTogTgNZYPANAuQahAkXEf1g7BXiliIkecxQa5cfyKwx +lELn0Mvb3K+yTR/TjNaoNo5DJ7EYmAagOA38irA+wBvUQOkje0Jj03Y2do2JhgV9BjevWqOqApYh +6UJUMjWxsjrL9qt6GbNzgnhXL3SDHNsllAqQukfQ0nuI0lDyLO+drEKr99xL8MXnuV5xVjuGTKCV +uukpf/YjspoVkIw2xKWqPRI1pQMLb9cFX0CN8MUD3ynOwFgonxriSywF1mKsA1zvYmG5inKlAYU0 +n2BfeS5/R6xKXSuV1bXphEduIFcYOMa1DL8Zsx9JGIVLZel/nKHISDJYhTnc0IrGjJ9id+f006aL +IdomZ7U4YaFargYmSGq4DtqLldFR7b+x92WtewF5axhz2wYbRWyqmzg1ZXkdtwsMv98DVO3aHr1G +X0qsWHoCett3GZlFtaBZxfsNr3gA55t99QsYwu6sLxX1W70vi8fMmIWwvpuNv64KkfL/m63qBmeU +Nj3RGd9hc7gwLioT8the6jYCPENh3VRoi0ufMEZxmuNIA68knVEsE11Q6ZTrfRl4ujALVPRENxhF +ILKNoYqXaEMk6pSN55GMbMlIz48k+CpKYkhAY8SPOkWHOa/PmTr7aVVSOdYsBayBe6sWcRy2kRMk +jksKn4hcd1NK4xMZ/e9wU5NcwuYHucLnDqb6laaC1iz8/Uo4U06eXm1VA+EL16OB0Yr6RSZ9Yaa7 +rsMDhOO0fwCgC7/Vnom1Gm5VUXL21kAF2XkENXGaIyvlet94R+yi2jXFQt38/L8H2ZNDE8Ubys6h +3HbaATA8isJGelvyHWdYvgy7hjWn3SjcMW6Whk5RiJgdomvOlmADECZNuKLYZxCe0EFPyJNx6mLa +OuY1A40J78smG+/V41YDbXDyDR+Xc3wQq5gqCVa79onoTH2taMY6umKuqcMsBDwNaIOpsxcIUGtG +tqdmp26C/YoGQdcGCGBdRsiYTjBmYf8MPCdvkS4QuuOccSicCxedlogj3n2sVBNhV4vuMqE1be2D +9wCDmHjj1wwjIpWWEVFvHJVR1XYyIOJt9cxl3YXtm4++PbMG6YpwSZ+P1cf6dKKQWJcHiCUU/2wZ +YSds70D5QqnOEuS6PapkCvUOighlb1FZ8KH90wISYcdpcdbiFP55uutEdeWGPmuq7VGJ9FvxLXil +hN+M37pr/X0is1FcrRx/ICKtd2cy+QGZnJPNQBftQpTTBTTFJozjtbmJzREGJjoznpIUC3g8Roku +5gKYyKqAtZ4zYj0HbdTxc08BjAsmMLdmg+DBxh8fTmr/yhr4ipQA+2JoRx69TCIHOppRV8ozrrNu +MG0MqDjSXEXP5mHoVEtUY9gH5p5rGsLSZbyCLld3hmQd91ug1FOBmFTknSgi4JzO7Y8LcgHt+ISQ +wAFO/0Pp86o6VnfTRNtknP5fvprXwd5MkFG2ZKq/hsKAhsfNhVwn6DemxjxYqPaek4Y+9mTJOJPN +u5SRWqk8T4I2BVj4forNNj4mCm5JG6GqdgTJ8ok4+1+iEi/ExpXx/A+n+gRezysvJYgwIMlLSFSH +3bKU0lq7q9mBOZ/MvHQjP4HdT52VU3g+a9RMFaMfb07rMp3/DOjmKKGQhBWGXOviSpTKVmcsYnAv +my5+j7+uqaedh2k7BQ+ATz26nP2AnaZ6l1mHv7/OBajuUCSumoq3vXzhm/9GBgO2UPeLJ0IdWot7 +0Jjoo9yb8I6Ooegpm8RFEk7PbKI0EhZVjOKIUPMNjLzvzycASUxMqA7q9I2jGGYpcsrEB39Tono6 +oRZ0ETy6Quf6Jm5F3I0Q6cZxUa/n3SkhWetOCKFGR5J2f3a+3YvKOe2PPcjdOxYybxdb9YBuYMDE +6mLLOiFWBx2OPwr0VOtmr1YvvsRJXgAJc7YN9FI0cRIW87nVe2HVjJY50ROEspVVYyTC6tYKEkxj +y4WzSUuxvNFbyJq1EiDi4BNAEnRt4Zzeqln48O2cqjDQj274okDdxF8TbuwTral/iW0D8P+XfXtV +0bnLV+aInyNPS8FG2Uxe/MfwMuLTvdxjivSrZ3ijy3z7lcjwg9AtL8z9avp1TR+ijqHbpCX4usyZ +kXs4+p0yD0gKmc2wV3whO4Kl/NPlO+Qw20xyG4AF2TBt8KSMIZxjIcYoiH4lnfGjrWIT0iSIpG/q +Az72eQaKECln9ejg98L0dYRn+v2qAm182GgU2kuVw4Mn6yMHaJ9XO7vq6mqrcbjT/qjEmDiEJPTG +cnsS+yr6vatQvBrGcJSBGbdheTIKrgkZZWvyLi7JZume2047LCobicAH61TM7FhNQ6/y463eHcXx +yThLDEn5WKpg1H3/iowpTUa/ilyEB1bCngNusTktv6LMn6CYOr+c0mB6F3LF6J5TIr+Inv8mEGCC +LfW52cXFGaA3sJPWv70WF4VeN9sunfGqcTJ5UluALVeMN5jrV1Hvq2xEzZ+oLPL7sESngq+VdqoC +MLq8BYssvvlcLh9A9QuGHCeS0IsSLJHgUSeAmx/9W07J4EbNwEsKLkj9rhw2sTadK/T81Bozlqn2 +HSHvztpaJy72rvVP5EMXEdVHoTCmVUfN32eP+5ePcaZ9NumHkippH5dGCjyLExSzmPha5PctfdHs +Hf8o2spjeQvjHlDSW0G+/X6bu4rKJp7O/Yfk4qvaGg/GVDkKCOXFS+qhJ1L2bvNgZA+U7j6tX0+y +vruCCLhsKjyPkT/2pOb+KW9m+N/cQ0sWkNdZ/6AmVIrsQoXtCZUGRH3E+v1BFaozc4ZA1DVt6Rni +gjrL29ThrS/h3lj1950SuCENt8dZbsapNvWjuoeJ1QTH4m0ye/7CsmiaPKSTVyYb5unaAXaD0gGC +GOjL5zhiLLC0N/Uepp8FJRu3bZ2R6BUC+dgo0SHAq79eSQWmm7X4oG3WiNaVtVOW1r7ZDgZdHlRE +LGLGJDMrTZxdqmzt+rpQJ9Z2jBh1ZqN0C2xXkadf+tZXEurV0+/7pPLxVgXYwd+Fqk2D377tjEbG +H6pvwDI2PysQxLARNlHPW7y7XIz6419TBkLkweTx66yi+vc7hkDaCv5RMCnOKKyIYYQIHoo6zuxy +yh7y0/2b2L39hn67V5+ox2N5FsqE6KqfEIHf/H2ogvcp4KngorBIhGm9TEQUPLQc0iwKcb8gu+ST +cqCG8tlPkLlQyp4eu/TAJNAogSyqUfbzCys7/G9pd4zNqTxNJOLM+TxmsfPZ3bLgc+tEatySaoYZ +JFu559mt4+nnA5eL1zBSEJJcQJLMMtDKIFd1f6RSUynVI8ewGUzM85y9efQb3kTCgktrgZ2SdMRd +JDPCTDO15yGDz0UQsJQNutgKZrdg+UUlFjcnjzpNG8qYTrpEjhJD6JtoCSBvbN6r5HMKl956xlln +0TtW4Vh332C90je/vwpfAKh7hrY9g8NJKU0xzyVTjVOAv2mHfcQQb0Bu3mRDInajRG1bC4LIMo1C +BDL5iNnx30sjslqvIXUyrj29ePElFhE5Cl7p4K/t04YuTzMfdXMtZ0+If4/HN3HCPMGnVg7xG9l2 +zJGntoHp22ECLly//BwKx9QnCVGBgQCnMgBSxYI4PM1s7ZOD93H7NVivFOQM7cdjjXOlcIOcaPDK +z/qDRxLop6/70KwtLs33/r9g4A4JtWufzEmWp8AGIHH5L2ueM/mITQ0TrqgFmFP7aNPd5LQDL5+4 +X6Wdol3Vjms8myiFt/5WybShdMfZBI/knYREDK6ycGFqcNdxuVyjsx93Co+OP9Ra2s8e13lTSGwh +2UWJTd76viMEEdmVIZ8tCFtBSZdXDVy/IaJrh/z/By/ybX68pZ44WqnlJIQxVeGGctXvS2NZm1sD +hyt+2mBqgeSwUUL9JS/4Yo0Za0rRo57iMCTAYXMmK6ET5NP5lM13Uijo2Z6Us48iQnwhHwri7Oum +5fxtlTP7md3ruKwl4ikHBsyNz8twxuo5ehFpS3x3Q9svaM7QBpEiVqL9VZjYVziljRAYFvWJXopJ +89goAf97A0e6fCnYVVMMchAIOZ8CByq3Vctg0ssjKmZU5UUJMwyNs/ITERd7CTbuStLcNA/Uq+fk +2UIxQFI7SMqJZRTviJYUc5NR5bvUcrlGoRzR8wD3idGFkmFrgamuohHjh1vjxTE5jClXWOVazP7G +2L3Xw8TQlxi6+CQjXpbIC6HPv4HylgnEm2Ry+r3a3wyy2B3S59kw7JtjOFqI9dak8dEWLgbpZcGO +X3UJHhoPQ2HmyCz843ZHxtJz3m/bEPeaXWbO8UJg9EouMhmFsw2TyeBGX907ycqv4HOkKYloE2WY +KkuxaaOXfjzEEZ6QRf2YN3pPf+4uzEC9Ew2l9gi37nByWbOXgSuRZ+TMDDgg1it+krcUSOjTnOGM +1iLAHJs9PyZNoTmzjKDzBrLgHEwH2WiWAgteDKQEZrt0GQatwGzX5xLVa8IfClTDDXegOew95E3o +tB79BZgsWsgBGMzfw1rfWU9A7mM5THSMeHEfrkqlFFu2/ztZBLldRI2BzVPOH/gwxkCyOlu1IZFJ +8rDHwE5j192o8Sz5NQgcOiSgdJ7ksmvoqISZclSqc68R62IcVHjztqEv8U3sQb72lodKL+XgbiBx +nQe/YruEOFFexAMh1Pm0zVBPnnYFFH8OxxOhzAR3T+Mi1G7l3uc46rokwonZRLIvPVAwL1uFI0Xb +8nZWoAFveHM6NbTCLkD2i0wt3shj3VjxiPhWL7yJBW3hY2XdUVJltscjuwOM/pnfTt03YEm1Lmin +Nr0TsfeTwxKFPq4NQSKvCrthri0RIZWjiXUOvHZSQLWcPwhKZ1Z6SFej9NV14zTAKyhx9ie0+Vsr ++7LhRv084c7Z1nYweHdU5o64iYHjSpeekCz16zq5umf+jrMmpUP5pdQqUvv3bmJof3KGX4me49mw +itgI8kfBrLzqW4ggRVUyTuNJ7wUgE9PSIWt3SjP0biffGZkE7zscd+My2V47cDZQaaj2Rtx1ZvAU +T0Boq5vRtmitcyIdnp/mH20cFWKCsebrRCXkB9o2euRTsciYonZnebwoWgc1y9ipELDYKsOTH12g +1ugx9z0v1wtoPVzR1HU2QUJyVEVbSU5qSVGciKGSG7j3hC2xEL6fpnFr2tynGx0GYSlatYfxEzFt +HLuSYs6+3RDRN8WHfyVU/OqyoJY5iZvCjExP2l3BFPvcuZboyl84VUF5qhy9NqAWQjux3byvHgnz +dqxSUKGq/c5fjJRMAxtFqEBC0/u1MtakZrJd2Ujuu2LM4Zf5SaJfjd308eCZNfxmzVGcCFVNAh3s +5+smbysEyZv+NrdOVFdVkkpxyWVRVvQv2l4GoyKA1eGGdt0RWxhXIoNcn+KscI4flZ5MF6DwXxQk +K2bkFcovNJD+zF4Zt1/H/O19Hi+DznEzzB9vY87DTL+rlLp9aHJuy2QsvwDj27QqBt0INoWArcFc +z8/vpjyrYcNVlV6K3CWHjS/I5jUZNUawL10l0EGQtET2If4DiInyT/LAwCnsu8nfNulGL/bWXCoT +wnmuvrW6yVwu+6aFg9IoWc3nxm5ASJg9G2P66MwiA0iPaBfm4JN5HhcDEAOUshtgIQ5ZNnQ7NEfg +zmfE+64dtjUqwd0T0yZrtpgmDKwqJGtkSlIAEsDYCbInM9H1scsIhlqkrr7Wy6CAVeEIPaTeQ0NQ +m3UtqmB4ROhngP2TwOQxO6n7KaQiDj5+E38cY6qYw0PJ2lrHX/f1JewRg7CpXZSYLSjzEZA2DU+N +Tuo9BDTESzfsOJX1B8wXbxJSDQjKTdtdHKgkXltH1xvVvfW03XGrkwPYAD4USv0RlUbhRGXnOqbC +/6BAVle905AT/nJUUnSAM15M38UhiR2bJipupGq36sH4aaW0Gqt6e7At/PEcmGXDCZkOokBofUDe +pWuTXLQE6hAn8dc/9e4GQiA/F2Y43Vw3NcDMWtNhgEQkY1UbpongnyqOYvdgZdNPugvo7t7A1hSH +K/fviCC5PiOgtlx9CG3oiIMsHyiuU2rJtA60KxIDaTSuUhKBiu9Z1fCjlzuZErwHwruxcMZtK2co +xINEo1km7Ug2Fw2mvlYF7RIpnkpQ6T5vTk5jHtIJ4KtIvI7wGjBhyPaOB++KFdk+vSh6GYLrHr6q +vL6fgl57cQ3QW/T6/TKYZeP2RyqGCImD6rbV7kdA7Sakg9UOS/xH0f+k6thLSV5BCKbdqydVlC3R +KcX4RFGavIwiyf11gkKlbVFsAQ8Yx1xOnfEASuj5GJ0M+r8po/GCuUT2jE1iYpTMM9NIycsXNDsi +tE6tBJ1vILSCqlSYZuU5QU0gMYYf7qpoGDKKv92GckCAQc2a/Kl3LsJykWp7iGu+WCafFKWBxwUl +lIAi+ojUCUSePZZBXpRvx9+EfpHX34B8DJ70uPP9cFxfWyQUTDbXxGGahFYSWlEXoyIgSLKb7ZKd +7blFmKTg1jJGRk5XFMqEDrfjoiqMXHIv35zn+82grLPH+0fnmmc7zR923VbpKsHAdSh0qXfdtBMZ +THodE946PjmZQm/woZHCtxrkXmMhpszm4bsGCVPCoEiDn+VjNVypUVEgFzELqkcL4qkWWi6kKlWp +uvaFm+doM6JTXi2VqU85JYP+zS9ezz7efzXVNNTuIUsuCAaV5IcjnvL3nv5GE1Uns1XrU3DIICU4 +vqUGdfWJPn6HuaZkbUA5t2oKQoTNuW6kCexhKdTqx4foUe4v2cYsoPJ8XqtZS2AjdU38H48PnEea +XRBKSWyLuAGYJf5Wi0+pSPGdPN6Z5yf4ZutZF3rwvH63X4qx2WDz9xoPbUoKSmr3G4M2wYMuEJ0E +NknOPxr7M9qIsS9P7YYJfx7mBjk9o3oJSe5AjJRv3MneKGFzFGxxGpWX68MOB0R+bERIxlrrb5zl +UCLtFIRSGRjHCLLWyyEHVDGQ2NjHRE+4uiNXk5MfVSmC2nPwU9z2Ooq7g6dgo1YVuug0obyb663/ +LvpYLxh2rkVjiIgKLsx3+jlusszNYCX87MxDEtFZTHlH4Ws5CY/6nY++HT8T695EoS+BhpH3Khhv +vV6wh6LBuQwhUgCpXucQCNTqymePkiVpMjEiPejDueYiu1zyQtlkoBclgiEinBjPO172pwzO0eIj +IacHPmRHyTG5wd6h0HQ6nDtiEos1RShtQbkNS/zFXQLt5TFkaICqlBfvFWUpBZyRGRKLjqpYa9OY +Xwt1+R8qp8dQWz6+kp3IB5cDj7vg39zUVMT7+NCYtjVv3m6xCF3bmD5K8tPPSMcriyOjHHNXwEZt +DpMGRnu4OJPKBlAuUJYcsXG+7JNOtXdg7FoKyJxS5sCxEVJa+tnEDBKqBYWdvu21dSpeRtarTSCu +/iJnk3VEzuojeYeQPN+vPAl5l0NMM7ayVVcGZVDJWMjY9L/x0a6Pqtv/z+wlkbAM389Y7+Krk+44 +txx6jO3DU2WcX+w1W3PMd9PCwAW4QLS8hZ7gXRbpPK2F1JE6AhP57EfqWWgYm7kPdeScYBW6HWmh +AcXhZv2NtNdE+VHSpvs6DL7zA9kLwtGJ+T5eAV3ksLCOKEd81AmlOsZzOkVpFsy6XhoMHvJYDQyJ +hH9KYaXyQSfExGYHrQdMhqQIy707ik+42nE4HQfkH8ASd6MZjbfJiTFxy1V6L+URDPHFg3IBMOzs +hfP3Gf9rSIULcdCGRsHECYqTwsCESKGCH7qww3a5prfCWdCIbBlzsSgIq+63CkPx9GQhkugqLUFU +ywi7d1qimXSqkDL0NdUAuBYy5PLuunkRXxI5/C6a2SJXuyNALItZP/wBSCJaJb8DLtSBxc9WtW5W +tq4NDD1ti9B6pdqR/BT989MvIE0Qdco6+Yug+cC/b+myP1vcLbjMZ9OED1Nda/LO8Xiqg0MShnuh +J3eN/BOwECfub2/YiirC3LSqVtuqkMvQnZNENBDV2Zh7/vilUNKvqcF2yboSu2UqYUIQr5lMMran +JSUIvl5p5OeWq8Fy5roLrpx4BUVQS6SCPjHlBhkkLUKKOIIxSW+fdzPaET+/hPCZpNcv/9mGrBvt +5D62NBHaXjTLo6XS2cuHjW7QJDxj1yRZ/Jh7QWv5x7m6yf2aYNTfdYnuIQUcuAYcI7p9bfZEpFw+ +KsCvBzKoJKVDVyh1gQ/0z94VIAhcrtbxIhJ3y6cCz/HluMLO/x2CoA8OTZTicxk/0cY+rHcXNHZ2 +wjHWwjElG3aju6n/fnzq3sUEoArvI84tpEJsYBZLcLLreCjhHBwmyJPv0e5oCHI5P3gCVJRGdyIe +eSjJ5qYoALS4fpgplZQESWT/9udiHUSW++Hm3wE9zsyB40ZUHlZVtdlkDwb6rg/feRBT1Hh5xXuu +tmAVKatAlfdLW+pAIuhD05ILe7SAJPHg0AWl24u0bUKypm97U1hUS2KeUYCv0H/hQvW7sbXgDP5o +0aNbM9FnnpaRvUC5KWKVIhMS/xQ/W/ygM3KIhnXidWgowkDjWia1wB8fpM1UqwQmhc5e2cP6lCvi +ztyKG8/xljW6SMqiAZICJMY06RMrl+Kuj0/bvNPlZ/VBud/2u8pZIQ/ns84sEHg9Mqjc2aLYPHR9 +RMdQ/X7h80u2uBo/zCsPGZAoIE4RvYhBEacRL1KA8pvrmGFo7G4vryTpOpGaA0dBkhV1ZDtN58tA +3mh2sTNzWaoNfLJcrbpupfisvpLe88aoB+ydrAqqkTOleZs2misyx3zuPtbh2v8eWZh72GgD9BCJ +UH9G2ewfN0FUDuju/NVNZJDoT5AXI4tOTAPUh8luYEO17lf+kpd6Yz9X3QUIT1NqV0o+0CilmRar +JWI/U1tiDLQ1RGI5cBwVCL0oP8TDk2wC2BJOP56Pv46hP+2bjt+0UVlWAPXfbo+4/z0nSWaA0EwU +Ju7vExBc+QmRjLAYPUv8EvtXAZ30Sv06WBFHN+IMuPCAesLyjLeucdNYUD8uRKza0bex8uS0ftJt +1zAzrlf2tQrUeTNUOY6LZoi9wSX246QFQd3MNwEEKLv3npKMUynTs3rI+4SBUlwINNwNiRwXVNBP +fyPn7uJlsSJP5WZpx2qRhmifjoBMUN5iz2fJwkETmuLcKiKRf+V/M006mpTJiRjI497WWHJCGiDi ++znvrnmKlHrDtlpRnoLZf1GeW5rvEA8Fe27IQdHFaPDJdEoPb6/YNbh3w2hskT9Chw6aw6cRECv1 +c+vPBMM0bigoOj/2gic1rozkEvSBPk92aDDDOZ5LrUBFjvx0CzPKddhYYKXKgCrGy8585wh4q+0i +rWF4JJD68D+xoIAq8ICAEiQ16goDdrMuZDi3Ij4bJwgNCEA6b339yRBHif9NKBVG63vZKMqYkH/F +bvdUjxLWhdpj+GtTbbSmeeww5IuCEJ6oGUAdPbcxMqTHcd2R7FMMerX94+LzvN5Yrrr4UJt0gh2N +8+N6VIXZ1W31SOAjrYMi6NWopJll72nicWi07xMfa6K4sn5YpXy7B/w6S5gpl2b7xLwYJXnnMcC4 +d5cy956rBsL/vlLDJXV7VPquk9dpdT2RmnHtz84l/V0LRM1lCfkftgmljJrQhc1Ls12r8CNQMk/g +Ji+kF0PfWBIZ6ALnf6PPiXWYfF99ZvzK1HUuDW4uEbXsTUgi2RLsF51hZJ4MOMwn8JPAvI+ONEnA +b7GC51y8N2NDi1GRbg7bqVeqjGwLcKwufRv9DGKT/6zw0kPBVNFNb9TfOa6c1v31hQIIG+yU4IWT +AdN1c5nwiTxzzK93UqOCbcVcImgWzzOYjS5RJYx6nNZPD5fZiv+iPmDnzs8PuH0pnZKjwOGDdkMx +JJeORJLP9/iU/2n1h5Avt0ukbJxdEkNTs5G7pKvGWGIL39gOnh0Bz9ZZIOaKoWcIeZ0UC437hFCA ++ni72o+RNmg2rFAVamHTF8rcLLA1jUx9lEHm2lNydOrWSgCdIdRB91Obww03SLAkyFC/SopSiKTm +YopNaRoG8PJz+uJgeHDdKJHjlhXFk1Jv1gbIW//QIw/Zw1kEvL8NuzaPKW7LNL0qEuN6XiiPY6xZ +STt6CbPoUmEI1a13Hd2gU10vtasX/NIAGcBhpcEkE1oc09IwH0VyXm1OtLyquP7z9OTGNY+/mjix +N8tqQ3IvlhpV8W/gCTLeMfqa50CsVUB12wYGxXocuSjBMcrtL/WUbRGKSMWFn9YU4ZoeA9GTJtlp +APOrt1+SOm4zFOsvDQOaHQuzkPsNo3OQGvL2pavsSaGDPnvp9aUDyKrN327+dSjesbmjLpbEQgDA +/Hny/KGEE23jpDjTgtJz1i/KROU33nZ165s2ASlFhuk5EifOyGjZtKVvSYRVezv8AOCrldB894Po +IwDTyHwbyh5J5nCsu3Enj2DNNipJwsjGun80vtGHCD8kzNhwhb75pm2//g/FHQ6PPhD8UcEOkV4+ +ySl8gFzFtAPnzJuMnEsUlrX3sg17aQ/3znKtDfTXhcE41Kb5i3b/cc2wrkTzSTNV5krXJ+GNrhhf +VCBJgO7simqi9YLMTlEyCtzo4XdxF2A7HTXS2Dv6C6WSK6VQc8PFjIborQcy8Nt2hA20IBIk5TbE +DwZjphD1ikuu+rTx6iteRxuXH1PkkflSwm/NinrCsuKMlrGS6Ayh/+LR0djoxO00aFp9n7HldlBh +dEaqVnfuXhYv9bhrjR3eec0S24EbIUg3kXZHMJqUg36Xmg9HCC7a4yXPf3oQ++EHHI36b/BEhHXy +HHrBq3T7Xu+i/mQ51Lb3XABVcs9fTzU14DdzFyRTfOTC8OIjPNlGkb7d7xeG4Ti4oS44UBhFZ+rm +weRT1aoYTpcBCOHMxaSpEZvE3TmYDQHeQthksxAcVluxsBz9RUiuTW2RF//lKFagPe+t5Vv/sbeF +zQNwhhd47Nx2jQ9QD66ZoqpCeG74AnZDAUxKDY/8KS6dbD1F3gEpPdo2Jgp5WPSCabJi6MLOiX9F +zDmvZCpTUXH/9VmHlQVUa6V1NIYFGfi8Orf5kd8m66TQnAnOoeTrCd5zZMfHB3GzL77zFW6qRKae +Ir06mh5LlExTszrJWYmMdK1+Nd9ccOSkfsuuii2nHAQK+ZtErdGOM6qelWhS6p14q1yzRidI3/qX +Ek/UrYxDxX4b7vRZB/hlglspfcrghtDaYnRf4N5pPrcNAedGpm72Sc+5nOKARngVYBTZFBlK4m70 +JKDcb25qEklai3hsWWv7+AO+FkwZSpXRgSspA2s2xt5HCacb2QTPhVovEyd5lOO8OentpjSDrYF2 +bfki7YV7kHbkGVdzvmhILKdXcOtXsOdJjpfNmjWrfCOy7/4f06Wp8Tf++Q/NeGCnm1U+LyC7xQua +FHGJ219yyvuHVjOcri8Jer4DwLquo7Lp5WTW7pV1dElL+VxVxj1J5rMATOdJDYonvtcqZ/JGhrxq +2Iy75PWiIkSwOAO5RMm60qxtuj8sCcG5BWIf9kcmvqqdgp+qqk6sL8rITRadMA9541NiOB7TuPZA +/Ga1d/TYN2QHbsFtOdZl7cAPSEiV6OzfjabRUVlIwbqzjhXgz5hrrr/BVldoq54Yed2GVx1ZwVjt +SVsTVjfT73oATGEv+I+YJ5F3nUUQpKWQHBoZRrUEZbB0VqVfIkt522goGAcR7MnMy7jqAVKpJM6o +mxaZ90UvHjVxKvp/bYUac2NeDxxWWXVhJoNdngQxiR9E+6kTEewLBWTFEfCo08+53BCN0XOoXJ23 +V4nkwiRv4WpUqhWDna8IwOWQVqUqNPgYKXNVpKTveNFBlpL4o5iSok5/sUVYWXFqdWFWjM46xmMP +d3HBgHiFpQlHEAD1vezWeWIjZpF+sf5CK72YhzzMAm0b1+9w+GOhoups3dgJcUetKNOox1XPlDSy +0l8DEGoUSnMksKWyE3leTSz+JvW1Rnhq/RrFHI+6l9fJji4VNhblL5zX8eday2z1cyB3GhFvC4CX +XyK9Sq8z4gKynji3GiiEr0wlGyUz81ir0XvWxxkBBxYtRiG+ZnxDbHeErV4ahI38WKXN2JiSki1k +iHBFNGg9DcfP8RDJGaEzHbuNnYqSBemqueshBQNTUz8jP5n6bw9TtF/5QqVGoXfkikwdYJF/CtyT +y8l6P145vYHbKTMu8Yolo8ex1bXR7MwomwW6E8n55ciMjguKnfyTnKH1w1GzXrs6XoXyG+ARwuKg +k4q/FAkSpyvtAkhrjJ2Z7qvBIt776Ze6NaCFAnVjtGYoEVRbBrBP/cSq/+3EpW5BB2G21L+L3XEC +YKVaQW3lX9BvJ1odop0KFIsxEhZMFs+r46nqobmvDZNI+x6ASePOV82FPYQhM8xcYvkQAWcUxBcL +gjt10MRfq8HP2wa+1wAIlg3kz5jnuVNIvdJz5iVSyjWAcsDEAkh1jaM0lkygHNC4kcpp47cenGZj +UZLRPK0fHubOKRq3cF05Cmnp5mP94MN/PLnLhLJ5xOSJZBohSgEQMHv7Kw4C2pnnSyKxghsM6nPp +YVTdKRh6u6E5dfW7Xj9jk7cZsc+eTSMcp6o/hDKr2g15aqXs+iA2iBD3hCrP0Q/eoF3/+res8+jO +YK2035pt3ZTRJkGHHUYLhnuEtXKArgMBJgToZhYpeLf9a2NMPDrBXKiS2Mler9mKhfhW5A2ednqE +VTnIqM14/FmEGfEhDYIlskMkXd2TYXjoFH/IVzLBytu9nTOSX8p7LP6CJvcAKFC5Mq+x5zZmggKF +vkxisqAHdvkwWUyLE/MK5e86W+iAOmAD+qLV1MVeGDzV+pAPgJT3Ffgvg4WoHc0gfXodosQ7UnmC +H9qs7ZNSOd4fdJlmOnE/7wx//fpC6FzQWkNc170b//VYRmulZ2BU8cpjzYurYpAl9Bl6pzULt11r +UON86W2whLyl0125iYERidNBI/vekYi6F14KZ3j5A7QkYe9d5k/TlMbFU1O5AKZlCa3AEUHYrs1V +zrTy8NlukjB0HSNtK2SSsdPdxYA5dmHbOFrYBWG2khOOw9FMjNebr8nAkwGPmj16LHFE/ko+UT+J +9BzhKh9hQB1PIVvmmPrOsbs/IkQYLqbnwjEE51U2J8vrxJa72jFN2BrJLG+fqJIbIIM+kRbv/7dr +y9N7qT1t/YMPj6bw3tqZsBI4070JuLN5P5ASCxIU3Y7QIiOVELgc/QG0Txe+7we3f61rUacpF8iY +FvQ2YMc85dXaBz8HLLc2LWl0Qc3sjfI6Oa8Tp82rZBJqiZ6BJ79FkXLUMgG1DIzXOGf827aHW5jZ +XEvdmyJQGmSjP19TMb6ZTnmsVOuGpQq+eoWfWdHeD7DLRqi53TvrIBDHs7J6EYs23tWWxCIRwTPs +Rh5pVY+gjNI2zE6XBMrImlpBLcGQ9d8fiGrYKDVYdGxYY9MGCJvoNCh6iiUKAjexTY57TgQoEExD +r7qTC+MvJeVbq/ZeYRy04361u15GsmhYFPuwwZu5pcF4S1mW1wJbo+TQUE125+4K+JMJ0ksv42j0 +OTYWTGOSSaR5lxqpp7JSIJw32NSPNFa/7yLhU38gAF1gnR22qJuHyr49LS6PFzFiIbA76dZKYA7r +zl8wgyR7zYMR2iiUexVrwSk43CEzGYZmKiuP2DgjpzR5yJIX1+q7dkH8lFcsAb/J3XGB2K7Nh92B +MiftJf039GL/+nowZ9PUpdjguICSwqkggOZl9o2WftSSGK5m+jFXLUmWxsk33RvvTFSMuom/zMHJ +7srWJOWIL5qotvSjlRBpElepGTaDCyfPkbijrOKifOP3eUC2ziNiT8clh5I2OTXOaekUWZhEtGJw +sTYzMKci6X2XQi3TCk+r0PMNRMovIh3nfLg443aA/4Qn71CoxDjqzMi8GLkEt+t4qAbRShpACSNx +JQDx/p6OZK4CJtPBcN+HXGg2SxtVX2Iger+ncpgrhCD8fof8mp7oIsHYb2ULoYWhBTMdNjuvPwIO +cGoKcErvavgEkKrsr4624PXbjvIQ74JgJTGOR/7zPuCvqERrDRSimJ4n8qeNLCQUHBwdBHvZdEWu +BsaPhcQiMEvZVFbfeBz4XdvMZLfeXw2ElDJ9qagXPk5nzmVn1YCTqCC2DNqyukDFt6B+rQmZRDd2 +gwx4ZNyWngn6djc3iAOpWTuEzjZIH5LLJQc0r4aJT6YA+hWMhlvMmg1BhGrwmkP/CxwLq/4Y9+Vh +sKFfj1I18uvtnDhepJYAWzBVkBYlSVaRSXdWOSRjCahyPji8nC94RU9xyI5YEPugbdR54Sy0qMXp +r5VLeOLqGYip91jA5eqcVu/xnCDd/+2XijOSNy9jtXCRpyIZKsHzed6YI9+sWpnjfq6nGJRPV/kg +DFy1Tan/dAVqHctaXDyyoIGFVCtRmn6nhmThXFPPufLt9wtFLTkGK06lENgRbzexJkZifRtakl4V +qqTdO+bGkY5CtR8lD/pTjA3qwWuMyGT0MSHFK73uZTMBh1QXrmGGfMu8I2UhliUSLq9sVGdNouVZ +dkmqMieVrLpfX/UUmo+/KFEteJR4LscZYO6x3flf4CHBX17BlFlqStbpCMUA29u1dJm8gz0a/ORX +JEmsqA+NGoNpyJq/jHsJz0wDOcLR/i/Gt9cTRJP6KM3P7emQ6ZycqvX0NRXXjY34ejI3ukbOT5bi +yvlqhvXvJ2W7l10KW4jKnllWKtI+WZu1mmH+glpAOs1YmGFoURk20766hNC3NONO8tIDeKn9xQ4e +QzOjNflVoqr75M+JjzZkI/GzlwL8HukYPZXagxPx6B2mAKiJXMTx6hMNb7+121kEeqgBqsMzWWs6 +JdcXUY9QKBTzieMLljSyFHALA4/yy3WSxHF7/LlW+coXe2ciq89hFAD+9+U57qhj9qjLXCMR9OyW +PYpzQ9eT8qLvgYErfeyGl9JvHmLzDSMG34sU+525uOqxD847E72DvOvxOU+A1rkhkZy1UFvavA1P +ks+ZKeiILVqg/7MsKC3aziut3KqTJgB67btFPfxvWz+WvO5XxLMdwwV7QWzw7l6AFU55pdn+F4Q5 +nfnKtnJyp16LHpHt1fCbXnM3POfsDs/OAKxdC2vPrEnWy2T5YJZyAkUEDK+lDA8a1lU54OMeyYol +Q4tquXb+oHC5TkcVnCJKJzzDRi8GKTFGwm+7BjrXAnE1G1q+BWxvFq8w/+gzf0QHGX3owtaK8ubP +A5IQktPA1KgvV76IKwvMjPA/SwE+l+CFhNbKJscupsjMQ6o6fNurmed/oKYDL5kIq+lmN9J2vDBM +fAaNLbhljor1zphhiYnxTu5wRyzboqB4xdWkzp8Sic4jPkyvmB3hbT9mgleoXRIUFkWtZnumb0/H +jlp54HprQPtNbd6b0c7LHrdmMLLaXpNbQC2Vh756x4UsWbxZ0EvCGnGcpq52u0n50OCRZmex6JPh +ChTps9xsN6yZHwau7dHUdH7g/qGvcImEGUXmAjWalVDvyuA+fIEx1V5r5EVFnfIiLHOAv/BfdwPc +SIhrZxzXUXmKCPzV3+d5qV3Qm972Qt3pDq/L4v0I8T9QwYwCMqai4v5TqBTXujVr1lU0c6s6ZQCg +dG8dWNK8GrCXvTgnwRmVjtEsh+5Jms0q3IeOFfdymuw37cDS0NsinPIAM8AcCeu4gkfoEc6In+Jw +9pbCo6QEqszkSx79AZPBUOIklFpC7Glf1eMbitOBBYMBHqj69iQsUJf6rUZxth3vl87fjK67bGaJ +JXilKWEmKJ1FKjidqApyXcagWMi73Cb9JPlU4/IVbL/tq5bS5R8dqPtlvG4pXl8idQdVhAQ/aMZe +LvBI/ScnRibb10I01t7wA2v97bjngkHwABHfYfvKF5F+6KSM1S8Sr8HdGSMaZB9EBxHFMNn/rYB/ +DJ9BcebnP68puQ9MuMHNufS/gxdpTNPi+EzLJ1ypwTVDc6wPVrWM5XhXvqYdtSsKcT6GQ4aAXI54 ++T/1P+8YJhIo1Ca4y4nGLcn6xfeviZHnPf0ECS/LOj2A/+EAFBFthz+fRcH9uZ8ofDcczfCKqro6 +9GK8NsuQo8w5O+Iua7sKeecw9L3C429VUbZItJ7VgdoWVkZetLGyJUuYbovwj2Qr/EivRN0408g7 +fbLGoyRj32P8G8PuT1pyQySEKkXoYGh1nl0rNP30hlk6IBZV0eXkR6183J6TfbZWPQ30OhEs6DFY +Yot/jRnfdEzoGYlp6JCUv37D5W+CgzBLr3dlYJhGhaUqQ0R41U1g9YtZzCN6x8KHN/2u4xWVq5BC +8fmtx/KpWeBFogzD1+K33/1ZF+mDzED/8uXB1sOG82n2rp4ySM+RmDkMrRrOluljgJJBK8MjjQhZ +cH2gNppNuL0IhQZUfCEFxDGVZrzweNzUltJZS2a5KLvbsKBjOaynNASaHBGWLrsH8ByfmHDp6Ekn +9FtJe2jx6h4PDxXI0p4LBO5w0QNYe/e2oGIRj3enSM8hXWDsmQ22KPx7qkeuXykkIzLWS4Hd0IlB +WHlKX+puhoHCS5QbAFraQWbE+1XaW8lQXnaB9zrBVrh0+rNgQiQlNfEkLM5WNhWUxoQUfaG9/d8Z +tVK+g/MnNoIBEAsicdNYFVD4eBwzd5nAYNicN27wOYA0XLMqrI6V21V5dieLQyZIfiXfSOxtr06t +CXfMDeuIgv+5iTDwq8nje4QZfwy6xKf0bm4lsSHGG+6hvveDGW1Hn0OLTD4Gy8kuLGHd8J6+PBmG +30XLBQYpOF4ZwFGky77CpDATG3f4pS6k1iHEItAFeqUH57zLj11tPzAOYXQut4sUISbpHQkaUpnU +gXn5x0bFAby2OzxAgw1v71xA/Fx/fdZS+eD7FHaCgwUcuyHqts+qQL7p8FjzEBqzDYh+/5S3/SI8 +e0jePcMIgR+4BSeh9nLZzC7BaMuiWys3CC3ek5II051ICNiyY/k6rBzIJnGMBueMpnO/PLz4nszk +MEUXlfM35SiST3HY2ceMI68Z8y30HIE6TxuayFRJKUZr+VmLixbLCJUR5F7F1KqTYEGy72Em0qfb +1bZ5wtP0xmO9Z7PayNT87Snt3R7jnfB8KwmevQuQDHzYGe8eGzLvsLbLSbCeMF3jb1r2J+sj2FKG +VY0rRzqjLf/2UlLYlaCKuQ2Zd2h3FYIYYvgK53u0X3xsKhK+2Bktqoo/A+FbadzPqmyPdHmgH0Wt +kknIdLTlECmzjVVeBZinWMhCFczeweA7VC+OlTYR3SUMM/73ADM4DpCPGW/3/MGCMuZMD4PGfj3o +7Y3RTcDBk3ok9rbKY04Ld7yaFoBveVAYV+Ze91GVHsh5YwRkIoed/CQNqt9v7uCFEsVGyNMig7vX +d45aU5E/q+0Quz2yIfMVGB7tkDAwcbT0npb+P+9hSdBHbhgsyHkwsfZcQUjnie/OgGBXPAKz6mxs +EjN+P3iCCc4aMrpqQcm8PgWueOCM4jN/05LVcpRXc3AGgyyJReYeeHkWkz4iNbfLG2iVFrnXiMMU +PGRPI/kADMkPI9/VLkU3UnIZvbpD5RvGkJx3UrZl8SnccGwz5zbXPYizjrpAsxCeTeH8Lbt7XKaj +5MsKsYo8kPreaQyrCS+DXQjAcTg/s5RbwaHqZnRPs0RvgCFpxPVUCQUAQ2fLcwXU0mTn//iFI7dn +dt4tVT8qqfCNZ0BOPKK5N5OGctojYRQAYN1kBsM+yy7PcJOehyWxd644EpBUQ6Evr1DqWqupaG5D +kdpE3yvkdy4NTdGdkG0beXapQv8xn3uiROhBg+0V3jjo84xaJFaBsf1a+Sv8DlHWbvczIAVkC0SZ +eKm2TzvDdW5y2H6XGVf2I5KSAyYyr9OFek/12HUpJDd1TGbXpxYPGBeRIw1Tz/PsD0qY6pr0HELs +Xx611wTKMZSa7SUFr0/urycc+fal0ln8dp/16FSjV7vVmgWAt3/fjvWz82vh8JUVE92y2mE1BRhk +IFn80SDlZrg6o19iQdXey+OuA9piNFXRsu5pLQwft2iOc5VKomAFA4VQUgWVgYvs2yYs9jdRUXUb +UY/BoaADf2TmndbCG9nwsWMqjp5Glw9vqM35OtF5M5awRywP0gKaJ5d3zCRUQU4zqxcbKufQwKlg +WqBLPESgqVsFx4sVmCW9avONWq0HFqThreQjzYSbdiAL2hheSyxmeuuXvYXs5AVz1UFwEJWqWee6 +IIW1jO57qTo4d9gKM7Fe2I+5kVWog8T95p88CsJChrusmdbOFg1SdNBax2ar9VemOW8WhVoB3cah +M9zOzsMU2lZqj3kreU01QfU8+A0L914ODsZyLM7xi9gSFqjeOqxEj7bCUuRqmOJpLUVM7iFz4jxq +lWc129QoeNz0QO9SDwcqOjTykA4UsTeqew5hlpU7G5ZmN3HaraPY39pGBZvNwqDwHwqJ9N9dRJ5i +6KMDkfCWKV7X6tZ7RYg+gpJslemkaAfy9jveOvClXMB3zoHDWn4JSBt9iA4mKkHL+zydEWn5wwcz +fNFM84RoV8b7vBwF0Hss/JaZXBJ0AY5ZAwND9IVuIPCAWAebtkYXzN7UH0cnC2Q3d/7HjK5hEnky +/4a7r3hknzZhf7FUStGwdQp8q++d9lAgUlamr1cnf1RqivNs4bFCj2SEHHtPPRXsoXCIE+TY0nCc +O+4GKczEeNHg/anYx5jklpaL9VJogy8ASuQBAmI+L11+xFPtZ5rPZGOElVA88q2cKyBcWfoStUQf +J8m6Ze6kD8foB+ZZdzjYnbTGreaUeJqOf1QdRAorxw6cPniP7+t0PGn2ZcQ/TeaP18ef9EA+DSg+ +UnwVPbjsXtMhyFXv7DxFRp4ZP+kuWtF65+0g9nOxrV+kkNApqWal8I4oAjj+XK61irK/INHgqmRP +hejYN9YJf0fnq5voKJ1pFhJDwxkjUJ92eXGr2rKimkD/AoSUu7HLiCRP7hqo2NN2Fm3qQEeis3b6 +UlOAjERRiyNSeyn2ibEm1YOe5zdTdVtNJd+xZu28djaey549XbrNwVBGeahMjcyVaTIW+xsmdmem +7mJ1ptrBSRYt5us6CqWT7EUz6MVlWXYkFZOILr93XA2qlrJRLURN5NLq7ttqXS+ItMB/jVVm2CmO +yAlapYI1sY0MTVZRAQyQNujCgmLIHbz5ruzjMe4ZAfHtKQdRDtqgYjgOgqpeDQXDW7t49UFHmWoi +szevBYY8gsup/CPDTYlpvQ0aLnm4A3am7Q4YeLLE5S7qld2+AIauiSbLa2Cp9gbcHmLSjDOX5yJN +yPPu3+RGQz3OfbslYYuc2If4IqJwITuogXkh14klVtSBH2Z8u6OwASEU1t9oOjncavAjPzw3SZyk +1/2Z1xHAmubxFJGwl/MgwOBmt0Mt31S4h8wqK3FBsEoweYV+S52bS1mcUAAI+H8jvccmLw6INOD8 +Sq03hD8V4VhOsmEYqaWwYNPR3LhYw7gFUUbLFz+QQ+eTamttEO08ZOyZvRZpiiqiDbfXupL163w3 +K2sGfx9HrcdnvKSS9wVKFz3cyLriWfrMQQjgqxsZ5xY7eMYcICMPbQVEnK6anQGMn2JqSLCid+5+ +4noRp2/eqecKiaiV04YPj92XYpHmWnHCM4pbb3a9u6biUTZgEMwgvTwEyTXIGAhCt2vz/h/R4Q67 +23WKgJM800xhPhkCpJO7lD49PpJNdweCkj0tLMoffQ6yPN4UxEkRx+3Tf/wU9x1wxGSBX27lghPQ +XyeJ3rXkQ2FwjWAXeOYbt/0GFPd/Zv/JLDwGcNDTaa21+x/xtkN53wEXJi4QSsaPmlT51vdB32xN +TuUPzLhHIETZEC2bIHFxYms+Xj4LKD3JFkPqR7klTZDCfk2norOL7ipEUdlwkDRCgjgIbsTevcRu +wyVp2tFN4H5IAIfQm4W3Qe2K6Djgqp1RwVH/33S6O8raVTMmES2lR8cfW75+mgkt5DX5uMfDnZNl +5Dz7snalYuJwseAHEASga446wxC/1uzQmXpsWWh9R/iqfqEa82y2AV9aBh6sVFKOQkbFU268VyVD +X8G2qbwCxr8WO+jQrq6Ihvzjr69PLp65LSh9VAlzc5HhU5bFXiWkwrJlxln/y6BYe3GC3rEoQg14 +gS5M0A0gJacDJW59GETNMIz5s19QB21DYKdqh0vos0eVhAhcwdCaJCUXwyQyd0sa4qZ0tEKCeThS +38L058CUh1+SGtmcFZRzMeIZnZb6YjPx6EloinjS4ddM++V0aCt6lJ3ODvSRKq6t1BYxpFjhrxoD +0WB7Vs9dtA6vw+EOfiBnkMV9WaHc5sufDwMsanu8UjaeBs41TdyWR2xLIdkiKSpwNEpMqkwpaOdD +Qedj/NNpYOcLxDkHXlfsvVriPiJF2+yKu/Rp9PEaqhqjUb0nHO0h8phjipu2/H860LdKz9k9hNWn +KUhB2fz/w17aKyefhTVtohR38qntVn2JF6kWCPy05o+j7GoRAoN/hIsMU0UN9f4adp99f8L44ntd +4+ecIrpQtyvjqNfJQi1/H8TbeDSUQXismG7eQ1RDQLadGL6ytPBsdzOiriMCmV/QhC/iFQSTyo57 +wHJLA9GwA8avqETt4esU4/o11tBfBVcFitHVCzecKTnLVUHpP83YlcUXglEjf0Ajq+oZ0mR4B1ND +rCosy6RFYVoIXuPdIkD6L8VdKNg96Y7kYBTsc4TJmVAlaTxjWZbc/z6SCW4uu2WUMWU8R2qtA/qV +X6m1jM8RQVdKVdmq4PmmqjHkhmnXRKMx9LLQNdkgUYT0ALiA9lbAETtnDH8d2bg8M9+YxWL0E6iB +qmAryu/jPd//JDRFpiDCUPTec5e7Ter9Y2FYL3556UQC8ZUxD6p+9tBl73NN2QuGRlsAEsov/eBp +K+h9jhIbipkghSSFU2xTxXuToGdqKHrIZPtwtRdqGABgLph9iQemXp0Uhm6jYCFh97TV3COEDr4Y +P1MbQFmdBLkchcWvxd6JZXl+sUbkIghvxeeU8jMDuou9qTtkinUcwobJejptXIfPSF2fjgDIJPi6 +vYm5+Q84WyNHI1Z10iOm55MdNSuaYm8QbihSBPLJkzZPs/KNjvVUd0ZMwQJj1IVh20KWkwsMSAwl +GGlVOUYqi54coL8gAd2GdKx/hp6uDHQaOhT2+zBgNzBq/hAKtrE69IL/MTi+IUZH5AK/6JcYD7SX +lULj9AUK+4X+d0aMTnGPMq3FmNN/TgI5SVZKs45u1Y8dT+xdAbZxMWjL8TWhSanFC/vfYXesomwV +s6xJMCVNPnhPFlti0cmRbNURwa1lat0+c4Kzgd3fLCQFSIC74iWwJJAiQ7GzvUSPgIURPePT0/FR +CfRRjFhWmvDBZkCyH8rqFYmfeY7dS4gkMXW5DW0UO6RlBwz/5AU69SQTeQyYbiNiCrWS6hxonv0m +oKah+S/ilt1VzRBOgrVAsq9seGp8Xz275HnvawIE328vl6REvnpuLG6KfU0ZDfwiwFmAPNqVfNtX +vzOdcrgO5EEVCBRviUZcKCMVU5FUoevZ91aB9tFB8N7vasAGMj7k8qQV/cw35xyojsrPBfXqq2h5 +rdRzsfka1jRS7QtsdChpe2M/g5BtfZj2Fu1c0QlTZtT4kmhSa+gxwzRw/NS26H7CleeCOt7Po20v +u1AnuTILVYueNVK6LaAo61Fu3t2lqe+Gb43EHZE+91IOZ+HVFwT0oZewEs3veXWJzywWCLdDD6gH +I5MKdW2RFktnsddz5i3pocionX0lYCIpnmBxg1ma5pg860qWVt+oCf28QQ4gegS0+MVL9c+x86FS +MwnsefZQp8Q7zsLB2X0MMtcaoUSXNyWfSWnPUKpmuLz5V8JJfxTe+L+/+plju7yf7tB2B2FKgDZo +xSmbVAftKQYCdvCHQU8nU6BxkW/vWCNhwPhGtDRKqscoQ7CJCC1NvUvM1owWjwQnIygSOMdg+NXS +tNGjl7/ebmPCEdPkhZNI46/NJP35x4uCwrPjJUDWdWUwTp0Mhp2z4yJuF3IJw8Eq+0mFv2WtZS7M +OWL061JJoDmnt8mBf8uimZhQN4VAD3oIyi0HPFXXBybbcUfyGf9ittCxDqa2t/qRTXBzigMCrr/Y +rpiPJLOzQyFkZmnujEVKpEsGTgHSxKklfHiO96QP5xt0VoqILoPT+i0KVO/pVe6MJJB2vxRZSG21 +WO3u7Tp/vOST4nmi6XbrAFvmNIsJLtbhzExAw3Tg7+d+DAZilMp2yzcL0nV3aV2nJX0qMzRGGC90 +exFICM8YlnbBCiKQHCg8yIUlY6k62IpIgNtbrNwzLLnH6Mz6pdI+6WS+heaJmRMLwNksKcNOuxs3 +ePxXaDFnt9/MlgeV5/cREavozpBn6sDBU6w0xdGBBi6sP/7ou8ZtEaj58Vz/6W0AN0crXf/h9yJZ +Ujg3RE697BQyvp4V4K0JXKPbQSS04agVDVHCWdA/+cE64N7lx5iBjS7zefzME3FP+E5+B6R05uoz +ef+tgSH0VyEMMnPiLsFHHuDEOWk9A6WCpSGaQZX/GuwymfyhBDOqGxiMtnyhBsCX0fcbLoSv2Aw9 +NrUwxDXkwgO4SHx9NDFIG8LKMElcrL/M9WM9E/c+9JoqTyI2aC8CxAvsk2wDObBkm1bhA8ahx8o1 +9M2mDXyYhX7+wn7Vrqn7eThchnnF5y7n3I5nwBrUSj/Dh4sCzhL14KU/dvidnczR33OjHSvWbeba +Z8c1bmIoXzmWjt3msZPXR2tWJ7ChNd8w3cugQ8yvEconTw8NKIjL5NhKMw2bDLqPr+uVZVUA5gjB +Pr27O9vq/QVX2qCXEktajKY+LyblG3iInTiiuTeXI4Eoj1qVeZXI6ZXxq/FeBAxDMgHJssO1R9ou +02uQOVDFicOX6VhXa91NiO7FMYmqVP1PGs8+36+AAh+lP8hl5nFsZmuLanPscphSdoGInWelYHs0 +3+7yGqtX5mlYtCVinzAIcXflvhEgRKSZ6wITwEpYfN2HTh+bsUD+QX9gwtWNPViwmrwg8Tppy7cA +QIspg7+Z5KZ4I87/vAflwRYYOzdApEpMdCSK43yw7Cun/hFoUu7d0I6zcJq2SERpMoDto7Nlkblo +ihh84owwAJxqJn9vaz9VZMVqQhmyOun1Aytgox07LtAuGXRhKhyojNLzWLdR4F3wZeqpkCnbSGBG +t8gjJ9z598Vk/VccaOSaseWVbcye9CUL+BeEZB21U6CHm2sjMoe7eulrH+Ywj1kcMNp+ZppcfC3B +MU17WYYT/ZP3sAQCaXI0BsGEuYKjimrJFYPm6/0zMLCOK/BSbfOGwxQoi4Q7HzaIqE5PDRIOP330 +9eissFxVOZfE5Iwda9o/WQ6WM0uXIVj0LVf3MCFa7xBUZPEoBW8WEgr7m6dY8VKRpRDgSBrk8tdk +PVw0pUY9CDoZXX9gWdd3hNs9gKwsUQlc4sRzYR49viwNuHgRPwYbAWMO1YL5OzV3E41Bmme4fBCo +joI+onvkYTr+SyhxLll2DSs2fI4erIcyS0PtmPTc4A8cYSvjfU31r+s3RqI7etFIWXMH4hz0B+vf +qA/EYXZLvhQp1kBiQmpo4zmqmHbYRKSEeYpwPscFAqB+LjxboSz1SAe8PGSkps1SpMN66smQV5sm +So5RyDHZ1iVE4ztqB7Kxs41KXrw3RX3SNSF7jKTF/ubmfRh/iI/gxIUc4LPGHSlIpYEIwjVbgfyp +J+upRGiI9tePaP601LrjMgcCpSle2HeNfyNAcmQLwTC4Upi1BhxfNeKTnXoNVsslGQ6ALk3SMUZl +cs7N+mBjotbrO8TB3w1fzWntqS+1+Ld8Xf1IMFDHsekE9rXjsn51NX8MoAa1UDCayySvRB4BHI/Q +hszSHhju2A6xbYB0Okox1ddnw6CG1Emfx72uBNYUUD9QwuOcYR3ipldkCszIy8Nb6CeY4K/mbhlC +yPBN/7SvGZ60KrGtPeRhn4g3Fspennyelapqf4qbftkgbQgbd2gXDLPo3Si9+/Iu4GN+uCCU/yjw +dPuIujiYTxF76T+oCI34iQvabYEJZIHbpSgoQAA1N3vUeztU2+gGGc8ayKiau1DFXAYqDH6pX4ED +XJ4/Td6Qj8Vh+hFbWvoWB8ImoBE43gv8OJxms2mbHidyi1+SN6kcJ0Gqve3kfBwvrKpLlmAuMf6k +fkK9FvM085sSMkojBkkuR7xqv2oz9pNG+ClyJ5SqKj3HoB0x2A3Q32gm6czbsNtOA8H7YEbTW3TG +Cp0BZrt6GsxKtnguAI/ga4g4IQ/8wp5GM8IIT1ZlGlLmN4eDQL6pDlq4syJtI109qA364UKcf+Ps +efrvqkRy2hu5fFGktBVZPT6uWbwQKA/cIkKyeJoklda59UvXaSRlo9BfxvK8c1iGVgPjApWrlzwI +5U72cgVUKMo1JZRdiUaBUPhOuBOcK9vPYhnL+1XGpRv5OKujA0p8OW62lHt8RV0H9kV7zAlpXdJM +1FD4Bg6+H1J7sIBSZj1/1ZQdTpAF0scDjzcBEjOcuBNLI8wWMrpWZWkZK6+FwMROlKncM36naxsG +LC8DV4pJtuzJZHoAPSlGQ+SD3gErBzG+lM65YbtGH39vxsmzNFQtsIPsKuKU9/8fNr3nygNK4tK+ +25I8lxUicw7a5KoXUNtgMe0XQqlwYdV8ua8sWYotTcTz2H3YU55N8KZwH3KjDVd3R6RD7sHzCA8Q +1SPij8w+l+TMLIIzmpiOdSEzQpdvy9K6oyXawbkLr10adS/tXX+LQnyeKgSNUjLUGYEChMygJNbi +BrC3i4LSX3UpkPB+g0P6STeqy2raLqHHNbyemHoR6IobPwxFvFyvFhHdl6nxO4CnxliZ6hI+3TPg +SWWkVFbS1W5ztE0dA9XMJdcVHGThqFTlrfrS8Xh3B5+asFWGsj4vu9oRGb3P1y2yLide4FY3aLdc +UmoKPEmD05E+LHpg+7KL35WKqJ/sgvt5wWETV6MPYWZxZ+Fet4mdIrJYYt5kfYYwns+QPQ6okbNU +/ubGAS+0GZ/5EjJ4nthW6ACCmcEl1wbG2o9JFegNKNQajCccjtlbaJeJzHH950e9DFGy6mEeFbmB +TcJaQ/+Qu1/w5+CdH6iX8DAZGDqxrxgjHywIOPavvmxlMIxwIIJrlOqHx+cDJk7Cf+hEuyyobRsN +cyVyn1qaEOAl0Ts0Lpj/9K0baG0i9A1yU2Sj+dAdX2M0NeWAIAjoU7MMQv1Pzoxf6kmzFG9oM7OV +lLU78rz+0NA07gM83H7aYmdC/UGJuFI92yp8h22x8zrnN+Gqd6Qbane9jmPpYnC1OvcNuQed+yvq +BodOG/7pWtMbyLd39JBqOEQ4Ag9FbpxVbB7q6hfGwDrhIDTXMMCPoaVX7asaAprxSzfUKIlxXX+J +2v5UJ/4pR/roNcZLzWknNcwjEMT7mVEqPwPb/EBgda6ed64SJBNd5v4a4buc8573yRFpVmJtXfiz +A/5JxUwFbXq+a3z2u/ngH9BIxIrfU6lC7LqefwYmZBpRBKMOfEkhxDi5n+y9FzDkCj+rH3ei5NGb +MNu2+VPuQpN8rqmLTs6JOZxo242fEMPczvioRy8KHXCatelOrlUiFpEAvKsc/fKc8VJo9vO+Aw2E +SKnDrm2sc8ruj+m/mbaWAqKh5Qg8eZgCKVHSyAhDaR19tTPGZc5+BpuV3zikgTpjGOppLDGWOEoc +VvYOtIdjcRrtBPxpW5SbSL7AQG85SPhF+eAFvhwkKMb9kzeBZ69YNCcKxEi74pNOUNnHXh+4qlxo +JSuuAcwy0O0vQboviFToTbY7kiNOV0k/pVHSLlT6AlRCRSqroDNJj7hzBfEWkWpmADZtLR9xUvO7 +9FGyM3qKhA/p3Px1EgUi8mBtvsAID1Nn/Co9NbnmW9Xdar7oi24c6A94IGTG6/471R7KucDWZmdO +QfjiyvdOTju64ICvbQFb58ApSRImvAjFvIlyUT43JoEBMc91iZv7VMvIL2QLrXcBpjr0iDnEMV5S +mjAmTr6sbbZ+EV0/F98SCUjoddgh+Z4KOr+ojHi5JifvGpGNufVKasgPbjsCm7ftAZuRPWoQN8Bw +gVEpVzTciR13M5qWtVmBsWnuI1TrJRtFPgf34rsQ8Hc0T+nKKxmW8n3f0dlAcVWX4pTcA0uhXOgB +xhN+UzyAmt522im2oIahR043WfFWDbKtT6bfVnSwZlmWiBCqONl4vTz0ASfycSppo8yqzDYJYdnQ +NyJJ8O93egmIawckv1cOIqX3J7rkiUMmnhIkdFYyrUFzn4iUELaVkDQdoNcTI2Qb47WttYum6rnA +/KIewrXQe5lI3TeHsiF0Ezb1KorxVy4qp3kwyDL4i/88hqpZwwiIjYQAg+AAvn+EPzuRXJ27avi3 +Pqn975+pYF6nGC5MsWM6wK/xcUuIjsMeinFP6mMpB1tNgcfi8pwakUV6fZ79c1QkOCZnz0dSXaPv +wWYUMVt+ZwYCSbhRa4rm3Irbm5yieT76sjTyaxBSw2y5hY4Znx6hrpEILWP9CtNZGHPIk9gjdOeB +ZrYcywVxTikcdbZTxk7CBNtbrqQCXs+h1d7RvHuaw3WncunIb66XxMudZsrzNEo219SBiluVP2cz +Zvlgk78u2E96jAurkgtis0nVKJxfbQdSIhtXW/G1ZvSwBq1/VEdMZHjNe3f9DZVtphBxYeKzd/Rw +UubAeOrKaQ1dVP/O6On1wEhtAAwBmgjSCVwb4UGz+5EgEHBFLZBieMbptgAsLEDswpCI3x5mPL0V +/yj/FeXVXHkMOiWNbmdnxLgmhb0iqMndxqadXpw0+HBdwTVhZBgP3RarKSAtpHtqW/y3Xy5mRKMX +1cFgZSDs8465Sf0xkq7Rf1tZkVFA6P35v7enO+66Np+US4j6kBv0ScuApzYxy1UEY9mCaX0cqVU+ +JcfjjSPprKQ9KXgVc5q/a0gRYPP9K8vo9r8Jl+6lYyKRvTpEmJZu3yGy2QOe4WFzZujMmWsqFDyn +a7kRR0aIM+aa7cC6k80aohs4/T/RzkUfpqtnT8rzGlUerRvwn9j9L04Zfxvjx8N2SJQu5lg0Te+o +qQjLlBK7iyOfIJRH8EwkeeBqjomfxcsEaXNNv4SVGlbysPbggQ72Y46bUYo9Xtz8fM4tM5eFH5p6 +z20EPHEIGTdDWvMSrIWApW366KWwAogt9w10cbQePPm4UWKNg3NHVW1wDDGL9g8ESRtxQF7ZycGG +ByjCSEYp1FahzRt8ZYQ08IxPgg5KslEaCjXr3kc7nG2GFqqhemNR0Y/BDco6j7gD8zx6IerpXjUC +4jicRJlPF0Z3ak1pQbtW2L9PT4MIQWCmSYFqTldosymOHK5SltmxkX01VWpFc+y9DzFklwRynxvr +4+820ARTTusSDl2AHebAZX14AhVboqrMcCl8bO0cL2dlTS3Xi2Uysy/GDzXDS+64d+zP0fTZti7l +i1i/dYMTNLSM0FBe2+N4T129zQx9BCcZT5m/v7oe0BZPc3K0xa0807mue15jJQzv2sjWSD8WoZPj +JjfwY2uoaO0fjZutE2go4BIPbyoNnB5PDho5LrXZu8TNAFshezDxVQPmAL0kOXyFavddcCatMVzw +ohiGB1H3p35T1gX9KmgMs7yp88eipHzk/Mi+GUJG8vSqGCoMevEyI9C2z7tW0q/FrCvZIKCRerYK +ntTyHdtgm4JBKR7NVv91nq716ILg20ies9xfXq9vid3+M5bK6OhReEtrtkY46CmKbV3t+lAmMxBx +hD/uIB9U0DUFgniYdSZIcHpNb723fskH0MVp6C9DhoKK8LNZqAqxVsRegANzc0P+XLH1p99Misph +gH0Tv2YEw3R4F7khVsVGSitvT969vx7VKDQX+iBRzDXkCQlBmf2yhqyzGVut7VQVIQhU2763//Tl ++Ka9xTTuDAtJRlHKQlQs13RK3MoPEZl2xAky71ZKzt86ubGwgcOjCKiy4cptE+JE0J/F6mMgA9UC +X+x8vfqGEubRzaC5fOwLVbHNRs5H66aQGprH2H3ciCRdPGnMVpOJ5hEBzmeoFRCl9Wzg6NQS/P1R +QCG/2juta27wM/GfrdzmpsVbtnvOcwIGQe0NDjUK0kfNkHz6vqUwMMNzwXkr3bCWK/2Qr2XrXyke +tkLXl5LX5CTRdEzLTnJVzbVizMJvWDyTT0mhh4Lm8c0F6mf1zYGKM79OR5zSaH9KASKPXQN6rhYp +DiuA/SKrmNuRT5MJ5zNpT/hMwiw6rdj6LFH1dh9jI/Ia8SSagJipEVPBjPJW+spJZQMd+CYCAojw +cYU4WFKaV7XnktUILVbkAI5yJMXQrOshssoH9vFj5v1tbvkshgqQqbGCsrFy6ZyWNVvxDmLlEicE +CXqmXzCEtYDkE417UN8z3A7ISpLzN6sBUoABvcHcRY4NU9PBcj1ym7Evd7oot0SQHDO94Fc8u5vM +jjdFEXX+yMJVeJfVkuItXzjLw4Z4lCc7XecXjSPwwr+ysA1KhAfzy7qnhW7TNuUsKY8cc82puAvE +OwAeQkDiqkhx/SfWXzSq9EcbwtXfMCDuKIYZoa1RwnpenTSoarcfawHoSGL2WrBRsPtq73AY2qnn +DOrOFDCG+wY8RV3O/8eqbSYaG+oaU5bmjoAQv3Wg7YnhAfKrs/PwzVzhnqolRi/OnPg00AyFgV5r +xlgzXM4MTvcmLlmWn/uU8NGERv+v4SSVj7ZKjm7O+GrhQZSiKhLWaGex6G/3ecowLfs/AHLCUzWb +0em7/5Uxc7cf6V/DyB00k6xjjSIyspccvwE2OMveEjsL5yjDYD1f8ZwOhbpcUMtOJk0upMfUbUQA +CenjJOsOfrWEuM8y87AIiaMcZ7sy/gi46vW3CY1NtD6RbAlgA+XxBXgW8wCYuqAfbPcbJIZAKQ+e +hQ5nQy64WeokT89EBo5yId09XdwrCA/dG9zk1ifVqbDVthEDYiFMBACZF1MzETyqz0dvAZjYEaLS +dgp512U9p/C5B4xQ3P0tPyRujVvUTQbcp4M/S5hux14ZnCyC42Nlucnl5RkQCHyRmBxm5OBltHUI +xlLcegsqvgyHtCl6JJ37l9S2yn1il6vFX5ctT+ElhGj/L1kkAMnMwO3AEuTuU5gcyVCIn5KbbA0y +yVIQAt5S9djj//VTUttVwm4KGYoT1yG7FxB5vISvPHf1itfR3to8PovLad9/zNUzxILR9oWdhckO +T7lxFOPpy3ltrqppkWvAinrK1EUvYj/T7YhohgKAuGtTZB0MFos/Crq71Uo2js/vtLXgBdlZetPJ +uXsm37fJ8+qzY96uLuXrFuDGMaLJyTfjDsSBqt+Qsnn7KJyGdMNsg4NRVG+EWZ3Th0SR0dBE8KNM +eMXl6yFI1sEynjHKP8IyUugXr+/zJ5TAnDafU4LgH+XtPE+goGioXciITNIk7g5GlukRhtLOj2Oj +KZriZHfmsR1elYYUWwoqszvDmAKNOHDEnXW6OqcKKDLmq9np9RLrgYrQ0znWttkwoa1L86f67pv8 +l5XRR/Pq/qJaMrXDs83vUMUBjOg/VpR6urmnp0/wR8KdcOtBMPnVpQb/c4LSLXbtmoBFxrQq5X7/ +GYLflBb/LI+uUJP6OaVhPjmSYpD5dUQFiO3g95kyUju4AmQogWEYxcEhnF1fK3Flz8PkPS0Tu61H +f/bOfojysu+yEknJ4/2FxqoBT6LemxTjxt78lOPqaLc7yxIxxnaRU61D/EbEMfgSD9evfFxQRi9i +jNGh4u7LqrvUpLuSghU4cyKaxX2WdknedIIZ7Cn/xgP9tGF9dxhbYlyWOLi+j8fFr8JXkukPIqKR +0Q7T9g7PavKZ3RrYJVO9XeFDo3BtVAgkG4wasUor3JdEwS5j3kPsxxNnEG3IZDknUmBMsHnLlKXr +amqAhuUZe+evcrbXrR31OjXeRY1wWqqT9W5q192ZUBR+rzk3PJahj12ATNx9YpxgompvRm9Cd7zT +c+1uC9uI8fi/D9FLRPmhkEbZJ3ggUVwcgdFfLrbKDTH3fT2BgoSGGXRyKPjWJaRvU7nSepZcSrc4 +xSzqkJ4xcwwkY1bicANPWcFLmkIyFPHGqNHHCGdIDu16LtfnWxwgyJsMtjy4SMwjtiovwCLMbWW0 +PwpFwcOwRbILqqRP9ikw/vBYUZb+LrjDLyqmplXx96WzAUb1akmKFncuInlg85BkW0kiqwiPKl2W +xTxTo+H6ZU4UoGDrRUmFIeulP2BOnqaSkWMwpJy7zVBjmmxys9I2oxIFC6mk1wv9h5GpbcOa/BUL +7lOnZWy56JQ3Qw0Cj9XMpmZs9pZzpcGAQYGnXtyYpfAwllP8Op5VNlcyMwKiOtdLbSWRskpAjinJ +geJ/iMWVULey2bHHN2GqoBpgKHYCP/bl+z5LgJSL5ltffv8wpfynqbHfp9FOTjnT+c6JvTyI7tIj +m2YXx0bjE1Lbe4D4A9mqIY3pg/dfhSbec3mneoy9z+qopEhHyKOL+3yuFOcFJBa7FJ0le+sbIAW/ +FopQ1YiCnX0ECZpE98Q8/6kF9Uk45bhRwu1NPgXqwb7d8oYWXl/B77Vt/1xgJPY0naMOC0SXYVff +448r8LoDel86Ka5GlCrmzR6W62JsEO8gJKziJ6q7p13erz4d0z++XIdKH69uh9o1xJxxbn9JVV5g +cr1Rte2NIxLLiEyZho69fiPvx5rGujb6x95flER4K/eyZa9bXUvsnHA1JnQA6N52IJl9fgockvO2 +oIXRbtmeXDZmd9MSpdBLP0R/1GJ/X/WKOgZjIYBL5oYTkDJExVFpPg7DIZiGMCiE2AnE8GQKJqLC +Q7IPNoO3OuKgl2qLe+CO1wyjr2GTeCMWWqxu3eoJgZVppv3pZGTyD3KY33iEanFKGVeF3FRjCU1o +ITlw7ckricG6pMQvurni+NX6xzJVO4eglsVWiJK6fPe1OPUUe35OswKq3vcHOt0fwv+cX2JalEVJ +uSLYwfs0AZmE3Lm8IcmHMbD0vIFTNAiNuyh4WPzj3devnycj4+74fCBxCx+zcuikJbhDC6Pufr2p +ulJ7m1hCIr/3O+F2ROVuE7+Gfh5kPh57ZkgyjKtwD81vU7I/t9M1VF1nIbZVvO8LealT9P7/A0YF +0/quxe7bJBarfpi3TrKXQJPXg3RG0TNkh6DBdlgiLqkooYc4UDyf/y/XO6LHAXtdn3FjY1tiuZv/ +HYHTPNAbMsjFw4XCQQhGviPwD2qmvsXiMjHsdrxkJnswWN2Mw2cqp3Fvd+9wXlS9Ei3qHuu2HLF4 +vBXmencyvVqMXEwdDmIUDQC1r0q3z+8Sh9uRZGLYlorD9WRrKwRNMjVbClXHWTsxLiSoRbmZzk+q +VRQEZadO9pANJ9OYiWuX9johFwQWwB08w4lqufy/lLu3JbLjwq76sCvX14itZCEATVuneRqr8ehm +Do+HPZnGmhlVSd514vUPUw5AAKSycfhjLEMqIFF4MOby/2gNfBFjybdDSSHjpfZ9EoztXN5xP8Px +EaJ9DaxDIUoJgudl7YOEwPD+H94xvF565nX+jtJcdmC3PiurR+RRKRzzxj9szieI+WCQfLcxCyZC +tWTPXgtttOtW7WmBWZDWWpwFRimVT4rSkklyd9HLqsN8lEaJ2Iq5eUPMC5WfTLEbpo0hVN5sbFne +590DvCdLc2Fd7i3G56LMofySsfIRU8wrNQCIQ6qeeZwQQQ68kR4uquPPCMpH2G7Ue0hhqmkoSx+J +5nT313a993gT4aCM2igHyu59udr/AhB+6slliKOoO13KoZMXVekb7jbiPrAaaxtl/uWXSzk1uSet +PNTb7nU8222dAI9fucrESE2v59xcZ5DNWWuIZ8CsuF+5tpFqYLhetsF7Z8GakqDUtWuZogQ/XZEK +8dSfzkpTeXhuDwyqi8CYG5zX5ywh9SP7pvg1s6vA6iiE8m+I6vVN93RvMwWVNzGBVZklgwj0qQiE +STndzUQBcu1nvDESAGUUlE2LWqZAS+eUBjuR5vOYqoAW8xafzWDaZOvBQP5QxBjKM+nxPCtcz+Fl +spoOi7zuPRdDH/+KZR9nKRunwUY2W8r8JO8Cr5lprEVeyDLWJ9o4pogmo7HZpSCq8Hb0iTTgNwqH +iuqzrbMyjbWHLQKqk8R8RaY1Ee7lquOF1fE0Rns2z2qFj7KrRtJYYzePTSaWBUbQEh4jvhURygRJ +yEVwuAr40v13fGqVN54887DlitvrPptq7+XKPgNDwLyszjypUnXuvye5AhzdfArhka9idpf6Ct0e +ijM4Qbjt+jvPX1esZB1mBOe5a0AsQzviZWrYDxgX1VWcb2JxYeKdncTb+EI90aGxFuzaZ8YOMGjg +0mfHFy9oJQ74pZwTN3Pc+hfyk20IjDIY4aIDfODjrC21EYmHyVp1drmvQp1om1Pe87KOo/3LPm/r +z01X7FDiVnzCihCF8dJ55eA3RfoS5BYXPLjKnhi0jD0qhuZZMrWYCkeUmquX9waYd/BoJFC9YyNd +FrMWbjeeq5WMPwCBdDp5O844Z1Hg/pGrsHUY8jiIpIsduISW0Yn5v46aE2qW6GcLBIwJX3dL1ICw +F/f7XMa82GE0pLycLqxa3n3TsIgiHtvSaFwolsJP4i+bCYRbfpcEBS4F/9e1m3iMt/pdsGMJXOVN +H4dqxYWPgF2qy7GUAsQfvw/ZBXGlR+9tUrt8pnhH8gnBJzL/IBShLLT+zuwEBBdsHEG3KdFUkFBt +CM4vHgwfgvHDqTQAqOVs7eZUn+z7BAAse8iU9OCje5IcQFrg2n3eQ3uOEJdOuPvUheafckWKX+SO +FlFlQxVWU3sO1vMEy0vwR9d+ZWp3SXhcAGO22VLa87KWH6TZ7OsOZ81iAu323kaJ0fFlC/a4TQWH ++c0dpfvMdkj4zkf++II2U6HQ5NAv8gITZIhh8NT0UeBKgh69czLoz4XEpzEonieLZipeRlFGG+qz +F32EeoZiZA/JH/pQZiazF++rTX2BTb0lZATiZtFABUa6Q3ApuPtxG0GKP5em9uNIpJsyrG0d9c1d +Tid2cb3Ewy6Gf8FaFcfPTFO3fJfIEbGMayVjSKnHwr6w3nBOSJ37apCdF+PbmJo13ThhiJRSLKQq +sVqpBiqibdBEerP8QeRo6gYImOmNIChm18E0uUlJ1aMEr/fNXhzvgjjSZPe+AiJfjOwfYeip2nvx +DZjwEgwhY6CEdz1W1lEZbiOrCvxjWk5bfPcJFoNxG/Z2QikS6U4MznPSnu3lwHEznCkHTw7yr/Cu +d/WHE1mGcioTwnEUnLpWTc0aZvQyOWCc/cSbnUQTXZeKmZeQqMwLajuZBNMTk298nPUcteUJkNAf +9D0CXSohinqVkeWR9KaN0yaGN/t/AgQ4p5+anb4affkcmMqpksqCr9IES0bE9SeNR5ocK2HrAkJi +sIkC9go0ZkW5GCWqWEJhvlEEOTSNsoEYqTJEcoQ7VqgVB+D8ryp79Dv6FqcME6VA2eZALAGTypU8 +z2C4copd49oMRoded8t3FUFGlOZWPMp8BdJ54tawDYAjlw17y+wD3hTx426HDZ7VsmezmL50YEU/ +sCfSnT+/lbuSbkUSBysh2J+izQNMgjFzCQmoiDXeHzRSJBdo2Ldt33P9n4/W54BIMjPNwOOtykxn +oecAHBBGoEvIjIHdG3meCv/V79gBRZFShT35M8vGGrY8whQJTI1UUQk7gP942170+i0xrUfug5hH +/kl6pSiLfLFCS1nFdSieY9hCwyEXmponNTswIadjTFpk9jjMuD8lQ+PgyhavG4skyHCuAzNFxtBz +0KsafMHFG1PhqyuGfxbymhcU5u3LWeLFRVMmjHKBIk33YiDvLquhTPnPIaik0VNNrDI0nRp1f0L0 +VB/MjBk206oY+cQx36fOuC0xf25lPhAJFULwVpao/d+ruFC9Tm9iJHdqCswSRHTaSaGWA3tAHF03 +B7WhGlHGm3083WiDoNGtMwDjwwiY8UN4KYZWZuK3UqXDR4ZN7L2A0lxZDJs1LW9HzhH9FDzDl+KK +iqzgmY9p4tcEStx/R7G7c3Tti0JyulOZeJO99eKimWbGjCaCVfpMLVFA+b8fu7bhgc08yo8+cjFT +YtlrJNVJohGrRsYD/ms4QA+X9Ab3ZLdMVII/Ll0ESDhUiRxv7zxZc8qjqMKrZTFKnmlBDsy5h1t/ ++KVeohXfoZZO3IlJkgABea3caVCZx5Jun1mne4x8IaUmWBBR6FtSlGoOhiILn92x6MtHoDDwAcNp +BdPfIdpKQ4wMX4y30g2GX2XsCV2fAzz5FWzPdLIe7OM+YaFxREsrOB191ly0aWSSNuXzEyqRBIzt +GfUZveiCK8ztpdQOrAauor5g7p9t3+pztqEHGo26MhdyQKf/hecc4c/lPySEGOrGMVT+PYX6H68y +voTJ4taTIWPG27QOFDRBQtaYDexErGr+r/lyxHg9wWmXSEXkvSmMTjOcECtW9VArL5RFVochEsf+ +Q4UxP3NbS9SbrD1/VKNNwobruNrQ1ar5LqDSb4THxs/EuHPv2pimZvTBDLrfLUAf3ZUb16W/wtbP +7CT3deeZrRG/DfLWUm+ZPehP7jVIL+BHDEy1WR8dZ8LkzwcjtGeR/49lNthccjiKjA2W09xqoVJE +ugsmsoYJeWor9i11C71LEtE+WqJGOvBMVNBKhdJc0eqivgCfHYbBxsyG5e81OYSZmlqBtH/gI9ty +YsePLl9ILIwb/zZqqmPYWKxSEmzVgi/uc3yJLHaKJkGx5vEthkt9E0D4IJpCOi+2pqDXr2xgaUu7 +U8kuY0v5IOqhY3M0MTIwRwyrLZ59nQClHZEulw1raLbmkwfGkgew9NgyTM82i6A6qj/UM/ZsCAGZ +LqbC4bECguSozoIet6iqFC4Z6YACdMCNGwVT5LFT4y62jlPUTImRpXaFB0DQx+sb5U7ijZL5a8BE +EWDEHAbazgWjAd+/MbJR9CdqR0zIop+zpkztCFfkqRa5kc2SlhVdVD8YTi8VFofdBcdvAnnHB8Mh +hTOgghq7Qr7Cl14v88a5w5ZQ1sRoDfRN6J8jCYQNlCOOksxKek0JIc+Hx1LXUAzmV21RA0CZog4Q +LkhBrZPYaITY0bJYy777IYre9LW+Jy7VwJ35aF1/uien/0yuXZVpJY7KzErC7TUUfnsF0Uz8kDAi +Vs+Nax4+15b6hHXeVfhnwB82TjUpdG1pu4aZhyG2iPAkHaFTS30Wgi+He/0TsSotnlODoyUyF1zz +JIv55/R2Fc5mdQFYG47RoOa/vKvMxq/Gd5nxWfWruNhAYh9OvQjWPJolVB4ZKV6ZBwGaIDNe6poG +6M5Hr8VBUbZ3yWsAl5eV4fT7nsWory92xOfdxyovQnFhWfmcREayhnEGyxZNlFiJreVZjEyz6Nqg +A+JdbdfUn7jtaAMRJ4gJ/25yZlej02b9F/9fv69ZBz9hq9rMOd7lzYSp8nwr3dNLupN669YWlefg +j6eRPtmbh9yC/mZsqfqKqOjzjWk9Frcky/cOr6M83lEDkg9NwOhzV6udxDjBD6147JTsTUABI6RG +oZYEjxEHQX6DsOe2GEleFWv3flKu3ALuDGkcKVp0xMA9ixy5mZS8flc5CELC9EZyau07Q7l4Ks1e +NQ2JzALXvCeUr24dt+aDRQu2l2LOTIuD2AiLx994XtVgcRUH1tMBg+i1feIhurPmHAHAP55Tbk4K +GmHsbeUXtFrsLXepuVYQ+Z5rXw87zPYKVcH7vqeMhosqo8F63oUGGKMdShk9k1Szq6RIL+gI+Q13 +AhDlnb1N9XhuLBXNHqN3qoF8NkaM+M6pd5LS/dbsrAfVQOXK2k7TbihrpcFpTXyNCkKaLTxX3sjO +JChId2UaXgnXPQGZI3JS96unPLAW2KlUbfDALgUWbKH08YVfFQyNLEh5mPacnpyZIwpucvvojPmH +lALExL1iCgAIaNpU+zgHGAXKPzfLMU3WXF/PSfgSB7B03Fv1JI4T8g13kZRB7avgjdQzF4w4yJjH +z9Bnizk+7tkk86hUutEOI8DNrIqhAC7jRRiNdhDSK90/9/Rw/pJVmZZ8gSCAKwkReC1cvTWoN3bu +cEeqgAdmZnktJ2/eVG4XuToWCIP07rOfRHo2dJs55whAqemsunBK81wBPUjPp/MuzvsW3Ne4sxXh +2MddwLxiFdiIxUC1L6QIAd39ExyHT1cCuIe1DlzRIefO0YVh9z357FFQaKCIFKz7sKBPkxHxFO0R +u6N7OpLORltsL8T8zZveD14kAPKUNi+08zywnrwNhSpZsxW/kKk2iQyWOktYqevjFX5BinzP49KO +e6PPf/ibRO4z5WVhQ7qtiqAhoPuXIlgXD4ytwCSTeq+jyfoJmU6x2yaMQmpOqoI75pYbgwjs4UPI +fRtyi1CkRzbKNtJwUuK0IsvtcCLXB4FzLg2JiuiAJugevynURzIpkliP5v1lgZeHWOlKPrFkfQln +DA95lpq6c3nlXchHTi7adRdD1gGqS+CeiNIU/I7UIulC71MJlOvaF+IdeyiAwaZ5olFJylgO7GR+ +NdpR2qsb9u6I41EF0/HvFWGOlLSI2E6qeiFnuMDJYQuOw/M8zyAHHlRAKKyAwucLJO5/0KtcepWP +MMWke3vuvrexepZP+EvM2Ed9MsommUZQBQ8nj95FgtkarA9B1B8MLFQFE58Qi6nfpcPOvvtER710 +V1HExChEdSIiLY8qUfwIwVDcDPbaYHUoWxK9ssm2RcTaC2v3YQUVQwZ/Iz1wUBUmrNzVwIJH0lsy +vUY3r3nGVHDtcwoYUdUvCbsZkgeeJTq4uoSXl5fXxaArtnxv4OkUUfijPqLHGb3uUtKigKE8TT7l +Pf0BbGheJrylMH4DxyDd2X/OUSyE2dXH7LioFFMZn5gTBFDLklc3TIBYqNdXJtJmFMPBnVEZYtc4 +y0E8p7fZOX7XChSTcXU/juTf7LrRDjIdXbqg8PA/XJFDkrjB8h2LWLSUC6hSj/YWJepyOfP5tmrE +PjE8QOE7ADz13P2gfg/X4ddzqwPpLm8PUghQbFD/Ynuy2lvf5Ni4DnamLXI2x2HnOEq2ClOTvHLB +iWXYTTUQ+DxcTlQu0arpqukzr7LUygwKgL44fMZUKS/nEg7odH6hmqti2FzgRLEUYXYHgLVRrcn0 +EZEBNnPBGXIStBRcDzfU6l+XSVIK1c3T6kQXd8PveY4tBwE8eZpRi7cK5uUXSdMz14qpMYwx4mV6 +58miGzBSk2a7wwEbYbL2ExVJAE1Ss5N0IkWIsxxp4dy+uePWlU0g4Uas+RMtD88QRL6KWYaCrJ9L +sW3hMuzCotooRSMs5vGx1ix7HkVb2koJ8hHXY1I6WzYZA6lp1K2PafQMupyRYlhvcgm6hKIK3TCx +H9f/hp5QaP+CaBLudEEQx52aet/8C6fyrbMHynKiuXCiLi1riO4QibEhPbcACpCGJxV8xIHkvXAy +Cn8Y+lQ4s7LSoKkOwOioqHt+/Pp2l34Ns5jxc/My3wEYHAmlaNiHcFiRjp260N7bnLmF1O4ZpwzE +YEYGSfsGBcFPF2Yjfmwa4Xy2LHAtCQFA0P0AsuFvFbxXqHdzu23efWGKs3n3FRXABTDwudGn3+Is +WvOxnqnh8i9rukrMDDZ3L+Fs9sKlL4tx0kQEZ9QIoAZipJlemjLjNzjtdEcCmf1GmgXSoEnqNx++ +NrCri52I5cnHYFJqSNibbjT9rnNVzlZqVxGh +`pragma protect end_protected +module DVI_TX_Top ( + I_rst_n, + I_serial_clk, + I_rgb_clk, + I_rgb_vs, + I_rgb_hs, + I_rgb_de, + I_rgb_r, + I_rgb_g, + I_rgb_b, + O_tmds_clk_p, + O_tmds_clk_n, + O_tmds_data_p, + O_tmds_data_n +) +; +input I_rst_n; +input I_serial_clk; +input I_rgb_clk; +input I_rgb_vs; +input I_rgb_hs; +input I_rgb_de; +input [7:0] I_rgb_r; +input [7:0] I_rgb_g; +input [7:0] I_rgb_b; +output O_tmds_clk_p; +output O_tmds_clk_n; +output [2:0] O_tmds_data_p; +output [2:0] O_tmds_data_n; +wire VCC; +wire GND; + \~rgb2dvi.DVI_TX_Top rgb2dvi_inst ( + .I_rgb_clk(I_rgb_clk), + .I_serial_clk(I_serial_clk), + .I_rst_n(I_rst_n), + .I_rgb_de(I_rgb_de), + .I_rgb_vs(I_rgb_vs), + .I_rgb_hs(I_rgb_hs), + .I_rgb_r(I_rgb_r[7:0]), + .I_rgb_g(I_rgb_g[7:0]), + .I_rgb_b(I_rgb_b[7:0]), + .O_tmds_clk_p(O_tmds_clk_p), + .O_tmds_clk_n(O_tmds_clk_n), + .O_tmds_data_p(O_tmds_data_p[2:0]), + .O_tmds_data_n(O_tmds_data_n[2:0]) +); + VCC VCC_cZ ( + .V(VCC) +); + GND GND_cZ ( + .G(GND) +); + GSR GSR ( + .GSRI(VCC) +); +endmodule /* DVI_TX_Top */ diff --git a/boards/tang_primer_20k_dock_alt/dvi_tx.vo b/boards/tang_primer_20k_dock_alt/dvi_tx.vo index 94258cc1..0fded162 100644 --- a/boards/tang_primer_20k_dock_alt/dvi_tx.vo +++ b/boards/tang_primer_20k_dock_alt/dvi_tx.vo @@ -1,3369 +1,3369 @@ -//Copyright (C)2014-2024 Gowin Semiconductor Corporation. -//All rights reserved. -//File Title: Post-PnR Simulation Model file -//Tool Version: V1.9.9.03 (64-bit) -//Created Time: Sun Jun 2 18:05:57 2024 - -`timescale 100 ps/100 ps -module DVI_TX_Top( - I_rst_n, - I_serial_clk, - I_rgb_clk, - I_rgb_vs, - I_rgb_hs, - I_rgb_de, - I_rgb_r, - I_rgb_g, - I_rgb_b, - O_tmds_clk_p, - O_tmds_clk_n, - O_tmds_data_p, - O_tmds_data_n -); -input I_rst_n; -input I_serial_clk; -input I_rgb_clk; -input I_rgb_vs; -input I_rgb_hs; -input I_rgb_de; -input [7:0] I_rgb_r; -input [7:0] I_rgb_g; -input [7:0] I_rgb_b; -output O_tmds_clk_p; -output O_tmds_clk_n; -output [2:0] O_tmds_data_p; -output [2:0] O_tmds_data_n; -wire GND; -wire [7:0] I_rgb_b; -wire I_rgb_clk; -wire I_rgb_de; -wire [7:0] I_rgb_g; -wire I_rgb_hs; -wire [7:0] I_rgb_r; -wire I_rgb_vs; -wire I_rst_n; -wire I_serial_clk; -wire O_tmds_clk_n; -wire O_tmds_clk_p; -wire [2:0] O_tmds_data_n; -wire [2:0] O_tmds_data_p; -wire VCC; -wire \rgb2dvi_inst/sdataout_r ; -wire \rgb2dvi_inst/sdataout_g ; -wire \rgb2dvi_inst/sdataout_b ; -wire \rgb2dvi_inst/sdataout_clk ; -wire \rgb2dvi_inst/n36_6 ; -wire \rgb2dvi_inst/de_d ; -wire \rgb2dvi_inst/c1_d ; -wire [9:0] \rgb2dvi_inst/q_out_r ; -wire [9:0] \rgb2dvi_inst/q_out_g ; -wire [9:0] \rgb2dvi_inst/q_out_b ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n132_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_1_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n364_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n236_5_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ; -wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit ; -wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_r/din_d ; -wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_r/cnt ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n132_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_1_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n364_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n236_5_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ; -wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit ; -wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_g/din_d ; -wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_g/cnt ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n132_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_1_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n364_0_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n236_5_COUT ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ; -wire \rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ; -wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit ; -wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_b/din_d ; -wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_b/cnt ; -VCC VCC_cZ ( - .V(VCC) -); -GND GND_cZ ( - .G(GND) -); -GSR GSR ( - .GSRI(VCC) -); -ELVDS_OBUF \rgb2dvi_inst/u_LVDS_r ( - .I(\rgb2dvi_inst/sdataout_r ), - .O(O_tmds_data_p[2]), - .OB(O_tmds_data_n[2]) -); -ELVDS_OBUF \rgb2dvi_inst/u_LVDS_g ( - .I(\rgb2dvi_inst/sdataout_g ), - .O(O_tmds_data_p[1]), - .OB(O_tmds_data_n[1]) -); -ELVDS_OBUF \rgb2dvi_inst/u_LVDS_b ( - .I(\rgb2dvi_inst/sdataout_b ), - .O(O_tmds_data_p[0]), - .OB(O_tmds_data_n[0]) -); -ELVDS_OBUF \rgb2dvi_inst/u_LVDS_clk ( - .I(\rgb2dvi_inst/sdataout_clk ), - .O(O_tmds_clk_p), - .OB(O_tmds_clk_n) -); -OSER10 \rgb2dvi_inst/u_OSER10_r ( - .D0(\rgb2dvi_inst/q_out_r [0]), - .D1(\rgb2dvi_inst/q_out_r [1]), - .D2(\rgb2dvi_inst/q_out_r [2]), - .D3(\rgb2dvi_inst/q_out_r [3]), - .D4(\rgb2dvi_inst/q_out_r [4]), - .D5(\rgb2dvi_inst/q_out_r [5]), - .D6(\rgb2dvi_inst/q_out_r [6]), - .D7(\rgb2dvi_inst/q_out_r [7]), - .D8(\rgb2dvi_inst/q_out_r [8]), - .D9(\rgb2dvi_inst/q_out_r [9]), - .PCLK(I_rgb_clk), - .FCLK(I_serial_clk), - .RESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/sdataout_r ) -); -defparam \rgb2dvi_inst/u_OSER10_r .GSREN="false"; -defparam \rgb2dvi_inst/u_OSER10_r .LSREN="true"; -OSER10 \rgb2dvi_inst/u_OSER10_g ( - .D0(\rgb2dvi_inst/q_out_g [0]), - .D1(\rgb2dvi_inst/q_out_g [1]), - .D2(\rgb2dvi_inst/q_out_g [2]), - .D3(\rgb2dvi_inst/q_out_g [3]), - .D4(\rgb2dvi_inst/q_out_g [4]), - .D5(\rgb2dvi_inst/q_out_g [5]), - .D6(\rgb2dvi_inst/q_out_g [6]), - .D7(\rgb2dvi_inst/q_out_g [7]), - .D8(\rgb2dvi_inst/q_out_g [8]), - .D9(\rgb2dvi_inst/q_out_g [9]), - .PCLK(I_rgb_clk), - .FCLK(I_serial_clk), - .RESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/sdataout_g ) -); -defparam \rgb2dvi_inst/u_OSER10_g .GSREN="false"; -defparam \rgb2dvi_inst/u_OSER10_g .LSREN="true"; -OSER10 \rgb2dvi_inst/u_OSER10_b ( - .D0(\rgb2dvi_inst/q_out_b [0]), - .D1(\rgb2dvi_inst/q_out_b [1]), - .D2(\rgb2dvi_inst/q_out_b [2]), - .D3(\rgb2dvi_inst/q_out_b [3]), - .D4(\rgb2dvi_inst/q_out_b [4]), - .D5(\rgb2dvi_inst/q_out_b [5]), - .D6(\rgb2dvi_inst/q_out_b [6]), - .D7(\rgb2dvi_inst/q_out_b [7]), - .D8(\rgb2dvi_inst/q_out_b [8]), - .D9(\rgb2dvi_inst/q_out_b [9]), - .PCLK(I_rgb_clk), - .FCLK(I_serial_clk), - .RESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/sdataout_b ) -); -defparam \rgb2dvi_inst/u_OSER10_b .GSREN="false"; -defparam \rgb2dvi_inst/u_OSER10_b .LSREN="true"; -OSER10 \rgb2dvi_inst/u_OSER10_clk ( - .D0(GND), - .D1(GND), - .D2(GND), - .D3(GND), - .D4(GND), - .D5(VCC), - .D6(VCC), - .D7(VCC), - .D8(VCC), - .D9(VCC), - .PCLK(I_rgb_clk), - .FCLK(I_serial_clk), - .RESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/sdataout_clk ) -); -defparam \rgb2dvi_inst/u_OSER10_clk .GSREN="false"; -defparam \rgb2dvi_inst/u_OSER10_clk .LSREN="true"; -INV \rgb2dvi_inst/n36_s2 ( - .I(I_rst_n), - .O(\rgb2dvi_inst/n36_6 ) -); -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n274_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n274_s0 .INIT=8'h3A; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0 .INIT=8'hCA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0 ( - .I0(I_rgb_r[0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0 .INIT=16'hFCC4; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0 .INIT=16'h4F44; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0 .INIT=16'hF004; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n681_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n681_s1 .INIT=8'h35; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s0 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ), - .I1(\rgb2dvi_inst/c1_d ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15 .INIT=16'h71BE; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1 .INIT=16'hCA00; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1 .INIT=16'h3500; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1 .INIT=16'h3A00; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n403_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n403_s4 .INIT=4'h9; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n402_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n402_s4 .INIT=8'hE1; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1 .INIT=16'hE8FE; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2 ( - .I0(I_rgb_r[0]), - .I1(I_rgb_r[1]), - .I2(I_rgb_r[2]), - .I3(I_rgb_r[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2 .INIT=16'h8000; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3 ( - .I0(I_rgb_r[7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3 .INIT=8'hDB; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1 .INIT=16'h96D7; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2 .INIT=8'h01; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1 .INIT=16'h8E00; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1 .INIT=8'h14; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s2 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3 .INIT=8'h07; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s15 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15 .INIT=16'h6FF9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16 .INIT=16'h96AA; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16 .INIT=8'h0B; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s2 .INIT=16'hAAC3; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3 .INIT=16'hAA3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s4 ( - .I0(I_rgb_r[0]), - .I1(I_rgb_r[1]), - .I2(I_rgb_r[2]), - .I3(I_rgb_r[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s4 .INIT=16'h7EE8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s5 ( - .I0(I_rgb_r[3]), - .I1(I_rgb_r[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s5 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6 ( - .I0(I_rgb_r[6]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ), - .I2(I_rgb_r[3]), - .I3(I_rgb_r[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6 .INIT=16'h8EE8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8 ( - .I0(I_rgb_r[3]), - .I1(I_rgb_r[5]), - .I2(I_rgb_r[6]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s4 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5 .INIT=8'h96; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s3 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19 .INIT=16'h5A3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20 .INIT=16'hDD4B; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17 .INIT=16'h0002; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9 ( - .I0(I_rgb_r[0]), - .I1(I_rgb_r[1]), - .I2(I_rgb_r[2]), - .I3(I_rgb_r[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s22 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s22 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s16 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ), - .I1(I_rgb_r[3]), - .I2(I_rgb_r[5]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10 .INIT=16'h6A95; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6 .INIT=16'hEA15; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s4 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n401_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n401_s4 .INIT=16'hAAA9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s6 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s3 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s3 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s2 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s12 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s12 .INIT=16'h1001; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s23 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s23 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n680_s3 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n680_s3 .INIT=16'hFFD5; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2 .INIT=16'hA088; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s7 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s7 .INIT=16'h9669; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s4 .INIT=16'h6900; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_6_s0 ( - .D(I_rgb_r[6]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_5_s0 ( - .D(I_rgb_r[5]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_4_s0 ( - .D(I_rgb_r[4]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 ( - .D(I_rgb_r[3]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 ( - .D(I_rgb_r[2]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0 ( - .D(I_rgb_r[1]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 ( - .D(I_rgb_r[0]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/de_d_s0 ( - .D(I_rgb_de), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/de_d ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/de_d_s0 .INIT=1'b0; -DFFP \rgb2dvi_inst/TMDS8b10b_inst_r/c1_d_s0 ( - .D(GND), - .CLK(I_rgb_clk), - .PRESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/c1_d ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/c1_d_s0 .INIT=1'b1; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_9_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [9]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_9_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_8_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [8]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_8_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_7_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_7_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_5_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_r [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_7_s0 ( - .D(I_rgb_r[7]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_7_s0 .INIT=1'b0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n135_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n135_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n134_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n134_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n133_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n133_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n132_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n132_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s1 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_1_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n364_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n364_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s2 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n239_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n239_s6 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_5_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(VCC), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s3 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3 .ALU_MODE=1; -MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ), - .S0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), - .O(\rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ) -); -INV \rgb2dvi_inst/TMDS8b10b_inst_r/n404_s5 ( - .I(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), - .O(\rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ) -); -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n274_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n274_s0 .INIT=8'h3A; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0 .INIT=8'hCA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0 .INIT=8'hB2; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s0 .INIT=16'h1F11; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0 .INIT=16'hF004; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n681_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/c1_d ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n681_s1 .INIT=8'h53; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0 ( - .I0(\rgb2dvi_inst/c1_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ), - .I1(\rgb2dvi_inst/c1_d ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0 .INIT=8'hAC; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s13 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s13 .INIT=8'h96; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s11 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s11 .INIT=8'h01; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1 .INIT=16'hCA00; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1 .INIT=16'h3500; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1 .INIT=16'h3A00; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n403_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n403_s4 .INIT=4'h9; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n402_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n402_s4 .INIT=8'hE1; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1 ( - .I0(I_rgb_g[0]), - .I1(I_rgb_g[1]), - .I2(I_rgb_g[2]), - .I3(I_rgb_g[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1 .INIT=16'h8000; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2 ( - .I0(I_rgb_g[7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ), - .I3(I_rgb_g[0]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2 .INIT=16'h8100; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3 .INIT=16'hFDD4; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1 .INIT=16'hCFF5; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2 .INIT=16'h30A0; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s3 .INIT=8'h01; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1 .INIT=8'h14; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s2 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3 .INIT=8'h07; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s1 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15 .INIT=16'hF96F; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12 .INIT=16'hDD0F; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2 .INIT=16'hAAC3; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3 .INIT=16'hAA3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s4 ( - .I0(I_rgb_g[3]), - .I1(I_rgb_g[5]), - .I2(I_rgb_g[6]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s4 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6 ( - .I0(I_rgb_g[6]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ), - .I2(I_rgb_g[3]), - .I3(I_rgb_g[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6 .INIT=16'h7117; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s7 ( - .I0(I_rgb_g[0]), - .I1(I_rgb_g[1]), - .I2(I_rgb_g[2]), - .I3(I_rgb_g[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s7 .INIT=16'h7EE8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8 ( - .I0(I_rgb_g[3]), - .I1(I_rgb_g[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8 .INIT=4'h8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ), - .I1(I_rgb_g[7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s4 .INIT=16'hACCA; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s6 .INIT=8'h96; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s3 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s15 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17 .INIT=16'h5A3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18 .INIT=16'hDD4B; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10 ( - .I0(I_rgb_g[0]), - .I1(I_rgb_g[1]), - .I2(I_rgb_g[2]), - .I3(I_rgb_g[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s5 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s16 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s11 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ), - .I2(I_rgb_g[3]), - .I3(I_rgb_g[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s11 .INIT=16'h6999; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6 .INIT=16'hEA15; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s4 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n401_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n401_s4 .INIT=16'hAAA9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s3 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16 .INIT=16'h5554; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s7 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s7 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n680_s3 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n680_s3 .INIT=16'hFFD5; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2 .INIT=16'hA088; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7 .INIT=16'h9669; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_6_s0 ( - .D(I_rgb_g[6]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_5_s0 ( - .D(I_rgb_g[5]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_4_s0 ( - .D(I_rgb_g[4]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 ( - .D(I_rgb_g[3]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 ( - .D(I_rgb_g[2]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 ( - .D(I_rgb_g[1]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 ( - .D(I_rgb_g[0]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_9_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [9]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_9_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_8_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [8]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_8_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_g [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0 ( - .D(I_rgb_g[7]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0 .INIT=1'b0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n135_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n135_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n134_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n134_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n133_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n133_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n132_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n132_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s1 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_1_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n364_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n364_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s2 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n239_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n239_s6 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_5_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), - .I3(GND), - .CIN(VCC), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s3 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3 .ALU_MODE=1; -MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ), - .S0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), - .O(\rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ) -); -INV \rgb2dvi_inst/TMDS8b10b_inst_g/n404_s5 ( - .I(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), - .O(\rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ) -); -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n274_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n274_s0 .INIT=8'h3A; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0 .INIT=8'hCA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0 .INIT=8'hB2; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0 .INIT=16'h4F44; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0 .INIT=16'hFFE0; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0 .INIT=16'h55C3; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n681_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n681_s1 .INIT=8'h35; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0 .INIT=16'hC3AA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1 .INIT=16'hC355; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ), - .I2(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0 .INIT=8'hCA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15 .INIT=16'hDC2B; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1 .INIT=16'hCA00; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1 .INIT=16'h3500; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I3(\rgb2dvi_inst/de_d ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1 .INIT=16'h3A00; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n403_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n403_s4 .INIT=4'h9; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n402_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n402_s4 .INIT=8'hE1; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1 ( - .I0(I_rgb_b[0]), - .I1(I_rgb_b[1]), - .I2(I_rgb_b[2]), - .I3(I_rgb_b[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1 .INIT=16'h8000; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2 ( - .I0(I_rgb_b[7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ), - .I3(I_rgb_b[0]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2 .INIT=16'h8100; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3 .INIT=16'hFDD4; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1 .INIT=16'h7EBD; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s2 .INIT=8'h01; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s1 .INIT=16'h000D; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s2 .INIT=8'h20; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1 .INIT=8'h07; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1 .INIT=8'h14; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s14 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s14 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s15 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16 .INIT=16'h6FF9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16 .INIT=16'hD728; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s18 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s18 .INIT=16'hC3AA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s3 .INIT=16'h3CAA; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2 .INIT=8'hAC; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3 .INIT=16'h3CAA; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2 .INIT=16'hAAC3; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3 .INIT=16'hAA3C; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s4 ( - .I0(I_rgb_b[3]), - .I1(I_rgb_b[5]), - .I2(I_rgb_b[6]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s4 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6 ( - .I0(I_rgb_b[6]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ), - .I2(I_rgb_b[3]), - .I3(I_rgb_b[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6 .INIT=16'h7117; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s7 ( - .I0(I_rgb_b[0]), - .I1(I_rgb_b[1]), - .I2(I_rgb_b[2]), - .I3(I_rgb_b[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s7 .INIT=16'h7EE8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8 ( - .I0(I_rgb_b[3]), - .I1(I_rgb_b[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8 .INIT=4'h8; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ), - .I1(I_rgb_b[7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s3 .INIT=16'h4DD4; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4 .INIT=8'h96; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17 .INIT=16'h0096; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18 .INIT=16'h5A3C; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s19 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s19 .INIT=4'h6; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s20 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s20 .INIT=8'hC5; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4 .INIT=4'h8; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10 ( - .I0(I_rgb_b[0]), - .I1(I_rgb_b[1]), - .I2(I_rgb_b[2]), - .I3(I_rgb_b[4]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10 .INIT=16'h6996; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_3_s12 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_3_s12 .INIT=16'h4004; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s11 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ), - .I2(I_rgb_b[3]), - .I3(I_rgb_b[5]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s11 .INIT=16'h6999; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6 .INIT=16'hEA15; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s4 .INIT=8'h96; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s16 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s16 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n401_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n401_s4 .INIT=16'hAAA9; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s3 .INIT=16'h6996; -LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s3 .INIT=8'h96; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s2 .INIT=16'h6996; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2 ( - .I0(\rgb2dvi_inst/de_d ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2 .INIT=16'hA088; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s2 .INIT=4'h6; -LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1 .INIT=4'h6; -LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ), - .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ), - .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7 .INIT=16'h9669; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_6_s0 ( - .D(I_rgb_b[6]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_5_s0 ( - .D(I_rgb_b[5]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_4_s0 ( - .D(I_rgb_b[4]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 ( - .D(I_rgb_b[3]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 ( - .D(I_rgb_b[2]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0 ( - .D(I_rgb_b[1]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 ( - .D(I_rgb_b[0]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 .INIT=1'b0; -DFFP \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 ( - .D(I_rgb_vs), - .CLK(I_rgb_clk), - .PRESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 .INIT=1'b1; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [9]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [8]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [6]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [5]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [4]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [3]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [2]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [1]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0 ( - .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/q_out_b [0]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0 .INIT=1'b0; -DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0 ( - .D(I_rgb_b[7]), - .CLK(I_rgb_clk), - .CLEAR(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0 .INIT=1'b0; -DFFP \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0 ( - .D(I_rgb_hs), - .CLK(I_rgb_clk), - .PRESET(\rgb2dvi_inst/n36_6 ), - .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0 .INIT=1'b1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n135_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n135_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n134_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n134_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n133_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n133_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n132_s ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n132_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s1 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s1 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_1_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s0 .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n364_s ( - .I0(GND), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_0_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n364_s .ALU_MODE=0; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s2 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s2 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n239_s6 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n239_s6 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_5_COUT ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s4 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), - .I3(GND), - .CIN(GND), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s4 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s5 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), - .I3(GND), - .CIN(VCC), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s5 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s3 .ALU_MODE=1; -ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s3 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), - .I3(GND), - .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ), - .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ), - .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ) -); -defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s3 .ALU_MODE=1; -MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s0 ( - .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ), - .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ), - .S0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), - .O(\rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ) -); -INV \rgb2dvi_inst/TMDS8b10b_inst_b/n404_s5 ( - .I(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), - .O(\rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ) -); -endmodule +//Copyright (C)2014-2024 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: Post-PnR Simulation Model file +//Tool Version: V1.9.9.03 (64-bit) +//Created Time: Sun Jun 2 18:05:57 2024 + +`timescale 100 ps/100 ps +module DVI_TX_Top( + I_rst_n, + I_serial_clk, + I_rgb_clk, + I_rgb_vs, + I_rgb_hs, + I_rgb_de, + I_rgb_r, + I_rgb_g, + I_rgb_b, + O_tmds_clk_p, + O_tmds_clk_n, + O_tmds_data_p, + O_tmds_data_n +); +input I_rst_n; +input I_serial_clk; +input I_rgb_clk; +input I_rgb_vs; +input I_rgb_hs; +input I_rgb_de; +input [7:0] I_rgb_r; +input [7:0] I_rgb_g; +input [7:0] I_rgb_b; +output O_tmds_clk_p; +output O_tmds_clk_n; +output [2:0] O_tmds_data_p; +output [2:0] O_tmds_data_n; +wire GND; +wire [7:0] I_rgb_b; +wire I_rgb_clk; +wire I_rgb_de; +wire [7:0] I_rgb_g; +wire I_rgb_hs; +wire [7:0] I_rgb_r; +wire I_rgb_vs; +wire I_rst_n; +wire I_serial_clk; +wire O_tmds_clk_n; +wire O_tmds_clk_p; +wire [2:0] O_tmds_data_n; +wire [2:0] O_tmds_data_p; +wire VCC; +wire \rgb2dvi_inst/sdataout_r ; +wire \rgb2dvi_inst/sdataout_g ; +wire \rgb2dvi_inst/sdataout_b ; +wire \rgb2dvi_inst/sdataout_clk ; +wire \rgb2dvi_inst/n36_6 ; +wire \rgb2dvi_inst/de_d ; +wire \rgb2dvi_inst/c1_d ; +wire [9:0] \rgb2dvi_inst/q_out_r ; +wire [9:0] \rgb2dvi_inst/q_out_g ; +wire [9:0] \rgb2dvi_inst/q_out_b ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n132_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n558_1_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n364_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n236_5_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ; +wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit ; +wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_r/din_d ; +wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_r/cnt ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n132_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n558_1_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n364_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n236_5_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ; +wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit ; +wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_g/din_d ; +wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_g/cnt ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n132_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n558_1_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n364_0_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n236_5_COUT ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ; +wire \rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ; +wire [3:1] \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit ; +wire [7:0] \rgb2dvi_inst/TMDS8b10b_inst_b/din_d ; +wire [4:1] \rgb2dvi_inst/TMDS8b10b_inst_b/cnt ; +VCC VCC_cZ ( + .V(VCC) +); +GND GND_cZ ( + .G(GND) +); +GSR GSR ( + .GSRI(VCC) +); +ELVDS_OBUF \rgb2dvi_inst/u_LVDS_r ( + .I(\rgb2dvi_inst/sdataout_r ), + .O(O_tmds_data_p[2]), + .OB(O_tmds_data_n[2]) +); +ELVDS_OBUF \rgb2dvi_inst/u_LVDS_g ( + .I(\rgb2dvi_inst/sdataout_g ), + .O(O_tmds_data_p[1]), + .OB(O_tmds_data_n[1]) +); +ELVDS_OBUF \rgb2dvi_inst/u_LVDS_b ( + .I(\rgb2dvi_inst/sdataout_b ), + .O(O_tmds_data_p[0]), + .OB(O_tmds_data_n[0]) +); +ELVDS_OBUF \rgb2dvi_inst/u_LVDS_clk ( + .I(\rgb2dvi_inst/sdataout_clk ), + .O(O_tmds_clk_p), + .OB(O_tmds_clk_n) +); +OSER10 \rgb2dvi_inst/u_OSER10_r ( + .D0(\rgb2dvi_inst/q_out_r [0]), + .D1(\rgb2dvi_inst/q_out_r [1]), + .D2(\rgb2dvi_inst/q_out_r [2]), + .D3(\rgb2dvi_inst/q_out_r [3]), + .D4(\rgb2dvi_inst/q_out_r [4]), + .D5(\rgb2dvi_inst/q_out_r [5]), + .D6(\rgb2dvi_inst/q_out_r [6]), + .D7(\rgb2dvi_inst/q_out_r [7]), + .D8(\rgb2dvi_inst/q_out_r [8]), + .D9(\rgb2dvi_inst/q_out_r [9]), + .PCLK(I_rgb_clk), + .FCLK(I_serial_clk), + .RESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/sdataout_r ) +); +defparam \rgb2dvi_inst/u_OSER10_r .GSREN="false"; +defparam \rgb2dvi_inst/u_OSER10_r .LSREN="true"; +OSER10 \rgb2dvi_inst/u_OSER10_g ( + .D0(\rgb2dvi_inst/q_out_g [0]), + .D1(\rgb2dvi_inst/q_out_g [1]), + .D2(\rgb2dvi_inst/q_out_g [2]), + .D3(\rgb2dvi_inst/q_out_g [3]), + .D4(\rgb2dvi_inst/q_out_g [4]), + .D5(\rgb2dvi_inst/q_out_g [5]), + .D6(\rgb2dvi_inst/q_out_g [6]), + .D7(\rgb2dvi_inst/q_out_g [7]), + .D8(\rgb2dvi_inst/q_out_g [8]), + .D9(\rgb2dvi_inst/q_out_g [9]), + .PCLK(I_rgb_clk), + .FCLK(I_serial_clk), + .RESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/sdataout_g ) +); +defparam \rgb2dvi_inst/u_OSER10_g .GSREN="false"; +defparam \rgb2dvi_inst/u_OSER10_g .LSREN="true"; +OSER10 \rgb2dvi_inst/u_OSER10_b ( + .D0(\rgb2dvi_inst/q_out_b [0]), + .D1(\rgb2dvi_inst/q_out_b [1]), + .D2(\rgb2dvi_inst/q_out_b [2]), + .D3(\rgb2dvi_inst/q_out_b [3]), + .D4(\rgb2dvi_inst/q_out_b [4]), + .D5(\rgb2dvi_inst/q_out_b [5]), + .D6(\rgb2dvi_inst/q_out_b [6]), + .D7(\rgb2dvi_inst/q_out_b [7]), + .D8(\rgb2dvi_inst/q_out_b [8]), + .D9(\rgb2dvi_inst/q_out_b [9]), + .PCLK(I_rgb_clk), + .FCLK(I_serial_clk), + .RESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/sdataout_b ) +); +defparam \rgb2dvi_inst/u_OSER10_b .GSREN="false"; +defparam \rgb2dvi_inst/u_OSER10_b .LSREN="true"; +OSER10 \rgb2dvi_inst/u_OSER10_clk ( + .D0(GND), + .D1(GND), + .D2(GND), + .D3(GND), + .D4(GND), + .D5(VCC), + .D6(VCC), + .D7(VCC), + .D8(VCC), + .D9(VCC), + .PCLK(I_rgb_clk), + .FCLK(I_serial_clk), + .RESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/sdataout_clk ) +); +defparam \rgb2dvi_inst/u_OSER10_clk .GSREN="false"; +defparam \rgb2dvi_inst/u_OSER10_clk .LSREN="true"; +INV \rgb2dvi_inst/n36_s2 ( + .I(I_rst_n), + .O(\rgb2dvi_inst/n36_6 ) +); +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n274_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n274_s0 .INIT=8'h3A; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n596_s0 .INIT=8'hCA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0 ( + .I0(I_rgb_r[0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0 .INIT=16'hFCC4; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s0 .INIT=16'h4F44; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s0 .INIT=16'hF004; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n681_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n681_s1 .INIT=8'h35; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s0 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s0 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ), + .I1(\rgb2dvi_inst/c1_d ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n689_s0 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15 .INIT=16'h71BE; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1 .INIT=16'hCA00; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1 .INIT=16'h3500; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1 .INIT=16'h3A00; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n403_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n403_s4 .INIT=4'h9; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n402_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n402_s4 .INIT=8'hE1; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s1 .INIT=16'hE8FE; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2 ( + .I0(I_rgb_r[0]), + .I1(I_rgb_r[1]), + .I2(I_rgb_r[2]), + .I3(I_rgb_r[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2 .INIT=16'h8000; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3 ( + .I0(I_rgb_r[7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3 .INIT=8'hDB; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s1 .INIT=16'h96D7; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s2 .INIT=8'h01; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n653_s1 .INIT=16'h8E00; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s1 .INIT=8'h14; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n682_s2 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s3 .INIT=8'h07; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s14 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s15 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_20 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15 .INIT=16'h6FF9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16 .INIT=16'h96AA; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s17 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s16 .INIT=8'h0B; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s2 .INIT=16'hAAC3; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3 .INIT=16'hAA3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s4 ( + .I0(I_rgb_r[0]), + .I1(I_rgb_r[1]), + .I2(I_rgb_r[2]), + .I3(I_rgb_r[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s4 .INIT=16'h7EE8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s5 ( + .I0(I_rgb_r[3]), + .I1(I_rgb_r[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s5 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6 ( + .I0(I_rgb_r[6]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ), + .I2(I_rgb_r[3]), + .I3(I_rgb_r[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s6 .INIT=16'h8EE8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8 ( + .I0(I_rgb_r[3]), + .I1(I_rgb_r[5]), + .I2(I_rgb_r[6]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s4 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s5 .INIT=8'h96; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s3 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19 .INIT=16'h5A3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20 .INIT=16'hDD4B; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_24 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17 .INIT=16'h0002; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n604_s4 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9 ( + .I0(I_rgb_r[0]), + .I1(I_rgb_r[1]), + .I2(I_rgb_r[2]), + .I3(I_rgb_r[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_27 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s21 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s22 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_28 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s22 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_s16 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_8 ), + .I1(I_rgb_r[3]), + .I2(I_rgb_r[5]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_10 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10 .INIT=16'h6A95; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6 .INIT=16'hEA15; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n685_s4 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n401_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n401_s4 .INIT=16'hAAA9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n683_s6 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_4 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n686_s3 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n687_s3 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n684_s2 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s12 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s12 .INIT=16'h1001; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s23 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_22 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_25 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s23 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n680_s3 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n680_s3 .INIT=16'hFFD5; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n596_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n274_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n606_s2 .INIT=16'hA088; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s7 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_14 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n603_s7 .INIT=16'h9669; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_19 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_21 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n630_s4 .INIT=16'h6900; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_6_s0 ( + .D(I_rgb_r[6]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_5_s0 ( + .D(I_rgb_r[5]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_4_s0 ( + .D(I_rgb_r[4]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 ( + .D(I_rgb_r[3]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 ( + .D(I_rgb_r[2]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0 ( + .D(I_rgb_r[1]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 ( + .D(I_rgb_r[0]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/de_d_s0 ( + .D(I_rgb_de), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/de_d ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/de_d_s0 .INIT=1'b0; +DFFP \rgb2dvi_inst/TMDS8b10b_inst_r/c1_d_s0 ( + .D(GND), + .CLK(I_rgb_clk), + .PRESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/c1_d ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/c1_d_s0 .INIT=1'b1; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n114_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n603_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n604_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n605_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n606_7 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/cnt_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_9_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n680_8 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [9]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_9_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_8_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n681_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [8]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_8_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_7_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n682_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_7_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n683_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_5_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n684_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n685_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n686_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n687_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n688_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_r/n689_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_r [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_7_s0 ( + .D(I_rgb_r[7]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_r/din_d [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/din_d_7_s0 .INIT=1'b0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n135_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n135_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n134_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n135_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n134_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n133_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n134_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n133_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n132_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n133_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n132_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n132_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n403_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n402_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n401_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s1 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_6 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n560_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n560_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n559_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n559_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_1_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n558_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n558_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n364_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n364_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n364_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_8 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n561_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n561_s2 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n239_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n239_s6 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n239_14 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n238_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n237_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_5_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n236_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(VCC), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_16 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n367_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n367_15 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n366_s3 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_r/n366_11 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_r/n365_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3 .ALU_MODE=1; +MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_r/n679_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_r/n670_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_r/n647_6 ), + .S0(\rgb2dvi_inst/TMDS8b10b_inst_r/n630_3 ), + .O(\rgb2dvi_inst/TMDS8b10b_inst_r/n679_3 ) +); +INV \rgb2dvi_inst/TMDS8b10b_inst_r/n404_s5 ( + .I(\rgb2dvi_inst/TMDS8b10b_inst_r/cnt [1]), + .O(\rgb2dvi_inst/TMDS8b10b_inst_r/n404_10 ) +); +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n274_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n274_s0 .INIT=8'h3A; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0 .INIT=8'hCA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0 .INIT=8'hB2; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s0 .INIT=16'h1F11; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0 .INIT=16'hF004; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n681_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/c1_d ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n681_s1 .INIT=8'h53; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s0 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0 ( + .I0(\rgb2dvi_inst/c1_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ), + .I1(\rgb2dvi_inst/c1_d ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n689_s0 .INIT=8'hAC; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s13 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s13 .INIT=8'h96; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s11 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s11 .INIT=8'h01; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1 .INIT=16'hCA00; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1 .INIT=16'h3500; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1 .INIT=16'h3A00; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n403_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n403_s4 .INIT=4'h9; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n402_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n402_s4 .INIT=8'hE1; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1 ( + .I0(I_rgb_g[0]), + .I1(I_rgb_g[1]), + .I2(I_rgb_g[2]), + .I3(I_rgb_g[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s1 .INIT=16'h8000; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2 ( + .I0(I_rgb_g[7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ), + .I3(I_rgb_g[0]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2 .INIT=16'h8100; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3 .INIT=16'hFDD4; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1 .INIT=16'hCFF5; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2 .INIT=16'h30A0; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s3 .INIT=8'h01; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1 .INIT=8'h14; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n682_s2 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s3 .INIT=8'h07; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n684_s1 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15 .INIT=16'hF96F; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s16 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12 .INIT=16'hDD0F; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2 .INIT=16'hAAC3; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3 .INIT=16'hAA3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s4 ( + .I0(I_rgb_g[3]), + .I1(I_rgb_g[5]), + .I2(I_rgb_g[6]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s4 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6 ( + .I0(I_rgb_g[6]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ), + .I2(I_rgb_g[3]), + .I3(I_rgb_g[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6 .INIT=16'h7117; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s7 ( + .I0(I_rgb_g[0]), + .I1(I_rgb_g[1]), + .I2(I_rgb_g[2]), + .I3(I_rgb_g[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s7 .INIT=16'h7EE8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8 ( + .I0(I_rgb_g[3]), + .I1(I_rgb_g[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8 .INIT=4'h8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_7 ), + .I1(I_rgb_g[7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s9 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s4 .INIT=16'hACCA; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s5 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s6 .INIT=8'h96; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s3 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s15 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17 .INIT=16'h5A3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_20 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18 .INIT=16'hDD4B; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n604_s4 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10 ( + .I0(I_rgb_g[0]), + .I1(I_rgb_g[1]), + .I2(I_rgb_g[2]), + .I3(I_rgb_g[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s10 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n630_s5 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_25 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_s16 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s11 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_10 ), + .I2(I_rgb_g[3]), + .I3(I_rgb_g[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n114_s11 .INIT=16'h6999; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6 .INIT=16'hEA15; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n685_s4 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n401_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n401_s4 .INIT=16'hAAA9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s20 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n687_s3 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n686_s2 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_21 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16 .INIT=16'h5554; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s7 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_9 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n683_s7 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n680_s3 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n680_s3 .INIT=16'hFFD5; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n596_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n274_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2 .INIT=16'hA088; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7 .INIT=16'h9669; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_6_s0 ( + .D(I_rgb_g[6]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_5_s0 ( + .D(I_rgb_g[5]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_4_s0 ( + .D(I_rgb_g[4]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 ( + .D(I_rgb_g[3]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 ( + .D(I_rgb_g[2]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 ( + .D(I_rgb_g[1]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 ( + .D(I_rgb_g[0]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n114_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n603_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n604_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n605_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n606_7 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_9_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n680_8 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [9]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_9_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_8_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n681_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [8]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_8_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n682_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_7_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n683_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n684_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n685_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n686_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n687_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n688_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_g/n689_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_g [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/dout_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0 ( + .D(I_rgb_g[7]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_g/din_d [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/din_d_7_s0 .INIT=1'b0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n135_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n135_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n134_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n135_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n134_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n133_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n134_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n133_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n132_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n133_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n132_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n132_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n403_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n402_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n401_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s1 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_6 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n560_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n560_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n559_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_1_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n558_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n558_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n364_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n364_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n364_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_8 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n561_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n561_s2 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n239_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n239_s6 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n239_14 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n238_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n237_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_5_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n236_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_0_18 ), + .I3(GND), + .CIN(VCC), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_16 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n367_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n367_15 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n366_s3 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_g/n366_11 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_g/n365_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_g/n365_s3 .ALU_MODE=1; +MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_g/n679_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_g/n670_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_g/n647_5 ), + .S0(\rgb2dvi_inst/TMDS8b10b_inst_g/n630_3 ), + .O(\rgb2dvi_inst/TMDS8b10b_inst_g/n679_3 ) +); +INV \rgb2dvi_inst/TMDS8b10b_inst_g/n404_s5 ( + .I(\rgb2dvi_inst/TMDS8b10b_inst_g/cnt [1]), + .O(\rgb2dvi_inst/TMDS8b10b_inst_g/n404_10 ) +); +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n274_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n274_s0 .INIT=8'h3A; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n596_s0 .INIT=8'hCA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0 .INIT=8'hB2; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s0 .INIT=16'h4F44; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0 .INIT=16'hFFE0; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s0 .INIT=16'h55C3; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n681_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n681_s1 .INIT=8'h35; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s0 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s0 .INIT=16'hC3AA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s1 .INIT=16'hC355; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s0 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ), + .I2(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n689_s0 .INIT=8'hCA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15 .INIT=16'hDC2B; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s1 .INIT=16'hCA00; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1 .INIT=16'h3500; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I3(\rgb2dvi_inst/de_d ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1 .INIT=16'h3A00; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n403_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n403_s4 .INIT=4'h9; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n402_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n402_s4 .INIT=8'hE1; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1 ( + .I0(I_rgb_b[0]), + .I1(I_rgb_b[1]), + .I2(I_rgb_b[2]), + .I3(I_rgb_b[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s1 .INIT=16'h8000; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2 ( + .I0(I_rgb_b[7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ), + .I3(I_rgb_b[0]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2 .INIT=16'h8100; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3 .INIT=16'hFDD4; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1 .INIT=16'h7EBD; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n630_s2 .INIT=8'h01; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_5 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s1 .INIT=16'h000D; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s2 .INIT=8'h20; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1 .INIT=8'h07; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s1 .INIT=8'h14; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n682_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n688_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s14 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s14 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s15 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_21 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_20 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s16 .INIT=16'h6FF9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s16 .INIT=16'hD728; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s17 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s18 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s18 .INIT=16'hC3AA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n605_s3 .INIT=16'h3CAA; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2 .INIT=8'hAC; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3 .INIT=16'h3CAA; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2 .INIT=16'hAAC3; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3 .INIT=16'hAA3C; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s4 ( + .I0(I_rgb_b[3]), + .I1(I_rgb_b[5]), + .I2(I_rgb_b[6]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s4 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6 ( + .I0(I_rgb_b[6]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ), + .I2(I_rgb_b[3]), + .I3(I_rgb_b[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6 .INIT=16'h7117; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s7 ( + .I0(I_rgb_b[0]), + .I1(I_rgb_b[1]), + .I2(I_rgb_b[2]), + .I3(I_rgb_b[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s7 .INIT=16'h7EE8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8 ( + .I0(I_rgb_b[3]), + .I1(I_rgb_b[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8 .INIT=4'h8; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_7 ), + .I1(I_rgb_b[7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s9 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n653_s3 .INIT=16'h4DD4; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4 .INIT=8'h96; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s3 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s2 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_5 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s17 .INIT=16'h0096; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_6 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18 .INIT=16'h5A3C; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s19 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_26 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s19 .INIT=4'h6; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s20 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_27 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s20 .INIT=8'hC5; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4 .INIT=4'h8; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10 ( + .I0(I_rgb_b[0]), + .I1(I_rgb_b[1]), + .I2(I_rgb_b[2]), + .I3(I_rgb_b[4]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s10 .INIT=16'h6996; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_25 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s19 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_23 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_3_s12 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_22 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_25 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_23 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_24 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_3_s12 .INIT=16'h4004; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s11 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_10 ), + .I2(I_rgb_b[3]), + .I3(I_rgb_b[5]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n114_s11 .INIT=16'h6999; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6 .INIT=16'hEA15; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_8 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n685_s4 .INIT=8'h96; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s16 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_19 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_s16 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n401_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n401_s4 .INIT=16'hAAA9; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n683_s5 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_4 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n686_s3 .INIT=16'h6996; +LUT3 \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n687_s3 .INIT=8'h96; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_6 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_6 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n684_s2 .INIT=16'h6996; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2 ( + .I0(\rgb2dvi_inst/de_d ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n596_2 ), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n274_2 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n606_s2 .INIT=16'hA088; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s2 .INIT=4'h6; +LUT2 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n653_3 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s1 .INIT=4'h6; +LUT4 \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I2(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ), + .I3(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ), + .F(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7 .INIT=16'h9669; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_6_s0 ( + .D(I_rgb_b[6]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_5_s0 ( + .D(I_rgb_b[5]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_4_s0 ( + .D(I_rgb_b[4]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 ( + .D(I_rgb_b[3]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 ( + .D(I_rgb_b[2]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0 ( + .D(I_rgb_b[1]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 ( + .D(I_rgb_b[0]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0 .INIT=1'b0; +DFFP \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 ( + .D(I_rgb_vs), + .CLK(I_rgb_clk), + .PRESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/c1_d ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 .INIT=1'b1; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n114_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n603_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n604_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n605_5 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n606_7 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n680_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [9]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n681_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [8]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n682_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n683_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [6]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n684_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [5]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n685_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [4]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n686_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [3]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n687_4 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [2]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n688_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [1]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0 ( + .D(\rgb2dvi_inst/TMDS8b10b_inst_b/n689_3 ), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/q_out_b [0]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0 .INIT=1'b0; +DFFC \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0 ( + .D(I_rgb_b[7]), + .CLK(I_rgb_clk), + .CLEAR(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/din_d [7]) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0 .INIT=1'b0; +DFFP \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0 ( + .D(I_rgb_hs), + .CLK(I_rgb_clk), + .PRESET(\rgb2dvi_inst/n36_6 ), + .Q(\rgb2dvi_inst/TMDS8b10b_inst_b/c0_d ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0 .INIT=1'b1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n135_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n135_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n134_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n135_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n134_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n133_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n134_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n133_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n132_s ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n133_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n132_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n132_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n403_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n402_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n401_10 ), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_3 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s1 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_5 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s1 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_6 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n560_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_2 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n559_5 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_1_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n558_4 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n558_s0 .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n364_s ( + .I0(GND), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_4 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_0_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n364_3 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n364_s .ALU_MODE=0; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s2 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_8 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n561_9 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n561_s2 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n239_s6 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_15 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n239_s6 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [2]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n239_14 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [3]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n238_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [4]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [3]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n237_12 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_5_COUT ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n236_11 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s4 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor ), + .I3(GND), + .CIN(GND), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_12 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s4 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s5 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_13 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_0_22 ), + .I3(GND), + .CIN(VCC), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_16 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n367_s5 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [1]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n367_15 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n366_s3 .ALU_MODE=1; +ALU \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s3 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_3 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit [2]), + .I3(GND), + .CIN(\rgb2dvi_inst/TMDS8b10b_inst_b/n366_11 ), + .COUT(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_11 ), + .SUM(\rgb2dvi_inst/TMDS8b10b_inst_b/n365_12 ) +); +defparam \rgb2dvi_inst/TMDS8b10b_inst_b/n365_s3 .ALU_MODE=1; +MUX2_LUT5 \rgb2dvi_inst/TMDS8b10b_inst_b/n679_s0 ( + .I0(\rgb2dvi_inst/TMDS8b10b_inst_b/n670_5 ), + .I1(\rgb2dvi_inst/TMDS8b10b_inst_b/n647_5 ), + .S0(\rgb2dvi_inst/TMDS8b10b_inst_b/n630_3 ), + .O(\rgb2dvi_inst/TMDS8b10b_inst_b/n679_3 ) +); +INV \rgb2dvi_inst/TMDS8b10b_inst_b/n404_s5 ( + .I(\rgb2dvi_inst/TMDS8b10b_inst_b/cnt [1]), + .O(\rgb2dvi_inst/TMDS8b10b_inst_b/n404_10 ) +); +endmodule diff --git a/boards/tang_primer_20k_dock_alt/gowin_rpll.ipc b/boards/tang_primer_20k_dock_alt/gowin_rpll.ipc index 9cda9a9b..81b9b468 100644 --- a/boards/tang_primer_20k_dock_alt/gowin_rpll.ipc +++ b/boards/tang_primer_20k_dock_alt/gowin_rpll.ipc @@ -1,24 +1,24 @@ -[General] -ipc_version=4 -file=gowin_rpll -module=Gowin_rPLL -target_device=gw2a18c-011 -type=clock_rpll -version=1.0 - -[Config] -CKLOUTD3=false -CLKFB_SOURCE=0 -CLKIN_FREQ=27 -CLKOUTD=false -CLKOUTP=false -CLKOUT_BYPASS=false -CLKOUT_DIVIDE_DYN=true -CLKOUT_FREQ=125 -CLKOUT_TOLERANCE=1 -DYNAMIC=false -LANG=0 -LOCK_EN=true -MODE_GENERAL=true -PLL_PWD=false -RESET_PLL=false +[General] +ipc_version=4 +file=gowin_rpll +module=Gowin_rPLL +target_device=gw2a18c-011 +type=clock_rpll +version=1.0 + +[Config] +CKLOUTD3=false +CLKFB_SOURCE=0 +CLKIN_FREQ=27 +CLKOUTD=false +CLKOUTP=false +CLKOUT_BYPASS=false +CLKOUT_DIVIDE_DYN=true +CLKOUT_FREQ=125 +CLKOUT_TOLERANCE=1 +DYNAMIC=false +LANG=0 +LOCK_EN=true +MODE_GENERAL=true +PLL_PWD=false +RESET_PLL=false diff --git a/boards/tang_primer_20k_dock_alt/gowin_rpll.mod b/boards/tang_primer_20k_dock_alt/gowin_rpll.mod index bb9adb5e..9978d778 100644 --- a/boards/tang_primer_20k_dock_alt/gowin_rpll.mod +++ b/boards/tang_primer_20k_dock_alt/gowin_rpll.mod @@ -1,32 +1,32 @@ --series GW2A --device GW2A-18 --device_version C --package PBGA256 --part_number GW2A-LV18PG256C8/I7 - - --mod_name Gowin_rPLL --file_name gowin_rpll --path E:/gw/basics-graphics-music/labs/06_vga/run/src/gowin_rpll/ --type PLL --rPll true --file_type vlg --dev_type GW2A-18C --dyn_idiv_sel false --idiv_sel 8 --dyn_fbdiv_sel false --fbdiv_sel 37 --dyn_odiv_sel false --odiv_sel 8 --dyn_da_en false --rst_sig false --rst_sig_p false --fclkin 27 --clkfb_sel 0 --en_lock true --clkout_bypass false --en_clkoutp false --clkoutp_bypass false --en_clkoutd false --clkoutd_bypass false +-series GW2A +-device GW2A-18 +-device_version C +-package PBGA256 +-part_number GW2A-LV18PG256C8/I7 + + +-mod_name Gowin_rPLL +-file_name gowin_rpll +-path E:/gw/basics-graphics-music/labs/06_vga/run/src/gowin_rpll/ +-type PLL +-rPll true +-file_type vlg +-dev_type GW2A-18C +-dyn_idiv_sel false +-idiv_sel 8 +-dyn_fbdiv_sel false +-fbdiv_sel 37 +-dyn_odiv_sel false +-odiv_sel 8 +-dyn_da_en false +-rst_sig false +-rst_sig_p false +-fclkin 27 +-clkfb_sel 0 +-en_lock true +-clkout_bypass false +-en_clkoutp false +-clkoutp_bypass false +-en_clkoutd false +-clkoutd_bypass false -en_clkoutd3 false \ No newline at end of file diff --git a/boards/tang_primer_20k_dock_alt/gowin_rpll.v b/boards/tang_primer_20k_dock_alt/gowin_rpll.v index 8ca521ec..15b4cae3 100644 --- a/boards/tang_primer_20k_dock_alt/gowin_rpll.v +++ b/boards/tang_primer_20k_dock_alt/gowin_rpll.v @@ -1,64 +1,64 @@ -//Copyright (C)2014-2024 Gowin Semiconductor Corporation. -//All rights reserved. -//File Title: IP file -//Tool Version: V1.9.9.03 (64-bit) -//Part Number: GW2A-LV18PG256C8/I7 -//Device: GW2A-18 -//Device Version: C -//Created Time: Sun Jun 2 18:04:20 2024 - -module Gowin_rPLL (clkout, lock, clkin); - -output clkout; -output lock; -input clkin; - -wire clkoutp_o; -wire clkoutd_o; -wire clkoutd3_o; -wire gw_gnd; - -assign gw_gnd = 1'b0; - -rPLL rpll_inst ( - .CLKOUT(clkout), - .LOCK(lock), - .CLKOUTP(clkoutp_o), - .CLKOUTD(clkoutd_o), - .CLKOUTD3(clkoutd3_o), - .RESET(gw_gnd), - .RESET_P(gw_gnd), - .CLKIN(clkin), - .CLKFB(gw_gnd), - .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), - .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) -); - -defparam rpll_inst.FCLKIN = "27"; -defparam rpll_inst.DYN_IDIV_SEL = "false"; -defparam rpll_inst.IDIV_SEL = 7; -defparam rpll_inst.DYN_FBDIV_SEL = "false"; -defparam rpll_inst.FBDIV_SEL = 36; -defparam rpll_inst.DYN_ODIV_SEL = "false"; -defparam rpll_inst.ODIV_SEL = 8; -defparam rpll_inst.PSDA_SEL = "0000"; -defparam rpll_inst.DYN_DA_EN = "false"; -defparam rpll_inst.DUTYDA_SEL = "1000"; -defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; -defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; -defparam rpll_inst.CLKOUT_DLY_STEP = 0; -defparam rpll_inst.CLKOUTP_DLY_STEP = 0; -defparam rpll_inst.CLKFB_SEL = "internal"; -defparam rpll_inst.CLKOUT_BYPASS = "false"; -defparam rpll_inst.CLKOUTP_BYPASS = "false"; -defparam rpll_inst.CLKOUTD_BYPASS = "false"; -defparam rpll_inst.DYN_SDIV_SEL = 2; -defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; -defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; -defparam rpll_inst.DEVICE = "GW2A-18C"; - -endmodule //Gowin_rPLL +//Copyright (C)2014-2024 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: IP file +//Tool Version: V1.9.9.03 (64-bit) +//Part Number: GW2A-LV18PG256C8/I7 +//Device: GW2A-18 +//Device Version: C +//Created Time: Sun Jun 2 18:04:20 2024 + +module Gowin_rPLL (clkout, lock, clkin); + +output clkout; +output lock; +input clkin; + +wire clkoutp_o; +wire clkoutd_o; +wire clkoutd3_o; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +rPLL rpll_inst ( + .CLKOUT(clkout), + .LOCK(lock), + .CLKOUTP(clkoutp_o), + .CLKOUTD(clkoutd_o), + .CLKOUTD3(clkoutd3_o), + .RESET(gw_gnd), + .RESET_P(gw_gnd), + .CLKIN(clkin), + .CLKFB(gw_gnd), + .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) +); + +defparam rpll_inst.FCLKIN = "27"; +defparam rpll_inst.DYN_IDIV_SEL = "false"; +defparam rpll_inst.IDIV_SEL = 7; +defparam rpll_inst.DYN_FBDIV_SEL = "false"; +defparam rpll_inst.FBDIV_SEL = 36; +defparam rpll_inst.DYN_ODIV_SEL = "false"; +defparam rpll_inst.ODIV_SEL = 8; +defparam rpll_inst.PSDA_SEL = "0000"; +defparam rpll_inst.DYN_DA_EN = "false"; +defparam rpll_inst.DUTYDA_SEL = "1000"; +defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUT_DLY_STEP = 0; +defparam rpll_inst.CLKOUTP_DLY_STEP = 0; +defparam rpll_inst.CLKFB_SEL = "internal"; +defparam rpll_inst.CLKOUT_BYPASS = "false"; +defparam rpll_inst.CLKOUTP_BYPASS = "false"; +defparam rpll_inst.CLKOUTD_BYPASS = "false"; +defparam rpll_inst.DYN_SDIV_SEL = 2; +defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; +defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; +defparam rpll_inst.DEVICE = "GW2A-18C"; + +endmodule //Gowin_rPLL From 9c708a7497a7721aa8dcb2ac80f2c43c4a5dd297 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 19:26:25 -0700 Subject: [PATCH 45/65] Add .vo file exclusion for tabs in prepare_public_package.bash --- scripts/admin/prepare_public_package.bash | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/admin/prepare_public_package.bash b/scripts/admin/prepare_public_package.bash index bd6d29e7..45d2b533 100755 --- a/scripts/admin/prepare_public_package.bash +++ b/scripts/admin/prepare_public_package.bash @@ -110,7 +110,7 @@ fi # For some reason "--exclude=\*.mk" does not work here exclude_space_ok="--exclude-dir=urgReport --exclude=*.xdc" -exclude_tabs_ok="$exclude_space_ok --exclude=Makefile --exclude=*.mk" +exclude_tabs_ok="$exclude_space_ok --exclude=Makefile --exclude=*.mk --exclude=*.vo" if grep -rqI $exclude_tabs_ok $'\t' "$pkg_src_root"/* then From b581052a8625dfb721a900f1206263b6c24deb4c Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 19:27:16 -0700 Subject: [PATCH 46/65] Removed spaces at the end of the line --- .../de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference | 2 +- boards/qmtech_kintex_7/board_specific_top.sv | 2 +- boards/tang_nano_1k/board_specific.cst | 12 ++++++------ boards/tang_nano_1k/board_specific_top.sv | 4 ++-- boards/tang_nano_1k_min/board_specific.cst | 12 ++++++------ boards/tang_nano_9k_hdmi/board_specific_top.sv | 4 ++-- .../tang_primer_20k_dock_alt/board_specific_top.sv | 10 +++++----- boards/tang_primer_20k_dock_alt/dvi_tx.v | 2 +- boards/tang_primer_20k_lite/board_specific_top.sv | 2 +- boards/trion_t20/board_specific_top.sv | 14 +++++++------- labs/2_graphics/2_2_game/lab_top.sv | 2 +- scripts/steps/01_clean.source_bash | 2 +- 12 files changed, 34 insertions(+), 34 deletions(-) diff --git a/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference b/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference index bd9f24e1..338beb92 100644 --- a/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference +++ b/boards/de2_115/DE2_115_GOLDEN_TOP.qsf.for_reference @@ -311,7 +311,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] #============================================================ -# USB +# USB #============================================================ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] diff --git a/boards/qmtech_kintex_7/board_specific_top.sv b/boards/qmtech_kintex_7/board_specific_top.sv index cfb52fa3..0a3b947f 100644 --- a/boards/qmtech_kintex_7/board_specific_top.sv +++ b/boards/qmtech_kintex_7/board_specific_top.sv @@ -110,7 +110,7 @@ module board_specific_top .blue ( ), .mic ( '0 ), - .gpio ( ) + .gpio ( ) ); endmodule diff --git a/boards/tang_nano_1k/board_specific.cst b/boards/tang_nano_1k/board_specific.cst index 50027764..24e1f252 100644 --- a/boards/tang_nano_1k/board_specific.cst +++ b/boards/tang_nano_1k/board_specific.cst @@ -12,12 +12,12 @@ IO_PORT "key[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_LOC "key[0]" 13; IO_PORT "key[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP; -IO_LOC "led[2]" 11; -IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "led[1]" 10; -IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "led[0]" 9; -IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[2]" 11; +IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[1]" 10; +IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[0]" 9; +IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; IO_LOC "gpio[0]" 16 ; IO_PORT "gpio[0]" IO_TYPE=LVCMOS33; IO_LOC "gpio[1]" 17 ; IO_PORT "gpio[1]" IO_TYPE=LVCMOS33; diff --git a/boards/tang_nano_1k/board_specific_top.sv b/boards/tang_nano_1k/board_specific_top.sv index fc88393e..40360834 100644 --- a/boards/tang_nano_1k/board_specific_top.sv +++ b/boards/tang_nano_1k/board_specific_top.sv @@ -51,7 +51,7 @@ module board_specific_top lab_top # ( .clk_mhz ( clk_mhz ), - .pixel_mhz ( pixel_mhz ), + .pixel_mhz ( pixel_mhz ), .w_key ( w_tm_key ), .w_sw ( w_tm_led ), @@ -89,7 +89,7 @@ module board_specific_top .uart_tx ( ), .mic ( ), - .gpio ( gpio ) + .gpio ( gpio ) ); //------------------------------------------------------------------------ diff --git a/boards/tang_nano_1k_min/board_specific.cst b/boards/tang_nano_1k_min/board_specific.cst index b0f63764..677a531c 100644 --- a/boards/tang_nano_1k_min/board_specific.cst +++ b/boards/tang_nano_1k_min/board_specific.cst @@ -12,9 +12,9 @@ IO_PORT "key[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP; IO_LOC "key[0]" 13; IO_PORT "key[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP; -IO_LOC "led[2]" 11; -IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "led[1]" 10; -IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; -IO_LOC "led[0]" 9; -IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[2]" 11; +IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[1]" 10; +IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; +IO_LOC "led[0]" 9; +IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8; diff --git a/boards/tang_nano_9k_hdmi/board_specific_top.sv b/boards/tang_nano_9k_hdmi/board_specific_top.sv index 944b2f49..093a4ca3 100644 --- a/boards/tang_nano_9k_hdmi/board_specific_top.sv +++ b/boards/tang_nano_9k_hdmi/board_specific_top.sv @@ -61,7 +61,7 @@ module board_specific_top `endif //------------------------------------------------------------------------ - + wire clk_hdl; wire clk_hd; wire clk_px; @@ -228,7 +228,7 @@ module board_specific_top //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver + inmp441_mic_i2s_receiver # ( .clk_mhz ( clk_mhz ) ) diff --git a/boards/tang_primer_20k_dock_alt/board_specific_top.sv b/boards/tang_primer_20k_dock_alt/board_specific_top.sv index 981a5c08..b2c22996 100644 --- a/boards/tang_primer_20k_dock_alt/board_specific_top.sv +++ b/boards/tang_primer_20k_dock_alt/board_specific_top.sv @@ -270,15 +270,15 @@ module board_specific_top // assign GPIO_2 = {VGA_HS, VGA_VS, 2'bz, VGA_G}; `ifdef ENABLE_VGA16 - assign GPIO_3 = {2'bz, VGA_R[3], VGA_R[1], 2'bz, VGA_R[4], VGA_R[2]}; - assign GPIO_2 = {VGA_G[5], VGA_G[3], VGA_G[1], VGA_B[4], VGA_R[0], VGA_G[4], VGA_G[2], VGA_G[0]}; + assign GPIO_3 = {2'bz, VGA_R[3], VGA_R[1], 2'bz, VGA_R[4], VGA_R[2]}; + assign GPIO_2 = {VGA_G[5], VGA_G[3], VGA_G[1], VGA_B[4], VGA_R[0], VGA_G[4], VGA_G[2], VGA_G[0]}; assign GPIO_1 = {VGA_B[2], VGA_B[0], VGA_HS, 1'bz, VGA_B[3], VGA_B[1], VGA_VS, 1'bz}; `elsif ENABLE_VGA666 assign GPIO_3 = { VGA_G[4], VGA_G[5], VGA_R[2], VGA_B[4], VGA_VS, VGA_HS, VGA_B[0], VGA_R[1] }; - assign GPIO_2 = { VGA_B[3], VGA_G[2], VGA_R[0], VGA_R[4], VGA_G[0], VGA_B[5], VGA_G[1], VGA_B[1] }; - assign GPIO_1 = { VGA_R[5], 3'bz, VGA_B[2], VGA_G[3], VGA_R[3], 1'bz }; + assign GPIO_2 = { VGA_B[3], VGA_G[2], VGA_R[0], VGA_R[4], VGA_G[0], VGA_B[5], VGA_G[1], VGA_B[1] }; + assign GPIO_1 = { VGA_R[5], 3'bz, VGA_B[2], VGA_G[3], VGA_R[3], 1'bz }; `elsif ENABLE_HDMI DVI_TX_Top myDVI( @@ -302,6 +302,6 @@ module board_specific_top assign GPIO_2 = { VGA_B, VGA_R }; assign GPIO_3 = { 2'bz, VGA_VS, VGA_HS, VGA_G }; - `endif + `endif endmodule diff --git a/boards/tang_primer_20k_dock_alt/dvi_tx.v b/boards/tang_primer_20k_dock_alt/dvi_tx.v index 895c637e..309f3a61 100644 --- a/boards/tang_primer_20k_dock_alt/dvi_tx.v +++ b/boards/tang_primer_20k_dock_alt/dvi_tx.v @@ -1120,6 +1120,6 @@ wire GND; .G(GND) ); GSR GSR ( - .GSRI(VCC) + .GSRI(VCC) ); endmodule /* DVI_TX_Top */ diff --git a/boards/tang_primer_20k_lite/board_specific_top.sv b/boards/tang_primer_20k_lite/board_specific_top.sv index 0d85e74d..a9a7776c 100644 --- a/boards/tang_primer_20k_lite/board_specific_top.sv +++ b/boards/tang_primer_20k_lite/board_specific_top.sv @@ -197,5 +197,5 @@ module board_specific_top assign GPIO_0 = { VGA_R, VGA_B }; assign GPIO_1 = { VGA_G, 2'b00, VGA_VS, VGA_HS }; - + endmodule diff --git a/boards/trion_t20/board_specific_top.sv b/boards/trion_t20/board_specific_top.sv index ddd665f1..3e048aaa 100755 --- a/boards/trion_t20/board_specific_top.sv +++ b/boards/trion_t20/board_specific_top.sv @@ -14,29 +14,29 @@ module board_specific_top //------------------------------------------------------------------------- // PLL interface - //------------------------------------------------------------------------- + //------------------------------------------------------------------------- input clk, // input pll_locked, // output pll_reset_n, //------------------------------------------------------------------------- - // button - //------------------------------------------------------------------------- + // button + //------------------------------------------------------------------------- input rst_button, - + input [w_key - 1: 0] keys, input [w_sw - 1: 0] sw, //------------------------------------------------------------------------- - // LED + // LED //------------------------------------------------------------------------- output [w_led - 1: 0] led_n, - + //------------------------------------------------------------------------- - // UART + // UART //------------------------------------------------------------------------- input RXD, diff --git a/labs/2_graphics/2_2_game/lab_top.sv b/labs/2_graphics/2_2_game/lab_top.sv index d139191b..708cc046 100644 --- a/labs/2_graphics/2_2_game/lab_top.sv +++ b/labs/2_graphics/2_2_game/lab_top.sv @@ -98,7 +98,7 @@ module lab_top .rgb ( rgb ), .display_on ( display_on ), .pixel_clk ( pixel_clk ) - + ); assign red = { w_red { rgb [2] } }; diff --git a/scripts/steps/01_clean.source_bash b/scripts/steps/01_clean.source_bash index 87ba984e..8b8b69f5 100644 --- a/scripts/steps/01_clean.source_bash +++ b/scripts/steps/01_clean.source_bash @@ -2,7 +2,7 @@ cd .. -rm -rf run log.txt +rm -rf run log.txt if [ -n "${openlane_dir-}" ] ; then rm -rf "$openlane_dir/designs/$lab_name" From 9c62d1d77e6245a8f0441bcf263516145007cc40 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Mon, 22 Jul 2024 19:50:54 -0700 Subject: [PATCH 47/65] Added undeclared wire --- labs/1_basics/1_02_mux/lab_top.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/labs/1_basics/1_02_mux/lab_top.sv b/labs/1_basics/1_02_mux/lab_top.sv index d46a5fb3..3c5a6dac 100644 --- a/labs/1_basics/1_02_mux/lab_top.sv +++ b/labs/1_basics/1_02_mux/lab_top.sv @@ -96,7 +96,7 @@ module lab_top //------------------------------------------------------------------------ wire [1:0] ab = { a, b }; - assign mux1 = ab [sel]; + wire mux1 = ab [sel]; //------------------------------------------------------------------------ From c65f8c2fd573709155a5052b7950745c51f28af6 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Wed, 24 Jul 2024 08:33:21 -0700 Subject: [PATCH 48/65] Started adding lcd_480_272 from vendor's example --- .../board_specific.cst | 95 ++++++ .../board_specific.sdc | 4 + .../board_specific.tcl | 11 + .../board_specific_top.sv | 290 ++++++++++++++++++ .../fpga_project_01.gprj | 7 + .../fpga_project_02.gprj | 2 + .../tang_nano_9k_lcd_480_272/gowin_rpll.ipc | 24 ++ .../tang_nano_9k_lcd_480_272/gowin_rpll.mod | 32 ++ boards/tang_nano_9k_lcd_480_272/gowin_rpll.v | 63 ++++ .../project_process_config_01.json | 32 ++ .../project_process_config_02.json | 53 ++++ peripherals/lcd_480_272.sv | 111 +++++++ 12 files changed, 724 insertions(+) create mode 100644 boards/tang_nano_9k_lcd_480_272/board_specific.cst create mode 100644 boards/tang_nano_9k_lcd_480_272/board_specific.sdc create mode 100644 boards/tang_nano_9k_lcd_480_272/board_specific.tcl create mode 100644 boards/tang_nano_9k_lcd_480_272/board_specific_top.sv create mode 100644 boards/tang_nano_9k_lcd_480_272/fpga_project_01.gprj create mode 100644 boards/tang_nano_9k_lcd_480_272/fpga_project_02.gprj create mode 100644 boards/tang_nano_9k_lcd_480_272/gowin_rpll.ipc create mode 100644 boards/tang_nano_9k_lcd_480_272/gowin_rpll.mod create mode 100644 boards/tang_nano_9k_lcd_480_272/gowin_rpll.v create mode 100644 boards/tang_nano_9k_lcd_480_272/project_process_config_01.json create mode 100644 boards/tang_nano_9k_lcd_480_272/project_process_config_02.json create mode 100644 peripherals/lcd_480_272.sv diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific.cst b/boards/tang_nano_9k_lcd_480_272/board_specific.cst new file mode 100644 index 00000000..a3feafaa --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/board_specific.cst @@ -0,0 +1,95 @@ +# The pin assignments +# All I/O pins here are 3.3V compatible unless specified otherwise + +IO_LOC "CLK" 52; + +IO_LOC "KEY[0]" 4; +IO_LOC "KEY[1]" 3; + +IO_LOC "LED[0]" 10; +IO_LOC "LED[1]" 11; +IO_LOC "LED[2]" 13; +IO_LOC "LED[3]" 14; +IO_LOC "LED[4]" 15; +IO_LOC "LED[5]" 16; + +IO_LOC "LARGE_LCD_DE" 33; +IO_LOC "LARGE_LCD_VS" 34; +IO_LOC "LARGE_LCD_HS" 40; +IO_LOC "LARGE_LCD_CK" 35; +IO_LOC "LARGE_LCD_INIT" 63; +IO_LOC "LARGE_LCD_BL" 86; + +IO_LOC "LARGE_LCD_R[3]" 75; +IO_LOC "LARGE_LCD_R[4]" 74; +IO_LOC "LARGE_LCD_R[5]" 73; +IO_LOC "LARGE_LCD_R[6]" 72; +IO_LOC "LARGE_LCD_R[7]" 71; + +IO_LOC "LARGE_LCD_G[2]" 70; +IO_LOC "LARGE_LCD_G[3]" 69; +IO_LOC "LARGE_LCD_G[4]" 68; +IO_LOC "LARGE_LCD_G[5]" 57; +IO_LOC "LARGE_LCD_G[6]" 56; +IO_LOC "LARGE_LCD_G[7]" 55; + +IO_LOC "LARGE_LCD_B[3]" 54; +IO_LOC "LARGE_LCD_B[4]" 53; +IO_LOC "LARGE_LCD_B[5]" 51; +IO_LOC "LARGE_LCD_B[6]" 42; +IO_LOC "LARGE_LCD_B[7]" 41; + +IO_LOC "UART_RX" 18; +IO_LOC "UART_TX" 17; + +# The following 4 pins (TF_CS, TF_MOSI, TF_SCLK, TF_MISO) +# are used for INMP441 microphone +# in basics-graphics-music labs + +IO_LOC "TF_CS" 38; # inmp441: lr +IO_LOC "TF_MOSI" 37; # inmp441: ws +IO_LOC "TF_SCLK" 36; # inmp441: sck +IO_LOC "TF_MISO" 39; # inmp441: sd + +# The first 3 GPIO pins are used for TM1638 I/O module +# which carries 8 LEDs, 8-digit 7-segment display and 8 keys + +IO_LOC "GPIO[0]" 25; # tm1638: sio_data +IO_LOC "GPIO[1]" 26; # tm1638: sio_clk +IO_LOC "GPIO[2]" 27; # tm1638: sio_stb +IO_LOC "GPIO[3]" 28; +IO_LOC "GPIO[4]" 29; +IO_LOC "GPIO[5]" 30; + +# The 4 pins SMALL_LCD_CLK, _CS, _RS and _DATA +# are used for the I2S audio output module PCM5102 +# in basics-graphics-music labs + +IO_LOC "SMALL_LCD_DATA" 77; # pcm5102: sck i2s_audio_out: mclk +IO_LOC "SMALL_LCD_CLK" 76; # pcm5102: bck i2s_audio_out: bclk +IO_LOC "SMALL_LCD_RESETN" 47; +IO_LOC "SMALL_LCD_CS" 48; # pcm5102: din i2s_audio_out: sdata +IO_LOC "SMALL_LCD_RS" 49; # pcm5102: lrck i2s_audio_out: lrclk + +# TMDS pins will be used later + +# IO_LOC "TMDS_CLK_P" 69,68; +# IO_LOC "TMDS_D_P[0]" 71,70; +# IO_LOC "TMDS_D_P[1]" 73,72; +# IO_LOC "TMDS_D_P[2]" 75,74; + +IO_LOC "FLASH_CLK" 59; +IO_LOC "FLASH_CSB" 60; +IO_LOC "FLASH_MOSI" 61; +IO_LOC "FLASH_MISO" 62; + +# The following pins are not used for the lab examples +# because they are 1.8V compatible + +# IO_LOC "GPIO_1_8_V_UNUSED[0]" 85; +# IO_LOC "GPIO_1_8_V_UNUSED[1]" 84; +# IO_LOC "GPIO_1_8_V_UNUSED[2]" 83; +# IO_LOC "GPIO_1_8_V_UNUSED[3]" 82; +# IO_LOC "GPIO_1_8_V_UNUSED[4]" 81; +# IO_LOC "GPIO_1_8_V_UNUSED[5]" 80; +# IO_LOC "GPIO_1_8_V_UNUSED[6]" 79; diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific.sdc b/boards/tang_nano_9k_lcd_480_272/board_specific.sdc new file mode 100644 index 00000000..bf0aab16 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/board_specific.sdc @@ -0,0 +1,4 @@ +# The timing constraints + +create_clock -name CLK -period 37.037 -waveform {0 18.518} [get_ports {CLK}] +create_clock -name LARGE_LCD_CK -period 111.11 -waveform {0 55.555} [get_ports {LARGE_LCD_CK}] diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific.tcl b/boards/tang_nano_9k_lcd_480_272/board_specific.tcl new file mode 100644 index 00000000..794089f1 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/board_specific.tcl @@ -0,0 +1,11 @@ +# Synthesis and Place & Route settings + +set_device GW1NR-LV9QN88PC6/I5 -name GW1NR-9 -device_version C + +set_option -synthesis_tool gowinsynthesis +set_option -output_base_name fpga_project +set_option -top_module board_specific_top +set_option -verilog_std sysv2017 + +set_option -use_mspi_as_gpio 1 +set_option -use_sspi_as_gpio 1 diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv new file mode 100644 index 00000000..b3d48995 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv @@ -0,0 +1,290 @@ +`include "config.svh" +`include "lab_specific_board_config.svh" + +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + +module board_specific_top +# ( + parameter clk_mhz = 27, + pixel_mhz = 9, + + w_key = 2, // The last key is used for a reset + w_sw = 0, + w_led = 6, + w_digit = 0, + w_gpio = 10, + + w_red = 5, + w_green = 6, + w_blue = 5 +) +( + input CLK, + + input [w_key - 1:0] KEY, + + output [w_led - 1:0] LED, + + output LARGE_LCD_DE, + output LARGE_LCD_VS, + output LARGE_LCD_HS, + output LARGE_LCD_CK, + output LARGE_LCD_INIT, + output LARGE_LCD_BL, + + output [7:7 + 1 - w_red ] LARGE_LCD_R, + output [7:7 + 1 - w_green ] LARGE_LCD_G, + output [7:7 + 1 - w_blue ] LARGE_LCD_B, + + input UART_RX, + output UART_TX, + + // The following 4 pins (TF_CS, TF_MOSI, TF_SCLK, TF_MISO) + // are used for INMP441 microphone + // in basics-graphics-music labs + + inout TF_CS, + inout TF_MOSI, + inout TF_SCLK, + inout TF_MISO, + + inout [w_gpio - 1:0] GPIO, + + // The 4 pins SMALL_LCD_CLK, _CS, _RS and _DATA + // are used for the I2S audio output + // in basics-graphics-music labs + + inout SMALL_LCD_CLK, + inout SMALL_LCD_RESETN, + inout SMALL_LCD_CS, + inout SMALL_LCD_RS, + inout SMALL_LCD_DATA, + + // TMDS pins will be used later + + // output TMDS_CLK_N, + // output TMDS_CLK_P, + // output [ 2:0] TMDS_D_N, + // output [ 2:0] TMDS_D_P, + + output FLASH_CLK, + output FLASH_CSB, + output FLASH_MOSI, + input FLASH_MISO +); + + wire clk = CLK; + + //------------------------------------------------------------------------ + + localparam w_tm_key = 8, + w_tm_led = 8, + w_tm_digit = 8; + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; + + `else // TM1638 module is not connected + + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; + + `endif + + //------------------------------------------------------------------------ + + wire [w_tm_key - 1:0] tm_key; + wire [w_tm_led - 1:0] tm_led; + wire [w_tm_digit - 1:0] tm_digit; + + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; + + wire rst; + wire [ 7:0] abcdefgh; + wire [ 23:0] mic; + wire [ 15:0] sound; + + //------------------------------------------------------------------------ + + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + assign rst = tm_key [w_tm_key - 1]; + assign lab_key = tm_key [w_tm_key - 1:0]; + + assign tm_led = lab_led; + assign tm_digit = lab_digit; + + assign LED = w_led' (~ lab_led); + + `else // TM1638 module is not connected + + assign rst = ~ KEY [w_key - 1]; + assign lab_key = ~ KEY [w_key - 1:0]; + + assign LED = ~ lab_led; + + `endif + + //------------------------------------------------------------------------ + + wire slow_clk; + + slow_clk_gen # (.fast_clk_mhz (clk_mhz), .slow_clk_hz (1)) + i_slow_clk_gen (.slow_clk (slow_clk), .*); + + //------------------------------------------------------------------------ + + lab_top + # ( + .clk_mhz ( clk_mhz ), + .pixel_mhz ( pixel_mhz ), + + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_key ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), + .w_gpio ( w_gpio ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) + ) + i_lab_top + ( + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), + + .key ( lab_key ), + .sw ( lab_key ), + + .led ( lab_led ), + + .abcdefgh ( abcdefgh ), + .digit ( lab_digit ), + + .vsync ( LARGE_LCD_VS ), + .hsync ( LARGE_LCD_HS ), + + .red ( LARGE_LCD_R ), + .green ( LARGE_LCD_G ), + .blue ( LARGE_LCD_B ), + + .display_on ( LARGE_LCD_DE ), + .pixel_clk ( LARGE_LCD_CK ), + + .uart_rx ( UART_RX ), + .uart_tx ( UART_TX ), + + .mic ( mic ), + .sound ( sound ), + .gpio ( gpio ) + ); + + //------------------------------------------------------------------------ + + Gowin_rPLL Gowin_rPLL_9Mhz + ( + .clkout(LCD_CLK), // 9MHz + .clkin(XTAL_IN) //27MHz + ); + + lcd_480_272 + ( + .PixelClk ( LARGE_LCD_CLK ), + .nRST ( rst ), + + .LCD_DE ( LARGE_LCD_DE ), + .LCD_HSYNC ( LARGE_LCD_HSYNC ), + .LCD_VSYNC ( LARGE_LCD_VSYNC ), + + .x ( x ), + .y ( y ) + ); + + assign LARGE_LCD_INIT = 1'b0; + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + wire [$left (abcdefgh):0] hgfedcba; + + generate + genvar i; + + for (i = 0; i < $bits (abcdefgh); i ++) + begin : abc + assign hgfedcba [i] = abcdefgh [$left (abcdefgh) - i]; + end + endgenerate + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + tm1638_board_controller + # ( + .clk_mhz ( clk_mhz ), + .w_digit ( w_tm_digit ) + ) + i_tm1638 + ( + .clk ( clk ), + .rst ( rst ), + .hgfedcba ( hgfedcba ), + .digit ( tm_digit ), + .ledr ( tm_led ), + .keys ( tm_key ), + .sio_data ( GPIO [0] ), + .sio_clk ( GPIO [1] ), + .sio_stb ( GPIO [2] ) + ); + + `endif + + //------------------------------------------------------------------------ + + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( TF_CS ), + .ws ( TF_MOSI ), + .sck ( TF_SCLK ), + .sd ( TF_MISO ), + .value ( mic ) + ); + + + //------------------------------------------------------------------------ + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + i_audio + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( SMALL_LCD_DATA ), + .bclk ( SMALL_LCD_CLK ), + .lrclk ( SMALL_LCD_RS ), + .sdata ( SMALL_LCD_CS ) + ); + +endmodule diff --git a/boards/tang_nano_9k_lcd_480_272/fpga_project_01.gprj b/boards/tang_nano_9k_lcd_480_272/fpga_project_01.gprj new file mode 100644 index 00000000..79b1311f --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/fpga_project_01.gprj @@ -0,0 +1,7 @@ + + + + + 5 + gw1nr9c-004 + diff --git a/boards/tang_nano_9k_lcd_480_272/fpga_project_02.gprj b/boards/tang_nano_9k_lcd_480_272/fpga_project_02.gprj new file mode 100644 index 00000000..8c6b9904 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/fpga_project_02.gprj @@ -0,0 +1,2 @@ + + diff --git a/boards/tang_nano_9k_lcd_480_272/gowin_rpll.ipc b/boards/tang_nano_9k_lcd_480_272/gowin_rpll.ipc new file mode 100644 index 00000000..bf8c92d9 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/gowin_rpll.ipc @@ -0,0 +1,24 @@ +[General] +ipc_version=4 +file=gowin_rpll +module=Gowin_rPLL +target_device=gw1nr9c-004 +type=clock_rpll +version=1.0 + +[Config] +CKLOUTD3=false +CLKFB_SOURCE=0 +CLKIN_FREQ=27 +CLKOUTD=false +CLKOUTP=false +CLKOUT_BYPASS=false +CLKOUT_DIVIDE_DYN=true +CLKOUT_FREQ=9 +CLKOUT_TOLERANCE=0 +DYNAMIC=true +LANG=0 +LOCK_EN=false +MODE_GENERAL=true +PLL_PWD=false +RESET_PLL=false diff --git a/boards/tang_nano_9k_lcd_480_272/gowin_rpll.mod b/boards/tang_nano_9k_lcd_480_272/gowin_rpll.mod new file mode 100644 index 00000000..39dc975c --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/gowin_rpll.mod @@ -0,0 +1,32 @@ +-series GW1NR +-device GW1NR-9C +-package QFN88P +-part_number GW1NR-LV9QN88PC6/I5 + + +-mod_name Gowin_rPLL +-file_name gowin_rpll +-path Y:/4.3inch_screen/lcd_led/src/gowin_rpll/ +-type PLL +-rPll true +-file_type vlg +-dev_type GW1NR-9C +-dyn_idiv_sel false +-idiv_sel 3 +-dyn_fbdiv_sel false +-fbdiv_sel 1 +-dyn_odiv_sel false +-odiv_sel 48 +-dyn_da_en true +-rst_sig false +-rst_sig_p false +-fclkin 27 +-clkfb_sel 0 +-en_lock false +-clkout_bypass false +-clkout_ft_dir 1 +-en_clkoutp false +-clkoutp_bypass false +-en_clkoutd false +-clkoutd_bypass false +-en_clkoutd3 false \ No newline at end of file diff --git a/boards/tang_nano_9k_lcd_480_272/gowin_rpll.v b/boards/tang_nano_9k_lcd_480_272/gowin_rpll.v new file mode 100644 index 00000000..95f15287 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/gowin_rpll.v @@ -0,0 +1,63 @@ +//Copyright (C)2014-2022 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: IP file +//GOWIN Version: V1.9.8.09 +//Part Number: GW1NR-LV9QN88PC6/I5 +//Device: GW1NR-9C +//Created Time: Tue Mar 21 12:46:45 2023 + +module Gowin_rPLL (clkout, clkin); + +output clkout; +input clkin; + +wire lock_o; +wire clkoutp_o; +wire clkoutd_o; +wire clkoutd3_o; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +rPLL rpll_inst ( + .CLKOUT(clkout), + .LOCK(lock_o), + .CLKOUTP(clkoutp_o), + .CLKOUTD(clkoutd_o), + .CLKOUTD3(clkoutd3_o), + .RESET(gw_gnd), + .RESET_P(gw_gnd), + .CLKIN(clkin), + .CLKFB(gw_gnd), + .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) +); + +defparam rpll_inst.FCLKIN = "27"; +defparam rpll_inst.DYN_IDIV_SEL = "false"; +defparam rpll_inst.IDIV_SEL = 2; +defparam rpll_inst.DYN_FBDIV_SEL = "false"; +defparam rpll_inst.FBDIV_SEL = 0; +defparam rpll_inst.DYN_ODIV_SEL = "false"; +defparam rpll_inst.ODIV_SEL = 48; +defparam rpll_inst.PSDA_SEL = "0000"; +defparam rpll_inst.DYN_DA_EN = "true"; +defparam rpll_inst.DUTYDA_SEL = "1000"; +defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUT_DLY_STEP = 0; +defparam rpll_inst.CLKOUTP_DLY_STEP = 0; +defparam rpll_inst.CLKFB_SEL = "internal"; +defparam rpll_inst.CLKOUT_BYPASS = "false"; +defparam rpll_inst.CLKOUTP_BYPASS = "false"; +defparam rpll_inst.CLKOUTD_BYPASS = "false"; +defparam rpll_inst.DYN_SDIV_SEL = 2; +defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; +defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; +defparam rpll_inst.DEVICE = "GW1NR-9C"; + +endmodule //Gowin_rPLL diff --git a/boards/tang_nano_9k_lcd_480_272/project_process_config_01.json b/boards/tang_nano_9k_lcd_480_272/project_process_config_01.json new file mode 100644 index 00000000..8b6c52aa --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/project_process_config_01.json @@ -0,0 +1,32 @@ +{ + "Allow_Duplicate_Modules" : false, + "Annotated_Properties_for_Analyst" : true, + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CRC_CHECK" : true, + "Clock_Conversion" : true, + "Clock_Route_Order" : 0, + "Correct_Hold_Violation" : true, + "DONE" : true, + "DOWNLOAD_SPEED" : "default", + "Default_Enum_Encoding" : "default", + "Disable_Insert_Pad" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "FORMAT" : "binary", + "FSM Compiler" : true, + "Fanout_Guide" : 10000, + "Frequency" : "Auto", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "Implicit_Initial_Value_Support" : false, + "IncludePath" : [ diff --git a/boards/tang_nano_9k_lcd_480_272/project_process_config_02.json b/boards/tang_nano_9k_lcd_480_272/project_process_config_02.json new file mode 100644 index 00000000..a861fbcd --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272/project_process_config_02.json @@ -0,0 +1,53 @@ + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "Multiple_File_Compilation_Unit" : true, + "Number_of_Critical_Paths" : "", + "Number_of_Start/End_Points" : "", + "OUTPUT_BASE_NAME" : "fpga_project", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "Pipelining" : true, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "Push_Tristates" : true, + "READY" : true, + "RECONFIG_N" : false, + "Ram_RW_Check" : true, + "Report_Auto-Placed_Io_Information" : false, + "Resolve_Mixed_Drivers" : false, + "Resource_Sharing" : true, + "Retiming" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SPI_FLASH_ADDR" : "00000000", + "SSPI" : true, + "Show_All_Warnings" : false, + "Synthesis On/Off Implemented as Translate On/Off" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "board_specific_top", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "Update_Compile_Point_Timing_Data" : false, + "Use_Clock_Period_for_Unconstrainted IO" : false, + "VCCAUX" : 3.3, + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_Sysv2017", + "WAKE_UP" : "0", + "Write_Vendor_Constraint_File" : true, + "dsp_balance" : false, + "show_all_warnings" : false, + "turn_off_bg" : false +} diff --git a/peripherals/lcd_480_272.sv b/peripherals/lcd_480_272.sv new file mode 100644 index 00000000..50974c83 --- /dev/null +++ b/peripherals/lcd_480_272.sv @@ -0,0 +1,111 @@ +// This module is created based on https://github.com/sipeed/TangNano-9K-example/lcd_4.3/src/VGA_timing.v + +module lcd_480_272 +( + input PixelClk, + input nRST, + + output LCD_DE, + output LCD_HSYNC, + output LCD_VSYNC, + + // Modified for basic-graphics-music: Removed LCD_RGB ports. + // These output signals are assigned in the top module code + // using input from lab_top module. + + /* + output [4:0] LCD_B, + output [5:0] LCD_G, + output [4:0] LCD_R + */ + + // Modified for basic-graphics-music: Added x and y outputs + + output [8:0] x, + output [8:0] y +); + + // Horizen count to Hsync, then next Horizen line. + + parameter H_Pixel_Valid = 16'd480; + parameter H_FrontPorch = 16'd50; + parameter H_BackPorch = 16'd30; + + parameter PixelForHS = H_Pixel_Valid + H_FrontPorch + H_BackPorch; + + parameter V_Pixel_Valid = 16'd272; + parameter V_FrontPorch = 16'd20; + parameter V_BackPorch = 16'd5; + + parameter PixelForVS = V_Pixel_Valid + V_FrontPorch + V_BackPorch; + + // Horizen pixel count + + reg [15:0] H_PixelCount; + reg [15:0] V_PixelCount; + + always @( posedge PixelClk or negedge nRST )begin + if( !nRST ) begin + V_PixelCount <= 16'b0; + H_PixelCount <= 16'b0; + end + else if( H_PixelCount == PixelForHS ) begin + V_PixelCount <= V_PixelCount + 1'b1; + H_PixelCount <= 16'b0; + end + else if( V_PixelCount == PixelForVS ) begin + V_PixelCount <= 16'b0; + H_PixelCount <= 16'b0; + end + else begin + V_PixelCount <= V_PixelCount ; + H_PixelCount <= H_PixelCount + 1'b1; + end + end + + // SYNC-DE MODE + + assign LCD_HSYNC = H_PixelCount <= (PixelForHS-H_FrontPorch) ? 1'b0 : 1'b1; + + assign LCD_VSYNC = V_PixelCount <= (PixelForVS-0) ? 1'b0 : 1'b1; + + assign LCD_DE = ( H_PixelCount >= H_BackPorch ) && ( H_PixelCount <= H_Pixel_Valid + H_BackPorch ) && + ( V_PixelCount >= V_BackPorch ) && ( V_PixelCount <= V_Pixel_Valid + V_BackPorch ) && PixelClk; + + // Modified for basic-graphics-music: Removed LCD_RGB port assignments. + // These output signals are assigned in the top module code + // using input from lab_top module. + + `ifdef COMMENTED_OUT + + // color bar + localparam Colorbar_width = H_Pixel_Valid / 16; + + assign LCD_R = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 0 )) ? 5'b00000 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 1 )) ? 5'b00001 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 2 )) ? 5'b00010 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 3 )) ? 5'b00100 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 4 )) ? 5'b01000 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 5 )) ? 5'b10000 : 5'b00000; + + assign LCD_G = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 6 )) ? 6'b000001: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 7 )) ? 6'b000010: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 8 )) ? 6'b000100: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 9 )) ? 6'b001000: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 10 )) ? 6'b010000: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 11 )) ? 6'b100000: 6'b000000; + + assign LCD_B = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 12 )) ? 5'b00001 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 13 )) ? 5'b00010 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 14 )) ? 5'b00100 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 15 )) ? 5'b01000 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 16 )) ? 5'b10000 : 5'b00000; + + `endif + + // Modified for basic-graphics-music: Added x and y outputs + + assign x = V_PixelCount - V_BackPorch; + assign y = H_PixelCount - H_BackPorch; + +endmodule From c2333eb2b369051168c6cfc5f275f8473fba6e24 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Wed, 24 Jul 2024 08:36:18 -0700 Subject: [PATCH 49/65] Renaming for clarity o_audio and i_audio -> inst_audio_out --- boards/alinx_ax4010/board_specific_top.sv | 2 +- boards/c5gx_audio/board_specific_top.sv | 2 +- boards/de0/board_specific_top.sv | 2 +- boards/de0_cv/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga666/board_specific_top.sv | 2 +- boards/de0_nano_soc_vga_pmod/board_specific_top.sv | 2 +- boards/de0_nano_vga666/board_specific_top.sv | 2 +- boards/de0_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de1/board_specific_top.sv | 2 +- boards/de10_lite/board_specific_top.sv | 2 +- boards/de10_lite_tm1638_arduino/board_specific_top.sv | 2 +- boards/de10_nano_vga666/board_specific_top.sv | 2 +- boards/de10_nano_vga_mister/board_specific_top.sv | 2 +- boards/de10_nano_vga_pmod/board_specific_top.sv | 2 +- boards/de2/board_specific_top.sv | 2 +- boards/de2_115/board_specific_top.sv | 2 +- boards/omdazz/board_specific_top.sv | 2 +- boards/omdazz_pmod_mic3/board_specific_top.sv | 2 +- boards/rzrd/board_specific_top.sv | 2 +- boards/rzrd_pmod_mic3/board_specific_top.sv | 2 +- boards/saylinx/board_specific_top.sv | 2 +- boards/saylinx_pmod_mic3/board_specific_top.sv | 2 +- boards/tang_nano_9k_lcd/board_specific_top.sv | 2 +- boards/tang_nano_9k_lcd_480_272/board_specific_top.sv | 2 +- boards/tang_primer_25k_dock/board_specific_top.sv | 2 +- boards/tang_primer_25k_dock_dvi/board_specific_top.sv | 2 +- boards/zeowaa/board_specific_top.sv | 2 +- boards/zeowaa_wo_dig_0/board_specific_top.sv | 2 +- 28 files changed, 28 insertions(+), 28 deletions(-) diff --git a/boards/alinx_ax4010/board_specific_top.sv b/boards/alinx_ax4010/board_specific_top.sv index 62e4f142..b5165a61 100644 --- a/boards/alinx_ax4010/board_specific_top.sv +++ b/boards/alinx_ax4010/board_specific_top.sv @@ -154,7 +154,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/c5gx_audio/board_specific_top.sv b/boards/c5gx_audio/board_specific_top.sv index d2acc2e9..454545ed 100644 --- a/boards/c5gx_audio/board_specific_top.sv +++ b/boards/c5gx_audio/board_specific_top.sv @@ -192,7 +192,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0/board_specific_top.sv b/boards/de0/board_specific_top.sv index 24bc98c2..d69f2632 100644 --- a/boards/de0/board_specific_top.sv +++ b/boards/de0/board_specific_top.sv @@ -184,7 +184,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index bdc663d3..589c5d1e 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -202,7 +202,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_nano_soc_vga666/board_specific_top.sv b/boards/de0_nano_soc_vga666/board_specific_top.sv index 8bbdf03b..e3ab8f37 100644 --- a/boards/de0_nano_soc_vga666/board_specific_top.sv +++ b/boards/de0_nano_soc_vga666/board_specific_top.sv @@ -289,7 +289,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv index 50050016..c37880a1 100644 --- a/boards/de0_nano_soc_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_soc_vga_pmod/board_specific_top.sv @@ -281,7 +281,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_nano_vga666/board_specific_top.sv b/boards/de0_nano_vga666/board_specific_top.sv index 4f3e1ff6..5b651a9d 100644 --- a/boards/de0_nano_vga666/board_specific_top.sv +++ b/boards/de0_nano_vga666/board_specific_top.sv @@ -292,7 +292,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de0_nano_vga_pmod/board_specific_top.sv b/boards/de0_nano_vga_pmod/board_specific_top.sv index cd870afb..598a7623 100644 --- a/boards/de0_nano_vga_pmod/board_specific_top.sv +++ b/boards/de0_nano_vga_pmod/board_specific_top.sv @@ -292,7 +292,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index a0f3a9b7..b8698acd 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -195,7 +195,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index 915e65c9..ccfc66c0 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -176,7 +176,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de10_lite_tm1638_arduino/board_specific_top.sv b/boards/de10_lite_tm1638_arduino/board_specific_top.sv index 075c521e..074f831d 100644 --- a/boards/de10_lite_tm1638_arduino/board_specific_top.sv +++ b/boards/de10_lite_tm1638_arduino/board_specific_top.sv @@ -268,7 +268,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de10_nano_vga666/board_specific_top.sv b/boards/de10_nano_vga666/board_specific_top.sv index a1a1faf5..bf254d73 100644 --- a/boards/de10_nano_vga666/board_specific_top.sv +++ b/boards/de10_nano_vga666/board_specific_top.sv @@ -315,7 +315,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de10_nano_vga_mister/board_specific_top.sv b/boards/de10_nano_vga_mister/board_specific_top.sv index c6339194..704d184b 100644 --- a/boards/de10_nano_vga_mister/board_specific_top.sv +++ b/boards/de10_nano_vga_mister/board_specific_top.sv @@ -321,7 +321,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de10_nano_vga_pmod/board_specific_top.sv b/boards/de10_nano_vga_pmod/board_specific_top.sv index 5c05cdc9..f72b0c77 100644 --- a/boards/de10_nano_vga_pmod/board_specific_top.sv +++ b/boards/de10_nano_vga_pmod/board_specific_top.sv @@ -314,7 +314,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index 01c35651..87a4cb0b 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -260,7 +260,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index 28593d15..ff6512e4 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -284,7 +284,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - i_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/omdazz/board_specific_top.sv b/boards/omdazz/board_specific_top.sv index dfe45fc6..0d7ada34 100644 --- a/boards/omdazz/board_specific_top.sv +++ b/boards/omdazz/board_specific_top.sv @@ -189,7 +189,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/omdazz_pmod_mic3/board_specific_top.sv b/boards/omdazz_pmod_mic3/board_specific_top.sv index 991d22c0..bec1a506 100644 --- a/boards/omdazz_pmod_mic3/board_specific_top.sv +++ b/boards/omdazz_pmod_mic3/board_specific_top.sv @@ -189,7 +189,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/rzrd/board_specific_top.sv b/boards/rzrd/board_specific_top.sv index dfe45fc6..0d7ada34 100644 --- a/boards/rzrd/board_specific_top.sv +++ b/boards/rzrd/board_specific_top.sv @@ -189,7 +189,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/rzrd_pmod_mic3/board_specific_top.sv b/boards/rzrd_pmod_mic3/board_specific_top.sv index 991d22c0..bec1a506 100644 --- a/boards/rzrd_pmod_mic3/board_specific_top.sv +++ b/boards/rzrd_pmod_mic3/board_specific_top.sv @@ -189,7 +189,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/saylinx/board_specific_top.sv b/boards/saylinx/board_specific_top.sv index 62e4f142..b5165a61 100644 --- a/boards/saylinx/board_specific_top.sv +++ b/boards/saylinx/board_specific_top.sv @@ -154,7 +154,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/saylinx_pmod_mic3/board_specific_top.sv b/boards/saylinx_pmod_mic3/board_specific_top.sv index 2ccb336c..67ccba09 100644 --- a/boards/saylinx_pmod_mic3/board_specific_top.sv +++ b/boards/saylinx_pmod_mic3/board_specific_top.sv @@ -154,7 +154,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index d9054cd2..af64929f 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -255,7 +255,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv index b3d48995..d622c1e4 100644 --- a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv @@ -276,7 +276,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - i_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/tang_primer_25k_dock/board_specific_top.sv b/boards/tang_primer_25k_dock/board_specific_top.sv index cbe06f98..8a976576 100644 --- a/boards/tang_primer_25k_dock/board_specific_top.sv +++ b/boards/tang_primer_25k_dock/board_specific_top.sv @@ -164,7 +164,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - i_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv index 52d945b0..fdb6e7fd 100644 --- a/boards/tang_primer_25k_dock_dvi/board_specific_top.sv +++ b/boards/tang_primer_25k_dock_dvi/board_specific_top.sv @@ -170,7 +170,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - i_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/zeowaa/board_specific_top.sv b/boards/zeowaa/board_specific_top.sv index a45d923b..6a33230c 100644 --- a/boards/zeowaa/board_specific_top.sv +++ b/boards/zeowaa/board_specific_top.sv @@ -133,7 +133,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), diff --git a/boards/zeowaa_wo_dig_0/board_specific_top.sv b/boards/zeowaa_wo_dig_0/board_specific_top.sv index 5634d43a..b34ec188 100644 --- a/boards/zeowaa_wo_dig_0/board_specific_top.sv +++ b/boards/zeowaa_wo_dig_0/board_specific_top.sv @@ -139,7 +139,7 @@ module board_specific_top # ( .clk_mhz ( clk_mhz ) ) - o_audio + inst_audio_out ( .clk ( clk ), .reset ( rst ), From 4c0d390f6ad87d443b7b0ede0d079106b570e5d9 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Wed, 24 Jul 2024 08:48:05 -0700 Subject: [PATCH 50/65] Draft of lcd 480x272 support in Tang Nano 9K --- .../board_specific_top.sv | 62 +++++++++++-------- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv index d622c1e4..a0740f10 100644 --- a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv @@ -5,18 +5,24 @@ module board_specific_top # ( - parameter clk_mhz = 27, - pixel_mhz = 9, - - w_key = 2, // The last key is used for a reset - w_sw = 0, - w_led = 6, - w_digit = 0, - w_gpio = 10, - - w_red = 5, - w_green = 6, - w_blue = 5 + parameter clk_mhz = 27, + pixel_mhz = 9, + + w_key = 2, // The last key is used for a reset + w_sw = 0, + w_led = 6, + w_digit = 0, + w_gpio = 10, + + screen_width = 480, + screen_height = 272, + + w_red = 5, + w_green = 6, + w_blue = 5, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input CLK, @@ -111,6 +117,10 @@ module board_specific_top wire rst; wire [ 7:0] abcdefgh; + + wire [w_x - 1:0] x; + wire [w_y - 1:0] y; + wire [ 23:0] mic; wire [ 15:0] sound; @@ -174,16 +184,13 @@ module board_specific_top .abcdefgh ( abcdefgh ), .digit ( lab_digit ), - .vsync ( LARGE_LCD_VS ), - .hsync ( LARGE_LCD_HS ), + .x ( x ), + .y ( y ), .red ( LARGE_LCD_R ), .green ( LARGE_LCD_G ), .blue ( LARGE_LCD_B ), - .display_on ( LARGE_LCD_DE ), - .pixel_clk ( LARGE_LCD_CK ), - .uart_rx ( UART_RX ), .uart_tx ( UART_TX ), @@ -194,26 +201,27 @@ module board_specific_top //------------------------------------------------------------------------ - Gowin_rPLL Gowin_rPLL_9Mhz + Gowin_rPLL i_Gowin_rPLL ( - .clkout(LCD_CLK), // 9MHz - .clkin(XTAL_IN) //27MHz + .clkout ( LARGE_LCD_CLK ), // 9 MHz + .clkin ( clk ) // 27 MHz ); lcd_480_272 ( - .PixelClk ( LARGE_LCD_CLK ), - .nRST ( rst ), + .PixelClk ( LARGE_LCD_CK ), + .nRST ( rst ), - .LCD_DE ( LARGE_LCD_DE ), - .LCD_HSYNC ( LARGE_LCD_HSYNC ), - .LCD_VSYNC ( LARGE_LCD_VSYNC ), + .LCD_DE ( LARGE_LCD_DE ), + .LCD_HSYNC ( LARGE_LCD_HS ), + .LCD_VSYNC ( LARGE_LCD_VS ), - .x ( x ), - .y ( y ) + .x ( x ), + .y ( y ) ); assign LARGE_LCD_INIT = 1'b0; + assign LARGE_LCD_BL = 1'b0; //------------------------------------------------------------------------ From f32e8cfea964743055a503a56e34faae75d6eafc Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Wed, 24 Jul 2024 08:49:20 -0700 Subject: [PATCH 51/65] Removed spaces at the end of the line --- peripherals/lcd_480_272.sv | 42 +++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/peripherals/lcd_480_272.sv b/peripherals/lcd_480_272.sv index 50974c83..e85628cf 100644 --- a/peripherals/lcd_480_272.sv +++ b/peripherals/lcd_480_272.sv @@ -27,15 +27,15 @@ module lcd_480_272 // Horizen count to Hsync, then next Horizen line. - parameter H_Pixel_Valid = 16'd480; + parameter H_Pixel_Valid = 16'd480; parameter H_FrontPorch = 16'd50; - parameter H_BackPorch = 16'd30; + parameter H_BackPorch = 16'd30; parameter PixelForHS = H_Pixel_Valid + H_FrontPorch + H_BackPorch; - parameter V_Pixel_Valid = 16'd272; - parameter V_FrontPorch = 16'd20; - parameter V_BackPorch = 16'd5; + parameter V_Pixel_Valid = 16'd272; + parameter V_FrontPorch = 16'd20; + parameter V_BackPorch = 16'd5; parameter PixelForVS = V_Pixel_Valid + V_FrontPorch + V_BackPorch; @@ -46,7 +46,7 @@ module lcd_480_272 always @( posedge PixelClk or negedge nRST )begin if( !nRST ) begin - V_PixelCount <= 16'b0; + V_PixelCount <= 16'b0; H_PixelCount <= 16'b0; end else if( H_PixelCount == PixelForHS ) begin @@ -64,9 +64,9 @@ module lcd_480_272 end // SYNC-DE MODE - + assign LCD_HSYNC = H_PixelCount <= (PixelForHS-H_FrontPorch) ? 1'b0 : 1'b1; - + assign LCD_VSYNC = V_PixelCount <= (PixelForVS-0) ? 1'b0 : 1'b1; assign LCD_DE = ( H_PixelCount >= H_BackPorch ) && ( H_PixelCount <= H_Pixel_Valid + H_BackPorch ) && @@ -82,23 +82,23 @@ module lcd_480_272 localparam Colorbar_width = H_Pixel_Valid / 16; assign LCD_R = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 0 )) ? 5'b00000 : - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 1 )) ? 5'b00001 : - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 2 )) ? 5'b00010 : - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 3 )) ? 5'b00100 : - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 4 )) ? 5'b01000 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 1 )) ? 5'b00001 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 2 )) ? 5'b00010 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 3 )) ? 5'b00100 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 4 )) ? 5'b01000 : ( H_PixelCount < ( H_BackPorch + Colorbar_width * 5 )) ? 5'b10000 : 5'b00000; - assign LCD_G = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 6 )) ? 6'b000001: - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 7 )) ? 6'b000010: - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 8 )) ? 6'b000100: - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 9 )) ? 6'b001000: - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 10 )) ? 6'b010000: + assign LCD_G = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 6 )) ? 6'b000001: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 7 )) ? 6'b000010: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 8 )) ? 6'b000100: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 9 )) ? 6'b001000: + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 10 )) ? 6'b010000: ( H_PixelCount < ( H_BackPorch + Colorbar_width * 11 )) ? 6'b100000: 6'b000000; - assign LCD_B = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 12 )) ? 5'b00001 : - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 13 )) ? 5'b00010 : - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 14 )) ? 5'b00100 : - ( H_PixelCount < ( H_BackPorch + Colorbar_width * 15 )) ? 5'b01000 : + assign LCD_B = ( H_PixelCount < ( H_BackPorch + Colorbar_width * 12 )) ? 5'b00001 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 13 )) ? 5'b00010 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 14 )) ? 5'b00100 : + ( H_PixelCount < ( H_BackPorch + Colorbar_width * 15 )) ? 5'b01000 : ( H_PixelCount < ( H_BackPorch + Colorbar_width * 16 )) ? 5'b10000 : 5'b00000; `endif From 58bfabb0f27888abdf67c6a7be17c1766a830c39 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Wed, 24 Jul 2024 09:11:53 -0700 Subject: [PATCH 52/65] Intermediate stage in LCD support --- boards/de2_115/board_specific_top.sv | 2 +- boards/tang_nano_9k_lcd/board_specific_top.sv | 186 +++++++++++------- .../board_specific_top.sv | 169 ++++++++-------- peripherals/lcd_480_272.sv | 8 +- 4 files changed, 210 insertions(+), 155 deletions(-) diff --git a/boards/de2_115/board_specific_top.sv b/boards/de2_115/board_specific_top.sv index ff6512e4..b2f6266b 100644 --- a/boards/de2_115/board_specific_top.sv +++ b/boards/de2_115/board_specific_top.sv @@ -229,7 +229,7 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE wire [9:0] x10; assign x = x10; wire [9:0] y10; assign y = y10; diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index af64929f..8772ca4a 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -1,22 +1,28 @@ `include "config.svh" `include "lab_specific_board_config.svh" -// `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( - parameter clk_mhz = 27, - pixel_mhz = 9, - - w_key = 2, // The last key is used for a reset - w_sw = 0, - w_led = 6, - w_digit = 0, - w_gpio = 10, - - w_red = 5, - w_green = 6, - w_blue = 5 + parameter clk_mhz = 27, + pixel_mhz = 9, + + w_key = 2, // The last key is used for a reset + w_sw = 0, + w_led = 6, + w_digit = 0, + w_gpio = 10, + + screen_width = 480, + screen_height = 272, + + w_red = 5, + w_green = 6, + w_blue = 5, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input CLK, @@ -111,6 +117,10 @@ module board_specific_top wire rst; wire [ 7:0] abcdefgh; + + wire [w_x - 1:0] x; + wire [w_y - 1:0] y; + wire [ 23:0] mic; wire [ 15:0] sound; @@ -147,53 +157,50 @@ module board_specific_top lab_top # ( - .clk_mhz ( clk_mhz ), - .pixel_mhz ( pixel_mhz ), - - .w_key ( w_lab_key ), // The last key is used for a reset - .w_sw ( w_lab_key ), - .w_led ( w_lab_led ), - .w_digit ( w_lab_digit ), - .w_gpio ( w_gpio ), - - .w_red ( w_red ), - .w_green ( w_green ), - .w_blue ( w_blue ) + .clk_mhz ( clk_mhz ), + + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_key ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( lab_key ), - .sw ( lab_key ), + .key ( lab_key ), + .sw ( lab_key ), - .led ( lab_led ), + .led ( lab_led ), - .abcdefgh ( abcdefgh ), - .digit ( lab_digit ), + .abcdefgh ( abcdefgh ), + .digit ( lab_digit ), - .vsync ( LARGE_LCD_VS ), - .hsync ( LARGE_LCD_HS ), + .x ( x ), + .y ( y ), - .red ( LARGE_LCD_R ), - .green ( LARGE_LCD_G ), - .blue ( LARGE_LCD_B ), + .red ( LARGE_LCD_R ), + .green ( LARGE_LCD_G ), + .blue ( LARGE_LCD_B ), - .display_on ( LARGE_LCD_DE ), - .pixel_clk ( LARGE_LCD_CK ), + .uart_rx ( UART_RX ), + .uart_tx ( UART_TX ), - .uart_rx ( UART_RX ), - .uart_tx ( UART_TX ), - - .mic ( mic ), - .sound ( sound ), - .gpio ( gpio ) + .mic ( mic ), + .sound ( sound ), + .gpio ( gpio ) ); - assign LARGE_LCD_INIT = 1'b0; - //------------------------------------------------------------------------ `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE @@ -237,33 +244,68 @@ module board_specific_top //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( TF_CS ), - .ws ( TF_MOSI ), - .sck ( TF_SCLK ), - .sd ( TF_MISO ), - .value ( mic ) - ); + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + Gowin_rPLL i_Gowin_rPLL + ( + .clkout ( LARGE_LCD_CLK ), // 9 MHz + .clkin ( clk ) // 27 MHz + ); + + lcd_480_272 + ( + .PixelClk ( LARGE_LCD_CK ), + .nRST ( rst ), + .LCD_DE ( LARGE_LCD_DE ), + .LCD_HSYNC ( LARGE_LCD_HS ), + .LCD_VSYNC ( LARGE_LCD_VS ), + + .x ( x ), + .y ( y ) + ); + + assign LARGE_LCD_INIT = 1'b0; + assign LARGE_LCD_BL = 1'b0; + + `endif //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - inst_audio_out - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), - .mclk ( SMALL_LCD_DATA ), - .bclk ( SMALL_LCD_CLK ), - .lrclk ( SMALL_LCD_RS ), - .sdata ( SMALL_LCD_CS ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE + + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( TF_CS ), + .ws ( TF_MOSI ), + .sck ( TF_SCLK ), + .sd ( TF_MISO ), + .value ( mic ) + ); + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( SMALL_LCD_DATA ), + .bclk ( SMALL_LCD_CLK ), + .lrclk ( SMALL_LCD_RS ), + .sdata ( SMALL_LCD_CS ) + ); + + `endif endmodule diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv index a0740f10..8772ca4a 100644 --- a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv @@ -157,74 +157,52 @@ module board_specific_top lab_top # ( - .clk_mhz ( clk_mhz ), - .pixel_mhz ( pixel_mhz ), - - .w_key ( w_lab_key ), // The last key is used for a reset - .w_sw ( w_lab_key ), - .w_led ( w_lab_led ), - .w_digit ( w_lab_digit ), - .w_gpio ( w_gpio ), - - .w_red ( w_red ), - .w_green ( w_green ), - .w_blue ( w_blue ) + .clk_mhz ( clk_mhz ), + + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_key ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( lab_key ), - .sw ( lab_key ), + .key ( lab_key ), + .sw ( lab_key ), - .led ( lab_led ), + .led ( lab_led ), - .abcdefgh ( abcdefgh ), - .digit ( lab_digit ), + .abcdefgh ( abcdefgh ), + .digit ( lab_digit ), - .x ( x ), - .y ( y ), + .x ( x ), + .y ( y ), - .red ( LARGE_LCD_R ), - .green ( LARGE_LCD_G ), - .blue ( LARGE_LCD_B ), + .red ( LARGE_LCD_R ), + .green ( LARGE_LCD_G ), + .blue ( LARGE_LCD_B ), - .uart_rx ( UART_RX ), - .uart_tx ( UART_TX ), + .uart_rx ( UART_RX ), + .uart_tx ( UART_TX ), - .mic ( mic ), - .sound ( sound ), - .gpio ( gpio ) + .mic ( mic ), + .sound ( sound ), + .gpio ( gpio ) ); //------------------------------------------------------------------------ - Gowin_rPLL i_Gowin_rPLL - ( - .clkout ( LARGE_LCD_CLK ), // 9 MHz - .clkin ( clk ) // 27 MHz - ); - - lcd_480_272 - ( - .PixelClk ( LARGE_LCD_CK ), - .nRST ( rst ), - - .LCD_DE ( LARGE_LCD_DE ), - .LCD_HSYNC ( LARGE_LCD_HS ), - .LCD_VSYNC ( LARGE_LCD_VS ), - - .x ( x ), - .y ( y ) - ); - - assign LARGE_LCD_INIT = 1'b0; - assign LARGE_LCD_BL = 1'b0; - - //------------------------------------------------------------------------ - `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE wire [$left (abcdefgh):0] hgfedcba; @@ -266,33 +244,68 @@ module board_specific_top //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( TF_CS ), - .ws ( TF_MOSI ), - .sck ( TF_SCLK ), - .sd ( TF_MISO ), - .value ( mic ) - ); + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + Gowin_rPLL i_Gowin_rPLL + ( + .clkout ( LARGE_LCD_CLK ), // 9 MHz + .clkin ( clk ) // 27 MHz + ); + lcd_480_272 + ( + .PixelClk ( LARGE_LCD_CK ), + .nRST ( rst ), + + .LCD_DE ( LARGE_LCD_DE ), + .LCD_HSYNC ( LARGE_LCD_HS ), + .LCD_VSYNC ( LARGE_LCD_VS ), + + .x ( x ), + .y ( y ) + ); + + assign LARGE_LCD_INIT = 1'b0; + assign LARGE_LCD_BL = 1'b0; + + `endif //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - inst_audio_out - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), - .mclk ( SMALL_LCD_DATA ), - .bclk ( SMALL_LCD_CLK ), - .lrclk ( SMALL_LCD_RS ), - .sdata ( SMALL_LCD_CS ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE + + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( TF_CS ), + .ws ( TF_MOSI ), + .sck ( TF_SCLK ), + .sd ( TF_MISO ), + .value ( mic ) + ); + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( SMALL_LCD_DATA ), + .bclk ( SMALL_LCD_CLK ), + .lrclk ( SMALL_LCD_RS ), + .sdata ( SMALL_LCD_CS ) + ); + + `endif endmodule diff --git a/peripherals/lcd_480_272.sv b/peripherals/lcd_480_272.sv index e85628cf..abd2ecdf 100644 --- a/peripherals/lcd_480_272.sv +++ b/peripherals/lcd_480_272.sv @@ -21,8 +21,8 @@ module lcd_480_272 // Modified for basic-graphics-music: Added x and y outputs - output [8:0] x, - output [8:0] y + output [6:0] x, + output [6:0] y ); // Horizen count to Hsync, then next Horizen line. @@ -105,7 +105,7 @@ module lcd_480_272 // Modified for basic-graphics-music: Added x and y outputs - assign x = V_PixelCount - V_BackPorch; - assign y = H_PixelCount - H_BackPorch; + assign x = 7' (V_PixelCount - V_BackPorch); + assign y = 7' (H_PixelCount - H_BackPorch); endmodule From 6d11520a37e5c4b9339928d71aac12692d9ea313 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Wed, 24 Jul 2024 09:15:35 -0700 Subject: [PATCH 53/65] Intermediate stage in LCD support 2 --- boards/tang_nano_9k_lcd/board_specific_top.sv | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index 8772ca4a..cdfc0830 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -246,23 +246,24 @@ module board_specific_top `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE - Gowin_rPLL i_Gowin_rPLL - ( - .clkout ( LARGE_LCD_CLK ), // 9 MHz - .clkin ( clk ) // 27 MHz - ); + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; - lcd_480_272 + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga ( - .PixelClk ( LARGE_LCD_CK ), - .nRST ( rst ), - - .LCD_DE ( LARGE_LCD_DE ), - .LCD_HSYNC ( LARGE_LCD_HS ), - .LCD_VSYNC ( LARGE_LCD_VS ), - - .x ( x ), - .y ( y ) + .clk ( clk ), + .rst ( rst ), + .hsync ( LARGE_LCD_HS ), + .vsync ( LARGE_LCD_VS ), + .display_on ( LARGE_LCD_DE ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( LARGE_LCD_CK ) ); assign LARGE_LCD_INIT = 1'b0; From f91f4732d8207f8cb14ffed71a8cd15604fb7402 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Wed, 24 Jul 2024 10:04:46 -0700 Subject: [PATCH 54/65] lcd 480x272 started to work --- .../board_specific_top.sv | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv index 8772ca4a..1c4b25c6 100644 --- a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv @@ -248,21 +248,21 @@ module board_specific_top Gowin_rPLL i_Gowin_rPLL ( - .clkout ( LARGE_LCD_CLK ), // 9 MHz - .clkin ( clk ) // 27 MHz + .clkout ( LARGE_LCD_CK ), // 9 MHz + .clkin ( clk ) // 27 MHz ); lcd_480_272 ( - .PixelClk ( LARGE_LCD_CK ), - .nRST ( rst ), + .PixelClk ( LARGE_LCD_CK ), + .nRST ( ~ rst ), - .LCD_DE ( LARGE_LCD_DE ), - .LCD_HSYNC ( LARGE_LCD_HS ), - .LCD_VSYNC ( LARGE_LCD_VS ), + .LCD_DE ( LARGE_LCD_DE ), + .LCD_HSYNC ( LARGE_LCD_HS ), + .LCD_VSYNC ( LARGE_LCD_VS ), - .x ( x ), - .y ( y ) + .x ( x ), + .y ( y ) ); assign LARGE_LCD_INIT = 1'b0; From 9d6a937dd0bc4fc2934ff6f5c93d99cb7e74c02a Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Wed, 24 Jul 2024 10:05:29 -0700 Subject: [PATCH 55/65] enabled tm1638 again --- boards/tang_nano_9k_lcd/board_specific_top.sv | 2 +- boards/tang_nano_9k_lcd_480_272/board_specific_top.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/tang_nano_9k_lcd/board_specific_top.sv b/boards/tang_nano_9k_lcd/board_specific_top.sv index cdfc0830..3441c07d 100644 --- a/boards/tang_nano_9k_lcd/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +// `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv index 1c4b25c6..03d0e88a 100644 --- a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv @@ -1,7 +1,7 @@ `include "config.svh" `include "lab_specific_board_config.svh" -`undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +// `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE module board_specific_top # ( From 8de917cb2d94b33684974504cadbdc7c37fefdf7 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Thu, 25 Jul 2024 00:23:22 -0700 Subject: [PATCH 56/65] Fixed bugs in 480x272 LCD support in Tang Nano 9K --- .../board_specific_top.sv | 10 ++++-- .../2_1_rectangle_ellipse_parabola/lab_top.sv | 36 ++++++++++++++++--- peripherals/lcd_480_272.sv | 8 ++--- 3 files changed, 43 insertions(+), 11 deletions(-) diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv index 03d0e88a..a7885774 100644 --- a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv @@ -126,7 +126,6 @@ module board_specific_top //------------------------------------------------------------------------ - `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE assign rst = tm_key [w_tm_key - 1]; @@ -155,6 +154,11 @@ module board_specific_top //------------------------------------------------------------------------ + wire [w_x - 1:0] mirrored_x = w_x' (screen_width - 1 - x); + wire [w_y - 1:0] mirrored_y = w_y' (screen_height - 1 - y); + + //------------------------------------------------------------------------ + lab_top # ( .clk_mhz ( clk_mhz ), @@ -186,8 +190,8 @@ module board_specific_top .abcdefgh ( abcdefgh ), .digit ( lab_digit ), - .x ( x ), - .y ( y ), + .x ( mirrored_x ), + .y ( mirrored_y ), .red ( LARGE_LCD_R ), .green ( LARGE_LCD_G ), diff --git a/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv b/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv index 85c982a0..b73d45b5 100644 --- a/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv +++ b/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv @@ -71,10 +71,39 @@ module lab_top //------------------------------------------------------------------------ // Pattern 1 - /**/ - wire [w_x * 2 - 1:0] x_2 = x * x; + always_comb + begin + red = '0; + green = '0; + blue = '0; + + if (x > 100 & y > 100 & x < 150 & y < 400) // Rectangle + begin + red = '0; + green = '1; + blue = '0; + end + `ifdef YOSYS + else if ((((x - 400) * (x - 400)) + 2 * (y - 300) * (y - 300) ) < (100 * 100)) // Ellipse + `else + else if ((((x - 400) ** 2) + 2 * (y - 300) ** 2) < 100 ** 2) // Ellipse + `endif + begin + red = '1; + green = '0; + blue = '0; + end + else if (x_2 [9 +: w_y] < y) // Parabola + begin + red = '0; + green = '0; + blue = '1; + end + end + +/* always_comb begin red = '0; @@ -104,8 +133,7 @@ module lab_top blue = '1; end end - - /**/ +*/ //------------------------------------------------------------------------ // Pattern 3 - dynamic diff --git a/peripherals/lcd_480_272.sv b/peripherals/lcd_480_272.sv index abd2ecdf..f1776e33 100644 --- a/peripherals/lcd_480_272.sv +++ b/peripherals/lcd_480_272.sv @@ -21,8 +21,8 @@ module lcd_480_272 // Modified for basic-graphics-music: Added x and y outputs - output [6:0] x, - output [6:0] y + output [8:0] x, + output [8:0] y ); // Horizen count to Hsync, then next Horizen line. @@ -105,7 +105,7 @@ module lcd_480_272 // Modified for basic-graphics-music: Added x and y outputs - assign x = 7' (V_PixelCount - V_BackPorch); - assign y = 7' (H_PixelCount - H_BackPorch); + assign x = 9' (H_PixelCount - H_BackPorch); + assign y = 9' (V_PixelCount - V_BackPorch); endmodule From 9ca6322a945c87ee3a47887dfc116447f7177eae Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Thu, 25 Jul 2024 08:37:33 -0700 Subject: [PATCH 57/65] Added no_tm1638 version of tang_nano_9k --- .../board_specific.cst | 0 .../board_specific.sdc | 0 .../board_specific.tcl | 0 .../board_specific_top.sv | 2 + .../fpga_project_01.gprj | 0 .../fpga_project_02.gprj | 0 .../gowin_rpll.ipc | 0 .../gowin_rpll.mod | 0 .../gowin_rpll.v | 0 .../project_process_config_01.json | 0 .../project_process_config_02.json | 0 .../board_specific.cst | 95 +++++++++++++++++++ .../board_specific.sdc | 4 + .../board_specific.tcl | 11 +++ .../board_specific_top.sv | 4 +- .../fpga_project_01.gprj | 7 ++ .../fpga_project_02.gprj | 2 + .../gowin_rpll.ipc | 24 +++++ .../gowin_rpll.mod | 32 +++++++ .../gowin_rpll.v | 63 ++++++++++++ .../project_process_config_01.json | 32 +++++++ .../project_process_config_02.json | 53 +++++++++++ .../2_1_rectangle_ellipse_parabola/lab_top.sv | 61 +++--------- 23 files changed, 343 insertions(+), 47 deletions(-) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/board_specific.cst (100%) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/board_specific.sdc (100%) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/board_specific.tcl (100%) create mode 100644 boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific_top.sv rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/fpga_project_01.gprj (100%) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/fpga_project_02.gprj (100%) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/gowin_rpll.ipc (100%) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/gowin_rpll.mod (100%) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/gowin_rpll.v (100%) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/project_process_config_01.json (100%) rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_no_tm1638}/project_process_config_02.json (100%) create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.cst create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.sdc create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.tcl rename boards/{tang_nano_9k_lcd_480_272 => tang_nano_9k_lcd_480_272_tm1638}/board_specific_top.sv (98%) create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_01.gprj create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_02.gprj create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.ipc create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.mod create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.v create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_01.json create mode 100644 boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_02.json diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific.cst b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.cst similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/board_specific.cst rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.cst diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific.sdc b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.sdc similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/board_specific.sdc rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.sdc diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific.tcl b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.tcl similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/board_specific.tcl rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific.tcl diff --git a/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific_top.sv new file mode 100644 index 00000000..1a425fca --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_no_tm1638/board_specific_top.sv @@ -0,0 +1,2 @@ +`define FORCE_NO_INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +`include "../tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv" diff --git a/boards/tang_nano_9k_lcd_480_272/fpga_project_01.gprj b/boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_01.gprj similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/fpga_project_01.gprj rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_01.gprj diff --git a/boards/tang_nano_9k_lcd_480_272/fpga_project_02.gprj b/boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_02.gprj similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/fpga_project_02.gprj rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/fpga_project_02.gprj diff --git a/boards/tang_nano_9k_lcd_480_272/gowin_rpll.ipc b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.ipc similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/gowin_rpll.ipc rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.ipc diff --git a/boards/tang_nano_9k_lcd_480_272/gowin_rpll.mod b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.mod similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/gowin_rpll.mod rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.mod diff --git a/boards/tang_nano_9k_lcd_480_272/gowin_rpll.v b/boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.v similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/gowin_rpll.v rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/gowin_rpll.v diff --git a/boards/tang_nano_9k_lcd_480_272/project_process_config_01.json b/boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_01.json similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/project_process_config_01.json rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_01.json diff --git a/boards/tang_nano_9k_lcd_480_272/project_process_config_02.json b/boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_02.json similarity index 100% rename from boards/tang_nano_9k_lcd_480_272/project_process_config_02.json rename to boards/tang_nano_9k_lcd_480_272_no_tm1638/project_process_config_02.json diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.cst b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.cst new file mode 100644 index 00000000..a3feafaa --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.cst @@ -0,0 +1,95 @@ +# The pin assignments +# All I/O pins here are 3.3V compatible unless specified otherwise + +IO_LOC "CLK" 52; + +IO_LOC "KEY[0]" 4; +IO_LOC "KEY[1]" 3; + +IO_LOC "LED[0]" 10; +IO_LOC "LED[1]" 11; +IO_LOC "LED[2]" 13; +IO_LOC "LED[3]" 14; +IO_LOC "LED[4]" 15; +IO_LOC "LED[5]" 16; + +IO_LOC "LARGE_LCD_DE" 33; +IO_LOC "LARGE_LCD_VS" 34; +IO_LOC "LARGE_LCD_HS" 40; +IO_LOC "LARGE_LCD_CK" 35; +IO_LOC "LARGE_LCD_INIT" 63; +IO_LOC "LARGE_LCD_BL" 86; + +IO_LOC "LARGE_LCD_R[3]" 75; +IO_LOC "LARGE_LCD_R[4]" 74; +IO_LOC "LARGE_LCD_R[5]" 73; +IO_LOC "LARGE_LCD_R[6]" 72; +IO_LOC "LARGE_LCD_R[7]" 71; + +IO_LOC "LARGE_LCD_G[2]" 70; +IO_LOC "LARGE_LCD_G[3]" 69; +IO_LOC "LARGE_LCD_G[4]" 68; +IO_LOC "LARGE_LCD_G[5]" 57; +IO_LOC "LARGE_LCD_G[6]" 56; +IO_LOC "LARGE_LCD_G[7]" 55; + +IO_LOC "LARGE_LCD_B[3]" 54; +IO_LOC "LARGE_LCD_B[4]" 53; +IO_LOC "LARGE_LCD_B[5]" 51; +IO_LOC "LARGE_LCD_B[6]" 42; +IO_LOC "LARGE_LCD_B[7]" 41; + +IO_LOC "UART_RX" 18; +IO_LOC "UART_TX" 17; + +# The following 4 pins (TF_CS, TF_MOSI, TF_SCLK, TF_MISO) +# are used for INMP441 microphone +# in basics-graphics-music labs + +IO_LOC "TF_CS" 38; # inmp441: lr +IO_LOC "TF_MOSI" 37; # inmp441: ws +IO_LOC "TF_SCLK" 36; # inmp441: sck +IO_LOC "TF_MISO" 39; # inmp441: sd + +# The first 3 GPIO pins are used for TM1638 I/O module +# which carries 8 LEDs, 8-digit 7-segment display and 8 keys + +IO_LOC "GPIO[0]" 25; # tm1638: sio_data +IO_LOC "GPIO[1]" 26; # tm1638: sio_clk +IO_LOC "GPIO[2]" 27; # tm1638: sio_stb +IO_LOC "GPIO[3]" 28; +IO_LOC "GPIO[4]" 29; +IO_LOC "GPIO[5]" 30; + +# The 4 pins SMALL_LCD_CLK, _CS, _RS and _DATA +# are used for the I2S audio output module PCM5102 +# in basics-graphics-music labs + +IO_LOC "SMALL_LCD_DATA" 77; # pcm5102: sck i2s_audio_out: mclk +IO_LOC "SMALL_LCD_CLK" 76; # pcm5102: bck i2s_audio_out: bclk +IO_LOC "SMALL_LCD_RESETN" 47; +IO_LOC "SMALL_LCD_CS" 48; # pcm5102: din i2s_audio_out: sdata +IO_LOC "SMALL_LCD_RS" 49; # pcm5102: lrck i2s_audio_out: lrclk + +# TMDS pins will be used later + +# IO_LOC "TMDS_CLK_P" 69,68; +# IO_LOC "TMDS_D_P[0]" 71,70; +# IO_LOC "TMDS_D_P[1]" 73,72; +# IO_LOC "TMDS_D_P[2]" 75,74; + +IO_LOC "FLASH_CLK" 59; +IO_LOC "FLASH_CSB" 60; +IO_LOC "FLASH_MOSI" 61; +IO_LOC "FLASH_MISO" 62; + +# The following pins are not used for the lab examples +# because they are 1.8V compatible + +# IO_LOC "GPIO_1_8_V_UNUSED[0]" 85; +# IO_LOC "GPIO_1_8_V_UNUSED[1]" 84; +# IO_LOC "GPIO_1_8_V_UNUSED[2]" 83; +# IO_LOC "GPIO_1_8_V_UNUSED[3]" 82; +# IO_LOC "GPIO_1_8_V_UNUSED[4]" 81; +# IO_LOC "GPIO_1_8_V_UNUSED[5]" 80; +# IO_LOC "GPIO_1_8_V_UNUSED[6]" 79; diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.sdc b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.sdc new file mode 100644 index 00000000..bf0aab16 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.sdc @@ -0,0 +1,4 @@ +# The timing constraints + +create_clock -name CLK -period 37.037 -waveform {0 18.518} [get_ports {CLK}] +create_clock -name LARGE_LCD_CK -period 111.11 -waveform {0 55.555} [get_ports {LARGE_LCD_CK}] diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.tcl b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.tcl new file mode 100644 index 00000000..794089f1 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific.tcl @@ -0,0 +1,11 @@ +# Synthesis and Place & Route settings + +set_device GW1NR-LV9QN88PC6/I5 -name GW1NR-9 -device_version C + +set_option -synthesis_tool gowinsynthesis +set_option -output_base_name fpga_project +set_option -top_module board_specific_top +set_option -verilog_std sysv2017 + +set_option -use_mspi_as_gpio 1 +set_option -use_sspi_as_gpio 1 diff --git a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv similarity index 98% rename from boards/tang_nano_9k_lcd_480_272/board_specific_top.sv rename to boards/tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv index a7885774..65451d7c 100644 --- a/boards/tang_nano_9k_lcd_480_272/board_specific_top.sv +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/board_specific_top.sv @@ -1,7 +1,9 @@ `include "config.svh" `include "lab_specific_board_config.svh" -// `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +`ifdef FORCE_NO_INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +`endif module board_specific_top # ( diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_01.gprj b/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_01.gprj new file mode 100644 index 00000000..79b1311f --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_01.gprj @@ -0,0 +1,7 @@ + + + + + 5 + gw1nr9c-004 + diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_02.gprj b/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_02.gprj new file mode 100644 index 00000000..8c6b9904 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/fpga_project_02.gprj @@ -0,0 +1,2 @@ + + diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.ipc b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.ipc new file mode 100644 index 00000000..bf8c92d9 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.ipc @@ -0,0 +1,24 @@ +[General] +ipc_version=4 +file=gowin_rpll +module=Gowin_rPLL +target_device=gw1nr9c-004 +type=clock_rpll +version=1.0 + +[Config] +CKLOUTD3=false +CLKFB_SOURCE=0 +CLKIN_FREQ=27 +CLKOUTD=false +CLKOUTP=false +CLKOUT_BYPASS=false +CLKOUT_DIVIDE_DYN=true +CLKOUT_FREQ=9 +CLKOUT_TOLERANCE=0 +DYNAMIC=true +LANG=0 +LOCK_EN=false +MODE_GENERAL=true +PLL_PWD=false +RESET_PLL=false diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.mod b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.mod new file mode 100644 index 00000000..39dc975c --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.mod @@ -0,0 +1,32 @@ +-series GW1NR +-device GW1NR-9C +-package QFN88P +-part_number GW1NR-LV9QN88PC6/I5 + + +-mod_name Gowin_rPLL +-file_name gowin_rpll +-path Y:/4.3inch_screen/lcd_led/src/gowin_rpll/ +-type PLL +-rPll true +-file_type vlg +-dev_type GW1NR-9C +-dyn_idiv_sel false +-idiv_sel 3 +-dyn_fbdiv_sel false +-fbdiv_sel 1 +-dyn_odiv_sel false +-odiv_sel 48 +-dyn_da_en true +-rst_sig false +-rst_sig_p false +-fclkin 27 +-clkfb_sel 0 +-en_lock false +-clkout_bypass false +-clkout_ft_dir 1 +-en_clkoutp false +-clkoutp_bypass false +-en_clkoutd false +-clkoutd_bypass false +-en_clkoutd3 false \ No newline at end of file diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.v b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.v new file mode 100644 index 00000000..95f15287 --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/gowin_rpll.v @@ -0,0 +1,63 @@ +//Copyright (C)2014-2022 Gowin Semiconductor Corporation. +//All rights reserved. +//File Title: IP file +//GOWIN Version: V1.9.8.09 +//Part Number: GW1NR-LV9QN88PC6/I5 +//Device: GW1NR-9C +//Created Time: Tue Mar 21 12:46:45 2023 + +module Gowin_rPLL (clkout, clkin); + +output clkout; +input clkin; + +wire lock_o; +wire clkoutp_o; +wire clkoutd_o; +wire clkoutd3_o; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +rPLL rpll_inst ( + .CLKOUT(clkout), + .LOCK(lock_o), + .CLKOUTP(clkoutp_o), + .CLKOUTD(clkoutd_o), + .CLKOUTD3(clkoutd3_o), + .RESET(gw_gnd), + .RESET_P(gw_gnd), + .CLKIN(clkin), + .CLKFB(gw_gnd), + .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) +); + +defparam rpll_inst.FCLKIN = "27"; +defparam rpll_inst.DYN_IDIV_SEL = "false"; +defparam rpll_inst.IDIV_SEL = 2; +defparam rpll_inst.DYN_FBDIV_SEL = "false"; +defparam rpll_inst.FBDIV_SEL = 0; +defparam rpll_inst.DYN_ODIV_SEL = "false"; +defparam rpll_inst.ODIV_SEL = 48; +defparam rpll_inst.PSDA_SEL = "0000"; +defparam rpll_inst.DYN_DA_EN = "true"; +defparam rpll_inst.DUTYDA_SEL = "1000"; +defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUT_DLY_STEP = 0; +defparam rpll_inst.CLKOUTP_DLY_STEP = 0; +defparam rpll_inst.CLKFB_SEL = "internal"; +defparam rpll_inst.CLKOUT_BYPASS = "false"; +defparam rpll_inst.CLKOUTP_BYPASS = "false"; +defparam rpll_inst.CLKOUTD_BYPASS = "false"; +defparam rpll_inst.DYN_SDIV_SEL = 2; +defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; +defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; +defparam rpll_inst.DEVICE = "GW1NR-9C"; + +endmodule //Gowin_rPLL diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_01.json b/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_01.json new file mode 100644 index 00000000..8b6c52aa --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_01.json @@ -0,0 +1,32 @@ +{ + "Allow_Duplicate_Modules" : false, + "Annotated_Properties_for_Analyst" : true, + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CRC_CHECK" : true, + "Clock_Conversion" : true, + "Clock_Route_Order" : 0, + "Correct_Hold_Violation" : true, + "DONE" : true, + "DOWNLOAD_SPEED" : "default", + "Default_Enum_Encoding" : "default", + "Disable_Insert_Pad" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "FORMAT" : "binary", + "FSM Compiler" : true, + "Fanout_Guide" : 10000, + "Frequency" : "Auto", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "Implicit_Initial_Value_Support" : false, + "IncludePath" : [ diff --git a/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_02.json b/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_02.json new file mode 100644 index 00000000..a861fbcd --- /dev/null +++ b/boards/tang_nano_9k_lcd_480_272_tm1638/project_process_config_02.json @@ -0,0 +1,53 @@ + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "Multiple_File_Compilation_Unit" : true, + "Number_of_Critical_Paths" : "", + "Number_of_Start/End_Points" : "", + "OUTPUT_BASE_NAME" : "fpga_project", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "Pipelining" : true, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "Push_Tristates" : true, + "READY" : true, + "RECONFIG_N" : false, + "Ram_RW_Check" : true, + "Report_Auto-Placed_Io_Information" : false, + "Resolve_Mixed_Drivers" : false, + "Resource_Sharing" : true, + "Retiming" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SPI_FLASH_ADDR" : "00000000", + "SSPI" : true, + "Show_All_Warnings" : false, + "Synthesis On/Off Implemented as Translate On/Off" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "board_specific_top", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "Update_Compile_Point_Timing_Data" : false, + "Use_Clock_Period_for_Unconstrainted IO" : false, + "VCCAUX" : 3.3, + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_Sysv2017", + "WAKE_UP" : "0", + "Write_Vendor_Constraint_File" : true, + "dsp_balance" : false, + "show_all_warnings" : false, + "turn_off_bg" : false +} diff --git a/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv b/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv index b73d45b5..605c8812 100644 --- a/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv +++ b/labs/2_graphics/2_1_rectangle_ellipse_parabola/lab_top.sv @@ -73,67 +73,36 @@ module lab_top wire [w_x * 2 - 1:0] x_2 = x * x; - always_comb - begin - red = '0; - green = '0; - blue = '0; + /**/ - if (x > 100 & y > 100 & x < 150 & y < 400) // Rectangle - begin - red = '0; - green = '1; - blue = '0; - end - `ifdef YOSYS - else if ((((x - 400) * (x - 400)) + 2 * (y - 300) * (y - 300) ) < (100 * 100)) // Ellipse - `else - else if ((((x - 400) ** 2) + 2 * (y - 300) ** 2) < 100 ** 2) // Ellipse - `endif - begin - red = '1; - green = '0; - blue = '0; - end - else if (x_2 [9 +: w_y] < y) // Parabola - begin - red = '0; - green = '0; - blue = '1; - end - end - -/* always_comb begin red = '0; green = '0; blue = '0; - if (x > 100 & y > 100 & x < 150 & y < 400) // Rectangle + if ( x >= screen_width / 2 + & x < screen_width * 2 / 3 + & y >= screen_height / 2 + & y < screen_height * 2 / 3 ) begin - red = x [w_x - 2 -: w_red]; - green = '1; - blue = y [w_y - 2 -: w_blue]; + green = x [w_x - 2 -: w_green]; end + `ifdef YOSYS - else if ((((x - 400) * (x - 400)) + 2 * (y - 300) * (y - 300) ) < (100 * 100)) // Ellipse + if (x * x + 2 * y * y < screen_width * screen_width / 4) // Ellipse `else - else if ((((x - 400) ** 2) + 2 * (y - 300) ** 2) < 100 ** 2) // Ellipse + if (x ** 2 + 2 * y ** 2 < (screen_width / 2) ** 2) // Ellipse `endif begin - red = '1; - green = x [w_x - 2 -: w_green]; - blue = y [w_y - 2 -: w_blue]; - end - else if (x_2 [9 +: w_y] < y) // Parabola - begin - red = x [w_x - 2 -: w_red]; - green = y [w_y - 2 -: w_green]; - blue = '1; + red = x [w_x - 2 -: w_red]; end + + if (x_2 [w_x +: w_y] < y) // Parabola + blue = y [w_y - 1 -: w_blue]; end -*/ + + /**/ //------------------------------------------------------------------------ // Pattern 3 - dynamic From ddbbb0df87e557f4cf7fe9c79e2393119e6796db Mon Sep 17 00:00:00 2001 From: Kinnevo Date: Sun, 28 Jul 2024 14:28:16 -0700 Subject: [PATCH 58/65] Update way to access VGA with new configuration structure --- boards/de10_lite/board_specific_top.sv | 83 +++++++++++++++++++++++--- 1 file changed, 74 insertions(+), 9 deletions(-) diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index ccfc66c0..11127e1d 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -4,11 +4,23 @@ module board_specific_top # ( parameter clk_mhz = 50, + pixel_mhz = 25, w_key = 2, w_sw = 10, w_led = 10, w_digit = 6, - w_gpio = 36 // GPIO[5:0] reserved for mic + w_gpio = 36, // GPIO[5:0] reserved for mic + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) + ) ( input MAX10_CLK1_50, @@ -24,11 +36,15 @@ module board_specific_top output logic [7:0] HEX4, output logic [7:0] HEX5, - output VGA_HS, - output VGA_VS, - output [ 3:0] VGA_R, - output [ 3:0] VGA_G, - output [ 3:0] VGA_B, + + output VGA_CLK, + output VGA_HS, + output VGA_VS, + output [w_red - 1:0] VGA_R, + output [w_green - 1:0] VGA_G, + output [w_blue - 1:0] VGA_B, + output VGA_BLANK_N, + output VGA_SYNC_N, inout [w_gpio - 1:0] GPIO ); @@ -48,6 +64,16 @@ module board_specific_top wire [ 7:0] abcdefgh; wire [w_digit - 1:0] digit; + // Graphics + + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; + + wire [ w_red - 1:0] red; + wire [ w_green - 1:0] green; + wire [ w_blue - 1:0] blue; + + wire [ 23:0] mic; wire [ 15:0] sound; @@ -71,7 +97,17 @@ module board_specific_top .w_sw ( w_lab_sw ), .w_led ( w_led ), .w_digit ( w_digit ), - .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic + .w_gpio ( w_gpio ), // GPIO[5:0] reserved for mic + + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) + + ) i_lab_top ( @@ -87,8 +123,9 @@ module board_specific_top .abcdefgh ( abcdefgh ), .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + .x ( x ), + .y ( y ), + .red ( VGA_R ), .green ( VGA_G ), @@ -152,6 +189,33 @@ module board_specific_top if (digit [5]) HEX5 <= ~ hgfedcba; end + `endif + + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( VGA_CLK ) + ); + + assign VGA_BLANK_N = 1'b1; + assign VGA_SYNC_N = 1'b0; + `endif //------------------------------------------------------------------------ @@ -187,4 +251,5 @@ module board_specific_top .sdata ( GPIO [29] ) // JP1 pin 34 ); // JP1 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + endmodule From 102fc499613179cced2c215a5d0f79a5fe40d043 Mon Sep 17 00:00:00 2001 From: Jorge Zavala Date: Sun, 28 Jul 2024 14:52:37 -0700 Subject: [PATCH 59/65] Update board_specific_top.sv updated the pixel_mhz to keep the same of clk_mhz --- boards/de10_lite/board_specific_top.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index 11127e1d..cf23e941 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -4,7 +4,7 @@ module board_specific_top # ( parameter clk_mhz = 50, - pixel_mhz = 25, + pixel_mhz = 50, w_key = 2, w_sw = 10, w_led = 10, From c2b142c7da586e75c89a58210f90cc6c69920df9 Mon Sep 17 00:00:00 2001 From: Jorge Zavala Date: Sun, 28 Jul 2024 14:54:35 -0700 Subject: [PATCH 60/65] Update board_specific_top.sv removed the VGA_CLK output --- boards/de10_lite/board_specific_top.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/boards/de10_lite/board_specific_top.sv b/boards/de10_lite/board_specific_top.sv index cf23e941..3c1aca87 100644 --- a/boards/de10_lite/board_specific_top.sv +++ b/boards/de10_lite/board_specific_top.sv @@ -37,7 +37,6 @@ module board_specific_top output logic [7:0] HEX5, - output VGA_CLK, output VGA_HS, output VGA_VS, output [w_red - 1:0] VGA_R, From 86cfb03edfd1c171a8500e5220d74c75f9015557 Mon Sep 17 00:00:00 2001 From: Narayanan94 Date: Sun, 28 Jul 2024 15:42:04 -0700 Subject: [PATCH 61/65] Add files via upload --- boards/de0_cv/board_specific_top.sv | 49 +++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 6 deletions(-) diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index 589c5d1e..066e1d7c 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -3,12 +3,17 @@ module board_specific_top # ( - parameter clk_mhz = 50, + parameter clk_mhz = 50, + pixel_mhz = 25, w_key = 4, w_sw = 10, w_led = 10, w_digit = 6, - w_gpio = 72 // GPIO_0[5:0] reserved for mic + w_gpio = 72, // GPIO_0[5:0] reserved for mic + screen_width = 640, + screen_height = 480, + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( input CLOCK_50, @@ -24,7 +29,9 @@ module board_specific_top output logic [ 6:0] HEX3, output logic [ 6:0] HEX4, output logic [ 6:0] HEX5, - + output VGA_CLK, + output VGA_BLANK_N, + output VGA_SYNC_N, output VGA_HS, output VGA_VS, output [ 3:0] VGA_R, @@ -36,7 +43,8 @@ module board_specific_top ); //------------------------------------------------------------------------ - + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; wire clk = CLOCK_50; wire rst = ~ RESET_N; @@ -87,8 +95,12 @@ module board_specific_top .abcdefgh ( abcdefgh ), .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + //.vsync ( VGA_VS ), + //.hsync ( VGA_HS ), + + + .x ( x ), + .y ( y ), .red ( VGA_R ), .green ( VGA_G ), @@ -120,7 +132,32 @@ module board_specific_top assign hgfedcba [i] = abcdefgh [$left (abcdefgh) - i]; end endgenerate + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( VGA_CLK ) + ); + + assign VGA_BLANK_N = 1'b1; + assign VGA_SYNC_N = 1'b0; + `endif //------------------------------------------------------------------------ `ifdef EMULATE_DYNAMIC_7SEG_ON_STATIC_WITHOUT_STICKY_FLOPS From d6f66ae9929f9a5f569df8d4ee55c68be6b6db2c Mon Sep 17 00:00:00 2001 From: Narayanan94 Date: Sun, 28 Jul 2024 15:46:19 -0700 Subject: [PATCH 62/65] Add files via upload --- boards/de0_cv/board_specific_top.sv | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/boards/de0_cv/board_specific_top.sv b/boards/de0_cv/board_specific_top.sv index 066e1d7c..66ac3433 100644 --- a/boards/de0_cv/board_specific_top.sv +++ b/boards/de0_cv/board_specific_top.sv @@ -29,9 +29,6 @@ module board_specific_top output logic [ 6:0] HEX3, output logic [ 6:0] HEX4, output logic [ 6:0] HEX5, - output VGA_CLK, - output VGA_BLANK_N, - output VGA_SYNC_N, output VGA_HS, output VGA_VS, output [ 3:0] VGA_R, @@ -95,8 +92,7 @@ module board_specific_top .abcdefgh ( abcdefgh ), .digit ( digit ), - //.vsync ( VGA_VS ), - //.hsync ( VGA_HS ), + .x ( x ), @@ -151,11 +147,10 @@ module board_specific_top .display_on ( ), .hpos ( x10 ), .vpos ( y10 ), - .pixel_clk ( VGA_CLK ) + .pixel_clk ( ) ); - assign VGA_BLANK_N = 1'b1; - assign VGA_SYNC_N = 1'b0; + `endif //------------------------------------------------------------------------ From e17030c49d8d2f0953a48b3a8169c566ce902da4 Mon Sep 17 00:00:00 2001 From: verilog Date: Sun, 28 Jul 2024 19:31:58 -0700 Subject: [PATCH 63/65] Added de1 Support to new framework Signed-off-by: Pete Delaney --- boards/de1/board_specific_top.sv | 271 ++++++++++++++++++++----------- 1 file changed, 172 insertions(+), 99 deletions(-) diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index b8698acd..a957605e 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -3,58 +3,86 @@ module board_specific_top # ( - parameter clk_mhz = 50, - w_key = 4, - w_sw = 10, // One onboard SW is used as a reset - w_led = 18, - w_digit = 4, - w_gpio = 72 // GPIO_1[5:0] reserved for mic + parameter clk_mhz = 50, + pixel_mhz = 25, + + w_key = 4, + w_sw = 10, // One onboard SW is used as a reset + w_led = 8, + w_digit = 4, + w_gpio = 72, // GPIO_1[5:0] reserved for mic + + // gpio 0..5 are reserved for INMP 441 I2S microphone. + // Odd gpio .. are reserved I2S audio. + + screen_width = 640, + screen_height = 480, + + w_red = 4, + w_green = 4, + w_blue = 4, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) ) ( - input CLOCK_50, + input CLOCK_50, - input [w_key - 1:0] KEY, - input [w_sw - 1:0] SW, + input [w_key - 1:0] KEY, + input [w_sw - 1:0] SW, + output logic [ 9:0] LEDR, + output logic [ 7:0] LEDG, - input UART_RXD, - output UART_TXD, + output logic [ 6:0] HEX0, // HEX[7] aka dp are not connected to FPGA at DE1 board + output logic [ 6:0] HEX1, + output logic [ 6:0] HEX2, + output logic [ 6:0] HEX3, - output [ 9:0] LEDR, // The last 4 LEDR are used like a 7SEG dp - output [ 7:0] LEDG, + output VGA_HS, + output VGA_VS, + output [w_red - 1:0] VGA_R, + output [w_green - 1:0] VGA_G, + output [w_blue - 1:0] VGA_B, - output logic [ 6:0] HEX0, // HEX[7] aka dp doesn't connected to FPGA at "DE1" board - output logic [ 6:0] HEX1, - output logic [ 6:0] HEX2, - output logic [ 6:0] HEX3, + input UART_RXD, + output UART_TXD, - output VGA_HS, - output VGA_VS, - output [ 3:0] VGA_R, - output [ 3:0] VGA_G, - output [ 3:0] VGA_B, - - inout [ 35:0] GPIO_0, - inout [ 35:0] GPIO_1 + inout [w_gpio / 2 - 1:0] GPIO_0, + inout [w_gpio / 2 - 1:0] GPIO_1 ); //------------------------------------------------------------------------ - localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset + + //------------------------------------------------------------------------ - wire clk = CLOCK_50; + wire clk = CLOCK_50; + wire rst = SW [w_lab_sw]; - wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] lab_key = ~ KEY; + // Keys, switches, LEDs - //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] lab_led; + wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + wire [ w_led - 1:0] lab_led; - wire [ 7:0] abcdefgh; - wire [ w_digit - 1:0] digit; + // A dynamic seven-segment display - wire [ 23:0] mic; - wire [ 15:0] sound; + wire [ 7:0] abcdefgh; + wire [ w_digit - 1:0] digit; + + // Graphics + + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; + + wire [ w_red - 1:0] red; + wire [ w_green - 1:0] green; + wire [ w_blue - 1:0] blue; + + // Microphone, sound output and UART + + wire [ 23:0] mic; + wire [ 15:0] sound; //------------------------------------------------------------------------ @@ -67,51 +95,57 @@ module board_specific_top lab_top # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_lab_sw ), - .w_led ( w_led - w_digit ), // The last 4 LEDR are used like a 7SEG dp - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_led ), + .w_digit ( w_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( lab_key ), - .sw ( lab_sw ), + .key ( ~ KEY ), + .sw ( lab_sw ), - .led ( lab_led ), + .led ( lab_led ), - .abcdefgh ( abcdefgh ), - .digit ( digit ), + .abcdefgh ( abcdefgh ), + .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + .x ( x ), + .y ( y ), - .red ( VGA_R ), - .green ( VGA_G ), - .blue ( VGA_B ), + .red ( VGA_R ), + .green ( VGA_G ), + .blue ( VGA_B ), - .uart_rx ( UART_RXD ), - .uart_tx ( UART_TXD ), + .mic ( mic ), + .sound ( sound ), - .mic ( mic ), - .sound ( sound ), + .uart_rx ( UART_RXD ), + .uart_tx ( UART_TXD ), - .gpio ( { GPIO_0, GPIO_1 } ) + .gpio ( { GPIO_0, GPIO_1 } ) ); //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // The last 4 LEDR are used like a 7SEG dp + assign LEDG = { { $bits (LEDG) - w_led { 1'b0 } }, lab_led }; //------------------------------------------------------------------------ - wire [$left (abcdefgh):0] hgfedcba; - logic [$left (digit):0] dp; + wire [$left (abcdefgh):0] hgfedcba; generate genvar i; @@ -143,18 +177,23 @@ module board_specific_top // positive logic - assign LEDR [$left(LEDR) - w_digit + 1] = digit [0] ? hgfedcba [$left (HEX0) + 1] : '0; - assign LEDR [$left(LEDR) - w_digit + 2] = digit [1] ? hgfedcba [$left (HEX1) + 1] : '0; - assign LEDR [$left(LEDR) - w_digit + 3] = digit [2] ? hgfedcba [$left (HEX2) + 1] : '0; - assign LEDR [$left(LEDR) - w_digit + 4] = digit [3] ? hgfedcba [$left (HEX3) + 1] : '0; + always_comb + begin + LEDR = '0; + + for (int i = 0; i < w_digit; i ++) + LEDR [$bits (LEDR) - w_digit + i] + = digit [i] ? hgfedcba [$left (HEX0) + 1] : '0; + end `else always_ff @ (posedge clk or posedge rst) + begin if (rst) begin { HEX0, HEX1, HEX2, HEX3 } <= '1; - dp <= '0; + LEDR <= '0; end else begin @@ -163,47 +202,81 @@ module board_specific_top if (digit [2]) HEX2 <= ~ hgfedcba [$left (HEX2):0]; if (digit [3]) HEX3 <= ~ hgfedcba [$left (HEX3):0]; - if (digit [0]) dp[0] <= hgfedcba [$left (HEX0) + 1]; - if (digit [1]) dp[1] <= hgfedcba [$left (HEX1) + 1]; - if (digit [2]) dp[2] <= hgfedcba [$left (HEX2) + 1]; - if (digit [3]) dp[3] <= hgfedcba [$left (HEX3) + 1]; + for (int i = 0; i < w_digit; i ++) + if (digit [i]) + LEDR [$bits (LEDR) - w_digit + i] <= hgfedcba [$left (HEX0) + 1]; end + end - assign LEDR [$left(LEDR):$left(LEDR) - w_digit + 1] = dp; // The last 4 LEDR are used like a 7SEG dp + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( ) + ); `endif //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( GPIO_1 [0] ), // JP2 pin 1 - .ws ( GPIO_1 [2] ), // JP2 pin 3 - .sck ( GPIO_1 [4] ), // JP2 pin 5 - .sd ( GPIO_1 [5] ), // JP2 pin 6 - .value ( mic ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE + + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( GPIO_1 [0] ), + .ws ( GPIO_1 [2] ), + .sck ( GPIO_1 [4] ), + .sd ( GPIO_1 [5] ), + .value ( mic ) + ); + + assign GPIO_1 [1] = 1'b0; // GND + assign GPIO_1 [3] = 1'b1; // VCC - assign GPIO_1 [1] = 1'b0; // GND - JP2 pin 2 - assign GPIO_1 [3] = 1'b1; // VCC - JP2 pin 4 + `endif + //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - inst_audio_out - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), - .mclk ( GPIO_1 [29] ), // JP2 pin 38 - .bclk ( GPIO_1 [27] ), // JP2 pin 36 - .lrclk ( GPIO_1 [23] ), // JP2 pin 32 - .sdata ( GPIO_1 [25] ) // JP2 pin 34 - ); // JP2 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( GPIO_1 [33] ), + .bclk ( GPIO_1 [31] ), + .lrclk ( GPIO_1 [27] ), + .sdata ( GPIO_1 [29] ) + ); + + + `endif endmodule From 25ed7e492befa10870a1cd81e1f9e39c043b9c43 Mon Sep 17 00:00:00 2001 From: Yuri Panchul Date: Sun, 28 Jul 2024 19:44:42 -0700 Subject: [PATCH 64/65] Removed unnecessery assign in DE1 wrapper --- boards/de1/board_specific_top.sv | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/boards/de1/board_specific_top.sv b/boards/de1/board_specific_top.sv index a957605e..8efe95e9 100644 --- a/boards/de1/board_specific_top.sv +++ b/boards/de1/board_specific_top.sv @@ -62,8 +62,7 @@ module board_specific_top // Keys, switches, LEDs - wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; - wire [ w_led - 1:0] lab_led; + wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; // A dynamic seven-segment display @@ -118,7 +117,7 @@ module board_specific_top .key ( ~ KEY ), .sw ( lab_sw ), - .led ( lab_led ), + .led ( LEDG ), .abcdefgh ( abcdefgh ), .digit ( digit ), @@ -141,10 +140,6 @@ module board_specific_top //------------------------------------------------------------------------ - assign LEDG = { { $bits (LEDG) - w_led { 1'b0 } }, lab_led }; - - //------------------------------------------------------------------------ - wire [$left (abcdefgh):0] hgfedcba; generate From 030534ea22bbeb3e28cca560e35a9c44f8e25a81 Mon Sep 17 00:00:00 2001 From: verilog Date: Sun, 11 Aug 2024 20:07:39 -0700 Subject: [PATCH 65/65] Update of de2 Board specific_top to Yuri's new framwork. Compiles but Display goes blank. Signed-off-by: Pete Delaney --- boards/de2/board_specific_top.sv | 270 +++++++++++++++++++------------ 1 file changed, 169 insertions(+), 101 deletions(-) diff --git a/boards/de2/board_specific_top.sv b/boards/de2/board_specific_top.sv index 87a4cb0b..397e76d5 100644 --- a/boards/de2/board_specific_top.sv +++ b/boards/de2/board_specific_top.sv @@ -3,25 +3,35 @@ module board_specific_top # ( - parameter clk_mhz = 50, - w_key = 4, + parameter clk_mhz = 50, + pixel_mhz = 25, + + w_key = 4, w_sw = 18, // One onboard SW is used as a reset w_led = 26, w_digit = 8, w_gpio = 72, // GPIO[5:0] reserved for mic - vga_clock = 25 // Pixel clock of VGA in MHz, recommend be equal with VGA_CLOCK from labs/common/vga.sv -) -( - input CLOCK_50, + vga_clock = 25, // Pixel clock of VGA in MHz, recommend be equal with VGA_CLOCK from labs/common/vga.sv + // gpio 0..5 are reserved for INMP 441 I2S microphone. + // Odd gpio .. are reserved I2S audio. - input [w_key - 1:0] KEY, - input [w_sw - 1:0] SW, + screen_width = 640, + screen_height = 480, - input UART_RXD, - output UART_TXD, + w_red = 4, + w_green = 4, + w_blue = 4, - output [ 17:0] LEDR, // The last 8 LEDR are used like a 7SEG dp - output [ 7:0] LEDG, + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ) +) +( + input CLOCK_50, + + input [w_key - 1:0] KEY, + input [w_sw - 1:0] SW, + output logic [ 17:0] LEDR, // The last 8 LEDR are used like a 7SEG dp + output logic [ 7:0] LEDG, output logic [ 6:0] HEX0, // HEX[7] aka dp doesn't connected to FPGA at DE2 board output logic [ 6:0] HEX1, @@ -32,39 +42,53 @@ module board_specific_top output logic [ 6:0] HEX6, output logic [ 6:0] HEX7, - output VGA_CLK, // VGA DAC input triggers CLK - output VGA_HS, - output VGA_VS, - output [ 9:0] VGA_R, - output [ 9:0] VGA_G, - output [ 9:0] VGA_B, - output VGA_BLANK, - output VGA_SYNC, - - inout [ 35:0] GPIO_0, - inout [ 35:0] GPIO_1 + output VGA_CLK, + output VGA_HS, + output VGA_VS, + output VGA_BLANK, + output VGA_SYNC, + output [w_red - 1:0] VGA_R, + output [w_green - 1:0] VGA_G, + output [w_blue - 1:0] VGA_B, + + input UART_RXD, + output UART_TXD, + + inout [w_gpio / 2 - 1:0] GPIO_0, + inout [w_gpio / 2 - 1:0] GPIO_1 ); //------------------------------------------------------------------------ - localparam w_lab_sw = w_sw - 1; // One onboard SW is used as a reset + localparam w_lab_sw = w_sw - 1; // One sw is used as a reset + localparam w_lab_led = w_led - w_digit; - wire clk = CLOCK_50; + //------------------------------------------------------------------------ - wire rst = SW [w_lab_sw]; - wire [w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; - wire [w_key - 1:0] lab_key = ~ KEY; + wire clk = CLOCK_50; + wire rst = SW [w_lab_sw]; - //------------------------------------------------------------------------ - wire [ w_led - w_digit - 1:0] lab_led; + // Keys, switches, LEDs + + wire [ w_lab_sw - 1:0] lab_sw = SW [w_lab_sw - 1:0]; + // wire [ w_lab_led - 1:0] lab_led; // FIX? + // wire [ w_led - w_digit - 1:0] lab_led; + + // A dynamic seven-segment display + + wire [ 7:0] abcdefgh; + wire [ w_digit - 1:0] digit; - wire [ 7:0] abcdefgh; - wire [ w_digit - 1:0] digit; + wire [ w_x - 1:0] x; + wire [ w_y - 1:0] y; - wire [ 3:0] vga_red_4b,vga_green_4b,vga_blue_4b; + wire [ w_red - 1:0] vga_red_4b; + wire [ w_green - 1:0] vga_green_4b; + wire [ w_blue - 1:0] vga_blue_4b; - wire [ 23:0] mic; - wire [ 15:0] sound; + // Microphone, sound output and UART + wire [ 23:0] mic; + wire [ 15:0] sound; //------------------------------------------------------------------------ @@ -77,46 +101,54 @@ module board_specific_top lab_top # ( - .clk_mhz ( clk_mhz ), - .w_key ( w_key ), - .w_sw ( w_lab_sw ), - .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp - .w_digit ( w_digit ), - .w_gpio ( w_gpio ) // GPIO[5:0] reserved for mic + .clk_mhz ( clk_mhz ), + .w_key ( w_key ), + .w_sw ( w_lab_sw ), + .w_led ( w_led - w_digit ), // The last 8 LEDR are used like a 7SEG dp + .w_digit ( w_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) ) i_lab_top ( - .clk ( clk ), - .slow_clk ( slow_clk ), - .rst ( rst ), + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), - .key ( lab_key ), - .sw ( lab_sw ), + .key ( ~ KEY ), + .sw ( lab_sw ), - .led ( lab_led ), + .led ( LEDG ), - .abcdefgh ( abcdefgh ), - .digit ( digit ), + .abcdefgh ( abcdefgh ), + .digit ( digit ), - .vsync ( VGA_VS ), - .hsync ( VGA_HS ), + .x ( x ), + .y ( y ), - .red ( vga_red_4b ), - .green ( vga_green_4b ), - .blue ( vga_blue_4b ), + .red ( vga_red_4b ), + .green ( vga_green_4b ), + .blue ( vga_blue_4b ), - .uart_rx ( UART_RXD ), - .uart_tx ( UART_TXD ), + .mic ( mic ), + .sound ( sound ), - .mic ( mic ), - .sound ( sound ), + .uart_rx ( UART_RXD ), + .uart_tx ( UART_TXD ), - .gpio ( { GPIO_0, GPIO_1 } ) + .gpio ( { GPIO_0, GPIO_1 } ) ); //------------------------------------------------------------------------ - assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = lab_led; // Last 8 LEDR are used like a 7SEG dp + //assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = w_led; // Last 8 LEDR are used like a 7SEG dp HACK? + // assign { LEDR [$left(LEDR) - w_digit:0], LEDG } = w_lab_led; // Last 8 LEDR are used like a 7SEG dp HACK? assign VGA_R = { vga_red_4b, 4'd0 }; assign VGA_G = { vga_green_4b, 4'd0 }; @@ -156,8 +188,7 @@ module board_specific_top assign VGA_CLK = clk_en; //------------------------------------------------------------------------ - - wire [$left (abcdefgh):0] hgfedcba; + wire [$left (abcdefgh):0] hgfedcba; logic [$left (digit):0] dp; generate @@ -183,18 +214,18 @@ module board_specific_top // inverted logic - assign HEX0 = digit [0] ? ~ hgfedcba [$left (HEX0):0] : '1; - assign HEX1 = digit [1] ? ~ hgfedcba [$left (HEX1):0] : '1; - assign HEX2 = digit [2] ? ~ hgfedcba [$left (HEX2):0] : '1; - assign HEX3 = digit [3] ? ~ hgfedcba [$left (HEX3):0] : '1; - assign HEX4 = digit [4] ? ~ hgfedcba [$left (HEX4):0] : '1; - assign HEX5 = digit [5] ? ~ hgfedcba [$left (HEX5):0] : '1; - assign HEX6 = digit [6] ? ~ hgfedcba [$left (HEX6):0] : '1; - assign HEX7 = digit [7] ? ~ hgfedcba [$left (HEX7):0] : '1; + assign HEX0 = digit [0] ? ~ hgfedcba [$left (HEX0):0] : '1; + assign HEX1 = digit [1] ? ~ hgfedcba [$left (HEX1):0] : '1; + assign HEX2 = digit [2] ? ~ hgfedcba [$left (HEX2):0] : '1; + assign HEX3 = digit [3] ? ~ hgfedcba [$left (HEX3):0] : '1; + assign HEX4 = digit [4] ? ~ hgfedcba [$left (HEX4):0] : '1; + assign HEX5 = digit [5] ? ~ hgfedcba [$left (HEX5):0] : '1; + assign HEX6 = digit [6] ? ~ hgfedcba [$left (HEX6):0] : '1; + assign HEX7 = digit [7] ? ~ hgfedcba [$left (HEX7):0] : '1; // positive logic - assign LEDR [ w_led - w_digit] = digit [0] ? hgfedcba [$left (HEX0) + 1] : '0; + assign LEDR [w_led - w_digit ] = digit [0] ? hgfedcba [$left (HEX0) + 1] : '0; assign LEDR [w_led - w_digit + 1] = digit [1] ? hgfedcba [$left (HEX1) + 1] : '0; assign LEDR [w_led - w_digit + 2] = digit [2] ? hgfedcba [$left (HEX2) + 1] : '0; assign LEDR [w_led - w_digit + 3] = digit [3] ? hgfedcba [$left (HEX3) + 1] : '0; @@ -206,11 +237,10 @@ module board_specific_top `else always_ff @ (posedge clk or posedge rst) - begin if (rst) begin { HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 } <= '1; - dp <= '0; + LEDR <= '0; end else begin @@ -231,44 +261,82 @@ module board_specific_top if (digit [5]) dp[5] <= hgfedcba [$left (HEX5) + 1]; if (digit [6]) dp[6] <= hgfedcba [$left (HEX6) + 1]; if (digit [7]) dp[7] <= hgfedcba [$left (HEX7) + 1]; + + + for (int i = 0; i < w_digit; i ++) + if (digit [i]) + LEDR [$bits (LEDR) - w_digit + i] <= hgfedcba [$left (HEX0) + 1]; end - end - assign LEDR [$left(LEDR):$left(LEDR) - w_digit + 1] = dp; // The last 4 LEDR are used like a 7SEG dp + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_GRAPHICS_INTERFACE_MODULE + + wire [9:0] x10; assign x = x10; + wire [9:0] y10; assign y = y10; + + vga + # ( + .CLK_MHZ ( clk_mhz ), + .PIXEL_MHZ ( pixel_mhz ) + ) + i_vga + ( + .clk ( clk ), + .rst ( rst ), + .hsync ( VGA_HS ), + .vsync ( VGA_VS ), + .display_on ( ), + .hpos ( x10 ), + .vpos ( y10 ), + .pixel_clk ( ) + ); `endif //------------------------------------------------------------------------ - inmp441_mic_i2s_receiver i_microphone - ( - .clk ( clk ), - .rst ( rst ), - .lr ( GPIO_1 [0] ), // JP2 pin 1 - .ws ( GPIO_1 [2] ), // JP2 pin 3 - .sck ( GPIO_1 [4] ), // JP2 pin 5 - .sd ( GPIO_1 [5] ), // JP2 pin 6 - .value ( mic ) - ); + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE - assign GPIO_1 [1] = 1'b0; // GND - JP2 pin 2 - assign GPIO_1 [3] = 1'b1; // VCC - JP2 pin 4 + inmp441_mic_i2s_receiver i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .lr ( GPIO_1 [0] ), // JP2 pin 1 + .ws ( GPIO_1 [2] ), // JP2 pin 3 + .sck ( GPIO_1 [4] ), // JP2 pin 5 + .sd ( GPIO_1 [5] ), // JP2 pin 6 + .value ( mic ) + ); + + assign GPIO_1 [1] = 1'b0; // GND- JP2 pin 2 + assign GPIO_1 [3] = 1'b1; // VCC- JP2 pin 4 + + `endif + //------------------------------------------------------------------------ - i2s_audio_out - # ( - .clk_mhz ( clk_mhz ) - ) - inst_audio_out - ( - .clk ( clk ), - .reset ( rst ), - .data_in ( sound ), - .mclk ( GPIO_1 [29] ), // JP2 pin 38 - .bclk ( GPIO_1 [27] ), // JP2 pin 36 - .lrclk ( GPIO_1 [23] ), // JP2 pin 32 - .sdata ( GPIO_1 [25] ) // JP2 pin 34 - ); // JP2 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ) + ) + inst_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( GPIO_1 [29] ), // JP2 pin 38 + .bclk ( GPIO_1 [27] ), // JP2 pin 36 + .lrclk ( GPIO_1 [23] ), // JP2 pin 32 + .sdata ( GPIO_1 [25] ) // JP2 pin 34 + ); // JP2 pin 30 - GND, pin 29 - VCC 3.3V (30-45 mA) + + + `endif endmodule