From 3bc963d38b7fd4e9cb0e4ea909f749de96d6e3fd Mon Sep 17 00:00:00 2001 From: Ryan Krebs Date: Fri, 7 Aug 2026 01:09:53 -0400 Subject: [PATCH 01/12] push to test, deal with reg mapping later --- src/didaq.c | 47 +++++++++++++++++++++++++++++++++++++------- src/didaq.h.in | 2 +- src/didaq_internal.h | 1 + src/didaq_regs.h | 26 +++++++++++++----------- 4 files changed, 56 insertions(+), 20 deletions(-) diff --git a/src/didaq.c b/src/didaq.c index 11c2ba7..59a19e8 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -231,6 +231,7 @@ didaq_dev_t * didaq_open(const didaq_setup_t * setup) didaq_sched_read_COIN_CTL(dev,0, &dev->coin_ctl[0]); didaq_sched_read_COIN_CTL(dev,1, &dev->coin_ctl[1]); didaq_complete(dev); + dev->revision_int = ((dev->revision & 0xfff0) >> 4) * 16 + (dev->revision & 0xf); dev->selected_adc = -1; dev->clock_estimate = 250000000; @@ -497,6 +498,30 @@ int didaq_read_scalers(didaq_dev_t *dev, didaq_scalers_t * scal) { didaq_reg_scaler_t raw_scalers[48] = {0}; + // there needs to be a firm. ver. check here now... + int beam_trig_100mHz_gated_start = 32; + int beam_servo_1Hz_start = 38; + int num_pps_scaler_addr = 46; + int num_pps_scaler_addr_sel = 0; + int total_beam_trig_start_addr = 41; + + // either we scrap the old format, or we need this check, and likely needs to be at open... + if(dev->revision_int > 2*16+14) + { + if(DIDAQ_NUM_BEAMS != 12) + { + fprintf(ferr, "Software version %d.%d.%d does not support current firmware version %d.%d\n", + DIDAQ_VERSION_MAJOR, DIDAQ_VERSION_MINOR, DIDAQ_VERSION_REV, + ((dev->revision & 0xfff0)>>4), dev->revision & 0xf); + return -1; + } + beam_trig_100mHz_gated_start = 32; + beam_servo_1Hz_start = 36; + num_pps_scaler_addr = 45; + num_pps_scaler_addr_sel = 1; + total_beam_trig_start_addr = 44; + } + int ret = 0; ret = didaq_sched_write_SCAL_SEL(dev, &scal_latch[0]); CHECK(ret); @@ -525,17 +550,17 @@ int didaq_read_scalers(didaq_dev_t *dev, didaq_scalers_t * scal) for (int i = 0; i < DIDAQ_NUM_BEAMS; i++) { scal->beam_trig_100mHz[i] = raw_scalers[26 + i/2].scalers[(i) % 2]; - scal->beam_trig_100mHz_gated[i] = raw_scalers[31 + i/2].scalers[(i) % 2]; - scal->beam_servo_1Hz[i] = raw_scalers[36 + i/2].scalers[(i) % 2]; + scal->beam_trig_100mHz_gated[i] = raw_scalers[beam_trig_100mHz_gated_start + i/2].scalers[(i) % 2]; + scal->beam_servo_1Hz[i] = raw_scalers[beam_servo_1Hz_start + i/2].scalers[(i) % 2]; } - scal->num_pps = raw_scalers[41].scalers[0]; + scal->num_pps = raw_scalers[num_pps_scaler_addr].scalers[num_pps_scaler_addr_sel]; scal->clk_rate = raw_scalers[47].scalers[1] <<16; scal->clk_rate += raw_scalers[47].scalers[0]; dev->clock_estimate = scal->clk_rate; - scal->total_beam_100mHz = raw_scalers[42].scalers[0]; - scal->total_beam_100mHz_gated = raw_scalers[42].scalers[1]; - scal->total_beam_1Hz= raw_scalers[43].scalers[0]; + scal->total_beam_100mHz = raw_scalers[total_beam_trig_start_addr].scalers[0]; + scal->total_beam_100mHz_gated = raw_scalers[total_beam_trig_start_addr].scalers[1]; + scal->total_beam_1Hz= raw_scalers[total_beam_trig_start_addr].scalers[0]; return 0; } @@ -762,7 +787,15 @@ int didaq_set_thresholds( didaq_dev_t * dev, dev->cached_phased_init = true; for (int beam = 0; beam < countof(phased->beam_trig_thresholds); beam++) { - ret = didaq_sched_write_BEAM_THRESH(dev, DIDAQ_NUM_BEAMS -1 -beam, // seem to be backwards? + int beam_index = DIDAQ_NUM_BEAMS -1 -beam; + if(dev->revision_int > 16*2 + 14) + { + beam_index = beam; + // maybe add if bm > 10, write_BEAM_THRESH2 or something instead of the headache of version + // dependent register mapping? + } + + ret = didaq_sched_write_BEAM_THRESH(dev, beam_index, & (didaq_reg_phas_thresh_t) { .trig = phased->beam_trig_thresholds[beam], .servo = phased->beam_servo_thresholds[beam] diff --git a/src/didaq.h.in b/src/didaq.h.in index 94f0095..1f6724e 100644 --- a/src/didaq.h.in +++ b/src/didaq.h.in @@ -8,7 +8,7 @@ #define DIDAQ_VERSION_REV @@ -#define DIDAQ_NUM_BEAMS 10 +#define DIDAQ_NUM_BEAMS 12 #define DIDAQ_NUM_COINC 2 #define DIDAQ_NUM_CHANNELS 24 #define DIDAQ_MAX_LEN 4096 diff --git a/src/didaq_internal.h b/src/didaq_internal.h index 6b9d6ca..45214c5 100644 --- a/src/didaq_internal.h +++ b/src/didaq_internal.h @@ -47,6 +47,7 @@ struct didaq_dev size_t spi_bufsiz_complete; size_t spi_max_bufsiz; uint32_t revision; + uint32_t revision_int; uint32_t board_id; FILE * ferr; int dbg; diff --git a/src/didaq_regs.h b/src/didaq_regs.h index d0dc3b7..112c55e 100644 --- a/src/didaq_regs.h +++ b/src/didaq_regs.h @@ -29,6 +29,8 @@ int didaq_complete(didaq_dev_t * dev); * this will prepopulate a buffer * type: the type we read to. the sizeof this type is relevant for endianess. * + * NOTE: this doesn't support registers moving based on firmware version + * * */ #define DIDAQ_REGS(REG)\ /** name , baseaddr , naddr, rw, varlen, type */\ @@ -50,18 +52,18 @@ int didaq_complete(didaq_dev_t * dev); REG(COIN_CTL , 0x0038, 2, 1, 0, didaq_reg_coin_trig_ctl_t )\ REG(COIN_THRESH , 0x003a, 12, 1, 0, didaq_reg_coin_thresh_t )\ REG(PHASED_CTL , 0x0046, 1, 1, 0, didaq_reg_phas_trig_ctl_t )\ - REG(BEAM_THRESH , 0x0047, 10, 1, 0, didaq_reg_phas_thresh_t)\ - REG(LAST_EVT_CTR , 0x0052, 1, 0, 0, uint32_t)\ - REG(LAST_TRIG_CTR , 0x0053, 1, 0, 0, uint32_t)\ - REG(LAST_DEAD_CTR , 0x0054, 1, 0, 0, uint32_t)\ - REG(LAST_CLK_CTR , 0x0055, 1, 0, 0, uint32_t)\ - REG(LAST_PPS_CTR , 0x0056, 1, 0, 0, didaq_reg_pps_counter_t)\ - REG(LAST_MISC0 , 0x0057, 1, 0, 0, didaq_reg_misc0_t)\ - REG(LAST_MISC1 , 0x0058, 1, 0, 0, didaq_reg_misc1_t)\ - REG(LAST_TRIG , 0x0059, 1, 0, 0, didaq_reg_meta_trig_t)\ - REG(RDOUT_CTL , 0x005B, 1, 1, 0, didaq_reg_rdout_ctl_t)\ - REG(SCAL_RD , 0x005C, 1, 0, 0, didaq_reg_scaler_t)\ - REG(SCAL_SEL , 0x005D, 1, 1, 0, didaq_reg_scal_sel_t)\ + REG(BEAM_THRESH , 0x0047, 12, 1, 0, didaq_reg_phas_thresh_t)\ + REG(LAST_EVT_CTR , 0x0053, 1, 0, 0, uint32_t)\ + REG(LAST_TRIG_CTR , 0x0054, 1, 0, 0, uint32_t)\ + REG(LAST_DEAD_CTR , 0x0055, 1, 0, 0, uint32_t)\ + REG(LAST_CLK_CTR , 0x0056, 1, 0, 0, uint32_t)\ + REG(LAST_PPS_CTR , 0x0057, 1, 0, 0, didaq_reg_pps_counter_t)\ + REG(LAST_MISC0 , 0x0058, 1, 0, 0, didaq_reg_misc0_t)\ + REG(LAST_MISC1 , 0x0059, 1, 0, 0, didaq_reg_misc1_t)\ + REG(LAST_TRIG , 0x005A, 1, 0, 0, didaq_reg_meta_trig_t)\ + REG(RDOUT_CTL , 0x005C, 1, 1, 0, didaq_reg_rdout_ctl_t)\ + REG(SCAL_RD , 0x005D, 1, 0, 0, didaq_reg_scaler_t)\ + REG(SCAL_SEL , 0x005E, 1, 1, 0, didaq_reg_scal_sel_t)\ REG(CORE_TEMPS , 0x0060, 5, 0, 0, uint32_t) From 04b0b1dff9ef21262ce84934bba189421052f941 Mon Sep 17 00:00:00 2001 From: Ryan Krebs Date: Fri, 7 Aug 2026 01:13:36 -0400 Subject: [PATCH 02/12] dev-> --- src/didaq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/didaq.c b/src/didaq.c index 59a19e8..adc61b9 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -510,7 +510,7 @@ int didaq_read_scalers(didaq_dev_t *dev, didaq_scalers_t * scal) { if(DIDAQ_NUM_BEAMS != 12) { - fprintf(ferr, "Software version %d.%d.%d does not support current firmware version %d.%d\n", + fprintf(dev->ferr, "Software version %d.%d.%d does not support current firmware version %d.%d\n", DIDAQ_VERSION_MAJOR, DIDAQ_VERSION_MINOR, DIDAQ_VERSION_REV, ((dev->revision & 0xfff0)>>4), dev->revision & 0xf); return -1; From ee001cb38ff4f8234a2b09ad15f44282100e129f Mon Sep 17 00:00:00 2001 From: Ryan Krebs Date: Fri, 7 Aug 2026 04:21:18 -0400 Subject: [PATCH 03/12] mapping --- examples/didaq-configure-phased-trig.c | 8 +++---- src/didaq_regs.h | 31 +++++++++++++------------- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/examples/didaq-configure-phased-trig.c b/examples/didaq-configure-phased-trig.c index 188a53a..8046460 100644 --- a/examples/didaq-configure-phased-trig.c +++ b/examples/didaq-configure-phased-trig.c @@ -16,7 +16,7 @@ didaq_trigger_setup_t s = { } }; -int thresh[DIDAQ_NUM_BEAMS] = {1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000 }; +int thresh[DIDAQ_NUM_BEAMS] = {1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000 ,100}; double servo_frac = 0.8; @@ -99,9 +99,9 @@ int main (int nargs, char ** args) th.beam_servo_thresholds[j] = thresh[j]* servo_frac; } didaq_set_thresholds(dev, &th, 0); - printf("Using thresholds of [%d, %d, %d, %d, %d, %d, %d, %d, %d, %d]\n", - thresh[0], thresh[1], thresh[2], thresh[3], thresh[4], - thresh[5], thresh[6], thresh[7], thresh[8], thresh[9] + printf("Using thresholds of %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", + thresh[0], thresh[1], thresh[2], thresh[3], thresh[4], thresh[5], + thresh[6], thresh[7], thresh[8], thresh[9], thresh[10], thresh[11] ); printf("Sleeping for 20 seconds to get a good read\n"); diff --git a/src/didaq_regs.h b/src/didaq_regs.h index 112c55e..467b3db 100644 --- a/src/didaq_regs.h +++ b/src/didaq_regs.h @@ -49,25 +49,26 @@ int didaq_complete(didaq_dev_t * dev); REG(CAPTURE_CTL , 0x000e, 1, 1, 0, didaq_reg_capture_ctl_t )\ REG(CAPTURE_STAT , 0x000f, 1, 0, 0, didaq_reg_capture_stat_t )\ REG(DATA , 0x0014, 24, 0, 4096, uint8_t )\ - REG(COIN_CTL , 0x0038, 2, 1, 0, didaq_reg_coin_trig_ctl_t )\ - REG(COIN_THRESH , 0x003a, 12, 1, 0, didaq_reg_coin_thresh_t )\ - REG(PHASED_CTL , 0x0046, 1, 1, 0, didaq_reg_phas_trig_ctl_t )\ - REG(BEAM_THRESH , 0x0047, 12, 1, 0, didaq_reg_phas_thresh_t)\ - REG(LAST_EVT_CTR , 0x0053, 1, 0, 0, uint32_t)\ - REG(LAST_TRIG_CTR , 0x0054, 1, 0, 0, uint32_t)\ - REG(LAST_DEAD_CTR , 0x0055, 1, 0, 0, uint32_t)\ - REG(LAST_CLK_CTR , 0x0056, 1, 0, 0, uint32_t)\ - REG(LAST_PPS_CTR , 0x0057, 1, 0, 0, didaq_reg_pps_counter_t)\ - REG(LAST_MISC0 , 0x0058, 1, 0, 0, didaq_reg_misc0_t)\ - REG(LAST_MISC1 , 0x0059, 1, 0, 0, didaq_reg_misc1_t)\ - REG(LAST_TRIG , 0x005A, 1, 0, 0, didaq_reg_meta_trig_t)\ - REG(RDOUT_CTL , 0x005C, 1, 1, 0, didaq_reg_rdout_ctl_t)\ - REG(SCAL_RD , 0x005D, 1, 0, 0, didaq_reg_scaler_t)\ - REG(SCAL_SEL , 0x005E, 1, 1, 0, didaq_reg_scal_sel_t)\ + REG(COIN_CTL , 0x0037, 2, 1, 0, didaq_reg_coin_trig_ctl_t )\ + REG(COIN_THRESH , 0x0039, 12, 1, 0, didaq_reg_coin_thresh_t )\ + REG(PHASED_CTL , 0x0045, 1, 1, 0, didaq_reg_phas_trig_ctl_t )\ + REG(BEAM_THRESH , 0x0046, 12, 1, 0, didaq_reg_phas_thresh_t)\ + REG(LAST_EVT_CTR , 0x0052, 1, 0, 0, uint32_t)\ + REG(LAST_TRIG_CTR , 0x0053, 1, 0, 0, uint32_t)\ + REG(LAST_DEAD_CTR , 0x0054, 1, 0, 0, uint32_t)\ + REG(LAST_CLK_CTR , 0x0055, 1, 0, 0, uint32_t)\ + REG(LAST_PPS_CTR , 0x0056, 1, 0, 0, didaq_reg_pps_counter_t)\ + REG(LAST_MISC0 , 0x0057, 1, 0, 0, didaq_reg_misc0_t)\ + REG(LAST_MISC1 , 0x0058, 1, 0, 0, didaq_reg_misc1_t)\ + REG(LAST_TRIG , 0x0059, 1, 0, 0, didaq_reg_meta_trig_t)\ + REG(RDOUT_CTL , 0x005A, 1, 1, 0, didaq_reg_rdout_ctl_t)\ + REG(SCAL_RD , 0x005C, 1, 0, 0, didaq_reg_scaler_t)\ + REG(SCAL_SEL , 0x005D, 1, 1, 0, didaq_reg_scal_sel_t)\ REG(CORE_TEMPS , 0x0060, 5, 0, 0, uint32_t) + #define DIDAQ_DEFINE_ENUM(NAME, ADDR, NADDR, RW, VAR, T) DIDAQ_##NAME, /** Enum of all didaq registers */ From 5004cabc2073a381dcd0158660d32a8113404667 Mon Sep 17 00:00:00 2001 From: Ryan Krebs Date: Fri, 7 Aug 2026 13:06:48 -0400 Subject: [PATCH 04/12] scaler addr --- src/didaq.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/didaq.c b/src/didaq.c index adc61b9..9a86f78 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -516,7 +516,7 @@ int didaq_read_scalers(didaq_dev_t *dev, didaq_scalers_t * scal) return -1; } beam_trig_100mHz_gated_start = 32; - beam_servo_1Hz_start = 36; + beam_servo_1Hz_start = 38; num_pps_scaler_addr = 45; num_pps_scaler_addr_sel = 1; total_beam_trig_start_addr = 44; @@ -791,8 +791,6 @@ int didaq_set_thresholds( didaq_dev_t * dev, if(dev->revision_int > 16*2 + 14) { beam_index = beam; - // maybe add if bm > 10, write_BEAM_THRESH2 or something instead of the headache of version - // dependent register mapping? } ret = didaq_sched_write_BEAM_THRESH(dev, beam_index, From 990cc9b05b4ac8e5e3376a92d028f34df0bcda47 Mon Sep 17 00:00:00 2001 From: Ryan Krebs Date: Fri, 7 Aug 2026 14:12:16 -0400 Subject: [PATCH 05/12] check int --- src/didaq.c | 9 +++++---- src/didaq_regs.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/didaq.c b/src/didaq.c index 9a86f78..74d3ebb 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -499,11 +499,11 @@ int didaq_read_scalers(didaq_dev_t *dev, didaq_scalers_t * scal) didaq_reg_scaler_t raw_scalers[48] = {0}; // there needs to be a firm. ver. check here now... - int beam_trig_100mHz_gated_start = 32; - int beam_servo_1Hz_start = 38; - int num_pps_scaler_addr = 46; + int beam_trig_100mHz_gated_start = 31; + int beam_servo_1Hz_start = 36; + int num_pps_scaler_addr = 41; int num_pps_scaler_addr_sel = 0; - int total_beam_trig_start_addr = 41; + int total_beam_trig_start_addr = 42; // either we scrap the old format, or we need this check, and likely needs to be at open... if(dev->revision_int > 2*16+14) @@ -587,6 +587,7 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) int ret = 0; ret += fprintf(f, "[[DIDAQ at 0x%p]]\n", dev); ret += fprintf(f, " Revision: 0x%x\n", dev->revision); + ret += fprintf(f, " Revision Int: 0x%d\n", dev->revision_int); ret += fprintf(f, " Board_ID: 0x%x\n", dev->board_id); ret += fprintf(f, " nxfers queued: %lu\n", dev->nxfers); ret += fprintf(f, " nxfers completed:%lu\n", dev->nxfers_complete); diff --git a/src/didaq_regs.h b/src/didaq_regs.h index 467b3db..822db43 100644 --- a/src/didaq_regs.h +++ b/src/didaq_regs.h @@ -61,7 +61,7 @@ int didaq_complete(didaq_dev_t * dev); REG(LAST_MISC0 , 0x0057, 1, 0, 0, didaq_reg_misc0_t)\ REG(LAST_MISC1 , 0x0058, 1, 0, 0, didaq_reg_misc1_t)\ REG(LAST_TRIG , 0x0059, 1, 0, 0, didaq_reg_meta_trig_t)\ - REG(RDOUT_CTL , 0x005A, 1, 1, 0, didaq_reg_rdout_ctl_t)\ + REG(RDOUT_CTL , 0x005B, 1, 1, 0, didaq_reg_rdout_ctl_t)\ REG(SCAL_RD , 0x005C, 1, 0, 0, didaq_reg_scaler_t)\ REG(SCAL_SEL , 0x005D, 1, 1, 0, didaq_reg_scal_sel_t)\ REG(CORE_TEMPS , 0x0060, 5, 0, 0, uint32_t) From 90bc467bb64e74f4d9377bdc75d8f457ad267985 Mon Sep 17 00:00:00 2001 From: Ryan Krebs Date: Fri, 7 Aug 2026 15:15:16 -0400 Subject: [PATCH 06/12] print loaded thresholds --- examples/didaq-configure-phased-trig.c | 2 +- src/didaq.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/examples/didaq-configure-phased-trig.c b/examples/didaq-configure-phased-trig.c index 8046460..5b982cb 100644 --- a/examples/didaq-configure-phased-trig.c +++ b/examples/didaq-configure-phased-trig.c @@ -16,7 +16,7 @@ didaq_trigger_setup_t s = { } }; -int thresh[DIDAQ_NUM_BEAMS] = {1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000 ,100}; +int thresh[DIDAQ_NUM_BEAMS] = {1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000 ,1000}; double servo_frac = 0.8; diff --git a/src/didaq.c b/src/didaq.c index 74d3ebb..d91e745 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -598,6 +598,10 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) didaq_reg_capture_stat_t capture_stat = {0}; didaq_reg_capture_ctl_t capture_ctl = {0}; + didaq_phased_thresholds_t p_thresh = {0}; + didaq_coin_thresholds_t c_thresh = {0}; + + if(didaq_get_thresholds(dev, & p_thresh, &c_thresh, true)) return -1; // should we just use the cached one here? meh. this is an important debug tool. if (didaq_sched_read_CAPTURE_CTL(dev,&capture_ctl)) return -1; @@ -609,11 +613,25 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) ret += fprintf(f, " capture_ctl = { .sw_trig = %u, .event_clr = %u, .run_ctr_rst = %u, .pps_en = %u, .ext_en = %u }\n", capture_ctl.sw_trig, capture_ctl.event_clr, capture_ctl.run_ctr_rst, capture_ctl.pps_en, capture_ctl.ext_en); ret += fprintf(f, " phased_ctl = { .en_trig = %u, .en_trig_to_data = %u, .req_consec_wins = %u, .divide_by_2 = %u, .channel_mask = 0b%b, .beam_mask = 0b%b }\n" , dev->phased_ctl.en_trig, dev->phased_ctl.en_trig_to_data, dev->phased_ctl.req_consec_wins, dev->phased_ctl.divide_by_2, dev->phased_ctl.channel_mask, dev->phased_ctl.beam_mask); + ret += fprintf(f, "Beam Trigger Thtrsholds: "); + + for(int bm = 0; bmcoin_ctl[0].en_module, dev->coin_ctl[0].en_readout, dev->coin_ctl[0].num_coinc, dev->coin_ctl[0].coin_win, dev->coin_ctl[0].include_mask , dev->coin_ctl[1].en_module, dev->coin_ctl[1].en_readout, dev->coin_ctl[1].num_coinc, dev->coin_ctl[1].coin_win, dev->coin_ctl[1].include_mask); + ret += fprintf(f, "Beam Trigger Thtrsholds: "); + + for(int ch = 0; ch Date: Fri, 7 Aug 2026 15:19:53 -0400 Subject: [PATCH 07/12] can I spell? --- src/didaq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/didaq.c b/src/didaq.c index d91e745..19123a7 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -613,11 +613,11 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) ret += fprintf(f, " capture_ctl = { .sw_trig = %u, .event_clr = %u, .run_ctr_rst = %u, .pps_en = %u, .ext_en = %u }\n", capture_ctl.sw_trig, capture_ctl.event_clr, capture_ctl.run_ctr_rst, capture_ctl.pps_en, capture_ctl.ext_en); ret += fprintf(f, " phased_ctl = { .en_trig = %u, .en_trig_to_data = %u, .req_consec_wins = %u, .divide_by_2 = %u, .channel_mask = 0b%b, .beam_mask = 0b%b }\n" , dev->phased_ctl.en_trig, dev->phased_ctl.en_trig_to_data, dev->phased_ctl.req_consec_wins, dev->phased_ctl.divide_by_2, dev->phased_ctl.channel_mask, dev->phased_ctl.beam_mask); - ret += fprintf(f, "Beam Trigger Thtrsholds: "); + ret += fprintf(f, "Beam Trigger Thresholds: "); for(int bm = 0; bmcoin_ctl[0].en_module, dev->coin_ctl[0].en_readout, dev->coin_ctl[0].num_coinc, dev->coin_ctl[0].coin_win, dev->coin_ctl[0].include_mask , dev->coin_ctl[1].en_module, dev->coin_ctl[1].en_readout, dev->coin_ctl[1].num_coinc, dev->coin_ctl[1].coin_win, dev->coin_ctl[1].include_mask); - ret += fprintf(f, "Beam Trigger Thtrsholds: "); + ret += fprintf(f, "Channel Trigger Thresholds: "); for(int ch = 0; ch Date: Fri, 7 Aug 2026 19:31:16 -0400 Subject: [PATCH 08/12] +1 scaler to a scaler addr --- examples/didaq-configure-phased-trig.c | 10 +++++++--- src/didaq.c | 15 +++++++++------ 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/examples/didaq-configure-phased-trig.c b/examples/didaq-configure-phased-trig.c index 5b982cb..2d59fcc 100644 --- a/examples/didaq-configure-phased-trig.c +++ b/examples/didaq-configure-phased-trig.c @@ -12,7 +12,7 @@ const char * dev = "/dev/spidev1.0"; didaq_trigger_setup_t s = { .phased = { - .enable = true, .enable_readout =true, + .enable = false, .enable_readout =false, } }; @@ -28,6 +28,11 @@ int main (int nargs, char ** args) { dev = args[++i]; } + else if (!strcmp(args[i]),"-e") + { + s.phased.enable = true; + s.phased.enable_readout true; + } else if (!strcmp(args[i],"-2")) { s.phased.divide_by_2 = true ; @@ -36,7 +41,6 @@ int main (int nargs, char ** args) { s.phased.require_consecutive_windows = true; } - else if (!strcmp(args[i], "-B") && i < nargs-1) { uint32_t M = strtoul(args[++i], 0, 0); @@ -73,7 +77,7 @@ int main (int nargs, char ** args) else { - fprintf(stderr,"Usage: didaq-configure-phased-trig [ -d DEVICE ] [ -2 -c] [ -B meam mask ] [ -C channel_mask ] [-t THRESH] [-T BEAM THRESH] [-f servo_frac] \n"); + fprintf(stderr,"Usage: didaq-configure-phased-trig [ -d DEVICE ] [ -e enable ] [ -2 -c ] [ -B meam mask ] [ -C channel_mask ] [ -t THRESH ] [ -T BEAM THRESH ] [ -f servo_frac ] \n"); return 0; } diff --git a/src/didaq.c b/src/didaq.c index 19123a7..3a8fdfc 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -517,9 +517,9 @@ int didaq_read_scalers(didaq_dev_t *dev, didaq_scalers_t * scal) } beam_trig_100mHz_gated_start = 32; beam_servo_1Hz_start = 38; + total_beam_trig_start_addr = 44; num_pps_scaler_addr = 45; num_pps_scaler_addr_sel = 1; - total_beam_trig_start_addr = 44; } int ret = 0; @@ -560,7 +560,7 @@ int didaq_read_scalers(didaq_dev_t *dev, didaq_scalers_t * scal) dev->clock_estimate = scal->clk_rate; scal->total_beam_100mHz = raw_scalers[total_beam_trig_start_addr].scalers[0]; scal->total_beam_100mHz_gated = raw_scalers[total_beam_trig_start_addr].scalers[1]; - scal->total_beam_1Hz= raw_scalers[total_beam_trig_start_addr].scalers[0]; + scal->total_beam_1Hz= raw_scalers[total_beam_trig_start_addr+1].scalers[0]; return 0; } @@ -613,23 +613,26 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) ret += fprintf(f, " capture_ctl = { .sw_trig = %u, .event_clr = %u, .run_ctr_rst = %u, .pps_en = %u, .ext_en = %u }\n", capture_ctl.sw_trig, capture_ctl.event_clr, capture_ctl.run_ctr_rst, capture_ctl.pps_en, capture_ctl.ext_en); ret += fprintf(f, " phased_ctl = { .en_trig = %u, .en_trig_to_data = %u, .req_consec_wins = %u, .divide_by_2 = %u, .channel_mask = 0b%b, .beam_mask = 0b%b }\n" , dev->phased_ctl.en_trig, dev->phased_ctl.en_trig_to_data, dev->phased_ctl.req_consec_wins, dev->phased_ctl.divide_by_2, dev->phased_ctl.channel_mask, dev->phased_ctl.beam_mask); - ret += fprintf(f, "Beam Trigger Thresholds: "); + ret += fprintf(f, " Beam Trigger Thresholds:\n"); for(int bm = 0; bmcoin_ctl[0].en_module, dev->coin_ctl[0].en_readout, dev->coin_ctl[0].num_coinc, dev->coin_ctl[0].coin_win, dev->coin_ctl[0].include_mask , dev->coin_ctl[1].en_module, dev->coin_ctl[1].en_readout, dev->coin_ctl[1].num_coinc, dev->coin_ctl[1].coin_win, dev->coin_ctl[1].include_mask); - ret += fprintf(f, "Channel Trigger Thresholds: "); + ret += fprintf(f, " Channel Trigger Thresholds:\n"); for(int ch = 0; ch Date: Fri, 7 Aug 2026 19:33:08 -0400 Subject: [PATCH 09/12] typo in example --- examples/didaq-configure-phased-trig.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/didaq-configure-phased-trig.c b/examples/didaq-configure-phased-trig.c index 2d59fcc..58353f7 100644 --- a/examples/didaq-configure-phased-trig.c +++ b/examples/didaq-configure-phased-trig.c @@ -28,10 +28,10 @@ int main (int nargs, char ** args) { dev = args[++i]; } - else if (!strcmp(args[i]),"-e") + else if (!strcmp(args[i],"-e")) { s.phased.enable = true; - s.phased.enable_readout true; + s.phased.enable_readout = true; } else if (!strcmp(args[i],"-2")) { From 8fbd7bc699d1cf62d1c708fed3b5b1351d40f0a3 Mon Sep 17 00:00:00 2001 From: Ryan Krebs Date: Fri, 7 Aug 2026 19:39:26 -0400 Subject: [PATCH 10/12] format print better --- src/didaq.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/didaq.c b/src/didaq.c index 3a8fdfc..363ffde 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -618,13 +618,13 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) for(int bm = 0; bmcoin_ctl[0].en_module, dev->coin_ctl[0].en_readout, dev->coin_ctl[0].num_coinc, dev->coin_ctl[0].coin_win, dev->coin_ctl[0].include_mask , dev->coin_ctl[1].en_module, dev->coin_ctl[1].en_readout, dev->coin_ctl[1].num_coinc, dev->coin_ctl[1].coin_win, dev->coin_ctl[1].include_mask); ret += fprintf(f, " Channel Trigger Thresholds:\n"); @@ -632,7 +632,7 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) for(int ch = 0; ch Date: Fri, 7 Aug 2026 19:41:57 -0400 Subject: [PATCH 11/12] new line --- src/didaq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/didaq.c b/src/didaq.c index 363ffde..48238ea 100644 --- a/src/didaq.c +++ b/src/didaq.c @@ -611,6 +611,7 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) ret += fprintf(f, " capture_stat = { .event_busy = %u, .event_rdy = %u }\n", capture_stat.event_bsy, capture_stat.event_rdy); ret += fprintf(f, " capture_ctl = { .sw_trig = %u, .event_clr = %u, .run_ctr_rst = %u, .pps_en = %u, .ext_en = %u }\n", capture_ctl.sw_trig, capture_ctl.event_clr, capture_ctl.run_ctr_rst, capture_ctl.pps_en, capture_ctl.ext_en); + ret += fprintf(f, "\n"); ret += fprintf(f, " phased_ctl = { .en_trig = %u, .en_trig_to_data = %u, .req_consec_wins = %u, .divide_by_2 = %u, .channel_mask = 0b%b, .beam_mask = 0b%b }\n" , dev->phased_ctl.en_trig, dev->phased_ctl.en_trig_to_data, dev->phased_ctl.req_consec_wins, dev->phased_ctl.divide_by_2, dev->phased_ctl.channel_mask, dev->phased_ctl.beam_mask); ret += fprintf(f, " Beam Trigger Thresholds:\n"); @@ -624,7 +625,7 @@ int didaq_dump(didaq_dev_t * dev, FILE * f, int flags) ret += fprintf(f, "\n"); ret += fprintf(f, " coin_ctl[2] = {\n " " { .en_module = %u, .en_readout = %u, .num_coinc = %u, .coinc_win = %u, .include_mask = 0b%b }, \n " - " { .en_module = %u, .en_readout = %u, .num_coinc = %u, .coinc_win = %u, .include_mask = 0b%b }\n; " + " { .en_module = %u, .en_readout = %u, .num_coinc = %u, .coinc_win = %u, .include_mask = 0b%b }\n" , dev->coin_ctl[0].en_module, dev->coin_ctl[0].en_readout, dev->coin_ctl[0].num_coinc, dev->coin_ctl[0].coin_win, dev->coin_ctl[0].include_mask , dev->coin_ctl[1].en_module, dev->coin_ctl[1].en_readout, dev->coin_ctl[1].num_coinc, dev->coin_ctl[1].coin_win, dev->coin_ctl[1].include_mask); ret += fprintf(f, " Channel Trigger Thresholds:\n"); From e9e84f4f4ec5390768e9a02c6ccef71fdb8467f6 Mon Sep 17 00:00:00 2001 From: Ryan Krebs Date: Tue, 11 Aug 2026 17:22:28 -0400 Subject: [PATCH 12/12] fix servo frac in phased example --- examples/didaq-configure-phased-trig.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/examples/didaq-configure-phased-trig.c b/examples/didaq-configure-phased-trig.c index 58353f7..59297d7 100644 --- a/examples/didaq-configure-phased-trig.c +++ b/examples/didaq-configure-phased-trig.c @@ -55,29 +55,26 @@ int main (int nargs, char ** args) } else if (!strcmp(args[i],"-t") && i < nargs-1) { - int all_thresh = strtoul(args[++i], 0, 0); for (int j = 0; j < DIDAQ_NUM_BEAMS; j++) { thresh[j] = all_thresh; } - } else if (!strcmp(args[i],"-T") && i < nargs-2) { - int beam = strtoul(args[++i], 0, 0); int thr= strtoul(args[++i], 0, 0); thresh[beam] = thr; } else if (!strcmp(args[i],"-f") && i < nargs-1) { - servo_frac = strtoul(args[++i], 0, 0); + servo_frac = atof(args[++i]); } else { - fprintf(stderr,"Usage: didaq-configure-phased-trig [ -d DEVICE ] [ -e enable ] [ -2 -c ] [ -B meam mask ] [ -C channel_mask ] [ -t THRESH ] [ -T BEAM THRESH ] [ -f servo_frac ] \n"); + fprintf(stderr,"Usage: didaq-configure-phased-trig [ -d DEVICE ] [ -e enable ] [ -2 divide_by_2 ] [ -c require_consecutive_windows ] [ -B meam mask ] [ -C channel_mask ] [ -t THRESH ] [ -T BEAM THRESH ] [ -f servo_frac ] \n"); return 0; } @@ -100,7 +97,7 @@ int main (int nargs, char ** args) for (int j = 0; j < DIDAQ_NUM_BEAMS; j++) { th.beam_trig_thresholds[j] = thresh[j]; - th.beam_servo_thresholds[j] = thresh[j]* servo_frac; + th.beam_servo_thresholds[j] = (int) (thresh[j]* servo_frac); } didaq_set_thresholds(dev, &th, 0); printf("Using thresholds of %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n",