diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 9977e293f41..01d68bc74fd 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -518,6 +518,13 @@ "SUB_RTT_BSP": [ "allwinner/d1s" ] + }, + { + "RTT_BSP": "novosns", + "RTT_TOOL_CHAIN": "sourcery-arm", + "SUB_RTT_BSP": [ + "novosns/ns800/ns800rt7p65-nssinepad" + ] } ] } diff --git a/bsp/novosns/ns800/README.md b/bsp/novosns/ns800/README.md new file mode 100644 index 00000000000..5cada71c070 --- /dev/null +++ b/bsp/novosns/ns800/README.md @@ -0,0 +1,3 @@ +# NS800 BSP 说明 + +NS800 系列 BSP 目前支持情况如下表所示： diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/SConscript b/bsp/novosns/ns800/libraries/HAL_Drivers/SConscript new file mode 100644 index 00000000000..33146e918e5 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/SConscript @@ -0,0 +1,13 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +import os + +cwd = GetCurrentDir() +src = ['drv_common.c'] +path = [cwd] + +group = SConscript(os.path.join(cwd, 'drivers', 'SConscript')) +group = group + DefineGroup('HAL_Driver', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/Kconfig b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/Kconfig new file mode 100644 index 00000000000..60cf532bb71 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/Kconfig @@ -0,0 +1 @@ +# comment "HAL_Drivers driver-level patch options are kept minimal; peripheral configs live in board/Kconfig" diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/SConscript b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/SConscript new file mode 100644 index 00000000000..753aebd7656 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/SConscript @@ -0,0 +1,24 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +import os + +cwd = GetCurrentDir() +src = [] +path = [cwd, cwd + '/config'] + +if GetDepend(['BSP_USING_GPIO', 'RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['BSP_USING_UART', 'RT_USING_SERIAL']): + src += ['drv_uart.c'] + +if GetDepend(['BSP_USING_CAN', 'RT_USING_CAN']): + src += ['drv_can.c'] + +if GetDepend(['BSP_USING_ECAP']): + src += ['drv_ecap.c'] + +group = DefineGroup('HAL_Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/adc_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/adc_config.h new file mode 100644 index 00000000000..ae9f9d1a23d --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/adc_config.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-06 zylx first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CONFIG +#define ADC1_CONFIG \ + { \ + .Instance = ADC1, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_16B, \ + .Init.ScanConvMode = ADC_SCAN_DISABLE, \ + .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \ + .Init.LowPowerAutoWait = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 1, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \ + .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \ + .Init.OversamplingMode = DISABLE, \ + } +#endif /* ADC1_CONFIG */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_CONFIG +#define ADC2_CONFIG \ + { \ + .Instance = ADC2, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_16B, \ + .Init.ScanConvMode = ADC_SCAN_DISABLE, \ + .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \ + .Init.LowPowerAutoWait = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 1, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \ + .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \ + .Init.OversamplingMode = DISABLE, \ + } +#endif /* ADC2_CONFIG */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_CONFIG +#define ADC3_CONFIG \ + { \ + .Instance = ADC3, \ + .Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \ + .Init.Resolution = ADC_RESOLUTION_16B, \ + .Init.ScanConvMode = ADC_SCAN_DISABLE, \ + .Init.EOCSelection = ADC_EOC_SINGLE_CONV, \ + .Init.LowPowerAutoWait = DISABLE, \ + .Init.ContinuousConvMode = DISABLE, \ + .Init.NbrOfConversion = 1, \ + .Init.DiscontinuousConvMode = DISABLE, \ + .Init.NbrOfDiscConversion = 1, \ + .Init.ExternalTrigConv = ADC_SOFTWARE_START, \ + .Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \ + .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \ + .Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \ + .Init.OversamplingMode = DISABLE, \ + } +#endif /* ADC3_CONFIG */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/dac_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/dac_config.h new file mode 100644 index 00000000000..fae6be33b8a --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/dac_config.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 thread-liu first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_CONFIG +#define DAC1_CONFIG \ + { \ + .Instance = DAC1, \ + } +#endif /* DAC2_CONFIG */ +#endif /* BSP_USING_DAC2 */ + +#ifdef BSP_USING_DAC2 +#ifndef DAC2_CONFIG +#define DAC2_CONFIG \ + { \ + .Instance = DAC2, \ + } +#endif /* DAC2_CONFIG */ +#endif /* BSP_USING_DAC2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/dma_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/dma_config.h new file mode 100644 index 00000000000..135ee6d5434 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/dma_config.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-02 zylx first version + * 2019-01-08 SummerGift clean up the code + * 2020-05-02 whj4674672 support stm32h7 dma1 and dma2 + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 stream0 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Stream0 +#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX +#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn +#endif + +/* DMA1 stream1 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler +#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART2_TX_DMA_INSTANCE DMA1_Stream1 +#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX +#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn +#endif + +/* DMA1 stream2 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler +#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 +#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn +#endif + +/* DMA1 stream3 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler +#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 +#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn +#endif + +/* DMA1 stream4 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler +#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 +#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn +#endif + + +/* DMA1 stream5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 +#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn +#endif + +/* DMA1 stream6 */ + +/* DMA1 stream7 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 +#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn +#endif + +/* DMA2 stream0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn +#endif + +/* DMA2 stream1 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler +#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 +#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn +#endif + +/* DMA2 stream2 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler +#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 +#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn +#endif + +/* DMA2 stream3 */ +#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn +#endif + +/* DMA2 stream4 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 +#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn +#endif + +/* DMA2 stream5 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler +#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 +#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn +#endif + +/* DMA2 stream6 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler +#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 +#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn +#endif + +/* DMA2 stream7 */ +#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler +#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN +#define QSPI_DMA_INSTANCE DMA2_Stream7 +#define QSPI_DMA_IRQ DMA2_Stream7_IRQn +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/i2c_hard_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/i2c_hard_config.h new file mode 100644 index 00000000000..7168665eba2 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/i2c_hard_config.h @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Add H7 hard I2C config + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timing = 0x307075B1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timing = 0x307075B1, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timing = 0x307075B1, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timing = 0x307075B1, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_HARD_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/lptim_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/lptim_config.h new file mode 100644 index 00000000000..a2bf17fc95d --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/lptim_config.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-11 wdfk-prog first version + */ + +#ifndef __LPTIM_CONFIG_H__ +#define __LPTIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef LPTIM_DEV_INFO_CONFIG +#define LPTIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_LPTIM1 +#ifndef LPTIM1_CONFIG +#define LPTIM1_CONFIG \ + { \ + .tim_handle.Instance = LPTIM1, \ + .tim_irqn = LPTIM1_IRQn, \ + .name = "lptim1", \ + } +#endif /* LPTIM1_CONFIG */ +#endif /* BSP_USING_LPTIM1 */ + +#ifdef BSP_USING_LPTIM2 +#ifndef LPTIM2_CONFIG +#define LPTIM2_CONFIG \ + { \ + .tim_handle.Instance = LPTIM2, \ + .tim_irqn = LPTIM2_IRQn, \ + .name = "lptim2", \ + } +#endif /* LPTIM1_CONFIG */ +#endif /* BSP_USING_LPTIM1 */ + +#ifdef BSP_USING_LPTIM3 +#ifndef LPTIM3_CONFIG +#define LPTIM3_CONFIG \ + { \ + .tim_handle.Instance = LPTIM3, \ + .tim_irqn = LPTIM3_IRQn, \ + .name = "lptim3", \ + } +#endif /* LPTIM3_CONFIG */ +#endif /* BSP_USING_LPTIM3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LPTIM_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/pwm_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/pwm_config.h new file mode 100644 index 00000000000..2a71f0a4b0d --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/pwm_config.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 zylx first version + * 2022-04-14 Miaowulue add PWM1 + * 2023-04-08 Wangyuqiang complete PWM defination + */ + +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM1 +#define PWM1_CONFIG \ + { \ + .tim_handle.Instance = TIM1, \ + .name = "pwm1", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 +#define PWM2_CONFIG \ + { \ + .tim_handle.Instance = TIM2, \ + .name = "pwm2", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#define PWM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .name = "pwm3", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#define PWM4_CONFIG \ + { \ + .tim_handle.Instance = TIM4, \ + .name = "pwm4", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#define PWM5_CONFIG \ + { \ + .tim_handle.Instance = TIM5, \ + .name = "pwm5", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM5 */ + +#ifdef BSP_USING_PWM6 +#define PWM6_CONFIG \ + { \ + .tim_handle.Instance = TIM6, \ + .name = "pwm6", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM6 */ + +#ifdef BSP_USING_PWM7 +#define PWM7_CONFIG \ + { \ + .tim_handle.Instance = TIM7, \ + .name = "pwm7", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM7 */ + +#ifdef BSP_USING_PWM8 +#define PWM8_CONFIG \ + { \ + .tim_handle.Instance = TIM8, \ + .name = "pwm8", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM8 */ + +#ifdef BSP_USING_PWM9 +#define PWM9_CONFIG \ + { \ + .tim_handle.Instance = TIM9, \ + .name = "pwm9", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM9 */ + +#ifdef BSP_USING_PWM10 +#define PWM10_CONFIG \ + { \ + .tim_handle.Instance = TIM10, \ + .name = "pwm10", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM10 */ + +#ifdef BSP_USING_PWM11 +#define PWM11_CONFIG \ + { \ + .tim_handle.Instance = TIM11, \ + .name = "pwm11", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM11 */ + +#ifdef BSP_USING_PWM12 +#define PWM12_CONFIG \ + { \ + .tim_handle.Instance = TIM12, \ + .name = "pwm12", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM12 */ + +#ifdef BSP_USING_PWM13 +#define PWM13_CONFIG \ + { \ + .tim_handle.Instance = TIM13, \ + .name = "pwm13", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM13 */ + +#ifdef BSP_USING_PWM14 +#define PWM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .name = "pwm14", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM14 */ + +#ifdef BSP_USING_PWM15 +#define PWM15_CONFIG \ + { \ + .tim_handle.Instance = TIM15, \ + .name = "pwm15", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM15 */ + +#ifdef BSP_USING_PWM16 +#define PWM16_CONFIG \ + { \ + .tim_handle.Instance = TIM16, \ + .name = "pwm16", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM16 */ + +#ifdef BSP_USING_PWM17 +#define PWM17_CONFIG \ + { \ + .tim_handle.Instance = TIM17, \ + .name = "pwm17", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM17 */ + +#ifdef BSP_USING_PWM18 +#define PWM18_CONFIG \ + { \ + .tim_handle.Instance = TIM18, \ + .name = "pwm18", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM18 */ + +#ifdef BSP_USING_PWM19 +#define PWM19_CONFIG \ + { \ + .tim_handle.Instance = TIM19, \ + .name = "pwm19", \ + .channel = RT_NULL \ + } +#endif /* BSP_USING_PWM19 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/qspi_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/qspi_config.h new file mode 100644 index 00000000000..b62430e9853 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/qspi_config.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-22 zylx first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = QUADSPI, \ + .Init.FifoThreshold = 4, \ + .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \ + .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \ + } +#endif /* QSPI_BUS_CONFIG */ +#endif /* BSP_USING_QSPI */ + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .Init.Channel = QSPI_DMA_CHANNEL, \ + .Init.Direction = DMA_PERIPH_TO_MEMORY, \ + .Init.PeriphInc = DMA_PINC_DISABLE, \ + .Init.MemInc = DMA_MINC_ENABLE, \ + .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \ + .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \ + .Init.Mode = DMA_NORMAL, \ + .Init.Priority = DMA_PRIORITY_LOW \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ + +#define QSPI_IRQn QUADSPI_IRQn +#define QSPI_IRQHandler QUADSPI_IRQHandler + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/sdio_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/sdio_config.h new file mode 100644 index 00000000000..bc3eb175550 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/sdio_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 BalanceTWK first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +/* #include "stm32h7xx_hal.h" */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SDIO +#define SDIO_BUS_CONFIG \ + { \ + .Instance = SDMMC1, \ + .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \ + .dma_rx.Instance = DMA2_Stream3, \ + .dma_rx.channel = DMA_CHANNEL_4, \ + .dma_rx.dma_irq = DMA2_Stream3_IRQn, \ + .dma_tx.Instance = DMA2_Stream6, \ + .dma_tx.channel = DMA_CHANNEL_4, \ + .dma_tx.dma_irq = DMA2_Stream6_IRQn, \ + } + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__SDIO_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/spi_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/spi_config.h new file mode 100644 index 00000000000..73259bf95c0 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/spi_config.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ + .irq_type = SPI1_IRQn, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI1_TX \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI1_RX \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ + .irq_type = SPI2_IRQn, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI2_TX \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI2_RX \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = SPI3, \ + .bus_name = "spi3", \ + .irq_type = SPI3_IRQn, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_TX_DMA_RCC, \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI3_TX \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI3_RX_DMA_RCC, \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI3_RX \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = SPI4, \ + .bus_name = "spi4", \ + .irq_type = SPI4_IRQn, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_TX_DMA_RCC, \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .dma_irq = SPI4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI4_TX \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI4_RX_DMA_RCC, \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .dma_irq = SPI4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI4_RX \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = SPI5, \ + .bus_name = "spi5", \ + .irq_type = SPI5_IRQn, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_TX_DMA_RCC, \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .dma_irq = SPI5_TX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI5_TX \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI5_RX_DMA_RCC, \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .dma_irq = SPI5_RX_DMA_IRQ, \ + .request = DMA_REQUEST_SPI5_RX \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/tim_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/tim_config.h new file mode 100644 index 00000000000..d325a4ac530 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/tim_config.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-11 zylx first version + */ + +#ifndef __TIM_CONFIG_H__ +#define __TIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM11 +#ifndef TIM11_CONFIG +#define TIM11_CONFIG \ + { \ + .tim_handle.Instance = TIM11, \ + .tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \ + .name = "timer11", \ + } +#endif /* TIM11_CONFIG */ +#endif /* BSP_USING_TIM11 */ + +#ifdef BSP_USING_TIM13 +#ifndef TIM13_CONFIG +#define TIM13_CONFIG \ + { \ + .tim_handle.Instance = TIM13, \ + .tim_irqn = TIM8_UP_TIM13_IRQn, \ + .name = "timer13", \ + } +#endif /* TIM13_CONFIG */ +#endif /* BSP_USING_TIM13 */ + +#ifdef BSP_USING_TIM14 +#ifndef TIM14_CONFIG +#define TIM14_CONFIG \ + { \ + .tim_handle.Instance = TIM14, \ + .tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \ + .name = "timer14", \ + } +#endif /* TIM14_CONFIG */ +#endif /* BSP_USING_TIM14 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_CONFIG_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/uart_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/uart_config.h new file mode 100644 index 00000000000..f01b721eab5 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/uart_config.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = UART1, \ + .rx_irq_type = UART1_RX_IRQn, \ + .tx_irq_type = UART1_TX_IRQn, \ + .irq_handler = UART1_IRQHandler, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = UART2, \ + .rx_irq_type = UART2_RX_IRQn, \ + .tx_irq_type = UART2_TX_IRQn, \ + .irq_handler = UART2_IRQHandler, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = UART3, \ + .rx_irq_type = UART3_RX_IRQn, \ + .tx_irq_type = UART3_TX_IRQn, \ + .irq_handler = UART3_IRQHandler, \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .rx_irq_type = UART4_RX_IRQn, \ + .tx_irq_type = UART4_TX_IRQn, \ + .irq_handler = UART4_IRQHandler, \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_can.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_can.c new file mode 100644 index 00000000000..ddba6a3f0f7 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_can.c @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-05 Xeon Xu the first version + * 2019-01-22 YLZ port from stm324xx-HAL to bsp stm3210x-HAL + * 2019-02-19 YLZ add support EXTID RTR Frame. modify send, recv functions. + * fix bug.port to BSP [stm32] + * 2019-03-27 YLZ support double can channels, support stm32F4xx (only Legacy mode). + * 2019-06-17 YLZ port to new STM32F1xx HAL V1.1.3. + * 2021-02-02 YuZhe XU fix bug in filter config + * 2021-8-25 SVCHAO The baud rate is configured according to the different APB1 frequencies. + f4-series only. + * 2025-09-20 wdfk_prog Implemented sendmsg_nonblocking op to support framework's async TX. + * 2026-02-02 wdfk_prog Drain multiple RX frames per ISR with a bounded limit. + */ + +#include "drv_can.h" + +#ifdef BSP_USING_CAN + +#define LOG_TAG "drv_can" +#include + + +#define RX_MB_COUNT (1) +static FLEXCANDRV_MsgObjType frame[RX_MB_COUNT]; /* one frame buffer per RX MB */ + +void CAN_Handler(void); +void CAN_Err_Handler(void); + + +static const struct ns800rt7_baud_rate_tab can_baud_rate_tab[] = +{ + {CAN1MBaud, 1000000}, + {CAN800kBaud, 800000}, + {CAN500kBaud, 500000}, + {CAN250kBaud, 250000}, + {CAN125kBaud, 125000}, + {CAN100kBaud, 100000}, + {CAN50kBaud, 50000}, + {CAN20kBaud, 20000}, + {CAN10kBaud, 10000} +}; + +#ifdef BSP_USING_CAN1 +static ns800rt7_can drv_can1 = +{ + .name = "can1", + .CanHandle.flexCanReg = (FLEXCANREG_TypeDef *)CAN1, + .irqn1 = CAN1_1_IRQn, + .irqn2 = CAN1_2_IRQn, +}; +#endif + +#ifdef BSP_USING_CANFD1 +static ns800rt7_can drv_can1 = +{ + .name = "canfd1", + .CanHandle.flexCanReg = (FLEXCANREG_TypeDef *)CANFD1, + .irqn1 = CANFD1_1_IRQn, + .irqn2 = CANFD1_2_IRQn, +}; +#endif + +#ifdef BSP_USING_CANFD2 +static ns800rt7_can drv_can1 = +{ + .name = "canfd2", + .CanHandle.flexCanReg = (FLEXCANREG_TypeDef *)CANFD2, + .irqn1 = CANFD2_1_IRQn, + .irqn2 = CANFD2_2_IRQn, +}; +#endif + +static void _can_gpio_init(void) +{ +#ifdef BSP_USING_CAN1 + GPIO_setAnalogMode(GPIO_4, GPIO_ANALOG_DISABLED); + GPIO_setAnalogMode(GPIO_10, GPIO_ANALOG_DISABLED); + GPIO_setPinConfig(GPIO_4_CANFD1_TX); + GPIO_setPinConfig(GPIO_10_CANFD1_RX); +#endif + +#ifdef BSP_USING_CANFD1 + GPIO_setAnalogMode(GPIO_4, GPIO_ANALOG_DISABLED); + GPIO_setAnalogMode(GPIO_10, GPIO_ANALOG_DISABLED); + GPIO_setPinConfig(GPIO_4_CANFD1_TX); + GPIO_setPinConfig(GPIO_10_CANFD1_RX); +#endif + +#ifdef BSP_USING_CANFD2 + GPIO_setAnalogMode(GPIO_4, GPIO_ANALOG_DISABLED); + GPIO_setAnalogMode(GPIO_10, GPIO_ANALOG_DISABLED); + GPIO_setPinConfig(GPIO_4_CANFD1_TX); + GPIO_setPinConfig(GPIO_10_CANFD1_RX); +#endif +} + +static void _can_clock_init(void) +{ + /* unlock RCC register access */ + RCC_unlockRccRegister(); + +#if CAN_CLOCK_SELECTION == CAN_USING_EXTERNAL_OSC + + /* setup external OSC if selected */ + /* configure HXTL */ + WRITE_REG(RCC->HXTLCR.WORDVAL, (HXTL_CONFIG | RCC_HXTLCR_KEY)); + RCC_enableHxtl(); + RCC_disableHxtlBypass(); + + uint32_t wait_time = 5000000; + while ((RCC_readHxtlRdyFlag() != 1) && (--wait_time)); + while (wait_time == 0) + { + } + + /* enable MIRC2 and HXTL kernal func */ + RCC_enablePeriphKernalUseMirc2(); + RCC_enablePeriphKernalUseHxtl(); + /* select the HXTL as the working clocks for CANFD1 */ + RCC_selectCanfdOscClkSource(RCC_CANFD1SEL, RCC_CANFD_OSCCLK_SEL_HXTLKER); +#elif CAN_CLOCK_SELECTION == CAN_USING_INTERNAL_CLOCK + + /* enable MIRC2 kernal func */ + RCC_enableKernalUseMirc2(); + /* select the HXTL as the working clocks for CANFD1 */ + RCC_selectCanfdOscClkSource(RCC_CANFD1SEL, RCC_CANFD_OSCCLK_SEL_MIRC2KER); +#endif + + /* enable CANFD clocks */ + RCC_enableCanfd1Clock(); + + /* lock RCC register access */ + RCC_lockRccRegister(); +} + +static rt_uint32_t get_can_baud_index(rt_uint32_t baud) +{ + rt_uint32_t len, index; + + len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); + for (index = 0; index < len; index++) + { + if (can_baud_rate_tab[index].baud_rate == baud) + return index; + } + + return 0; /* default baud is CAN1MBaud */ +} + +static rt_err_t _can_sendBlocking(ns800rt7_can *base, FLEXCANDRV_MsgObjType *TxMsgObj) +{ + /* Check if Message Buffer is idle. */ + if (StateIdle == base->mbState[TxMsgObj->msgBufId]) + { + base->mbState[TxMsgObj->msgBufId] = StateTxData; + + FLEXCANDRV_SetTxMsg(&base->CanHandle, TxMsgObj); + /* transmit canfd Tx message */ + FLEXCANDRV_TransmitMsg(&base->CanHandle, TxMsgObj); + + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +static rt_err_t _can_receiveNonBlocking(ns800rt7_can *base, FLEXCANDRV_MsgObjType *RxMsgObj) +{ + /* Check if Message Buffer is idle. */ + if (StateIdle == base->mbState[RxMsgObj->msgBufId]) + { + base->mbState[RxMsgObj->msgBufId] = StateRxData; + + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg) +{ + ns800rt7_can *drv_can; + rt_uint32_t baud_index; + uint32_t FlexcanClockFreq = HXTL_FREQ_VALUE; + + RT_ASSERT(can); + RT_ASSERT(cfg); + drv_can = (ns800rt7_can *)can->parent.user_data; + RT_ASSERT(drv_can); + + _can_gpio_init(); + _can_clock_init(); + + FLEXCANDRV_InitHwParType initHwPar; + initHwPar.canRamNum = 4; + initHwPar.canInstanceIdx = 1; + FLEXCANDRV_Init(&(drv_can->CanHandle), drv_can->CanHandle.flexCanReg, &initHwPar); + + /* get FLEXCAN controller default configuration */ + FLEXCANDRV_GetDefaultCfg(&(drv_can->CanCfg)); + + baud_index = get_can_baud_index(cfg->baud_rate); + + FLEXCANDRV_BitTimingCalc(&(drv_can->CanCfg.bitTiming), + FlexcanClockFreq, /* module clock source*/ + BAUD_DATA(baud_index), /* baudrate: 500K */ + 7500, /* sample point: 75% */ + 2500, /* SJW: 25% */ + 0); /* classic CAN bit timing */ + + FLEXCANDRV_BitTimingCalc(&(drv_can->CanCfg.fdBitTiming), + FlexcanClockFreq, /* module clock source*/ + BAUD_DATA(baud_index), /* baudrate: 500K */ + 7500, /* sample point: 75% */ + 2500, /* SJW: 25% */ + 1); /* CANFD bit timing */ + + drv_can->CanCfg.clkSrc = FLEXCANDRV_CLKSRC_OSC; + drv_can->CanCfg.msgNum = drv_can->FilterNum; + drv_can->CanCfg.msgCfg = drv_can->FilterConfig; + drv_can->CanCfg.individualMaskEnable = true; + drv_can->CanCfg.rxMBGlobalMask = 0xFFFFFFFF; + drv_can->CanCfg.loopbackEnable = false; + drv_can->CanCfg.msgBufDataLenSel = FLEXCANDRV_MB_SIZE_BYTE_8; + drv_can->CanCfg.fdEnable = true; + drv_can->CanCfg.fdISOEnable = true; + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + /* default mode */ + break; + case RT_CAN_MODE_LISTEN: + drv_can->CanCfg.listenMode = true; + break; + case RT_CAN_MODE_LOOPBACK: + drv_can->CanCfg.loopbackEnable = true; + break; + case RT_CAN_MODE_LOOPBACKANLISTEN: + break; + } + + /* init can */ + /* initialize FLEXCAN module */ + FLEXCANDRV_Configure(&(drv_can->CanHandle), &(drv_can->CanCfg)); + + return RT_EOK; +} + +static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) +{ + rt_uint32_t argval; + ns800rt7_can *drv_can; + struct rt_can_filter_config *filter_cfg; + struct rt_can_filter_item *item; + rt_uint8_t i, count, index; + + RT_ASSERT(can != RT_NULL); + drv_can = (ns800rt7_can *)can->parent.user_data; + RT_ASSERT(drv_can != RT_NULL); + FLEXCANREG_TypeDef *canReg = drv_can->CanHandle.flexCanReg; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + Interrupt_disable(drv_can->irqn1); + Interrupt_disable(drv_can->irqn2); + break; + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX || argval == RT_DEVICE_FLAG_INT_TX) + { + Interrupt_register(drv_can->irqn1, &CAN_Handler); + Interrupt_enable(drv_can->irqn1); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + Interrupt_register(drv_can->irqn2, &CAN_Err_Handler); + Interrupt_enable(drv_can->irqn2); + } + break; + case RT_CAN_CMD_SET_FILTER: + break; + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_NORMAL && + argval != RT_CAN_MODE_LISTEN && + argval != RT_CAN_MODE_LOOPBACK && + argval != RT_CAN_MODE_LOOPBACKANLISTEN) + { + return -RT_ERROR; + } + + if (argval != drv_can->device.config.mode) + { + drv_can->device.config.mode = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_SET_BAUD: + argval = (rt_uint32_t) arg; + if (argval != CAN1MBaud && + argval != CAN800kBaud && + argval != CAN500kBaud && + argval != CAN250kBaud && + argval != CAN125kBaud && + argval != CAN100kBaud && + argval != CAN50kBaud && + argval != CAN20kBaud && + argval != CAN10kBaud) + { + return -RT_ERROR; + } + + if (argval != drv_can->device.config.baud_rate) + { + drv_can->device.config.baud_rate = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_SET_PRIV: + return -RT_ERROR; + break; + case RT_CAN_CMD_GET_STATUS: + drv_can->device.status.rcverrcnt = FLEXCANREG_GetEcrRxerrcnt(canReg); + drv_can->device.status.snderrcnt = FLEXCANREG_GetEcrTxerrcnt(canReg); + /* drv_can->device.status.lasterrtype = errtype & 0x70; */ + /* drv_can->device.status.errcode = errtype & 0x07; */ + + rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status)); + break; + } + + return RT_EOK; +} + +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @internal + * @brief Low-level function to send a CAN message to a specific hardware mailbox. + * + * This function is part of the **blocking** send mechanism. It is called by + * `_can_int_tx` after a hardware mailbox has already been acquired. Its role is + * to format the message according to the STM32 hardware requirements and place + * it into the specified mailbox for transmission. + * + * @param[in] can A pointer to the CAN device structure. + * @param[in] buf A pointer to the `rt_can_msg` to be sent. + * @param[in] box_num The specific hardware mailbox index (0, 1, or 2) to use for this tran + * + * @return `RT_EOK` on success, or an error code on failure. + */ +static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) +{ + rt_ssize_t status; + ns800rt7_can *hcan; + hcan = (ns800rt7_can *) can->parent.user_data; + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + FLEXCANDRV_MsgObjType fdTxMsgObj; + + /* Check the parameters */ + RT_ASSERT(IS_CAN_DLC(pmsg->len)); + + fdTxMsgObj.msgBufId = box_num; + + /* Set up the DLC */ + fdTxMsgObj.dlc = pmsg->len & 0x0FU; + /* Set up the data field */ + for(uint8_t i=0u; i<8u; i++) + { + fdTxMsgObj.data[i] = pmsg->data[i]; + } + + status = _can_sendBlocking(hcan, &fdTxMsgObj); + + return status; +} + +static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) +{ + FLEXCANDRV_Type *hcan; + struct rt_can_msg *pmsg; + + RT_ASSERT(can); + + hcan = &(((ns800rt7_can *)can->parent.user_data)->CanHandle); + pmsg = (struct rt_can_msg *) buf; + + rt_uint8_t index; + + pmsg->hdr_index = index; /* one hdr filter per MB */ + pmsg->len = frame[0].dlc; + pmsg->id = frame[0].msgId; + pmsg->data[0] = frame[0].data[0]; + pmsg->data[1] = frame[0].data[1]; + pmsg->data[2] = frame[0].data[2]; + pmsg->data[3] = frame[0].data[3]; + pmsg->data[4] = frame[0].data[4]; + pmsg->data[5] = frame[0].data[5]; + pmsg->data[6] = frame[0].data[6]; + pmsg->data[7] = frame[0].data[7]; + + return RT_EOK; +} + +static const struct rt_can_ops _can_ops = +{ + .configure = _can_config, + .control = _can_control, + .sendmsg = _can_sendmsg, + .recvmsg = _can_recvmsg, +}; + +static uint32_t FLEXCANREG_GetMsgBufInterruptFlagAll(FLEXCANREG_TypeDef *obj) +{ + return obj->IFLAG1 | obj->IFLAG2 | obj->IFLAG3 | obj->IFLAG4; +} + +static uint8_t FLEXCANREG_GetMsgBufInterruptMask (FLEXCANREG_TypeDef *obj, uint32_t msgBufferIdx) +{ + uint32_t temp, temp1 = 0; + + temp1 = msgBufferIdx % 32; + temp = 0x00000001UL << temp1; + + if (msgBufferIdx > 95) + { + temp &= obj->IMASK4; + } + else if (msgBufferIdx > 63) + { + temp &= obj->IMASK3; + } + else if (msgBufferIdx > 31) + { + temp &= obj->IMASK2; + } + else + { + temp &= obj->IMASK1; + } + + if (temp) + { + return (1); + } + else + { + return (0); + } +} + +static void _can_tx_rx_isr(struct rt_can_device *can) +{ + uint8_t flag, mask; + RT_ASSERT(can); + ns800rt7_can *hcan; + hcan = (ns800rt7_can *) can->parent.user_data; + FLEXCANDRV_MsgObjType msgObj; + + /* Assertion. */ + RT_ASSERT(hcan); + + uint32_t result; + + do + { + /* For this implementation, we solve the Message with lowest MB index first. */ + for (result = 0; result < 128; result++) + { + flag = FLEXCANDRV_GetMsgObjFlag(&(hcan->CanHandle), result); + mask = FLEXCANREG_GetMsgBufInterruptMask(hcan->CanHandle.flexCanReg, result); + /* Get the lowest unhandled Message Buffer */ + if ((flag != 0) && (mask != 0)) + { + break; + } + } + + /* Does not find Message to deal with. */ + if (result == 128) + { + break; + } + + /* Get current State of Message Buffer. */ + switch (result) + { + /* Solve Rx Data Frame. */ + case 1: + msgObj.msgBufId = result; + FLEXCANDRV_GetRxMsg(&hcan->CanHandle, &msgObj); + FLEXCANDRV_ClearMsgObjFlag(&hcan->CanHandle, result); + memcpy(&frame[0], &msgObj, sizeof(msgObj)); + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | result << 8); + hcan->mbState[result] = StateIdle; + break; + + /* Solve Tx Data Frame. */ + case 0: + rt_hw_can_isr(can, RT_CAN_EVENT_TX_DONE | result << 8); + hcan->mbState[result] = StateIdle; + break; + + default: + break; + } + + /* Clear resolved Message Buffer IRQ. */ + FLEXCANDRV_ClearMsgObjFlag(&(hcan->CanHandle), result); + } + while((0 != FLEXCANREG_GetMsgBufInterruptFlagAll(hcan->CanHandle.flexCanReg))); +} + +static void _can_err_isr(struct rt_can_device *can) +{ + +} + +#ifdef BSP_USING_CAN1 +/** + * @brief This function handles CAN1 RX0 interrupts. + */ +void CAN1_1_IRQHandler(void) +{ + rt_interrupt_enter(); +#if 0 + if() + { + _can_rx_isr(&drv_can1.device); + } + else + { + _can_tx_isr(&drv_can1.device); + } +#endif + rt_interrupt_leave(); +} + +/** + * @brief This function handles CAN1 RX1 interrupts. + */ +void CAN1_2_IRQHandler(void) +{ + rt_interrupt_enter(); +#if 0 + if() + { + _can_rx_isr(&drv_can1.device); + } + else + { + _can_tx_isr(&drv_can1.device); + } +#endif + rt_interrupt_leave(); +} + +#endif /* BSP_USING_CAN1 */ + +#ifdef BSP_USING_CANFD1 +void CAN_Handler(void) +{ + rt_interrupt_enter(); + _can_tx_rx_isr(&drv_can1.device); + rt_interrupt_leave(); +} + +void CAN_Err_Handler(void) +{ + rt_interrupt_enter(); + _can_err_isr(&drv_can1.device); + rt_interrupt_leave(); +} +#endif /* BSP_USING_CANFD1 */ + +#ifdef BSP_USING_CANFD2 +void CANFD2_1_IRQHandler(void) +{ + rt_interrupt_enter(); + _can_sce_isr(&drv_can1.device); + rt_interrupt_leave(); +} + +void CANFD2_2_IRQHandler(void) +{ + rt_interrupt_enter(); + _can_sce_isr(&drv_can1.device); + rt_interrupt_leave(); +} +#endif /* BSP_USING_CANFD2 */ + +int rt_hw_can_init(void) +{ + int ret = RT_EOK; + struct can_configure config = CANDEFAULTCONFIG; + config.privmode = RT_CAN_MODE_NOPRIV; + + config.ticks = 50; + config.sndboxnumber = 1; + config.msgboxsz = RX_MB_COUNT; +#ifdef RT_CAN_USING_HDR + config.maxhdr = RX_MB_COUNT; /* filter count,one filter per MB */ +#endif + /* config default filter */ + FLEXCANDRV_MsgCfgType fdMsgCfgObj[2] = {0}; + + drv_can1.FilterConfig[0].msgBufId = 0; + drv_can1.FilterConfig[0].msgBufLen = 1; + drv_can1.FilterConfig[0].msgId = 0x78; + drv_can1.FilterConfig[0].isExtMsgId = false; + drv_can1.FilterConfig[0].msgType = FLEXCANDRV_MSGTYPE_TX; + drv_can1.FilterConfig[0].dlc = DLC_BYTE_8; + drv_can1.FilterConfig[0].isFd = false; + drv_can1.FilterConfig[0].intEnable = true; + drv_can1.FilterConfig[0].individualMask = 0xFFFFFFFF; + drv_can1.FilterConfig[0].rtrmask = false; + drv_can1.FilterConfig[0].rtrfilter = false; + + drv_can1.FilterConfig[1].msgBufId = 1; + drv_can1.FilterConfig[1].msgBufLen = 1; + drv_can1.FilterConfig[1].msgId = 0x400; + drv_can1.FilterConfig[1].isExtMsgId = false; + drv_can1.FilterConfig[1].msgType = FLEXCANDRV_MSGTYPE_RX; + drv_can1.FilterConfig[1].dlc = DLC_BYTE_8; + drv_can1.FilterConfig[1].isFd = false; + drv_can1.FilterConfig[1].intEnable = true; + drv_can1.FilterConfig[1].individualMask = 0; + drv_can1.FilterConfig[1].rtrmask = false; + drv_can1.FilterConfig[1].rtrfilter = false; + + drv_can1.FilterNum = 2; + +#ifdef BSP_USING_CANFD1 + drv_can1.device.config = config; + /* register CAN1 device */ + ret = rt_hw_can_register(&drv_can1.device, + drv_can1.name, + &_can_ops, + &drv_can1); +#endif /* BSP_USING_CAN1 */ + + return ret; +} + +INIT_BOARD_EXPORT(rt_hw_can_init); + +#endif /* BSP_USING_CAN */ + +/************************** end of file ******************/ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_can.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_can.h new file mode 100644 index 00000000000..9c9bac4c8e0 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_can.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-05 Xeon Xu the first version + * 2019-01-22 YLZ port from stm324xx-HAL to bsp stm3210x-HAL + * 2019-01-26 YLZ redefine `struct stm32_drv_can` add member `Rx1Message` + * 2019-02-19 YLZ port to BSP [stm32] + * 2019-06-17 YLZ modify struct stm32_drv_can. + */ + +#ifndef __DRV_CAN_H__ +#define __DRV_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define CAN_FILTER_NUM_MAX (16U) + +enum _can_state +{ + StateIdle = 0x0, /*!< MB idle.*/ + StateRxData = 0x1, /*!< MB receiving.*/ + StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + StateTxData = 0x3, /*!< MB transmitting.*/ + StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ +}; + +struct ns800rt7_baud_rate_tab +{ + rt_uint32_t baud_rate; + rt_uint32_t config_data; +}; +#define BAUD_DATA(NO) (can_baud_rate_tab[NO].config_data) + + +/* stm32 can device */ +typedef struct +{ + char *name; + FLEXCANDRV_ControllerCfgType CanCfg; + IRQn_Type irqn1; + IRQn_Type irqn2; + FLEXCANDRV_Type CanHandle; + FLEXCANDRV_MsgCfgType FilterConfig[CAN_FILTER_NUM_MAX]; + uint8_t FilterNum; + volatile uint8_t mbState[128]; + struct rt_can_device device; /* inherit from can device */ +} ns800rt7_can; + +int rt_hw_can_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__DRV_CAN_H__ */ + +/************************** end of file ******************/ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_config.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_config.h new file mode 100644 index 00000000000..9907a5c283e --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_config.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SOC_SERIES_NS800RT7) +#include "rt7/uart_config.h" + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dma.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dma.h new file mode 100644 index 00000000000..bb4293e09ee --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_dma.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-10 SummerGift first version + */ + +#ifndef __DRV_DMA_H_ +#define __DRV_DMA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct dma_config { + EDMA_TypeDef *Instance; + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + rt_uint32_t request; + +}; + +#ifdef __cplusplus +} +#endif + +#endif /*__DRV_DMA_H_ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_ecap.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_ecap.c new file mode 100644 index 00000000000..aca167fc794 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_ecap.c @@ -0,0 +1,479 @@ +/**************************************************************************//** +* +* @copyright (C) 2026 Novosense Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2026-5-7 Alex-J First version +* +******************************************************************************/ +#include +#include "drv_ecap.h" + +#if defined(BSP_USING_ECAP) + +#define DBG_TAG "drv.ecap" +#define DBG_LVL DBG_INFO +#include + +static const struct rt_ecap_config ecap1_config = +{ + .name = "ecap1", + .instance = ECAP1, + .irq_type = ECAP1_IRQn, + .input_xbar = XBAR_INPUT7, + .input_source = GPIO_PIN_16, + .gpio_port = GPIOA, + .gpio_pin = GPIO_PIN_16, + .gpio_mux = ALT0_FUNCTION, +}; + +static struct rt_ecap_device ecap1_dev; + +void ECAP1_IRQHandler (void); + +/* + * + */ +static void ecap_gpio_init (const struct rt_ecap_config *config) +{ + RT_ASSERT(config != RT_NULL); + + GPIO_setPinConfig(config->gpio_port, config->gpio_pin, config->gpio_mux); + GPIO_setAnalogMode(config->gpio_port, config->gpio_pin, GPIO_ANALOG_DISABLED); + GPIO_setPadConfig(config->gpio_port, config->gpio_pin, GPIO_PIN_TYPE_STD); + GPIO_setQualificationMode(config->gpio_port, config->gpio_pin, GPIO_QUAL_SYNC); + GPIO_setDirectionMode(config->gpio_port, config->gpio_pin, GPIO_DIR_MODE_IN); +} + +/* + * + */ +static void ecap_xbar_init (const struct rt_ecap_config *config) +{ + RT_ASSERT(config != RT_NULL); + + XBAR_setInputPin(XBAR, config->input_xbar, config->input_source); +} + +/* + * + */ +static void ecap_hw_init (const struct rt_ecap_config *config) +{ + RT_ASSERT(config != RT_NULL); + + /* + * Disable and clear all capture flags and interrupts. + */ + ECAP_disableInterrupt(config->instance, ECAP_ECEINT_CEVT1_M | ECAP_ECEINT_CEVT2_M | ECAP_ECEINT_CEVT3_M | + ECAP_ECEINT_CEVT4_M | ECAP_ECEINT_CTROVF_M | ECAP_ECEINT_CTREQPRD_M | + ECAP_ECEINT_CTREQCMP_M); + + ECAP_clearInterrupt(config->instance, ECAP_ECCLR_CEVT1_M | ECAP_ECCLR_CEVT2_M | ECAP_ECCLR_CEVT3_M | + ECAP_ECCLR_CEVT4_M | ECAP_ECCLR_CTROVF_M | ECAP_ECCLR_CTRPRD_M | + ECAP_ECCLR_CTRCMP_M); + + ECAP_disableTimeStampCapture(config->instance); + ECAP_stopCounter(config->instance); + + /* + * Capture mode: + * Event1 falling + * Event2 rising + * Event3 falling + * Event4 rising + */ + ECAP_enableCaptureMode(config->instance); + ECAP_setCaptureMode(config->instance, ECAP_CONTINUOUS_CAPTURE_MODE, ECAP_EVENT_4); + ECAP_setEventPrescaler(config->instance, 0U); + + ECAP_setEventPolarity(config->instance, ECAP_EVENT_1, ECAP_EVNT_FALLING_EDGE); + ECAP_setEventPolarity(config->instance, ECAP_EVENT_2, ECAP_EVNT_RISING_EDGE); + ECAP_setEventPolarity(config->instance, ECAP_EVENT_3, ECAP_EVNT_FALLING_EDGE); + ECAP_setEventPolarity(config->instance, ECAP_EVENT_4, ECAP_EVNT_RISING_EDGE); + + ECAP_enableCounterResetOnEvent(config->instance, ECAP_EVENT_1); + ECAP_enableCounterResetOnEvent(config->instance, ECAP_EVENT_2); + ECAP_enableCounterResetOnEvent(config->instance, ECAP_EVENT_3); + ECAP_enableCounterResetOnEvent(config->instance, ECAP_EVENT_4); + + ECAP_selectECAPInput(config->instance, ECAP_INPUT_XBAR_INPUT7); + + ECAP_setPhaseShiftCount(config->instance, 0U); + ECAP_enableLoadCounter(config->instance); + + ECAP_setSyncOutMode(config->instance, ECAP_SYNC_OUT_SYNCI); + ECAP_setEmulationMode(config->instance, ECAP_EMULATION_STOP); + ECAP_setSyncInPulseSource(config->instance, ECAP_SYNC_IN_PULSE_SRC_DISABLE); + + /* ECAP_startCounter(config->instance); */ + /* ECAP_enableTimeStampCapture(config->instance); */ + /* ECAP_reArm(config->instance); */ + + /* + * 当前配置是 Event4 完成后产生中断。 + */ + /* ECAP_enableInterrupt(config->instance, ECAP_ECEINT_CEVT4_M); */ +} + +/* + * + */ +static void ecap_hw_deinit (const struct rt_ecap_config *config) +{ + RT_ASSERT(config != RT_NULL); + + ECAP_disableInterrupt(config->instance, ECAP_ECEINT_CEVT1_M | ECAP_ECEINT_CEVT2_M | ECAP_ECEINT_CEVT3_M | + ECAP_ECEINT_CEVT4_M | ECAP_ECEINT_CTROVF_M | ECAP_ECEINT_CTREQPRD_M | + ECAP_ECEINT_CTREQCMP_M); + + ECAP_disableTimeStampCapture(config->instance); + ECAP_stopCounter(config->instance); +} + +static void ecap_hw_clear_flags (const struct rt_ecap_config *config) +{ + RT_ASSERT(config != RT_NULL); + + ECAP_clearInterrupt(config->instance, ECAP_ECCLR_CEVT1_M | ECAP_ECCLR_CEVT2_M | ECAP_ECCLR_CEVT3_M | + ECAP_ECCLR_CEVT4_M | ECAP_ECCLR_CTROVF_M | ECAP_ECCLR_CTRPRD_M | + ECAP_ECCLR_CTRCMP_M); + ECAP_clearGlobalInterrupt(config->instance); +} + +static void ecap_hw_rearm (const struct rt_ecap_config *config) +{ + RT_ASSERT(config != RT_NULL); + + ecap_hw_clear_flags(config); + ECAP_reArm(config->instance); +} + +static void ecap_calc_capture (struct rt_ecap_capture *cap) +{ + RT_ASSERT(cap != RT_NULL); + + /* + * 由于当前配置为： + * Event1 falling + * Event2 rising + * Event3 falling + * Event4 rising + * + * 且每个 event 都 reset counter。 + * + * 所以 cap1~cap4 并不是一个自由运行时间轴上的绝对时间戳， + * 而是每段边沿之间的间隔计数。 + * + * 这里给一个通用解释： + * cap2: falling -> rising + * cap3: rising -> falling + * cap4: falling -> rising + * + * 对 PWM 输入来说，需要根据实际输入波形起始边沿判断高低电平。 + */ + cap->period_high = cap->cap2; + cap->period_low = cap->cap3; + cap->period_total = cap->cap2 + cap->cap3; +} + +static rt_err_t rt_ecap_init (rt_device_t dev) +{ + struct rt_ecap_device *ecap; + + RT_ASSERT(dev != RT_NULL); + + ecap = (struct rt_ecap_device *)dev; + + ecap_gpio_init(ecap->config); + ecap_xbar_init(ecap->config); + ecap_hw_init(ecap->config); + + ecap->last_capture.status = ECAP_STATUS_IDLE; + + return RT_EOK; +} + +static rt_err_t rt_ecap_open (rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_ecap_device *ecap; + + RT_ASSERT(dev != RT_NULL); + + ecap = (struct rt_ecap_device *)dev; + + rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER); + + if (ecap->opened == 0U) + { + ecap_hw_clear_flags(ecap->config); + ECAP_startCounter(ecap->config->instance); + ECAP_enableTimeStampCapture(ecap->config->instance); + ECAP_reArm(ecap->config->instance); + ECAP_enableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M); + + Interrupt_register(ecap->config->irq_type, &ECAP1_IRQHandler); + Interrupt_enable(ecap->config->irq_type); + } + + ecap->opened++; + + rt_mutex_release(&ecap->lock); + + return RT_EOK; +} + +static rt_err_t rt_ecap_close (rt_device_t dev) +{ + struct rt_ecap_device *ecap; + + RT_ASSERT(dev != RT_NULL); + + ecap = (struct rt_ecap_device *)dev; + + rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER); + + if (ecap->opened > 0U) + { + ecap->opened--; + + if (ecap->opened == 0U) + { + ECAP_disableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M); + ECAP_disableTimeStampCapture(ecap->config->instance); + ECAP_stopCounter(ecap->config->instance); + Interrupt_disable(ecap->config->irq_type); + } + } + + rt_mutex_release(&ecap->lock); + + return RT_EOK; +} + +static rt_ssize_t rt_ecap_read (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + struct rt_ecap_device *ecap; + struct rt_ecap_capture *cap; + + RT_ASSERT(dev != RT_NULL); + RT_ASSERT(buffer != RT_NULL); + + ecap = (struct rt_ecap_device *)dev; + + if (size < sizeof(struct rt_ecap_capture)) + { + return 0; + } + + /* + * 阻塞等待一次完整 capture。 + * 如果不希望阻塞，可以改成 RT_WAITING_NO。 + */ + if (rt_sem_take(&ecap->rx_sem, RT_WAITING_FOREVER) != RT_EOK) + { + return 0; + } + + rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER); + + cap = (struct rt_ecap_capture *)buffer; + *cap = ecap->last_capture; + + rt_mutex_release(&ecap->lock); + + return sizeof(struct rt_ecap_capture); +} + +static rt_err_t rt_ecap_control (rt_device_t dev, int cmd, void *args) +{ + struct rt_ecap_device *ecap; + + RT_ASSERT(dev != RT_NULL); + + ecap = (struct rt_ecap_device *)dev; + + switch (cmd) + { + case ECAP_CMD_ENABLE: + ECAP_startCounter(ecap->config->instance); + ECAP_enableTimeStampCapture(ecap->config->instance); + ECAP_enableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M); + break; + + case ECAP_CMD_DISABLE: + ECAP_disableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M); + ECAP_disableTimeStampCapture(ecap->config->instance); + ECAP_stopCounter(ecap->config->instance); + break; + + case ECAP_CMD_REARM: + ecap_hw_rearm(ecap->config); + break; + + case ECAP_CMD_GET_LAST_CAPTURE: + if (args == RT_NULL) + { + return -RT_EINVAL; + } + + rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER); + *(struct rt_ecap_capture *)args = ecap->last_capture; + rt_mutex_release(&ecap->lock); + break; + + case ECAP_CMD_SET_CALLBACK: + { + struct rt_ecap_callback *cb; + + if (args == RT_NULL) + { + return -RT_EINVAL; + } + + cb = (struct rt_ecap_callback *)args; + + rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER); + ecap->rx_callback = cb->callback; + ecap->rx_user_data = cb->user_data; + rt_mutex_release(&ecap->lock); + break; + } + + case ECAP_CMD_CLEAR_FLAGS: + ecap_hw_clear_flags(ecap->config); + break; + + case ECAP_CMD_ENABLE_IRQ: + ECAP_enableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M); + Interrupt_register(ecap->config->irq_type, &ECAP1_IRQHandler); + Interrupt_enable(ecap->config->irq_type); + break; + + case ECAP_CMD_DISABLE_IRQ: + ECAP_disableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M); + Interrupt_disable(ecap->config->irq_type); + break; + + default: + return -RT_EINVAL; + } + + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +static const struct rt_device_ops ecap_ops = +{ + rt_ecap_init, + rt_ecap_open, + rt_ecap_close, + rt_ecap_read, + RT_NULL, + rt_ecap_control +}; +#endif + +static rt_err_t rt_hw_ecap_register (struct rt_ecap_device *ecap, const struct rt_ecap_config *config) +{ + struct rt_device *dev; + + RT_ASSERT(ecap != RT_NULL); + RT_ASSERT(config != RT_NULL); + + rt_memset(ecap, 0, sizeof(struct rt_ecap_device)); + + ecap->config = config; + + rt_mutex_init(&ecap->lock, config->name, RT_IPC_FLAG_PRIO); + rt_sem_init(&ecap->rx_sem, config->name, 0, RT_IPC_FLAG_FIFO); + + dev = &ecap->parent; + + dev->type = RT_Device_Class_Miscellaneous; + dev->rx_indicate = RT_NULL; + dev->tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + dev->ops = &ecap_ops; +#else + dev->init = rt_ecap_init; + dev->open = rt_ecap_open; + dev->close = rt_ecap_close; + dev->read = rt_ecap_read; + dev->write = RT_NULL; + dev->control = rt_ecap_control; +#endif + + return rt_device_register(dev, config->name, RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX); +} + +int rt_hw_ecap_init (void) +{ + rt_err_t ret; + + ret = rt_hw_ecap_register(&ecap1_dev, &ecap1_config); + + if (ret != RT_EOK) + { + LOG_E("register ecap1 failed, ret = %d", ret); + return ret; + } + + LOG_I("ecap1 register done"); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_ecap_init); + +/* + * + */ +void rt_hw_ecap1_isr(void) +{ + struct rt_ecap_device *ecap; + struct rt_ecap_capture cap; + + ecap = &ecap1_dev; + + rt_interrupt_enter(); + + rt_memset(&cap, 0, sizeof(cap)); + + cap.cap1 = ECAP_getEventTimeStamp(ecap->config->instance, ECAP_EVENT_1); + cap.cap2 = ECAP_getEventTimeStamp(ecap->config->instance, ECAP_EVENT_2); + cap.cap3 = ECAP_getEventTimeStamp(ecap->config->instance, ECAP_EVENT_3); + cap.cap4 = ECAP_getEventTimeStamp(ecap->config->instance, ECAP_EVENT_4); + + cap.status = ECAP_STATUS_DONE; + ecap_calc_capture(&cap); + + ecap->last_capture = cap; + + /* + * 当前是 one-shot capture mode，所以一次捕获完成后需要 re-arm。 + */ + ecap_hw_clear_flags(ecap->config); + + rt_sem_release(&ecap->rx_sem); + + if (ecap->rx_callback != RT_NULL) + { + ecap->rx_callback((struct rt_ecap_capture *)&ecap->last_capture, + ecap->rx_user_data); + } + + rt_interrupt_leave(); +} + +void ECAP1_IRQHandler (void) +{ + rt_hw_ecap1_isr(); +} + + +#endif /* #if defined(BSP_USING_ECAP) */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_ecap.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_ecap.h new file mode 100644 index 00000000000..23ffb0ac369 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_ecap.h @@ -0,0 +1,123 @@ +/**************************************************************************//** +* +* @copyright (C) 2026 Novosense Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2026-5-7 Alex-J First version +* +******************************************************************************/ + +#ifndef __DRV_ECAP_H__ +#define __DRV_ECAP_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ECAP_DEVICE_NAME_MAX 8U + +/* + * control command + */ +#define ECAP_CMD_ENABLE (0x01) +#define ECAP_CMD_DISABLE (0x02) +#define ECAP_CMD_REARM (0x03) +#define ECAP_CMD_GET_LAST_CAPTURE (0x04) +#define ECAP_CMD_SET_CALLBACK (0x05) +#define ECAP_CMD_CLEAR_FLAGS (0x06) +#define ECAP_CMD_ENABLE_IRQ (0x07) +#define ECAP_CMD_DISABLE_IRQ (0x08) + +/* + * ECAP capture status + */ +#define ECAP_STATUS_IDLE (0x00U) +#define ECAP_STATUS_DONE (0x01U) +#define ECAP_STATUS_OVERFLOW (0x02U) +#define ECAP_STATUS_CAPTURE (0x04U) +#define ECAP_STATUS_TIMEOUT (0x05U) + +/* + * Capture result. + * + * cap1~cap4 对应 ECAP CEVT1~CEVT4 的捕获值。 + * period_high / period_low 可根据当前边沿配置计算。 + */ +struct rt_ecap_capture +{ + rt_uint32_t cap1; + rt_uint32_t cap2; + rt_uint32_t cap3; + rt_uint32_t cap4; + + rt_uint32_t period_low; + rt_uint32_t period_high; + rt_uint32_t period_total; + + rt_uint32_t status; +}; + +typedef void (*rt_ecap_rx_callback_t)(struct rt_ecap_capture *capture, void *user_data); + +struct rt_ecap_callback +{ + rt_ecap_rx_callback_t callback; + void *user_data; +}; + +/* + * Static ECAP hardware configuration. + */ +struct rt_ecap_config +{ + const char *name; + + ECAP_TypeDef *instance; + IRQn_Type irq_type; + + rt_uint32_t input_xbar; + rt_uint32_t ecap_input; + rt_uint32_t input_source; + + GPIO_TypeDef *gpio_port; + GPIO_PinNum gpio_pin; + GPIO_AltFunc gpio_mux; + void (*irq_handler)(void); +}; + +/* + * ECAP device object. + */ +struct rt_ecap_device +{ + struct rt_device parent; + + const struct rt_ecap_config *config; + + struct rt_mutex lock; + struct rt_semaphore rx_sem; + + volatile struct rt_ecap_capture last_capture; + + rt_ecap_rx_callback_t rx_callback; + void *rx_user_data; + + rt_uint8_t opened; +}; + +int rt_hw_ecap_init(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.c new file mode 100644 index 00000000000..b3e67ae04df --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.c @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * + */ + +#include +#include "drv_gpio.h" +#include "NS800RT7xxx_TI_gpio.h" +#include +#include + +#ifdef BSP_USING_GPIO + +#define PIN_ENTRY(pin_macro) {pin_macro} + +static const rt_pin_info_t pin_map_table[225] = { + /* 0-21: 连续 */ + [0] = PIN_ENTRY(GPIO_0), + [1] = PIN_ENTRY(GPIO_1), + [2] = PIN_ENTRY(GPIO_2), + [3] = PIN_ENTRY(GPIO_3), + [4] = PIN_ENTRY(GPIO_4), + [5] = PIN_ENTRY(GPIO_5), + [6] = PIN_ENTRY(GPIO_6), + [7] = PIN_ENTRY(GPIO_7), + [8] = PIN_ENTRY(GPIO_8), + [9] = PIN_ENTRY(GPIO_9), + [10] = PIN_ENTRY(GPIO_10), + [11] = PIN_ENTRY(GPIO_11), + [12] = PIN_ENTRY(GPIO_12), + [13] = PIN_ENTRY(GPIO_13), + [14] = PIN_ENTRY(GPIO_14), + [15] = PIN_ENTRY(GPIO_15), + [16] = PIN_ENTRY(GPIO_16), + [17] = PIN_ENTRY(GPIO_17), + [18] = PIN_ENTRY(GPIO_18), + [19] = PIN_ENTRY(GPIO_19), + [20] = PIN_ENTRY(GPIO_20), + [21] = PIN_ENTRY(GPIO_21), + + /* 22-32: 不连续 */ + [22] = PIN_ENTRY(GPIO_22), + [23] = PIN_ENTRY(GPIO_23), + [24] = PIN_ENTRY(GPIO_24), + [25] = PIN_ENTRY(GPIO_25), + [26] = PIN_ENTRY(GPIO_26), + [27] = PIN_ENTRY(GPIO_27), + [28] = PIN_ENTRY(GPIO_28), + [29] = PIN_ENTRY(GPIO_29), + [30] = PIN_ENTRY(GPIO_30), + [31] = PIN_ENTRY(GPIO_31), + [32] = PIN_ENTRY(GPIO_32), + + /* 33-63: 连续 */ + [33] = PIN_ENTRY(GPIO_33), + [34] = PIN_ENTRY(GPIO_34), + [35] = PIN_ENTRY(GPIO_35), + [36] = PIN_ENTRY(GPIO_36), + [37] = PIN_ENTRY(GPIO_37), + [38] = PIN_ENTRY(GPIO_38), + [39] = PIN_ENTRY(GPIO_39), + [40] = PIN_ENTRY(GPIO_40), + [41] = PIN_ENTRY(GPIO_41), + [42] = PIN_ENTRY(GPIO_42), + [43] = PIN_ENTRY(GPIO_43), + [44] = PIN_ENTRY(GPIO_44), + [45] = PIN_ENTRY(GPIO_45), + [46] = PIN_ENTRY(GPIO_46), + [47] = PIN_ENTRY(GPIO_47), + [48] = PIN_ENTRY(GPIO_48), + [49] = PIN_ENTRY(GPIO_49), + [50] = PIN_ENTRY(GPIO_50), + [51] = PIN_ENTRY(GPIO_51), + [52] = PIN_ENTRY(GPIO_52), + [53] = PIN_ENTRY(GPIO_53), + [54] = PIN_ENTRY(GPIO_54), + [55] = PIN_ENTRY(GPIO_55), + [56] = PIN_ENTRY(GPIO_56), + [57] = PIN_ENTRY(GPIO_57), + [58] = PIN_ENTRY(GPIO_58), + [59] = PIN_ENTRY(GPIO_59), + [60] = PIN_ENTRY(GPIO_60), + [61] = PIN_ENTRY(GPIO_61), + [62] = PIN_ENTRY(GPIO_62), + [63] = PIN_ENTRY(GPIO_63), + + /* 64-94: 连续 */ + [64] = PIN_ENTRY(GPIO_64), + [65] = PIN_ENTRY(GPIO_65), + [66] = PIN_ENTRY(GPIO_66), + [67] = PIN_ENTRY(GPIO_67), + [68] = PIN_ENTRY(GPIO_68), + [69] = PIN_ENTRY(GPIO_69), + [70] = PIN_ENTRY(GPIO_70), + [71] = PIN_ENTRY(GPIO_71), + [72] = PIN_ENTRY(GPIO_72), + [73] = PIN_ENTRY(GPIO_73), + [74] = PIN_ENTRY(GPIO_74), + [75] = PIN_ENTRY(GPIO_75), + [76] = PIN_ENTRY(GPIO_76), + [77] = PIN_ENTRY(GPIO_77), + [78] = PIN_ENTRY(GPIO_78), + [79] = PIN_ENTRY(GPIO_79), + [80] = PIN_ENTRY(GPIO_80), + [81] = PIN_ENTRY(GPIO_81), + [82] = PIN_ENTRY(GPIO_82), + [83] = PIN_ENTRY(GPIO_83), + [84] = PIN_ENTRY(GPIO_84), + [85] = PIN_ENTRY(GPIO_85), + [86] = PIN_ENTRY(GPIO_86), + [87] = PIN_ENTRY(GPIO_87), + [88] = PIN_ENTRY(GPIO_88), + [89] = PIN_ENTRY(GPIO_89), + [90] = PIN_ENTRY(GPIO_90), + [91] = PIN_ENTRY(GPIO_91), + [92] = PIN_ENTRY(GPIO_92), + [93] = PIN_ENTRY(GPIO_93), + [94] = PIN_ENTRY(GPIO_94), + + /* 不连续引脚 */ + [99] = PIN_ENTRY(GPIO_99), + [100] = PIN_ENTRY(GPIO_100), + [103] = PIN_ENTRY(GPIO_103), + [104] = PIN_ENTRY(GPIO_104), + [105] = PIN_ENTRY(GPIO_105), + [106] = PIN_ENTRY(GPIO_106), + [133] = PIN_ENTRY(GPIO_133), + [183] = PIN_ENTRY(GPIO_183), + [184] = PIN_ENTRY(GPIO_184), + [198] = PIN_ENTRY(GPIO_198), + [199] = PIN_ENTRY(GPIO_199), + [200] = PIN_ENTRY(GPIO_200), + [201] = PIN_ENTRY(GPIO_201), + [202] = PIN_ENTRY(GPIO_202), + [203] = PIN_ENTRY(GPIO_203), + [204] = PIN_ENTRY(GPIO_204), + [205] = PIN_ENTRY(GPIO_205), + [206] = PIN_ENTRY(GPIO_206), + [207] = PIN_ENTRY(GPIO_207), + [208] = PIN_ENTRY(GPIO_208), + [209] = PIN_ENTRY(GPIO_209), + [210] = PIN_ENTRY(GPIO_210), + [211] = PIN_ENTRY(GPIO_211), + [212] = PIN_ENTRY(GPIO_212), + [213] = PIN_ENTRY(GPIO_213), + [214] = PIN_ENTRY(GPIO_214), + [215] = PIN_ENTRY(GPIO_215), + [216] = PIN_ENTRY(GPIO_216), + [217] = PIN_ENTRY(GPIO_217), + [218] = PIN_ENTRY(GPIO_218), + [219] = PIN_ENTRY(GPIO_219), + [220] = PIN_ENTRY(GPIO_220), + [221] = PIN_ENTRY(GPIO_221), + [222] = PIN_ENTRY(GPIO_222), + [223] = PIN_ENTRY(GPIO_223), + [224] = PIN_ENTRY(GPIO_224), +}; + +/* 1. PIN_NUM: 从(port, pin)获取引脚编号 */ +int get_pin_num(GPIO_TypeDef *port, GPIO_PinNum pin) +{ + /* 遍历数组查找匹配 */ + for (int i = 0; i < 225; i++) + { + if (pin_map_table[i].port == port && + pin_map_table[i].pin == (uint16_t)pin) + { + return i; /* 返回引脚编号 */ + } + } + return -1; /* 未找到 */ +} + +/* 2. PIN_PORT: 从引脚编号获取端口索引 */ +uint8_t get_port_index(GPIO_TypeDef *port) +{ + /* 由于新平台端口地址可能不连续，需要映射 */ + if (port == GPIOA) return 0; + if (port == GPIOB) return 1; + if (port == GPIOC) return 2; + if (port == GPIOD) return 3; + if (port == GPIOE) return 4; + if (port == GPIOF) return 5; + if (port == GPIOG) return 6; + if (port == GPIOH) return 7; + /* 如果有更多端口继续添加 */ + return 0xFF; /* 无效端口 */ +} + +/* 3. PIN_NO: 从引脚编号获取引脚索引 */ +uint8_t get_pin_index(uint16_t pin) +{ + /* 提取引脚位的位置 */ + switch (pin) + { + case GPIO_PIN_0: return 0; + case GPIO_PIN_1: return 1; + case GPIO_PIN_2: return 2; + case GPIO_PIN_3: return 3; + case GPIO_PIN_4: return 4; + case GPIO_PIN_5: return 5; + case GPIO_PIN_6: return 6; + case GPIO_PIN_7: return 7; + case GPIO_PIN_8: return 8; + case GPIO_PIN_9: return 9; + case GPIO_PIN_10: return 10; + case GPIO_PIN_11: return 11; + case GPIO_PIN_12: return 12; + case GPIO_PIN_13: return 13; + case GPIO_PIN_14: return 14; + case GPIO_PIN_15: return 15; + case GPIO_PIN_16: return 16; + case GPIO_PIN_17: return 17; + case GPIO_PIN_18: return 18; + case GPIO_PIN_19: return 19; + case GPIO_PIN_20: return 20; + case GPIO_PIN_21: return 21; + case GPIO_PIN_22: return 22; + case GPIO_PIN_23: return 23; + case GPIO_PIN_24: return 24; + case GPIO_PIN_25: return 25; + case GPIO_PIN_26: return 26; + case GPIO_PIN_27: return 27; + case GPIO_PIN_28: return 28; + case GPIO_PIN_29: return 29; + case GPIO_PIN_30: return 30; + case GPIO_PIN_31: return 31; + default: return 0xFF; /* 无效引脚 */ + } +} + +uint8_t get_port_index_by_num(int pin_num) +{ + const rt_pin_info_t *info = get_pin_info(pin_num); + + if (info == RT_NULL) + { + return 0xFF; + } + + return get_port_index(info->port); +} + +uint8_t get_pin_index_by_num(int pin_num) +{ + const rt_pin_info_t *info = get_pin_info(pin_num); + + if (info == RT_NULL) + { + return 0xFF; + } + + return get_pin_index(info->pin); +} + +const rt_pin_info_t* get_pin_info(int pin_num) +{ + if(pin_num < 0 || pin_num >=225) + return NULL; + + if(pin_map_table[pin_num].port == NULL) + { + return NULL; + } + + return &pin_map_table[pin_num]; +} + +#define PIN_STPORT(pin) (pin_map_table[(pin)].port) +#define PIN_STPIN(pin) (pin_map_table[(pin)].pin) + + +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0])) + +/* e.g. PE.7 */ +static rt_base_t ns800_pin_get(const char *name) +{ + char port_name; + int pin_index; + uint8_t port_index; + GPIO_TypeDef *port = RT_NULL; + char *endptr; + + if ((name == RT_NULL) || (name[0] == '\0')) + { + goto out; + } + + if ((name[0] != 'P') && (name[0] != 'p')) + { + goto out; + } + + port_name = (char)toupper((unsigned char)name[1]); + if (name[2] != '.') + { + goto out; + } + + pin_index = (int)strtol(&name[3], &endptr, 10); + if ((endptr == &name[3]) || (*endptr != '\0')) + { + goto out; + } + + if ((pin_index < 0) || (pin_index > 31)) + { + goto out; + } + + port_index = (uint8_t)(port_name - 'A'); + switch (port_index) + { + case 0: port = GPIOA; break; + case 1: port = GPIOB; break; + case 2: port = GPIOC; break; + case 3: port = GPIOD; break; + case 4: port = GPIOE; break; + case 5: port = GPIOF; break; + case 6: port = GPIOG; break; + case 7: port = GPIOH; break; + default: + goto out; + } + + return get_pin_num(port, (GPIO_PinNum)pin_index); + +out: + rt_kprintf("Px.y x:A~H y:0-31, e.g. PA.0\n"); + return -RT_EINVAL; +} + +static void ns800rt7_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + const rt_pin_info_t *info = get_pin_info(pin); + + if (info == RT_NULL) + { + return ; + } + + if(value == 0) + { + GPIO_clearPin(info->port, info->pin); + } + else if(value == 1) + { + GPIO_setPin(info->port, info->pin); + } +} + +static rt_ssize_t ns800rt7_pin_read(rt_device_t dev, rt_base_t pin) +{ + const rt_pin_info_t *info = get_pin_info(pin); + + if (info == RT_NULL) + { + return -RT_EINVAL; + } + + return (GPIO_readPin(info->port, info->pin)) ? PIN_HIGH : PIN_LOW; +} + +static void ns800rt7_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + const rt_pin_info_t *info = get_pin_info(pin); + + if (info == RT_NULL) + { + return ; + } + + GPIO_setAnalogMode(info->port, info->pin, GPIO_ANALOG_DISABLED); + GPIO_setQualificationMode(info->port, info->pin, GPIO_QUAL_SYNC); + GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_STD); + GPIO_setDriveLevel(info->port, info->pin, GPIO_DRV_MAX); + + if (mode == PIN_MODE_OUTPUT ) + { + GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_STD); + GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION); + GPIO_clearPin(info->port, info->pin); + GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_OUT); + } + else if (mode == PIN_MODE_INPUT) + { + GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_STD); + GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION); + GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_IN); + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_PULLUP); + GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION); + GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_IN); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_PULLDOWN); + GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION); + GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_IN); + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_OD); + GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION); + GPIO_clearPin(info->port, info->pin); + GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_OUT); + } + +} + +static rt_err_t ns800_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + return RT_EOK; +} + +static rt_err_t ns800_pin_dettach_irq(struct rt_device *device, rt_base_t pin) +{ + return RT_EOK; +} + +static rt_err_t ns800_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint8_t enabled) +{ + return RT_EOK; +} + + +static const struct rt_pin_ops _ns800rt7_pin_ops = +{ + ns800rt7_pin_mode, + ns800rt7_pin_write, + ns800rt7_pin_read, + ns800_pin_attach_irq, + ns800_pin_dettach_irq, + ns800_pin_irq_enable, + ns800_pin_get, + RT_NULL, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + +} + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &_ns800rt7_pin_ops, RT_NULL); +} + +#endif /* BSP_USING_GPIO */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.h new file mode 100644 index 00000000000..24a5980dbfa --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_gpio.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 balanceTWK first version + * 2020-09-01 thread-liu add GPIOZ + * 2020-09-18 geniusgogo optimization design pin-index algorithm + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + GPIO_TypeDef *port; + GPIO_PinNum pin; +} rt_pin_info_t; + + +#define PIN_NUM(...) get_pin_num(__VA_ARGS__) +#define PIN_PORT(pin) get_port_index_by_num(pin) +#define PIN_NO(pin) get_pin_index_by_num(pin) + +const rt_pin_info_t* get_pin_info(int pin_num); +int get_pin_num(GPIO_TypeDef *port, GPIO_PinNum pin); +uint8_t get_port_index(GPIO_TypeDef *port); +uint8_t get_pin_index(uint16_t pin); +uint8_t get_port_index_by_num(int pin_num); +uint8_t get_pin_index_by_num(int pin_num); + +int rt_hw_pin_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_log.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_log.h new file mode 100644 index 00000000000..a1b3a9190dd --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_log.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_uart.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_uart.c new file mode 100644 index 00000000000..76c084038a0 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_uart.c @@ -0,0 +1,533 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + * 2020-03-16 SummerGift add device close feature + * 2020-03-20 SummerGift fix bug caused by ORE + * 2026-05-10 Codex Reworked driver around BSP UART config tables + */ + +#include "board.h" +#include "drv_uart.h" +#include "drv_config.h" + +#ifdef RT_USING_SERIAL + +#define DRV_DEBUG +#define LOG_TAG "drv.uart" +#include + +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) +#error "Please define at least one BSP_USING_UARTx" +#endif + +#ifndef BSP_NS800_UART_TX_TIMEOUT +#define BSP_NS800_UART_TX_TIMEOUT 6000 +#endif + +#ifdef RT_USING_SERIAL_V2 +#define NS800_UART_BUF_CONFIG(_rxbuf, _txbuf) \ + .rx_bufsz = (_rxbuf), \ + .tx_bufsz = (_txbuf), +#define NS800_UART_DEFAULT_TX_TIMEOUT 0U +#else +#ifndef RT_SERIAL_RB_BUFSZ +#define RT_SERIAL_RB_BUFSZ 64 +#endif + +#define NS800_UART_BUF_CONFIG(_rxbuf, _txbuf) \ + .rx_bufsz = RT_SERIAL_RB_BUFSZ, \ + .tx_bufsz = 0U, +#define NS800_UART_DEFAULT_TX_TIMEOUT BSP_NS800_UART_TX_TIMEOUT +#endif + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif +}; + +#ifdef BSP_USING_UART1 +void UART1_IRQHandler(void); +#endif +#ifdef BSP_USING_UART2 +void UART2_IRQHandler(void); +#endif +#ifdef BSP_USING_UART3 +void UART3_IRQHandler(void); +#endif +#ifdef BSP_USING_UART4 +void UART4_IRQHandler(void); +#endif + +static struct ns800_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + { + .name = "uart1", + .Instance = UART1, + .rx_irq_type = UART1_RX_IRQn, + .tx_irq_type = UART1_TX_IRQn, + .irq_handler = UART1_IRQHandler, + .rx_port = GPIOA, + .rx_pin = GPIO_PIN_13, + .rx_mux = ALT6_FUNCTION, + .rx_pad = GPIO_PIN_TYPE_PULLUP, + .rx_direction = GPIO_DIR_MODE_IN, + .rx_drive_max = RT_FALSE, + .tx_port = GPIOA, + .tx_pin = GPIO_PIN_12, + .tx_mux = ALT6_FUNCTION, + .tx_pad = GPIO_PIN_TYPE_STD, + .tx_direction = GPIO_DIR_MODE_OUT, + .tx_drive_max = RT_FALSE, + .tx_block_timeout = NS800_UART_DEFAULT_TX_TIMEOUT, + NS800_UART_BUF_CONFIG(BSP_UART1_RX_BUFSIZE, BSP_UART1_TX_BUFSIZE) + }, +#endif +#ifdef BSP_USING_UART2 + { + .name = "uart2", + .Instance = UART2, + .rx_irq_type = UART2_RX_IRQn, + .tx_irq_type = UART2_TX_IRQn, + .irq_handler = UART2_IRQHandler, + .rx_port = GPIOB, + .rx_pin = GPIO_PIN_7, + .rx_mux = ALT1_FUNCTION, + .rx_pad = GPIO_PIN_TYPE_PULLUP, + .rx_direction = GPIO_DIR_MODE_IN, + .rx_drive_max = RT_FALSE, + .tx_port = GPIOB, + .tx_pin = GPIO_PIN_6, + .tx_mux = ALT1_FUNCTION, + .tx_pad = GPIO_PIN_TYPE_STD, + .tx_direction = GPIO_DIR_MODE_OUT, + .tx_drive_max = RT_TRUE, + .tx_block_timeout = NS800_UART_DEFAULT_TX_TIMEOUT, + NS800_UART_BUF_CONFIG(BSP_UART2_RX_BUFSIZE, BSP_UART2_TX_BUFSIZE) + }, +#endif +#ifdef BSP_USING_UART3 + { + .name = "uart3", + .Instance = UART3, + .rx_irq_type = UART3_RX_IRQn, + .tx_irq_type = UART3_TX_IRQn, + .irq_handler = UART3_IRQHandler, + .rx_port = GPIOB, + .rx_pin = GPIO_PIN_25, + .rx_mux = ALT11_FUNCTION, + .rx_pad = GPIO_PIN_TYPE_PULLUP, + .rx_direction = GPIO_DIR_MODE_IN, + .rx_drive_max = RT_FALSE, + .tx_port = GPIOB, + .tx_pin = GPIO_PIN_24, + .tx_mux = ALT11_FUNCTION, + .tx_pad = GPIO_PIN_TYPE_STD, + .tx_direction = GPIO_DIR_MODE_OUT, + .tx_drive_max = RT_TRUE, + .tx_block_timeout = NS800_UART_DEFAULT_TX_TIMEOUT, + NS800_UART_BUF_CONFIG(BSP_UART3_RX_BUFSIZE, BSP_UART3_TX_BUFSIZE) + }, +#endif +#ifdef BSP_USING_UART4 + { + .name = "uart4", + .Instance = UART4, + .rx_irq_type = UART4_RX_IRQn, + .tx_irq_type = UART4_TX_IRQn, + .irq_handler = UART4_IRQHandler, + .rx_port = GPIOB, + .rx_pin = GPIO_PIN_13, + .rx_mux = ALT7_FUNCTION, + .rx_pad = GPIO_PIN_TYPE_PULLUP, + .rx_direction = GPIO_DIR_MODE_IN, + .rx_drive_max = RT_FALSE, + .tx_port = GPIOB, + .tx_pin = GPIO_PIN_12, + .tx_mux = ALT7_FUNCTION, + .tx_pad = GPIO_PIN_TYPE_STD, + .tx_direction = GPIO_DIR_MODE_OUT, + .tx_drive_max = RT_TRUE, + .tx_block_timeout = NS800_UART_DEFAULT_TX_TIMEOUT, + NS800_UART_BUF_CONFIG(BSP_UART4_RX_BUFSIZE, BSP_UART4_TX_BUFSIZE) + }, +#endif +}; + +static struct ns800_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +static void ns800_uart_gpio_init(const struct ns800_uart_config *config) +{ + RT_ASSERT(config != RT_NULL); + + GPIO_setPinConfig(config->rx_port, config->rx_pin, config->rx_mux); + GPIO_setAnalogMode(config->rx_port, config->rx_pin, GPIO_ANALOG_DISABLED); + GPIO_setPadConfig(config->rx_port, config->rx_pin, config->rx_pad); + GPIO_setQualificationMode(config->rx_port, config->rx_pin, GPIO_QUAL_SYNC); + GPIO_setDirectionMode(config->rx_port, config->rx_pin, config->rx_direction); + if (config->rx_drive_max) + { + GPIO_setDriveLevel(config->rx_port, config->rx_pin, GPIO_DRV_MAX); + } + + GPIO_setPinConfig(config->tx_port, config->tx_pin, config->tx_mux); + GPIO_setAnalogMode(config->tx_port, config->tx_pin, GPIO_ANALOG_DISABLED); + GPIO_setPadConfig(config->tx_port, config->tx_pin, config->tx_pad); + GPIO_setQualificationMode(config->tx_port, config->tx_pin, GPIO_QUAL_SYNC); + GPIO_setDirectionMode(config->tx_port, config->tx_pin, config->tx_direction); + if (config->tx_drive_max) + { + GPIO_setDriveLevel(config->tx_port, config->tx_pin, GPIO_DRV_MAX); + } +} + +static UART_BitCountPerChar ns800_uart_data_bits(rt_uint32_t data_bits) +{ + switch (data_bits) + { + case DATA_BITS_7: + return UART_7_BITS_PER_CHAR; + case DATA_BITS_9: + return UART_9_BITS_PER_CHAR; + case DATA_BITS_8: + default: + return UART_8_BITS_PER_CHAR; + } +} + +static void ns800_uart_apply_runtime_cfg(struct ns800_uart *uart, struct serial_configure *cfg) +{ + RT_ASSERT(uart != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart->handle.Instance = uart->config->Instance; + uart->handle.baud_rate = cfg->baud_rate; + uart->handle.data_bits = cfg->data_bits; + uart->handle.stop_bits = cfg->stop_bits; + uart->handle.parity = cfg->parity; +} + +static void ns800_uart_clear_errors(UART_TypeDef *instance) +{ + UART_clearErrorFlags(instance, + UART_STAT_OR_M | + UART_STAT_NF_M | + UART_STAT_FE_M | + UART_STAT_PF_M); +} + +static rt_err_t ns800_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct ns800_uart *uart; + UART_BitCountPerChar bit_count; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct ns800_uart, serial); + + ns800_uart_apply_runtime_cfg(uart, cfg); + ns800_uart_gpio_init(uart->config); + + bit_count = ns800_uart_data_bits(cfg->data_bits); + + UART_resetModule(uart->handle.Instance); + UART_setBaud(uart->handle.Instance, cfg->baud_rate); + + if (cfg->parity == PARITY_ODD) + { + UART_setBitCountPerChar(uart->handle.Instance, bit_count, true); + UART_setParityMode(uart->handle.Instance, UART_PAR_ODD); + } + else if (cfg->parity == PARITY_EVEN) + { + UART_setBitCountPerChar(uart->handle.Instance, bit_count, true); + UART_setParityMode(uart->handle.Instance, UART_PAR_EVEN); + } + else + { + UART_setBitCountPerChar(uart->handle.Instance, bit_count, false); + } + + switch (cfg->stop_bits) + { + case STOP_BITS_2: + UART_setStopBitCount(uart->handle.Instance, UART_TWO_STOP_BIT); + break; + case STOP_BITS_1: + default: + UART_setStopBitCount(uart->handle.Instance, UART_ONE_STOP_BIT); + break; + } + + ns800_uart_clear_errors(uart->handle.Instance); + +#ifdef RT_USING_SERIAL_V2 + UART_enableTxFifo(uart->handle.Instance); + UART_resetTxFifo(uart->handle.Instance); + UART_setTxFifoWatermark(uart->handle.Instance, UART_FIFO_TX6); + + UART_enableRxFifo(uart->handle.Instance); + UART_resetRxFifo(uart->handle.Instance); + UART_setRxFifoWatermark(uart->handle.Instance, UART_FIFO_RX1); + UART_setRxIdleCharacter(uart->handle.Instance, UART_IDLE_CHARACTER_CNT0); +#else + /* + * RT-Thread serial v1 consumes RX data byte-by-byte from getc(). + * Keep the hardware in the simplest non-FIFO mode to avoid RDRF + * reasserting on idle-partial FIFO conditions. + */ + UART_disableTxFifo(uart->handle.Instance); + UART_disableRxFifo(uart->handle.Instance); + UART_setRxIdleCharacter(uart->handle.Instance, UART_IDLE_CHARACTER_CNT0); +#endif + + UART_enableTxModule(uart->handle.Instance); + UART_enableRxModule(uart->handle.Instance); + + uart->tx_block_timeout = uart->config->tx_block_timeout; + + return RT_EOK; +} + +static rt_err_t ns800_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct ns800_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct ns800_uart, serial); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + { + rt_uint32_t direction = (rt_uint32_t)arg; + + Interrupt_disable(uart->config->rx_irq_type); + if (direction == RT_DEVICE_FLAG_INT_RX) + { + UART_disableInterrupt(uart->handle.Instance, UART_INT_RX_DATA_REG_FULL); + } + else if (direction == RT_DEVICE_FLAG_INT_TX) + { + UART_disableInterrupt(uart->handle.Instance, UART_INT_TX_COMPLETE); + Interrupt_disable(uart->config->tx_irq_type); + } + break; + } + + case RT_DEVICE_CTRL_SET_INT: + { + rt_uint32_t direction = (rt_uint32_t)arg; + + if (direction == RT_DEVICE_FLAG_INT_RX) + { + UART_enableInterrupt(uart->handle.Instance, UART_INT_RX_DATA_REG_FULL); + Interrupt_register(uart->config->rx_irq_type, uart->config->irq_handler); + Interrupt_enable(uart->config->rx_irq_type); + } + else if (direction == RT_DEVICE_FLAG_INT_TX) + { + UART_enableInterrupt(uart->handle.Instance, UART_INT_TX_COMPLETE); + Interrupt_register(uart->config->tx_irq_type, uart->config->irq_handler); + Interrupt_enable(uart->config->tx_irq_type); + } + break; + } + + case RT_DEVICE_CTRL_CLOSE: + UART_disableTxModule(uart->handle.Instance); + UART_disableRxModule(uart->handle.Instance); + break; + + case UART_CTRL_SET_BLOCK_TIMEOUT: + { + rt_uint32_t block_timeout = (rt_uint32_t)arg; + + if (block_timeout == 0U) + { + return -RT_ERROR; + } + + uart->tx_block_timeout = block_timeout; + break; + } + + default: + break; + } + + return RT_EOK; +} + +static int ns800_putc(struct rt_serial_device *serial, char c) +{ + struct ns800_uart *uart; + rt_uint32_t block_timeout; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct ns800_uart, serial); + block_timeout = uart->tx_block_timeout; + + while (!UART_isSpaceAvailable(uart->handle.Instance)) + { + if (block_timeout-- == 0U) + { + return -1; + } + } + + UART_writeChar(uart->handle.Instance, (rt_uint8_t)c); + + while ((uart->handle.Instance->STAT.BIT.TC == false) && (--block_timeout != 0U)) + { + } + + return (block_timeout != 0U) ? 1 : -1; +} + +static int ns800_getc(struct rt_serial_device *serial) +{ + struct ns800_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct ns800_uart, serial); + + if (UART_isDataAvailable(uart->handle.Instance)) + { + return (int)UART_readChar(uart->handle.Instance); + } + + return -1; +} + +static void uart_isr(struct rt_serial_device *serial) +{ + struct ns800_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct ns800_uart, serial); + + if (UART_getStatusFlag(uart->handle.Instance, UART_RX_OVERRUN) || + UART_getStatusFlag(uart->handle.Instance, UART_NOISE_DETECT) || + UART_getStatusFlag(uart->handle.Instance, UART_FRAME_ERR) || + UART_getStatusFlag(uart->handle.Instance, UART_PARITY_ERR)) + { + ns800_uart_clear_errors(uart->handle.Instance); + } + + if (UART_getStatusFlag(uart->handle.Instance, UART_RX_DATA_REG_FULL)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + else if (UART_getStatusFlag(uart->handle.Instance, UART_TX_COMPLETE)) + { + UART_disableInterrupt(uart->handle.Instance, UART_INT_TX_COMPLETE); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } +} + +#ifdef BSP_USING_UART1 +void UART1_IRQHandler(void) +{ + rt_interrupt_enter(); + uart_isr(&uart_obj[UART1_INDEX].serial); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_UART2 +void UART2_IRQHandler(void) +{ + rt_interrupt_enter(); + uart_isr(&uart_obj[UART2_INDEX].serial); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_UART3 +void UART3_IRQHandler(void) +{ + rt_interrupt_enter(); + uart_isr(&uart_obj[UART3_INDEX].serial); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_UART4 +void UART4_IRQHandler(void) +{ + rt_interrupt_enter(); + uart_isr(&uart_obj[UART4_INDEX].serial); + rt_interrupt_leave(); +} +#endif + +static void ns800_uart_fill_default_config(struct serial_configure *config, + const struct ns800_uart_config *hw) +{ + RT_ASSERT(config != RT_NULL); + RT_ASSERT(hw != RT_NULL); + + *config = (struct serial_configure)RT_SERIAL_CONFIG_DEFAULT; + +#ifdef RT_USING_SERIAL_V2 + config->rx_bufsz = hw->rx_bufsz; + config->tx_bufsz = hw->tx_bufsz; +#else + config->bufsz = hw->rx_bufsz; +#endif +} + +static const struct rt_uart_ops ns800_uart_ops = +{ + .configure = ns800_configure, + .control = ns800_control, + .putc = ns800_putc, + .getc = ns800_getc, +}; + +int rt_hw_uart_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t i; + + for (i = 0; i < sizeof(uart_obj) / sizeof(uart_obj[0]); i++) + { + uart_obj[i].config = &uart_config[i]; + uart_obj[i].serial.ops = &ns800_uart_ops; + ns800_uart_fill_default_config(&uart_obj[i].serial.config, uart_obj[i].config); + uart_obj[i].tx_block_timeout = uart_obj[i].config->tx_block_timeout; + + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX, + RT_NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_uart.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_uart.h new file mode 100644 index 00000000000..cc6bf6ff967 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drivers/drv_uart.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-30 SummerGift first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include "rtdevice.h" +#include +#include + +#define UART_CTRL_SET_BLOCK_TIMEOUT 0x20 + +/* ns800 config class */ +struct ns800_uart_config +{ + const char *name; + UART_TypeDef *Instance; + IRQn_Type rx_irq_type; + IRQn_Type tx_irq_type; + void (*irq_handler)(void); + GPIO_TypeDef *rx_port; + GPIO_PinNum rx_pin; + GPIO_AltFunc rx_mux; + rt_uint32_t rx_pad; + GPIO_Direction rx_direction; + rt_bool_t rx_drive_max; + GPIO_TypeDef *tx_port; + GPIO_PinNum tx_pin; + GPIO_AltFunc tx_mux; + rt_uint32_t tx_pad; + GPIO_Direction tx_direction; + rt_bool_t tx_drive_max; + rt_uint32_t tx_block_timeout; + rt_uint16_t rx_bufsz; + rt_uint16_t tx_bufsz; +}; + +typedef struct { + UART_TypeDef *Instance; + + rt_uint32_t baud_rate; + + rt_uint8_t data_bits; + rt_uint8_t stop_bits; + rt_uint8_t parity; + rt_uint8_t bit_order; + rt_uint8_t invert; + rt_uint8_t bufsz; + rt_uint8_t flowcontrol; + rt_uint8_t reserved; +}UART_HandleTypeDef; + +/* ns800 uart dirver class */ +struct ns800_uart +{ + UART_HandleTypeDef handle; + struct ns800_uart_config *config; + rt_uint32_t DR_mask; + rt_uint32_t tx_block_timeout; + struct rt_serial_device serial; +}; + + +int rt_hw_uart_init(void); + +#endif /* __DRV_USART_H__ */ + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drv_common.c b/bsp/novosns/ns800/libraries/HAL_Drivers/drv_common.c new file mode 100644 index 00000000000..b47fb793e0c --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drv_common.c @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * + */ + +#include "drv_common.h" +#include + +#ifdef RT_USING_PIN +#include +#endif + +#ifdef RT_USING_SERIAL +#ifdef RT_USING_SERIAL_V2 +#include +#else +#include +#endif /* RT_USING_SERIAL */ +#endif /* RT_USING_SERIAL_V2 */ + +#define DBG_TAG "drv_common" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +/* SysTick configuration */ +void rt_hw_systick_init(void) +{ + /* update the system core clock value */ + SystemCoreClockUpdate(); + /* initialize systick(base time) */ + SysTick_Config(SystemCoreClock / SYSTICK_TIME_UNIT); + /* systick interrupt control */ + Systick_setInterrupt(ENABLE); + + NVIC_SetPriority(SysTick_IRQn, 0x0F); +} + +/** + * This is the timer interrupt service routine. + * + */ +volatile rt_tick_t g_tick_test; + +void SysTick_Handler(void) +{ + rt_interrupt_enter(); + + rt_tick_increase(); + g_tick_test = rt_tick_get(); + + rt_interrupt_leave(); +} + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void _Error_Handler(char *s, int num) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + LOG_E("Error_Handler at file:%s num:%d", s, num); + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint64_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * (reload / (1000000 / RT_TICK_PER_SECOND)); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +#define BSP_SCB_ENABLE_I_CACHE +#define BSP_SCB_ENABLE_D_CACHE +/** + * This function will initial NS800 board. + */ +rt_weak void rt_hw_board_init(void) +{ +#ifdef BSP_SCB_ENABLE_I_CACHE + /* Enable I-Cache---------------------------------------------------------*/ + SCB_EnableICache(); +#endif + +#ifdef BSP_SCB_ENABLE_D_CACHE + /* Enable D-Cache---------------------------------------------------------*/ + SCB_EnableDCache(); +#endif + + /* Initialize device clock and peripherals */ + Device_init(); + /* Disable peripheral register locks */ + Device_unlockPeriphReg(); + /* Interrupt initialization. Disable global interrupts. */ + Interrupt_initModule(); + Interrupt_initVectorTable(); + + rt_hw_systick_init(); + +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + +#ifdef RT_USING_SERIAL + rt_hw_uart_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + /* Set the shell console output device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO) + extern void rt_hw_console_init(void); + rt_hw_console_init(); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* Board underlying hardware initialization */ + rt_components_board_init(); +#endif +} +#ifdef RT_USING_CONSOLE + +void rt_hw_console_output(const char *str) +{ +#if defined(__ICCARM__) + rt_size_t size = rt_strlen(str); + + __write(0, str, size); +#else + rt_size_t i = 0, size = 0; + char a = '\r'; + FILE f; + + size = rt_strlen(str); + + for (i = 0; i < size; i++) + { + if (*(str + i) == '\n') + { + fputc(a, &f); + } + fputc(str[i], &f); + } +#endif +} +#endif + +#ifdef RT_USING_FINSH +char rt_hw_console_getchar(void) +{ + /* Note: the initial value of ch must < 0 */ + int ch = -1; + + if (UART1->STAT.BIT.RDRF) + { + ch = (uint8_t)UART1->DATA.WORDVAL; + } + else + { + rt_thread_mdelay(10); + } + return ch; +} +#endif + diff --git a/bsp/novosns/ns800/libraries/HAL_Drivers/drv_common.h b/bsp/novosns/ns800/libraries/HAL_Drivers/drv_common.h new file mode 100644 index 00000000000..9c56486a6d8 --- /dev/null +++ b/bsp/novosns/ns800/libraries/HAL_Drivers/drv_common.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-7 SummerGift first version + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include +#include +#ifdef RT_USING_DEVICE +#include +#endif /* RT_USING_DEVICE */ + +#ifdef __cplusplus +extern "C" { +#endif + +void _Error_Handler(char *s, int num); + +#ifndef Error_Handler +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#endif + +#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/.config b/bsp/novosns/ns800/ns800rt7p65-nssinepad/.config new file mode 100644 index 00000000000..65ac116100b --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/.config @@ -0,0 +1,1460 @@ +CONFIG_SOC_SERIES_NS800RT7=y +CONFIG_SOC_NS800RT7P6XX=y +CONFIG_BOARD_NS800RT7P65X=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +CONFIG_RT_CAN_USING_CANFD=y +CONFIG_RT_CANMSG_BOX_SZ=16 +CONFIG_RT_CANSND_BOX_NUM=1 +CONFIG_RT_CANSND_MSG_TIMEOUT=100 +CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 +# CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +CONFIG_PKG_USING_CMSIS_CORE=y +CONFIG_PKG_CMSIS_CORE_PATH="/packages/system/CMSIS/CMSIS-Core" +CONFIG_PKG_USING_CMSIS_CORE_LATEST_VERSION=y +CONFIG_PKG_CMSIS_CORE_VER="latest" +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER=y +CONFIG_PKG_NOVOSNS_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/novosns/novosns-series" +CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NOVOSNS_SERIES_DRIVER_VER="latest" +# end of NOVOSNS Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# On-chip Peripheral Drivers +# +CONFIG_BOARD_CLK_CONF=y +CONFIG_SYSCLK_USE_PLL=y +CONFIG_SYSCLK_SOURCE_USE_HXTL=y +CONFIG_PLLCLK_SOURCE_USE_HXTL=y +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_GPIO_PIN_IRQ is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_NS800_UART_TX_TIMEOUT=6000 +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +CONFIG_BSP_USING_ECAP=y +CONFIG_BSP_USING_CAN=y +CONFIG_BSP_USING_CANFD1=y +# end of On-chip Peripheral Drivers diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/.gitignore b/bsp/novosns/ns800/ns800rt7p65-nssinepad/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/Kconfig b/bsp/novosns/ns800/ns800rt7p65-nssinepad/Kconfig new file mode 100644 index 00000000000..d46bd3ba73d --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/Kconfig @@ -0,0 +1,28 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. +LIB_DIR := ../libraries/HAL_Drivers +PKGS_DIR := packages + +config SOC_SERIES_NS800RT7 + bool + default y + +config SOC_NS800RT7P6XX + bool + select SOC_SERIES_NS800RT7 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config BOARD_NS800RT7P65X + bool + depends on SOC_NS800RT7P6XX + default y + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "board/Kconfig" +rsource "$(LIB_DIR)/drivers/Kconfig" diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/README.md b/bsp/novosns/ns800/ns800rt7p65-nssinepad/README.md new file mode 100644 index 00000000000..a108b8e303d --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/README.md @@ -0,0 +1,5 @@ +# NS800RT7P65-NSSinePad BSP Introduction + +[中文](README_zh.md) + +## MCU: NS800RT7P65D @400MHz, 1024KB FLASH, 770KB RAM diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/README_zh.md b/bsp/novosns/ns800/ns800rt7p65-nssinepad/README_zh.md new file mode 100644 index 00000000000..dabb075c8c8 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/README_zh.md @@ -0,0 +1,102 @@ +# NS800RT7P65-NSSinePad 开发板 BSP 说明 + +## 简介 + +本文档为 tyustli 为 NS800RT7P65-NSSinePad 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------- | +| USB 转串口 | 支持 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART1 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +**请注意！！！** + +在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）： + +```bash +pkgs --update +``` + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST_LINK 仿真器下载程序，在通过 ST_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.1 build Mar 5 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 调试串口为串口1 映射说明 + + PD8 ------> USART1_TX + + PD9 ------> USART1_RX + +## 联系人信息 + +维护人: + +- [tyustli](https://github.com/tyustli) diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/SConscript b/bsp/novosns/ns800/ns800rt7p65-nssinepad/SConscript new file mode 100644 index 00000000000..99007d07604 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('env') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/SConstruct b/bsp/novosns/ns800/ns800rt7p65-nssinepad/SConstruct new file mode 100644 index 00000000000..8621cc11a46 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/SConstruct @@ -0,0 +1,73 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "CMSIS-Core-latest"), + os.path.join("packages", "novosns-series-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('env') +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/HAL_Drivers', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/SConscript b/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/SConscript new file mode 100644 index 00000000000..9bb9abae897 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.c b/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.c new file mode 100644 index 00000000000..62ab0863ff1 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/applications/main.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-06 Jiawei.Deng first version + */ + +#include +#include +#include + +/* defined the LED1 pin: GPIO_68 = PC4 */ +#define LED1_PIN PIN_NUM(GPIO_68) + +int main(void) +{ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + + while (1) + { +/* rt_kprintf("\r\n led1_thread_entry running! \r\n"); */ + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(LED1_PIN, PIN_LOW); + rt_thread_mdelay(1000); + } +} + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/Kconfig b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/Kconfig new file mode 100644 index 00000000000..e98f3308b0b --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/Kconfig @@ -0,0 +1,126 @@ +menu "On-chip Peripheral Drivers" + menuconfig BOARD_CLK_CONF + bool "Clock Configuration" + default y + if BOARD_CLK_CONF + config SYSCLK_USE_PLL + bool "Use PLL as system clock source" + default y + + config SYSCLK_SOURCE_USE_HXTL + bool "Use High-Speed Crystal Oscillator (HXTL) as system clock source" + default y + depends on SYSCLK_USE_PLL + + config PLLCLK_SOURCE_USE_HXTL + bool "Use High-Speed Crystal Oscillator (HXTL) as PLL clock source" + default y + depends on SYSCLK_USE_PLL + endif + + menuconfig BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + if BSP_USING_GPIO + config BSP_GPIO_PIN_IRQ + bool "Enable GPIO pin IRQ hooks" + default n + endif + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_NS800_UART_TX_TIMEOUT + int "UART TX timeout" + default 6000 + depends on !RT_USING_SERIAL_V2 + + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_BUFSIZE + int "UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_BUFSIZE + int "UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_BUFSIZE + int "UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_BUFSIZE + int "UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_ECAP + bool "Enable ECAP" + default n + + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CANFD1 + bool "Enable CANFD1" + select RT_CAN_USING_CANFD + default n + + endif + +endmenu diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/SConscript b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/SConscript new file mode 100644 index 00000000000..e9a27c4e21a --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/SConscript @@ -0,0 +1,24 @@ +import os +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Glob('board.c') +pkg_root = os.path.join(cwd, '..', 'packages', 'novosns-series', 'NS800RT7XXX') +path = [ + cwd, + os.path.join(pkg_root, 'Device', 'Inc'), + os.path.join(pkg_root, 'StdDriver', 'Inc'), + os.path.join(pkg_root, 'StdDriver', 'Inc', 'ti'), + os.path.join(cwd, '..', 'libraries', 'HAL_Drivers'), + os.path.join(cwd, '..', 'libraries', 'HAL_Drivers', 'drivers'), +] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/board.c b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/board.c new file mode 100644 index 00000000000..76eb83934c9 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/board.c @@ -0,0 +1,356 @@ +/** + * @file board.c + * @author Haven-X + * @brief Board setup for NS800RTxxx examples. + * + * @note Board Configurations + * Initializes the rest of the modules. + * + *

© Copyright (c) 2025 Novosense Limited. + * All rights reserved.

+ */ +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + + +/******************************************************************************* + * Variables + ******************************************************************************/ + + +/******************************************************************************* + * Functions + ******************************************************************************/ + +/** + * @brief Board Initialization. + * @note Call this function in your application if you wish to do all module + * initialization. + * If you wish to not use some of the initializations, instead of the + * Board_init use the individual Module_inits. + */ +void Board_init (void) +{ + PinMux_init(); + SerialCOM_init(); + LED_init(); + Switch_init(); +} + +/** + * @brief PinMux Initialization. + * @note Call this function in your application if you want all + * PinMux initialization to be done. + */ +void PinMux_init (void) +{ + /* Configure GPIO pins for SCI_COM. */ + GPIO_setPinConfig(GPIO_12_SCIA_TX); + GPIO_setPinConfig(GPIO_13_SCIA_RX); + + /* Configure GPIO pins for LED1 and LED2. */ + GPIO_setPinConfig(GPIO_68_GPIO68); + GPIO_setPinConfig(GPIO_69_GPIO69); + + /* Configure GPIO pins for KEY. */ + GPIO_setPinConfig(GPIO_41_GPIO41); +} + +/** + * @brief Board Serial Communication Interface Initialization. + * @note Call this function in the application to initialize the SCI serial port + * on the board for outputting debugging information. + */ +void SerialCOM_init(void) +{ + /* uart1 rx control */ + GPIO_setAnalogMode(BOARD_SERIALCOM_RX_PIN, GPIO_ANALOG_DISABLED); + GPIO_setPadConfig(BOARD_SERIALCOM_RX_PIN, GPIO_PIN_TYPE_PULLUP); + GPIO_setQualificationMode(BOARD_SERIALCOM_RX_PIN, GPIO_QUAL_SYNC); + GPIO_setQualificationPeriod(BOARD_SERIALCOM_RX_PIN, GPIO_SMP_SYSCLK_DIV_1); + GPIO_setDirectionMode(BOARD_SERIALCOM_RX_PIN, GPIO_DIR_MODE_IN); + /* uart1 tx control */ + GPIO_setAnalogMode(BOARD_SERIALCOM_TX_PIN, GPIO_ANALOG_DISABLED); + GPIO_setPadConfig(BOARD_SERIALCOM_TX_PIN, GPIO_PIN_TYPE_STD); + GPIO_setDriveLevel(BOARD_SERIALCOM_TX_PIN, GPIO_DRV_LOW); + GPIO_setPin(BOARD_SERIALCOM_TX_PIN); + GPIO_setDirectionMode(BOARD_SERIALCOM_TX_PIN, GPIO_DIR_MODE_OUT); + /* Reset uart before configure it */ + UART_resetModule(BOARD_SERIALCOM); + /* Set baudrate */ + UART_setBaud(BOARD_SERIALCOM, BOARD_SERIALCOM_BAUDRATE); + /* Set the number of stop bits */ + UART_setStopBitCount(BOARD_SERIALCOM, UART_ONE_STOP_BIT); + /* Set MSB bit reverses the order of the bits */ + UART_setMSB(BOARD_SERIALCOM, false); + /* Config tx fifo */ + UART_enableTxFifo(BOARD_SERIALCOM); + UART_resetTxFifo(BOARD_SERIALCOM); + UART_setTxFifoWatermark(BOARD_SERIALCOM, UART_FIFO_TX6); + + /* Enable transmitter */ + UART_enableTxModule(BOARD_SERIALCOM); + /* Enable receiver */ + UART_enableRxModule(BOARD_SERIALCOM); +} + +/** + * @brief Board LED Initialization. + * @note Call this function in the application to initialize the LED + * on the board. + */ +void LED_init (void) +{ + /* led1 initialization */ + GPIO_setAnalogMode(BOARD_LED1_PIN, GPIO_ANALOG_DISABLED); + GPIO_setDriveLevel(BOARD_LED1_PIN, GPIO_DRV_MAX); + GPIO_clearPin(BOARD_LED1_PIN); + GPIO_setDirectionMode(BOARD_LED1_PIN, GPIO_DIR_MODE_OUT); + /* led2 initialization */ + GPIO_setAnalogMode(BOARD_LED2_PIN, GPIO_ANALOG_DISABLED); + GPIO_setDriveLevel(BOARD_LED2_PIN, GPIO_DRV_MAX); + GPIO_clearPin(BOARD_LED2_PIN); + GPIO_setDirectionMode(BOARD_LED2_PIN, GPIO_DIR_MODE_OUT); +} + +/** + * @brief Board Switch Initialization. + * @note Call this function in the application to initialize the Switch + * on the board. + */ +void Switch_init (void) +{ + /* KEY initialization */ + GPIO_setAnalogMode(BOARD_KEY_PIN, GPIO_ANALOG_DISABLED); + GPIO_setPadConfig(BOARD_KEY_PIN, GPIO_PIN_TYPE_OD); + GPIO_setQualificationPeriod(BOARD_KEY_PIN, GPIO_SMP_SYSCLK_DIV_510); + GPIO_setQualificationMode(BOARD_KEY_PIN, GPIO_QUAL_6SAMPLE); + GPIO_setDirectionMode(BOARD_KEY_PIN, GPIO_DIR_MODE_IN); +} + +/** + * @brief Function to initialize the device. + * @note Mainly initialize the system clock and enable all peripheral clocks. + */ +void Device_init(void) +{ + System_setClock(); +#ifndef RT_USING_SMP + Device_enableAllPeripheralsInCpu1(); +#endif + Device_enableAllPeripherals(); +} + +/** + * @brief Set up clock source selection, PLL control, and clock dividers. + */ +void System_setClock (void) +{ + /* If CPU1 has been configured, do not repeat the configuration for CPU2. */ + if((MCM->CPUID.WORDVAL & 0x01) == 0x01) + { +#ifdef SYSCLK_USE_PLL +#ifdef SYSCLK_SOURCE_USE_HXTL + RCC_configHxtl(HXTL_CONFIG, RCC_HXTL_NORMAL, RCC_FUN_ON); +#endif + RCC_configPll(PLL_CONFIG, PLL_EXT_CONFIG, RCC_FUN_ON); + + RCC_setClock(RCC_SYSCLKSOURCE_PLL); +#else /* !SYSCLK_USE_PLL */ +#ifdef SYSCLK_SOURCE_USE_HXTL + RCC_configHxtl(HXTL_CONFIG, RCC_HXTL_NORMAL, RCC_FUN_ON); + RCC_setClock(RCC_SYSCLKSOURCE_HXTL); +#endif /* SYSCLK_SOURCE_USE_HXTL */ + +#ifdef SYSCLK_SOURCE_USE_MIRC1 + RCC_setClock(RCC_SYSCLKSOURCE_MIRC1); +#endif /* SYSCLK_SOURCE_USE_MIRC1 */ + +#ifdef SYSCLK_SOURCE_USE_MIRC2 + RCC_setClock(RCC_SYSCLKSOURCE_MIRC2); +#endif /* SYSCLK_SOURCE_USE_MIRC2 */ +#endif /* SYSCLK_USE_PLL */ + RCC_configClockDiv(SYSCLOCK_CFGR_DIV_CONFIG, SYSCLOCK_CFGR2_DIV_CONFIG); + } +} + +#if (DUAL_CORE_ENABLE == 0) +/** + * @brief Enable CPU1 for peripherals. + */ +void Device_enableAllPeripheralsInCpu1 (void) +{ + SYSCON->UNLOCK.WORDVAL = 0x55aa6699; + + WRITE_REG(SYSCON->AHBCPUSEL1.WORDVAL, 0x0); + WRITE_REG(SYSCON->AHBCPUSEL2.WORDVAL, 0x0); + WRITE_REG(SYSCON->APBCPUSEL1.WORDVAL, 0x0); + WRITE_REG(SYSCON->APBCPUSEL2.WORDVAL, 0x0); + WRITE_REG(SYSCON->APBCPUSEL3.WORDVAL, 0x0); + WRITE_REG(SYSCON->APBCPUSEL5.WORDVAL, 0x0); + WRITE_REG(SYSCON->APBCPUSEL6.WORDVAL, 0x0); + WRITE_REG(SYSCON->APBCPUSEL8.WORDVAL, 0x0); + + SET_BIT(SYSCON->AHBCPUSELEN1.WORDVAL, 0x00000330); + SET_BIT(SYSCON->AHBCPUSELEN2.WORDVAL, 0x00007303); + SET_BIT(SYSCON->APBCPUSELEN1.WORDVAL, 0xFF7FFFFF); + SET_BIT(SYSCON->APBCPUSELEN2.WORDVAL, 0x07FF800F); + SET_BIT(SYSCON->APBCPUSELEN3.WORDVAL, 0x00000300); + SET_BIT(SYSCON->APBCPUSELEN5.WORDVAL, 0x01070F0F); + SET_BIT(SYSCON->APBCPUSELEN6.WORDVAL, 0x03003F03); + SET_BIT(SYSCON->APBCPUSELEN8.WORDVAL, 0x03FF0010); + + SYSCON->UNLOCK.WORDVAL = 0x55aa6698; +} +#endif + +/** + * @brief Enable clocks for all peripherals. + */ +void Device_enableAllPeripherals (void) +{ + RCC_unlockRccRegister(); + + RCC_enableAhb1PeripheralClock(RCC_HCLKEN1_UPPEN_M | RCC_HCLKEN1_EMIFEN_M | RCC_HCLKEN1_SEMAEN_M | + RCC_HCLKEN1_MUEN_M | RCC_HCLKEN1_GPIOHEN_M | RCC_HCLKEN1_GPIOGEN_M | + RCC_HCLKEN1_GPIOFEN_M | RCC_HCLKEN1_GPIOEEN_M | RCC_HCLKEN1_GPIODEN_M | + RCC_HCLKEN1_GPIOCEN_M | RCC_HCLKEN1_GPIOBEN_M | RCC_HCLKEN1_GPIOAEN_M | + RCC_HCLKEN1_EMATHEN_M | RCC_HCLKEN1_QSPIEN_M | RCC_HCLKEN1_CPUXMMATHEN_M | + RCC_HCLKEN1_EDMA2EN_M | RCC_HCLKEN1_EDMA1EN_M | RCC_HCLKEN1_DMAMUX2EN_M | + RCC_HCLKEN1_DMAMUX1EN_M | RCC_HCLKEN1_SMPUEN_M | RCC_HCLKEN1_FMUEN_M); + + RCC_enableAhb2PeripheralClock(RCC_HCLKEN2_CANFD2EN_M | RCC_HCLKEN2_CANFD1EN_M | RCC_HCLKEN2_CAN1EN_M | + RCC_HCLKEN2_LIN2EN_M | RCC_HCLKEN2_LIN1EN_M | RCC_HCLKEN2_BGCRC2EN_M | + RCC_HCLKEN2_BGCRC1EN_M | RCC_HCLKEN2_CRC2EN_M | RCC_HCLKEN2_CRC1EN_M | + RCC_HCLKEN2_AESHASHEN_M | RCC_HCLKEN2_TRNGEN_M); + + RCC_enableApb1PeripheralClock(RCC_PCLKEN1_EPWM18EN_M | RCC_PCLKEN1_EPWM17EN_M | RCC_PCLKEN1_EQEP6EN_M | + RCC_PCLKEN1_EQEP5EN_M | RCC_PCLKEN1_EQEP4EN_M | RCC_PCLKEN1_EQEP3EN_M | + RCC_PCLKEN1_EQEP2EN_M | RCC_PCLKEN1_EQEP1EN_M | RCC_PCLKEN1_ECAP7EN_M | + RCC_PCLKEN1_ECAP6EN_M | RCC_PCLKEN1_ECAP5EN_M | RCC_PCLKEN1_ECAP4EN_M | + RCC_PCLKEN1_ECAP3EN_M | RCC_PCLKEN1_ECAP2EN_M | RCC_PCLKEN1_ECAP1EN_M | + RCC_PCLKEN1_EPWM16EN_M | RCC_PCLKEN1_EPWM15EN_M | RCC_PCLKEN1_EPWM14EN_M | + RCC_PCLKEN1_EPWM13EN_M | RCC_PCLKEN1_EPWM12EN_M | RCC_PCLKEN1_EPWM11EN_M | + RCC_PCLKEN1_EPWM10EN_M | RCC_PCLKEN1_EPWM9EN_M | RCC_PCLKEN1_EPWM8EN_M | + RCC_PCLKEN1_EPWM7EN_M | RCC_PCLKEN1_EPWM6EN_M | RCC_PCLKEN1_EPWM5EN_M | + RCC_PCLKEN1_EPWM4EN_M | RCC_PCLKEN1_EPWM3EN_M | RCC_PCLKEN1_EPWM2EN_M | + RCC_PCLKEN1_EPWM1EN_M); + + RCC_enableApb2PeripheralClock(RCC_PCLKEN2_CMPSS11EN_M | RCC_PCLKEN2_CMPSS10EN_M | RCC_PCLKEN2_CMPSS9EN_M | + RCC_PCLKEN2_SDFM1EN_M | RCC_PCLKEN2_CMPSS8EN_M | RCC_PCLKEN2_CMPSS7EN_M | + RCC_PCLKEN2_CMPSS6EN_M | RCC_PCLKEN2_CMPSS5EN_M | RCC_PCLKEN2_CMPSS4EN_M | + RCC_PCLKEN2_CMPSS3EN_M | RCC_PCLKEN2_CMPSS2EN_M | RCC_PCLKEN2_CMPSS1EN_M | + RCC_PCLKEN2_XBAREN_M | RCC_PCLKEN2_ADCDEN_M | RCC_PCLKEN2_ADCCEN_M | + RCC_PCLKEN2_ADCBEN_M | RCC_PCLKEN2_ADCAEN_M | RCC_PCLKEN2_SDFM4EN_M | + RCC_PCLKEN2_SDFM3EN_M | RCC_PCLKEN2_SDFM2EN_M); + + RCC_enableApb3PeripheralClock(RCC_PCLKEN3_ANALOGSS_M | RCC_PCLKEN3_DAC3EN_M | RCC_PCLKEN3_DAC1EN_M); + + RCC_enableApb5PeripheralClock(RCC_PCLKEN5_DCC1EN_M | RCC_PCLKEN5_CPUXWWDGEN_M | RCC_PCLKEN5_EPGEN_M | + RCC_PCLKEN5_PMBUSEN_M | RCC_PCLKEN5_I2C2EN_M | RCC_PCLKEN5_I2C1EN_M | + RCC_PCLKEN5_SPI4EN_M | RCC_PCLKEN5_SPI3EN_M | RCC_PCLKEN5_SPI2EN_M | + RCC_PCLKEN5_SPI1EN_M | RCC_PCLKEN5_UART4EN_M | RCC_PCLKEN5_UART3EN_M | + RCC_PCLKEN5_UART2EN_M | RCC_PCLKEN5_UART1EN_M); + + RCC_enableApb6PeripheralClock(RCC_PCLKEN6_DCC3EN_M | RCC_PCLKEN6_DCC2EN_M | RCC_PCLKEN6_BTIM2EN_M | + RCC_PCLKEN6_BTIM1EN_M | RCC_PCLKEN6_CPUXSTIM3EN_M | RCC_PCLKEN6_CPUXSTIM2EN_M | + RCC_PCLKEN6_CPUXSTIM1EN_M | RCC_PCLKEN6_CLB6EN_M | RCC_PCLKEN6_CLB5EN_M | + RCC_PCLKEN6_CLB4EN_M | RCC_PCLKEN6_CLB3EN_M | RCC_PCLKEN6_CLB2EN_M | + RCC_PCLKEN6_CLB1EN_M | RCC_PCLKEN6_TIM2EN_M | RCC_PCLKEN6_TIM1EN_M); + + RCC_enableApb8PeripheralClock(RCC_PCLKEN8_ADCAGG2EN_M | RCC_PCLKEN8_ADCAGG1EN_M | RCC_PCLKEN8_ADCCHK8EN_M | + RCC_PCLKEN8_ADCCHK7EN_M | RCC_PCLKEN8_ADCCHK6EN_M | RCC_PCLKEN8_ADCCHK5EN_M | + RCC_PCLKEN8_ADCCHK4EN_M | RCC_PCLKEN8_ADCCHK3EN_M | RCC_PCLKEN8_ADCCHK2EN_M | + RCC_PCLKEN8_ADCCHK1EN_M | RCC_PCLKEN8_AWKEN_M | RCC_PCLKEN8_LPTIMEN_M | + RCC_PCLKEN8_IWDG2EN_M | RCC_PCLKEN8_CPUXIWDG1EN_M | RCC_PCLKEN8_PWREN_M); + + RCC_lockRccRegister(); +} + +/** + * @brief Unlock all peripheral registers. + */ +void Device_unlockPeriphReg (void) +{ + /* Enables register writing function about FMU/ECAP/EPWM/XBAR/CMPSS/SDFM/DAC/ANASS/ADC/PGA/GPIO */ + SYSCON->SYSEALLOW1.WORDVAL = 0x7FFFFFFF; + SYSCON->SYSEALLOW2.WORDVAL = 0x7FFFFFFF; + SYSCON->SYSEALLOW3.WORDVAL = 0x00003FFF; +} + +/** + * @brief Disable clocks for all peripherals. + */ +void Device_disableAllPeripherals (void) +{ + RCC_unlockRccRegister(); + + RCC_disableAhb1PeripheralClock(RCC_HCLKEN1_UPPEN_M | RCC_HCLKEN1_EMIFEN_M | RCC_HCLKEN1_SEMAEN_M | + RCC_HCLKEN1_MUEN_M | RCC_HCLKEN1_GPIOHEN_M | RCC_HCLKEN1_GPIOGEN_M | + RCC_HCLKEN1_GPIOFEN_M | RCC_HCLKEN1_GPIOEEN_M | RCC_HCLKEN1_GPIODEN_M | + RCC_HCLKEN1_GPIOCEN_M | RCC_HCLKEN1_GPIOBEN_M | RCC_HCLKEN1_GPIOAEN_M | + RCC_HCLKEN1_EMATHEN_M | RCC_HCLKEN1_QSPIEN_M | RCC_HCLKEN1_CPUXMMATHEN_M | + RCC_HCLKEN1_EDMA2EN_M | RCC_HCLKEN1_EDMA1EN_M | RCC_HCLKEN1_DMAMUX2EN_M | + RCC_HCLKEN1_DMAMUX1EN_M | RCC_HCLKEN1_SMPUEN_M | RCC_HCLKEN1_FMUEN_M); + + RCC_disableAhb2PeripheralClock(RCC_HCLKEN2_CANFD2EN_M | RCC_HCLKEN2_CANFD1EN_M | RCC_HCLKEN2_CAN1EN_M | + RCC_HCLKEN2_LIN2EN_M | RCC_HCLKEN2_LIN1EN_M | RCC_HCLKEN2_BGCRC2EN_M | + RCC_HCLKEN2_BGCRC1EN_M | RCC_HCLKEN2_CRC2EN_M | RCC_HCLKEN2_CRC1EN_M | + RCC_HCLKEN2_AESHASHEN_M |RCC_HCLKEN2_TRNGEN_M); + + RCC_disableApb1PeripheralClock(RCC_PCLKEN1_EPWM18EN_M | RCC_PCLKEN1_EPWM17EN_M | RCC_PCLKEN1_EQEP6EN_M | + RCC_PCLKEN1_EQEP5EN_M | RCC_PCLKEN1_EQEP4EN_M | RCC_PCLKEN1_EQEP3EN_M | + RCC_PCLKEN1_EQEP2EN_M | RCC_PCLKEN1_EQEP1EN_M | RCC_PCLKEN1_ECAP7EN_M | + RCC_PCLKEN1_ECAP6EN_M | RCC_PCLKEN1_ECAP5EN_M | RCC_PCLKEN1_ECAP4EN_M | + RCC_PCLKEN1_ECAP3EN_M | RCC_PCLKEN1_ECAP2EN_M | RCC_PCLKEN1_ECAP1EN_M | + RCC_PCLKEN1_EPWM16EN_M | RCC_PCLKEN1_EPWM15EN_M | RCC_PCLKEN1_EPWM14EN_M | + RCC_PCLKEN1_EPWM13EN_M | RCC_PCLKEN1_EPWM12EN_M | RCC_PCLKEN1_EPWM11EN_M | + RCC_PCLKEN1_EPWM10EN_M | RCC_PCLKEN1_EPWM9EN_M | RCC_PCLKEN1_EPWM8EN_M | + RCC_PCLKEN1_EPWM7EN_M | RCC_PCLKEN1_EPWM6EN_M | RCC_PCLKEN1_EPWM5EN_M | + RCC_PCLKEN1_EPWM4EN_M | RCC_PCLKEN1_EPWM3EN_M | RCC_PCLKEN1_EPWM2EN_M | + RCC_PCLKEN1_EPWM1EN_M); + + RCC_disableApb2PeripheralClock(RCC_PCLKEN2_CMPSS11EN_M | RCC_PCLKEN2_CMPSS10EN_M | RCC_PCLKEN2_CMPSS9EN_M | + RCC_PCLKEN2_SDFM1EN_M | RCC_PCLKEN2_CMPSS8EN_M | RCC_PCLKEN2_CMPSS7EN_M | + RCC_PCLKEN2_CMPSS6EN_M | RCC_PCLKEN2_CMPSS5EN_M | RCC_PCLKEN2_CMPSS4EN_M | + RCC_PCLKEN2_CMPSS3EN_M | RCC_PCLKEN2_CMPSS2EN_M | RCC_PCLKEN2_CMPSS1EN_M | + RCC_PCLKEN2_XBAREN_M | RCC_PCLKEN2_ADCDEN_M | RCC_PCLKEN2_ADCCEN_M | + RCC_PCLKEN2_ADCBEN_M | RCC_PCLKEN2_ADCAEN_M | RCC_PCLKEN2_SDFM4EN_M | + RCC_PCLKEN2_SDFM3EN_M | RCC_PCLKEN2_SDFM2EN_M); + + RCC_disableApb3PeripheralClock(RCC_PCLKEN3_ANALOGSS_M | RCC_PCLKEN3_DAC3EN_M | RCC_PCLKEN3_DAC1EN_M); + + RCC_disableApb5PeripheralClock(RCC_PCLKEN5_DCC1EN_M | RCC_PCLKEN5_CPUXWWDGEN_M | RCC_PCLKEN5_EPGEN_M | + RCC_PCLKEN5_PMBUSEN_M | RCC_PCLKEN5_I2C2EN_M | RCC_PCLKEN5_I2C1EN_M | + RCC_PCLKEN5_SPI4EN_M | RCC_PCLKEN5_SPI3EN_M | RCC_PCLKEN5_SPI2EN_M | + RCC_PCLKEN5_SPI1EN_M | RCC_PCLKEN5_UART4EN_M |RCC_PCLKEN5_UART3EN_M | + RCC_PCLKEN5_UART2EN_M | RCC_PCLKEN5_UART1EN_M); + + RCC_disableApb6PeripheralClock(RCC_PCLKEN6_DCC3EN_M | RCC_PCLKEN6_DCC2EN_M | RCC_PCLKEN6_BTIM2EN_M | + RCC_PCLKEN6_BTIM1EN_M | RCC_PCLKEN6_CPUXSTIM3EN_M | RCC_PCLKEN6_CPUXSTIM2EN_M | + RCC_PCLKEN6_CPUXSTIM1EN_M | RCC_PCLKEN6_CLB6EN_M | RCC_PCLKEN6_CLB5EN_M | + RCC_PCLKEN6_CLB4EN_M | RCC_PCLKEN6_CLB3EN_M | RCC_PCLKEN6_CLB2EN_M | + RCC_PCLKEN6_CLB1EN_M | RCC_PCLKEN6_TIM2EN_M | RCC_PCLKEN6_TIM1EN_M); + + RCC_disableApb8PeripheralClock(RCC_PCLKEN8_ADCAGG2EN_M | RCC_PCLKEN8_ADCAGG1EN_M | RCC_PCLKEN8_ADCCHK8EN_M | + RCC_PCLKEN8_ADCCHK7EN_M | RCC_PCLKEN8_ADCCHK6EN_M | RCC_PCLKEN8_ADCCHK5EN_M | + RCC_PCLKEN8_ADCCHK4EN_M | RCC_PCLKEN8_ADCCHK3EN_M | RCC_PCLKEN8_ADCCHK2EN_M | + RCC_PCLKEN8_ADCCHK1EN_M | RCC_PCLKEN8_AWKEN_M | RCC_PCLKEN8_LPTIMEN_M | + RCC_PCLKEN8_IWDG2EN_M | RCC_PCLKEN8_CPUXIWDG1EN_M | RCC_PCLKEN8_PWREN_M); + RCC_lockRccRegister(); +} + +/** + * @brief Lock all peripheral registers. + */ +void Device_lockPeriphReg (void) +{ + /* Enables register writing function about FMU/ECAP/EPWM/XBAR/CMPSS/SDFM/DAC/ANASS/ADC/PGA/GPIO */ + SYSCON->SYSEALLOW1.WORDVAL = 0x00000000; + SYSCON->SYSEALLOW2.WORDVAL = 0x00000000; + SYSCON->SYSEALLOW3.WORDVAL = 0x00000000; +} + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/board.h b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/board.h new file mode 100644 index 00000000000..0a69dcbe5f8 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/board.h @@ -0,0 +1,288 @@ +/** + * @file board.h + * @author Haven-X + * @brief Header file of board.c + * + *

© Copyright (c) 2025 Novosense Limited. + * All rights reserved.

+ */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "NS800RTxxxx.h" +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define NS800_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define NS800_FLASH_SIZE (512 * 1024) +#define NS800_FLASH_END_ADDRESS ((uint32_t)(NS800_FLASH_START_ADRESS + NS800_FLASH_SIZE)) + +#define NS800RT7P65_SRAM_SIZE (256) + +extern int Image$$RW_RT_HEAD$$Limit; +#define HEAP_BEGIN (&Image$$RW_RT_HEAD$$Limit) +#define HEAP_END ((uint32_t)&Image$$RW_RT_HEAD$$Limit + 0x4000) + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** @defgroup BOARD_LEDx_PIN Board LEDx PIN + * @{ + * @brief Defines configuration macros for board ledx pin. + */ +#define BOARD_LED1_PIN GPIO_68 /* reserve */ +#define BOARD_LED2_PIN GPIO_69 /* reserve */ + +/** + * @} + */ + +/** @defgroup BOARD_SWITCHx_PIN Board SWITCHx PIN + * @{ + * @brief Defines configuration macros for board switchx pin. + */ +#define BOARD_KEY_PIN GPIO_41 + + +/** + * @} + */ + +/** @defgroup SERIAL_COM_PIN Serial Com port Pins + * @{ + * @brief Defines configuration macros for serial com port pin. + */ +#define BOARD_SERIALCOM_TX_PIN GPIO_12 +#define BOARD_SERIALCOM_RX_PIN GPIO_13 + +/** + * @} + */ + +#define BOARD_SERIALCOM_BAUDRATE (115200UL) +#define BOARD_SERIALCOM UART1 + + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** @defgroup HXTL_CONFIG High-Speed Crystal Oscillator (HXTL) Configuration + * @{ + * @brief Defines configuration macros for the High-Speed Crystal Oscillator (HXTL). + */ +#ifdef SYSCLK_SOURCE_USE_HXTL +#define HXTL_CONFIG ((RCC_HXTL_FILT_ENABLE << 15) | \ + (RCC_HXTL_FEEDBACK_RES_0_8M << 13) | \ + (RCC_HXTL_FEEDBACK_ENABLE << 12) | \ + (RCC_HXTL_STARTUP_16384 << 8) | \ + RCC_HXTL_24M_AGC_DISABLE) + +#else +#define HXTL_CONFIG 0U +#endif + +/** + * @} + */ + +/** @defgroup PLL_CONFIG PLL Configuration + * @{ + * @brief Defines configuration macros for the Phase-Locked Loop (PLL). + * @note Will configure the clock as follows: + * PLL_SYSCLK = PLLSOURCE * PLLM / ( (PLLN+1) * (2 * (PLLP+1))) + * + * PLLSOURCE optional: \b HXTL_FREQ_VALUE + * \b MIRC1_FREQ_VALUE + * \b MIRC2_FREQ_VALUE + * Example: + * if PLLSOURCE = HXTL_FREQ_VALUE = 20Mhz, PLLM_40, PLLN_DIV1, PLLP_DIV2, + * + * PLL_SYSCLK = 20Mhz * 40 / ( (0+1) * (2 * (0+1)) ) = 400MHz + */ +#ifdef SYSCLK_USE_PLL +#ifdef PLLCLK_SOURCE_USE_HXTL +#define PLL_CONFIG ((RCC_PLLM_40 << 8) | \ + (RCC_PLLN_DIV1 << 4) | \ + (RCC_PLLP_DIV2 << 17) | \ + (RCC_PLLSOURCE_HXTL)) +#else /* ndef PLLCLK_SOURCE_USE_HXTL */ +#ifdef PLLCLK_SOURCE_USE_MIRC2 +#define PLL_CONFIG ((RCC_PLLM_80 << 8) | \ + (RCC_PLLN_DIV1 << 4) | \ + (RCC_PLLP_DIV2 << 17) | \ + (RCC_PLLSOURCE_MIRC2)) +#else /* ndef PLLCLK_SOURCE_USE_MIRC2 */ +#define PLL_CONFIG ((RCC_PLLM_52 << 8) | \ + (RCC_PLLN_DIV1 << 4) | \ + (RCC_PLLP_DIV2 << 17) | \ + (RCC_PLLSOURCE_MIRC1)) +#endif /* PLLCLK_SOURCE_USE_MIRC2 */ +#endif /* PLLCLK_SOURCE_USE_HXTL */ +#else /* ndef SYSCLK_USE_PLL */ +#define PLL_CONFIG 0U +#endif /* SYSCLK_USE_PLL */ + +/** + * @} + */ + + + +/** @defgroup PLL_EXT_CONFIG PLL Extended Configuration + * @{ + * @brief Defines configuration macros for the Phase-Locked Loop (PLL) extended settings. + */ +#ifdef SYSCLK_USE_PLL +#define PLL_EXT_CONFIG ((RCC_PLLQ_DIV8 << 27) | \ + (RCC_PLLR_DIV8 << 22) | \ + (RCC_PLL_FORCELK_DISABLE << 18) | \ + (RCC_PLL_LKDT_SEL_0 << 16) | \ + (RCC_PLL_LOOP_FILTER_CAP_84PF << 8) | \ + (RCC_PLL_CHARGE_PUMP_CURRENT_4UA << 4) | \ + (RCC_PLL_LOOP_FILTER_RES_10K << 2) | \ + (RCC_PLL_VCO_400_800M)) +#else +#define PLL_EXT_CONFIG 0U +#endif + +/** + * @} + */ + + /** @defgroup SYS_CLOCK_DIV_CONFIG Systerm Clock Division Configuration + * @{ + * @brief Defines macros for configuring system clock division settings. + */ +#ifdef SYSCLK_USE_PLL +#define SYSCLOCK_CFGR_DIV_CONFIG ((RCC_APB5_HCLK_DIV4 << 28) | \ + (RCC_APB2_4_HCLK_DIV1 << 24) | \ + (RCC_APB1_3_HCLK_DIV1 << 20) | \ + (RCC_HCLKSOURCE_CPUCLK_2 << 12) | \ + (RCC_SYSCLK_DIV1 << 8)) +#define SYSCLOCK_CFGR2_DIV_CONFIG ((RCC_FLASH_DIV_2 << 0) | \ + (RCC_TRACE_DIV_2 << 4) | \ + (RCC_EMIF_DIV_2 << 8) | \ + (RCC_EPWM_DIV_1 << 12)) + +#else +#define SYSCLOCK_CFGR_DIV_CONFIG ((RCC_APB5_HCLK_DIV1 << 28) | \ + (RCC_APB2_4_HCLK_DIV1 << 24) | \ + (RCC_APB1_3_HCLK_DIV1 << 20) | \ + (RCC_HCLKSOURCE_CPUCLK << 12) | \ + (RCC_SYSCLK_DIV1 << 8)) +#define SYSCLOCK_CFGR2_DIV_CONFIG ((RCC_FLASH_DIV_1 << 0) | \ + (RCC_TRACE_DIV_1 << 4) | \ + (RCC_EMIF_DIV_1 << 8) | \ + (RCC_EPWM_DIV_1 << 12)) +#endif + + +/** + * @} + */ + +#define SYSTICK_TIME_UNIT (1000UL) /*!< Uint: 1M */ + + + + +/******************************************************************************* + * Functions + ******************************************************************************/ + +/** + * \brief Function to initialize the device. + * \note Mainly initialize the system clock and enable all peripheral clocks. + */ +void Device_init(void); + +/** + * \brief Set up clock source selection, PLL control, and clock dividers. + */ +void System_setClock(void); + +/** + * \brief Enable clocks for all peripherals. + */ +void Device_enableAllPeripherals(void); + +/** + * \brief Unlock all peripheral registers. + */ +void Device_unlockPeriphReg (void); + +/** + * \brief Disable clocks for all peripherals. + */ +void Device_disableAllPeripherals (void); + +/** + *\@brief Lock all peripheral registers. + */ +void Device_lockPeriphReg (void); + +/** + *\@brief All peripherals are hung on the CUP1 + */ +void Device_enableAllPeripheralsInCpu1 (void); + + +/** + * \brief Board Initialization. + * \note Call this function in your application if you wish to do all module + * initialization. + * If you wish to not use some of the initializations, instead of the + * Board_init use the individual Module_inits. + */ +void Board_init (void); + +/** + * \brief PinMux Initialization. + * \note Call this function in your application if you want all + * PinMux initialization to be done. + */ +void PinMux_init (void); + +/** + * \brief Board Serial Communication Interface Initialization. + * \note Call this function in the application to initialize the SCI serial port + * on the board for outputting debugging information. + */ +void SerialCOM_init(void); + +/** + * \brief Board LED Initialization. + * \note Call this function in the application to initialize the LED + * on the board. + */ +void LED_init (void); + +/** + * \brief Board Switch Initialization. + * \note Call this function in the application to initialize the Switch + * on the board. + */ +void Switch_init (void); + + +#ifdef __cplusplus +} +#endif + + +#endif /* __BOARD_H__ */ + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.icf b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.icf new file mode 100644 index 00000000000..870bdb144ca --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.icf @@ -0,0 +1,56 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000400; +define symbol __ICFEDIT_region_RAM_end__ = 0x20011FFF; +define symbol __ICFEDIT_region_VTRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_VTRAM_end__ = 0x200003FF; +define symbol __ICFEDIT_region_HEAP_start__ = 0x20012000; +define symbol __ICFEDIT_region_HEAP_end__ = 0x20015FFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x20016000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_SRAM1_start__ = 0x20100000; +define symbol __ICFEDIT_region_SRAM1_end__ = 0x2011FFFF; +define symbol __ICFEDIT_region_SRAM2_start__ = 0x20120000; +define symbol __ICFEDIT_region_SRAM2_end__ = 0x2013FFFF; +define symbol __ICFEDIT_region_BKPSRAM_start__ = 0x400B7000; +define symbol __ICFEDIT_region_BKPSRAM_end__ = 0x400B7FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; + +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region VTRAM_region = mem:[from __ICFEDIT_region_VTRAM_start__ to __ICFEDIT_region_VTRAM_end__]; +define region HEAP_region = mem:[from __ICFEDIT_region_HEAP_start__ to __ICFEDIT_region_HEAP_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; +define region SRAM1_region = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__]; +define region SRAM2_region = mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__]; +define region BKPSRAM_region = mem:[from __ICFEDIT_region_BKPSRAM_start__ to __ICFEDIT_region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit, section .bss.bkupsram }; + +define exported symbol Image$$RW_RT_HEAD$$Base = __ICFEDIT_region_HEAP_start__; +define exported symbol Image$$RW_RT_HEAD$$Limit = __ICFEDIT_region_HEAP_start__; +define exported symbol Image$$RW_RT_HEAD$$End = __ICFEDIT_region_HEAP_end__ + 1; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK }; +place in VTRAM_region { section .vt_dtcm }; +place in RAM2_region { section .dtcm_ext }; +place in SRAM1_region { section .sram1 }; +place in SRAM2_region { section .sram2 }; +place in BKPSRAM_region { section .bss.bkupsram }; diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.lds b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.lds new file mode 100644 index 00000000000..b2d84435ec5 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.lds @@ -0,0 +1,207 @@ +/* + * GNU ld linker script for NS800RT7P65 (Cortex-M7) + * + * Memory layout derived from the existing MDK scatter file: + * FLASH 0x08000000 512K + * VT_DTCM 0x20000000 1K + * DTCM 0x20000400 71K (general RW/ZI/stack region) + * RT_HEAP 0x20012000 16K (reserved for rt_system_heap_init) + * DTCM_EXT 0x20016000 40K (extra named sections only) + * SRAM1 0x20100000 128K + * SRAM2 0x20120000 128K + * BKPSRAM 0x400B7000 4K + */ + +ENTRY(Reset_Handler) + +_system_stack_size = 0x1000; + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + VT_DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x400 + DTCM (rwx) : ORIGIN = 0x20000400, LENGTH = 0x11C00 + RT_HEAP (rwx) : ORIGIN = 0x20012000, LENGTH = 0x4000 + DTCM_EXT (rwx) : ORIGIN = 0x20016000, LENGTH = 0xA000 + SRAM1 (rwx) : ORIGIN = 0x20100000, LENGTH = 0x20000 + SRAM2 (rwx) : ORIGIN = 0x20120000, LENGTH = 0x20000 + BKPSRAM (rwx) : ORIGIN = 0x400B7000, LENGTH = 0x1000 +} + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) + + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + *(.itcm) + *(.itcm*) + + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + _etext = .; + } > FLASH = 0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + _sidata = .; + } > FLASH + __exidx_end = .; + + .data : AT (_sidata) + { + . = ALIGN(4); + _sdata = .; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + *(.dtcm) + *(.dtcm*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + _edata = .; + } > DTCM + + .stack : + { + . = ALIGN(8); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(8); + _estack = .; + } > DTCM + + __bss_start = .; + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; + + *(.bss.init) + } > DTCM + __bss_end = .; + + .vt_dtcm (NOLOAD) : + { + . = ALIGN(4); + *(.vt_dtcm) + *(.vt_dtcm*) + . = ALIGN(4); + } > VT_DTCM + + .sram1 (NOLOAD) : + { + . = ALIGN(4); + *(.sram1) + *(.sram1*) + . = ALIGN(4); + } > SRAM1 + + .sram2 (NOLOAD) : + { + . = ALIGN(4); + *(.sram2) + *(.sram2*) + . = ALIGN(4); + } > SRAM2 + + .bkupsram (NOLOAD) : + { + . = ALIGN(4); + *(.bss.bkupsram) + *(.bss.bkupsram*) + . = ALIGN(4); + } > BKPSRAM + + .dtcm_ext (NOLOAD) : + { + . = ALIGN(4); + *(.dtcm_ext) + *(.dtcm_ext*) + . = ALIGN(4); + } > DTCM_EXT + + .rt_heap (NOLOAD) : + { + . = ALIGN(8); + PROVIDE(Image$$RW_RT_HEAD$$Base = .); + PROVIDE(Image$$RW_RT_HEAD$$Limit = .); + PROVIDE(__rt_heap_start = .); + . = . + LENGTH(RT_HEAP); + . = ALIGN(8); + PROVIDE(Image$$RW_RT_HEAD$$End = .); + PROVIDE(__rt_heap_end = .); + } > RT_HEAP + + _end = .; + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.sct b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.sct new file mode 100644 index 00000000000..e6366728be8 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/board/linker_scripts/link.sct @@ -0,0 +1,42 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_ITCM 0x00000000 0x00020000 { ; 128K ITCM -> code in sram + .ANY (.itcm) + } + + RW_VT_DTCM 0x20000000 0x00000400 { ; 1K VT_DTCM -> Vector Table + * (.vt_dtcm) + } + + RW_DTCM 0x20000400 0x0001FC00 { ; 127K DTCM -> fast sram + .ANY (.dtcm, +RW +ZI) +; startup_*.o(STACK) +; startup_*.o(HEAP) + } + + RW_RT_HEAD 0x20012000 EMPTY 0x4000 { + + } + +; RW_SRAM1 0x20100000 0x00020000 { ; sram with ECC +; * (.sram1) +; } + +; RW_SRAM2 0x20120000 0x00020000 { ; sram with ECC +; * (.sram2) +; } + +; RW_SRAMB 0x400B7000 UNINIT 0x00001000 { ; sram with backup +; * (.bss.bkupsram) +; } +} \ No newline at end of file diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.ewp b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.ewp new file mode 100644 index 00000000000..ca465a67483 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.ewp @@ -0,0 +1,2546 @@ + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications/main.c + + + $PROJ_DIR$\applications/rt_can.c + + + $PROJ_DIR$\applications/rt_ecap.c + + + + CMSIS-Core + + + CPU + + $PROJ_DIR$\../../../../libcpu/arm/common/div0.c + + + $PROJ_DIR$\../../../../libcpu/arm/common/showmem.c + + + $PROJ_DIR$\../../../../libcpu/arm/cortex-m7/context_iar.S + + + $PROJ_DIR$\../../../../libcpu/arm/cortex-m7/cpu_cache.c + + + $PROJ_DIR$\../../../../libcpu/arm/cortex-m7/cpuport.c + + + + Device + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/Device/Src/system_NS800RT7xxx.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/Device/Src/iar/startup_NS800RT7xxx.s + + + + DeviceDrivers + + $PROJ_DIR$\../../../../components/drivers/can/dev_can.c + + + $PROJ_DIR$\../../../../components/drivers/core/device.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/completion_comm.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/completion_up.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/condvar.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/dataqueue.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/pipe.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/ringblk_buf.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/ringbuffer.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/waitqueue.c + + + $PROJ_DIR$\../../../../components/drivers/ipc/workqueue.c + + + $PROJ_DIR$\../../../../components/drivers/pin/dev_pin.c + + + $PROJ_DIR$\../../../../components/drivers/serial/dev_serial.c + + + + Drivers + + $PROJ_DIR$\board/board.c + + + + Finsh + + $PROJ_DIR$\../../../../components/finsh/shell.c + + + $PROJ_DIR$\../../../../components/finsh/msh.c + + + $PROJ_DIR$\../../../../components/finsh/msh_parse.c + + + $PROJ_DIR$\../../../../components/finsh/cmd.c + + + + HAL_Driver + + $PROJ_DIR$\../libraries/HAL_Drivers/drv_common.c + + + + HAL_Drivers + + $PROJ_DIR$\../libraries/HAL_Drivers/drivers/drv_gpio.c + + + $PROJ_DIR$\../libraries/HAL_Drivers/drivers/drv_uart.c + + + $PROJ_DIR$\../libraries/HAL_Drivers/drivers/drv_can.c + + + $PROJ_DIR$\../libraries/HAL_Drivers/drivers/drv_ecap.c + + + + Kernel + + $PROJ_DIR$\../../../../src/clock.c + + + $PROJ_DIR$\../../../../src/components.c + + + $PROJ_DIR$\../../../../src/cpu_up.c + + + $PROJ_DIR$\../../../../src/defunct.c + + + $PROJ_DIR$\../../../../src/idle.c + + + $PROJ_DIR$\../../../../src/ipc.c + + + $PROJ_DIR$\../../../../src/irq.c + + + $PROJ_DIR$\../../../../src/kservice.c + + + $PROJ_DIR$\../../../../src/mem.c + + + $PROJ_DIR$\../../../../src/mempool.c + + + $PROJ_DIR$\../../../../src/object.c + + + $PROJ_DIR$\../../../../src/scheduler_comm.c + + + $PROJ_DIR$\../../../../src/scheduler_up.c + + + $PROJ_DIR$\../../../../src/thread.c + + + $PROJ_DIR$\../../../../src/timer.c + + + + Libc + + $PROJ_DIR$\../../../../components/libc/compilers/common/cctype.c + + + $PROJ_DIR$\../../../../components/libc/compilers/common/cstdlib.c + + + $PROJ_DIR$\../../../../components/libc/compilers/common/cstring.c + + + $PROJ_DIR$\../../../../components/libc/compilers/common/ctime.c + + + $PROJ_DIR$\../../../../components/libc/compilers/common/cunistd.c + + + $PROJ_DIR$\../../../../components/libc/compilers/common/cwchar.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/environ.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/syscall_close.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/syscall_lseek.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/syscall_mem.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/syscall_open.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/syscall_read.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/syscall_remove.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/syscall_write.c + + + $PROJ_DIR$\../../../../components/libc/compilers/dlib/syscalls.c + + + $PROJ_DIR$\../../../../src/klibc/kerrno.c + + + $PROJ_DIR$\../../../../src/klibc/kstdio.c + + + $PROJ_DIR$\../../../../src/klibc/kstring.c + + + $PROJ_DIR$\../../../../src/klibc/rt_vsnprintf_tiny.c + + + $PROJ_DIR$\../../../../src/klibc/rt_vsscanf.c + + + + StdDriver + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/adc.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/aeshash.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/anass.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/awk.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/bgcrc.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/btim.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/clb.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/cmpss.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/crc.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/dac.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/dcc.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/debug.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/dmamux.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/ecap.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/edma.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/emath_basic.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/emath_filter.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/emath_matrix.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/emath_transform.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/epg.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/epwm.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/eqep.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/exti.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/flash.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/flexcan.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/fmu.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/gpio.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/i2c.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/interrupt.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/iwdg1.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/iwdg2.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/lin.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/lptim.c + + + $PROJ_DIR$\packages/novosns-series/NS800RT7XXX/StdDriver/Src/mcm.c + + + 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b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U0670FF495355878281171423 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvprojx b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvprojx new file mode 100644 index 00000000000..21d4a4accc9 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/project.uvprojx @@ -0,0 +1,1556 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
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__CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, RT_USING_ARMLIBC, __RTTHREAD__ + + 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interrupt.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/interrupt.c + + + + + iwdg1.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/iwdg1.c + + + + + iwdg2.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/iwdg2.c + + + + + lin.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/lin.c + + + + + lptim.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/lptim.c + + + + + mcm.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/mcm.c + + + + + mu.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/mu.c + + + + + pmbus.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/pmbus.c + + + + + pwr.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/pwr.c + + + + + qspi.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/qspi.c + + + + + rcc.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/rcc.c + + + + + sdfm.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/sdfm.c + + + + + sema.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/sema.c + + + + + smpu.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/smpu.c + + + + + spi.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/spi.c + + + + + sram.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/sram.c + + + + + stim.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/stim.c + + + + + syscon.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/syscon.c + + + + + tim.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/tim.c + + + + + trng.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/trng.c + + + + + uart.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/uart.c + + + + + upp.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/upp.c + + + + + version.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/version.c + + + + + wwdg.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/wwdg.c + + + + + xbar.c + 1 + packages/novosns-series/NS800RT7XXX/StdDriver/Src/xbar.c + + + + + + + + + + + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.h b/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.h new file mode 100644 index 00000000000..3986a908b5f --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.h @@ -0,0 +1,433 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define SOC_SERIES_NS800RT7 +#define SOC_NS800RT7P6XX +#define BOARD_NS800RT7P65X + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CAN +#define RT_CAN_USING_CANFD +#define RT_CANMSG_BOX_SZ 16 +#define RT_CANSND_BOX_NUM 1 +#define RT_CANSND_MSG_TIMEOUT 100 +#define RT_CAN_NB_TX_FIFO_SIZE 256 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +#define PKG_USING_CMSIS_CORE +#define PKG_USING_CMSIS_CORE_LATEST_VERSION +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +#define PKG_USING_NOVOSNS_SERIES_DRIVER +#define PKG_USING_NOVOSNS_SERIES_DRIVER_LATEST_VERSION +/* end of NOVOSNS Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* On-chip Peripheral Drivers */ + +#define BOARD_CLK_CONF +#define SYSCLK_USE_PLL +#define SYSCLK_SOURCE_USE_HXTL +#define PLLCLK_SOURCE_USE_HXTL +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_NS800_UART_TX_TIMEOUT 6000 +#define BSP_USING_UART1 +#define BSP_USING_ECAP +#define BSP_USING_CAN +#define BSP_USING_CANFD1 +/* end of On-chip Peripheral Drivers */ + +#endif diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.py b/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.py new file mode 100644 index 00000000000..701999b1061 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/rtconfig.py @@ -0,0 +1,189 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'armclang': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' +else: + raise ValueError('Unsupported CROSS_TOOL: %s' % CROSS_TOOL) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = os.getenv('RTT_BUILD', 'debug') + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + ' -DNS800RT7P65X' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=gnu99' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=gnu99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-M7 ' + CFLAGS += ' -mcpu=cortex-M7 -mfpu=fpv5-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=gnu99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv5_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu VFPv5_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.ewp b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.ewp new file mode 100644 index 00000000000..1ca2a5511bd --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.ewp @@ -0,0 +1,2074 @@ + + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.eww b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvoptx b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvoptx new file mode 100644 index 00000000000..dc89326d3f7 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U0670FF495355878281171423 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvprojx b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvprojx new file mode 100644 index 00000000000..27e84d34c00 --- /dev/null +++ b/bsp/novosns/ns800/ns800rt7p65-nssinepad/template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32H743ZITx + STMicroelectronics + Keil.STM32H7xx_DFP.4.1.3 + https://www.keil.com/pack/ + IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F746NGHx$CMSIS\Flash\STM32F7x_1024.FLM)) + 0 + $$Device:STM32F746NGHx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746NGHx$CMSIS\SVD\STM32F7x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/novosns/ns800/tools/sdk_dist.py b/bsp/novosns/ns800/tools/sdk_dist.py new file mode 100644 index 00000000000..7ef49f3a2ba --- /dev/null +++ b/bsp/novosns/ns800/tools/sdk_dist.py @@ -0,0 +1,23 @@ +import os +import sys +import shutil + +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + + +# BSP dist function +def dist_do_building(BSP_ROOT, dist_dir): + from mkdist import bsp_copy_files + import rtconfig + + print("=> copy stm32 bsp library") + library_dir = os.path.join(dist_dir, 'libraries') + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + if rtconfig.BSP_LIBRARY_TYPE is not None: + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), + os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + + print("=> copy bsp drivers") + bsp_copy_files(os.path.join(library_path, 'HAL_Drivers'), os.path.join(library_dir, 'HAL_Drivers')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))