STM32WL33: LCSC_TypeDef RESERVED[6] should be RESERVED[7] — LCSC_ISR mapped to 0x40 instead of 0x44

[SteaveCZ]

Bug: LCSC_TypeDef incorrect RESERVED padding — LCSC_ISR mapped to wrong address (0x40 instead of 0x44)

Summary

The LCSC_TypeDef structure in Include/stm32wl33xx.h has incorrect padding between LCSC_STAT and LCSC_ISR. As a result, LCSC_ISR is mapped to offset 0x40 instead of the correct 0x44. Any code using LCSC interrupts silently reads/writes the wrong register.

Current definition (stm32wl33xx.h)

typedef struct {
  __IO uint32_t CR0;         // 0x00
  __IO uint32_t CR1;         // 0x04
  __IO uint32_t CR2;         // 0x08
  __IO uint32_t PULSE_CR;    // 0x0C
  __IO uint32_t ENR;         // 0x10
  __IO uint32_t WHEEL_SR;    // 0x14
  __IO uint32_t CONFR;       // 0x18
  __IO uint32_t COMP_CNT;    // 0x1C
  __IO uint32_t SR;          // 0x20
  __IO uint32_t STAT;        // 0x24
  __IO uint32_t RESERVED[6]; // 0x28–0x3C  ← WRONG: covers only up to 0x3C
  __IO uint32_t ISR;         // maps to 0x40  ← WRONG: should be 0x44
} LCSC_TypeDef;

Proposed fix

  __IO uint32_t RESERVED[7]; // 0x28–0x40 (was LCSC_VER in Rev5, reserved in Rev6)
  __IO uint32_t ISR;         // 0x44

References

• RM0511 Rev5, sections 15.8.11 (LCSC_VER @ 0x40), 15.8.12 (LCSC_ISR @ 0x44)
• RM0511 Rev6, section 15.8.11 (LCSC_ISR @ 0x44), changelog: "LCSC_VER register removed"
• Affected file: Include/stm32wl33xx.h @ 11a3b42

[ASAHSTM]

Hello @SteaveCZ,

Thank you for your report.
This issue has been tracked internally.

With Regards,

[ASAHSTM]

ST Internal Reference: ff6387959f69439c767372aaa624abca