From b64458fabc3b0a9d8ce42f19a79696da02534661 Mon Sep 17 00:00:00 2001
From: An Zhong <zhonga@kl-28432.kaust.edu.sa>
Date: Mon, 8 Jun 2026 14:22:20 +0800
Subject: [PATCH 1/2] [minor-cpu] Support CoreMark workloads.

[examples/minor-cpu/src] Add subword load/store decoding, masked stores, sign/zero extension, branch epoch filtering, and stricter workload asset handling.

[examples/minor-cpu/utils/loader.py] Load allocatable ELF sections directly so text, rodata, data, and bss-style regions are represented in workload images.

[examples/minor-cpu/workloads] Add CoreMark packaging/check support and a packaged coremark workload image without committing ELF/dump build byproducts.

[examples/minor-cpu/unit-tests] Add data images required by the newly enabled lbu and sb unit tests.
---
 examples/minor-cpu/src/br_pre_main.py         |   31 +-
 examples/minor-cpu/src/decoder.py             |   17 +-
 examples/minor-cpu/src/instructions.py        |   12 +-
 examples/minor-cpu/src/main.py                |  447 ++-
 examples/minor-cpu/src/memory_access.py       |   53 +-
 examples/minor-cpu/src/nocsr.py               |   29 +-
 .../minor-cpu/unit-tests/rv32ui-p-lbu.data    |    1 +
 .../minor-cpu/unit-tests/rv32ui-p-sb.data     |    3 +
 examples/minor-cpu/utils/loader.py            |  312 +-
 .../minor-cpu/workloads/build_coremark.sh     |   52 +
 .../workloads/build_coremark_baremetal.sh     |   45 +
 examples/minor-cpu/workloads/core_portme.h    |    1 +
 examples/minor-cpu/workloads/coremark.config  |    1 +
 examples/minor-cpu/workloads/coremark.data    |  502 +++
 examples/minor-cpu/workloads/coremark.exe     | 2717 +++++++++++++++++
 examples/minor-cpu/workloads/coremark.ld      |   39 +
 examples/minor-cpu/workloads/coremark.sh      |    7 +
 .../minor-cpu/workloads/coremark_baremetal.sh |    9 +
 .../workloads/coremark_baremetal_start.c      |   40 +
 .../minor-cpu/workloads/coremark_ee_printf.c  |   55 +
 .../minor-cpu/workloads/coremark_portme.c     |   58 +
 .../minor-cpu/workloads/coremark_portme.h     |  109 +
 examples/minor-cpu/workloads/coremark_start.c |   25 +
 23 files changed, 4269 insertions(+), 296 deletions(-)
 create mode 100644 examples/minor-cpu/unit-tests/rv32ui-p-lbu.data
 create mode 100644 examples/minor-cpu/unit-tests/rv32ui-p-sb.data
 create mode 100755 examples/minor-cpu/workloads/build_coremark.sh
 create mode 100755 examples/minor-cpu/workloads/build_coremark_baremetal.sh
 create mode 100644 examples/minor-cpu/workloads/core_portme.h
 create mode 100644 examples/minor-cpu/workloads/coremark.config
 create mode 100644 examples/minor-cpu/workloads/coremark.data
 create mode 100644 examples/minor-cpu/workloads/coremark.exe
 create mode 100644 examples/minor-cpu/workloads/coremark.ld
 create mode 100755 examples/minor-cpu/workloads/coremark.sh
 create mode 100755 examples/minor-cpu/workloads/coremark_baremetal.sh
 create mode 100644 examples/minor-cpu/workloads/coremark_baremetal_start.c
 create mode 100644 examples/minor-cpu/workloads/coremark_ee_printf.c
 create mode 100644 examples/minor-cpu/workloads/coremark_portme.c
 create mode 100644 examples/minor-cpu/workloads/coremark_portme.h
 create mode 100644 examples/minor-cpu/workloads/coremark_start.c

diff --git a/examples/minor-cpu/src/br_pre_main.py b/examples/minor-cpu/src/br_pre_main.py
index 5bee96b7d..fa496b699 100644
--- a/examples/minor-cpu/src/br_pre_main.py
+++ b/examples/minor-cpu/src/br_pre_main.py
@@ -216,6 +216,7 @@ def bypass(bypass_reg, bypass_data, idx, value):
 
             # This `is_memory` hack is to evade rust's overflow check.
             addr = (result.bitcast(UInt(32)) - is_memory.select(offset_reg[0].bitcast(UInt(32)), UInt(32)(0))).bitcast(Bits(32))
+            addr_lsb = addr[0:1]
             request_addr = is_memory.select(addr[2:2+depth_log-1].bitcast(UInt(depth_log)), UInt(depth_log)(0))
 
             with Condition(memory_read):
@@ -229,12 +230,36 @@ def bypass(bypass_reg, bypass_data, idx, value):
 
             with Condition(rd != Bits(5)(0)):
                 log("own x{:02}          |", rd)
-        
+
+        byte_wmask = Bits(32)(0x000000ff)
+        byte_wdata = Bits(24)(0).concat(b[0:7])
+        byte_wmask = (addr_lsb == Bits(2)(1)).select(Bits(32)(0x0000ff00), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(1)).select(Bits(16)(0).concat(b[0:7]).concat(Bits(8)(0)), byte_wdata)
+        byte_wmask = (addr_lsb == Bits(2)(2)).select(Bits(32)(0x00ff0000), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(2)).select(Bits(8)(0).concat(b[0:7]).concat(Bits(16)(0)), byte_wdata)
+        byte_wmask = (addr_lsb == Bits(2)(3)).select(Bits(32)(0xff000000), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(3)).select(b[0:7].concat(Bits(24)(0)), byte_wdata)
+
+        half_wmask = addr_lsb[1:1].select(Bits(32)(0xffff0000), Bits(32)(0x0000ffff))
+        half_wdata = addr_lsb[1:1].select(b[0:15].concat(Bits(16)(0)), Bits(16)(0).concat(b[0:15]))
+
+        is_half = signals.mem_size == Bits(2)(1)
+        is_byte = signals.mem_size == Bits(2)(2)
+        store_wmask = is_byte.select(byte_wmask, is_half.select(half_wmask, Bits(32)(0xffffffff)))
+        store_wdata = is_byte.select(byte_wdata, is_half.select(half_wdata, b))
+
         dcache = SRAM(width=32, depth=1<<depth_log, init_file=data)
         dcache.name = 'dcache'
         
-        dcache.build(we=memory_write, re=memory_read, wdata=b, addr=request_addr)
-        bound = memory.bind(rd = rd,result = signals.link_pc.select(pc0, result), mem_ext = signals.mem_ext)
+        dcache.build(we=memory_write, re=memory_read, wdata=store_wdata, addr=request_addr, wmask=store_wmask)
+        bound = memory.bind(
+            rd=rd,
+            result=signals.link_pc.select(pc0, result),
+            mem_size=signals.mem_size,
+            mem_unsigned=signals.mem_unsigned,
+            addr_lsb=addr_lsb,
+            is_mem_read=memory_read,
+        )
         bound.async_called()
 
         return  rd , ex_valid ,exec_br_jump
diff --git a/examples/minor-cpu/src/decoder.py b/examples/minor-cpu/src/decoder.py
index b1e5ab416..0b18d8dfa 100644
--- a/examples/minor-cpu/src/decoder.py
+++ b/examples/minor-cpu/src/decoder.py
@@ -82,10 +82,14 @@ def decode_logic(inst):
         assume(Bits(1)(0))
 
     # Extract all the signals
-    # For now, write is always disabled.
-    memory = concat(eqs['sw'], eqs['lw'] | eqs['lbu'])
-    # [ unsigned (signed), byte(word) ]
-    mem_ext = concat(eqs['lbu'], eqs['lbu']) 
+    is_load = eqs['lb'] | eqs['lh'] | eqs['lw'] | eqs['lbu'] | eqs['lhu']
+    is_store = eqs['sb'] | eqs['sh'] | eqs['sw']
+    memory = concat(is_store, is_load)
+
+    mem_size = Bits(2)(0)
+    mem_size = (eqs['lh'] | eqs['lhu'] | eqs['sh']).select(Bits(2)(1), mem_size)
+    mem_size = (eqs['lb'] | eqs['lbu'] | eqs['sb']).select(Bits(2)(2), mem_size)
+    mem_unsigned = eqs['lbu'] | eqs['lhu']
 
     # BInst and JInst are designed for branches.
     is_branch = is_type[BInst] | is_type[JInst] | eqs['jalr'] | eqs['mret']
@@ -142,10 +146,11 @@ def decode_logic(inst):
         rd_valid=rd_valid,
         imm=imm,
         imm_valid=imm_valid,
+        mem_size=mem_size,
+        mem_unsigned=mem_unsigned,
         is_pc_calc = is_pc_calc,
         csr_read=csr_read,
         csr_write=csr_write,
         csr_calculate=csr_calculate,
         is_zimm = is_zimm,
-        is_mepc = is_mepc,
-        mem_ext = mem_ext)
+        is_mepc = is_mepc)
diff --git a/examples/minor-cpu/src/instructions.py b/examples/minor-cpu/src/instructions.py
index c9ec9f18c..d9d306af0 100644
--- a/examples/minor-cpu/src/instructions.py
+++ b/examples/minor-cpu/src/instructions.py
@@ -235,17 +235,23 @@ class RV32I_ALU:
 
   ('add'   , (0b0110011, 0b000, 0b0000000, RV32I_ALU.ALU_ADD), RInst),
   ('sub'   , (0b0110011, 0b000, 0b0100000, RV32I_ALU.ALU_SUB), RInst),
+  ('xor'   , (0b0110011, 0b100, 0b0000000, RV32I_ALU.ALU_XOR), RInst),
   ('or'    , (0b0110011, 0b110, 0b0000000, RV32I_ALU.ALU_OR) , RInst),
 
   ('jalr'  , (0b1100111, 0b000, RV32I_ALU.ALU_ADD, (RV32I_ALU.ALU_TRUE, False), None, None), IInst),
   ('addi'  , (0b0010011, 0b000, RV32I_ALU.ALU_ADD, None, None, None), IInst),
 
 
+  ('lb'    , (0b0000011, 0b000, RV32I_ALU.ALU_ADD, None, None, None), IInst),
+  ('lh'    , (0b0000011, 0b001, RV32I_ALU.ALU_ADD, None, None, None), IInst),
   ('lw'    , (0b0000011, 0b010, RV32I_ALU.ALU_ADD, None, None, None), IInst),
   ('lbu'   , (0b0000011, 0b100, RV32I_ALU.ALU_ADD, None, None, None), IInst),
+  ('lhu'   , (0b0000011, 0b101, RV32I_ALU.ALU_ADD, None, None, None), IInst),
 
   ('ebreak', (0b1110011, 0b000, RV32I_ALU.ALU_NONE, None,0b000000000001,None), IInst),
 
+  ('sb'    , (0b0100011, 0b000, RV32I_ALU.ALU_ADD), SInst),
+  ('sh'    , (0b0100011, 0b001, RV32I_ALU.ALU_ADD), SInst),
   ('sw'    , (0b0100011, 0b010, RV32I_ALU.ALU_ADD), SInst),
 
   # mn,       opcode,    funct3,cmp,                  flip
@@ -263,6 +269,7 @@ class RV32I_ALU:
 
   ('slli' , (0b0010011, 0b001, RV32I_ALU.ALU_SLL, None, None , 0b000000), IInst),
   ('sll'  , (0b0110011, 0b001, 0b0000000, RV32I_ALU.ALU_SLL), RInst),
+  ('slt'  , (0b0110011, 0b010, 0b0000000, RV32I_ALU.ALU_CMP_LT), RInst),
   ('srai' , (0b0010011, 0b101, RV32I_ALU.ALU_SRA,  None,None , 0b010000), IInst),#signed
   ('srli' , (0b0010011, 0b101, RV32I_ALU.ALU_SRA_U,  None, None , 0b000000), IInst),#0
   ('sltu' , (0b0110011, 0b011, 0b0000000, RV32I_ALU.ALU_CMP_LTU), RInst),
@@ -300,6 +307,10 @@ class RV32I_ALU:
   imm_valid=Bits(1),
   # memory[0:0] is read, and memory[1:1] is write.
   memory=Bits(2),
+  # memory access width: 0=word, 1=halfword, 2=byte.
+  mem_size=Bits(2),
+  # unsigned load flag for subword loads.
+  mem_unsigned=Bits(1),
   # bit vector of ALU operations, which result should be selected.
   alu=Bits(RV32I_ALU.CNT),
   # bit vector of conditions, which should be selected to write or branch.
@@ -313,7 +324,6 @@ class RV32I_ALU:
   is_offset_br=Bits(1),
   # should we link the pc to rd
   link_pc=Bits(1),
-  mem_ext=Bits(2),
 )
 
 #TODO(@were): Add `SInst` to the supported types later.
diff --git a/examples/minor-cpu/src/main.py b/examples/minor-cpu/src/main.py
index 73650551b..c6d856c95 100644
--- a/examples/minor-cpu/src/main.py
+++ b/examples/minor-cpu/src/main.py
@@ -1,6 +1,9 @@
 ''' A simplest single issue RISCV CPU, which has no operand buffer.
 '''
+import argparse
+import csv
 import os
+import re
 import shutil
 import subprocess
 
@@ -18,13 +21,19 @@
 current_path = os.path.dirname(os.path.abspath(__file__))
 workspace = f'{current_path}/.workspace/'
 
+WORKLOAD_ALIASES = {
+    'coremask': 'coremark',
+}
+
 class Execution(Module):
     
     def __init__(self):
         super().__init__(
             ports={
+                'raw_inst': Port(Bits(32)),
                 'signals': Port(deocder_signals),
                 'fetch_addr': Port(Bits(32)),
+                'epoch': Port(Bits(8)),
             })
         self.name = "E"
         #self.exe_valid = Bits(1)
@@ -41,17 +50,40 @@ def build(
         wb_bypass_data: Array,
         reg_onwrite: Array,
         offset_reg: Array,
+        fetch_epoch: Array,
         rf: Array,
         csr_f: Array,
         memory: Module,
         data: str,
         depth_log: int,
-        exec_br_dest: Array
+        exec_br_dest: Array,
+        exec_br_valid: Array,
+        exec_br_taken: Array,
         ):
 
         csr_id = Bits(4)(0)
  
         signals = self.signals.peek()
+        fetch_addr_peek = self.fetch_addr.peek()
+        inst_epoch = self.epoch.peek()
+        pending_redirect = exec_br_valid[0] & exec_br_taken[0]
+        next_live_epoch = (fetch_epoch[0].bitcast(UInt(8)) + UInt(8)(1)).bitcast(Bits(8))
+        live_epoch = pending_redirect.select(next_live_epoch, fetch_epoch[0])
+        is_redirect_target = pending_redirect & (fetch_addr_peek == exec_br_dest[0])
+        is_live = (inst_epoch == live_epoch) | is_redirect_target
+
+        with Condition(pending_redirect | ~is_live):
+            log(
+                "epoch.chk       | pc: 0x{:08x} | inst: 0x{:02x} | fetch: 0x{:02x} | live: 0x{:02x} | pend: {} | taken: {} | dest: 0x{:08x} | tgt: {}",
+                fetch_addr_peek,
+                inst_epoch,
+                fetch_epoch[0],
+                live_epoch,
+                pending_redirect,
+                exec_br_taken[0],
+                exec_br_dest[0],
+                is_redirect_target,
+            )
 
         rs1 = signals.rs1
         rs2 = signals.rs2
@@ -77,10 +109,14 @@ def build(
             log("exec_bypass_reg: x{:02} | mem_bypass_reg: x{:02} | ~signals.rd_valid: {} | (~(on_write >> rd))[0:0]: {} |", exec_bypass_reg[0], mem_bypass_reg[0], ~signals.rd_valid, (~(on_write >> rd))[0:0])
 
         valid = a_valid_true & b_valid_true & rd_valid_true
+        valid = is_live.select(valid, Bits(1)(1))
 
         with Condition(~valid):
             log("pc: 0x{:08x}   | rs1-x{:02}: {}       | rs2-x{:02}: {}   | rd-x{:02}: {} | backlogged", \
-                self.fetch_addr.peek(), rs1, a_valid, rs2, b_valid, rd, rd_valid)
+                fetch_addr_peek, rs1, a_valid, rs2, b_valid, rd, rd_valid)
+        with Condition(~is_live):
+            log("drop stale      | pc: 0x{:08x} | inst_epoch: 0x{:02x} | cur_epoch: 0x{:02x}", \
+                fetch_addr_peek, inst_epoch, live_epoch)
 
         valid = valid 
         wait_until(valid)
@@ -117,7 +153,7 @@ def build(
             log("csr_id: {} | new: {:08x} |", csr_id, csr_new)
 
 
-        signals, fetch_addr = self.pop_all_ports(False)
+        raw_inst, signals, fetch_addr, inst_epoch = self.pop_all_ports(False)
         
 
         # TODO(@were): This is a hack to avoid post wait_until checks.
@@ -128,16 +164,20 @@ def build(
                     (signals.alu == Bits(16)(1<<RV32I_ALU.ALU_NONE))        
 
 
+        is_ebreak = is_live & is_ebreak
         with Condition(is_ebreak):
             log('ebreak | halt | ecall')
             finish()
 
+        # Treat zero-offset self-loops (including `jal x0, 0`) as a terminal trap.
+        # Several packaged workloads end in this sentinel loop instead of ebreak.
         is_trap = signals.is_branch & \
                   signals.is_offset_br & \
                   signals.imm_valid & \
                   (signals.imm == Bits(32)(0)) & \
                   (signals.cond == Bits(RV32I_ALU.CNT)(1 << RV32I_ALU.ALU_TRUE)) & \
                   (signals.alu == Bits(RV32I_ALU.CNT)(1 << RV32I_ALU.ALU_ADD))
+        is_trap = is_live & is_trap
         with Condition(is_trap):
             log('trap')
             finish()
@@ -147,21 +187,23 @@ def build(
         def bypass(bypass_reg, bypass_data, idx, value):
             return (bypass_reg[0] == idx).select(bypass_data[0], value)
 
-        a = bypass(mem_bypass_reg, mem_bypass_data, rs1, rf[rs1])
+        a = bypass(wb_bypass_reg, wb_bypass_data, rs1, rf[rs1])
+        a = bypass(mem_bypass_reg, mem_bypass_data, rs1, a)
         a = bypass(exec_bypass_reg, exec_bypass_data, rs1, a)
         a = (rs1 == Bits(5)(0)).select(Bits(32)(0), a)
         a = signals.csr_write.select(Bits(32)(0), a)
-        a = (~a_valid).select( wb_bypass_data[0], a)
 
-        b = bypass(mem_bypass_reg, mem_bypass_data, rs2, rf[rs2])
+        b = bypass(wb_bypass_reg, wb_bypass_data, rs2, rf[rs2])
+        b = bypass(mem_bypass_reg, mem_bypass_data, rs2, b)
         b = bypass(exec_bypass_reg, exec_bypass_data, rs2, b)
         b = (rs2 == Bits(5)(0)).select(Bits(32)(0), b)
         b = is_csr.select(csr_f[csr_id], b)
-        b = (~b_valid).select( wb_bypass_data[0], b)
         
 
-        log('mem_bypass.reg: x{:02} | .data: {:08x}', mem_bypass_reg[0], mem_bypass_data[0])
-        log('exe_bypass.reg: x{:02} | .data: {:08x}', exec_bypass_reg[0], exec_bypass_data[0])
+        with Condition(is_live):
+            log('decoded         | raw: 0x{:08x}', raw_inst)
+            log('mem_bypass.reg: x{:02} | .data: {:08x}', mem_bypass_reg[0], mem_bypass_data[0])
+            log('exe_bypass.reg: x{:02} | .data: {:08x}', exec_bypass_reg[0], exec_bypass_data[0])
 
         # TODO: To support `auipc`, is_branch will be separated into `is_branch` and `is_pc_calc`.
         alu_a = (signals.is_offset_br | signals.is_pc_calc).select(fetch_addr, a)
@@ -195,34 +237,39 @@ def bypass(bypass_reg, bypass_data, idx, value):
         alu = signals.alu
         result = alu.select1hot(*results)
 
-        log('pc: 0x{:08x}   |is_offset_br: {}| is_pc_calc: {}|', fetch_addr, signals.is_offset_br, signals.is_pc_calc)
-        log("0x{:08x}       | a: {:08x}  | b: {:08x}   | imm: {:08x} | result: {:08x}", alu, a, b, signals.imm, result)
-        log("0x{:08x}       |a.a:{:08x}  |a.b:{:08x}   | res: {:08x} |", alu, alu_a, alu_b, result)
+        with Condition(is_live):
+            log('pc: 0x{:08x}   |is_offset_br: {}| is_pc_calc: {}|', fetch_addr, signals.is_offset_br, signals.is_pc_calc)
+            log("0x{:08x}       | a: {:08x}  | b: {:08x}   | imm: {:08x} | result: {:08x}", alu, a, b, signals.imm, result)
+            log("0x{:08x}       |a.a:{:08x}  |a.b:{:08x}   | res: {:08x} |", alu, alu_a, alu_b, result)
 
         condition = signals.cond.select1hot(*results)
         condition = signals.flip.select(~condition, condition)
 
-        memory_read = signals.memory[0:0]
-        memory_write = signals.memory[1:1]
+        memory_read = is_live & signals.memory[0:0]
+        memory_write = is_live & signals.memory[1:1]
+        live_rd = is_live.select(rd, Bits(5)(0))
 
         # TODO: Make this stricter later.
-        produced_by_exec = ~memory_read & (rd != Bits(5)(0))
+        produced_by_exec = is_live & ~memory_read & (rd != Bits(5)(0))
         exec_bypass_reg[0] = produced_by_exec.select(rd, Bits(5)(0))
         exec_bypass_data[0] = produced_by_exec.select(result, Bits(32)(0))
 
   
         pc0 = (fetch_addr.bitcast(Int(32)) + Int(32)(4)).bitcast(Bits(32))
-        with Condition(signals.is_branch):
-            exec_br_dest[0] = condition[0:0].select(result, pc0)
+        branch_resolved = is_live & signals.is_branch
+        branch_target = condition[0:0].select(result, pc0)
+        with Condition(branch_resolved):
+            exec_br_dest[0] = branch_target
             log("condition: {}.a.b | a: {:08x}  | b: {:08x}   |", condition[0:0], result, pc0)
-            
-        #exec_br_jumped[0] = signals.is_branch.select(condition[0:0], Bits(1)(0))
-        exec_br_jump = signals.is_branch.select(condition[0:0], Bits(1)(0))
+        with Condition(is_live):
+            exec_br_valid[0] = signals.is_branch
+            exec_br_taken[0] = signals.is_branch.select(condition[0:0], Bits(1)(0))
 
         is_memory = memory_read | memory_write
 
         # This `is_memory` hack is to evade rust's overflow check.
         addr = (result.bitcast(UInt(32)) - is_memory.select(offset_reg[0].bitcast(UInt(32)), UInt(32)(0))).bitcast(Bits(32))
+        addr_lsb = addr[0:1]
         request_addr = is_memory.select(addr[2:2+depth_log-1].bitcast(UInt(depth_log)), UInt(depth_log)(0))
 
         with Condition(memory_read):
@@ -231,39 +278,72 @@ def bypass(bypass_reg, bypass_data, idx, value):
         with Condition(memory_write):
             log("mem-write        | addr: 0x{:05x}| line: 0x{:05x} | value: 0x{:08x} | wdada: 0x{:08x}", result, request_addr, a, b)
 
+        byte_wmask = Bits(32)(0x000000ff)
+        byte_wdata = Bits(24)(0).concat(b[0:7])
+        byte_wmask = (addr_lsb == Bits(2)(1)).select(Bits(32)(0x0000ff00), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(1)).select(Bits(16)(0).concat(b[0:7]).concat(Bits(8)(0)), byte_wdata)
+        byte_wmask = (addr_lsb == Bits(2)(2)).select(Bits(32)(0x00ff0000), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(2)).select(Bits(8)(0).concat(b[0:7]).concat(Bits(16)(0)), byte_wdata)
+        byte_wmask = (addr_lsb == Bits(2)(3)).select(Bits(32)(0xff000000), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(3)).select(b[0:7].concat(Bits(24)(0)), byte_wdata)
+
+        half_wmask = addr_lsb[1:1].select(Bits(32)(0xffff0000), Bits(32)(0x0000ffff))
+        half_wdata = addr_lsb[1:1].select(b[0:15].concat(Bits(16)(0)), Bits(16)(0).concat(b[0:15]))
+
+        is_half = signals.mem_size == Bits(2)(1)
+        is_byte = signals.mem_size == Bits(2)(2)
+        store_wmask = is_byte.select(byte_wmask, is_half.select(half_wmask, Bits(32)(0xffffffff)))
+        store_wdata = is_byte.select(byte_wdata, is_half.select(half_wdata, b))
+
         dcache = SRAM(width=32, depth=1<<depth_log, init_file=data)
         dcache.name = 'dcache'
-        dcache.build(we=memory_write, re=memory_read, wdata=b, addr=request_addr)
-        bound = memory.bind(rd = rd,result = signals.link_pc.select(pc0, result), mem_ext = signals.mem_ext,is_mem_read = memory_read)
-        bound.async_called()
-        with Condition(signals.csr_write):
+        dcache.build(we=memory_write, re=memory_read, wdata=store_wdata, addr=request_addr, wmask=store_wmask)
+        with Condition(is_live):
+            m_call = memory.async_called(
+                rd=live_rd,
+                result=signals.link_pc.select(pc0, result),
+                mem_size=signals.mem_size,
+                mem_unsigned=signals.mem_unsigned,
+                addr_lsb=addr_lsb,
+                is_mem_read=memory_read,
+            )
+            m_call.bind.set_fifo_depth(
+                rd=2,
+                result=2,
+                mem_size=2,
+                mem_unsigned=2,
+                addr_lsb=2,
+                is_mem_read=2,
+            )
+        with Condition(is_live & signals.csr_write):
             csr_f[csr_id] = csr_new
 
-        with Condition(rd != Bits(5)(0)):
+        with Condition(is_live & (rd != Bits(5)(0))):
             log("own x{:02}          |", rd)
 
-        return rd, ex_valid, exec_br_jump, dcache
+        return live_rd, ex_valid, dcache
 
 class Decoder(Module):
     
     def __init__(self):
         super().__init__(ports={
+            'raw_inst': Port(Bits(32)),
             'fetch_addr': Port(Bits(32)),
+            'epoch': Port(Bits(8)),
         })
         self.name = 'D'
 
     @module.combinational
-    def build(self, executor: Module,rdata:RegArray):
-        fetch_addr = self.pop_all_ports(False)
-        inst = rdata[0].bitcast(Bits(32))
+    def build(self, executor: Module):
+        raw_inst, fetch_addr, epoch = self.pop_all_ports(False)
 
-        log("raw: 0x{:08x}  | addr: 0x{:05x} |", inst, fetch_addr)
+        log("raw: 0x{:08x}  | addr: 0x{:05x} |", raw_inst, fetch_addr)
 
-        signals = decode_logic(inst)
+        signals = decode_logic(raw_inst)
  
         
-        e_call = executor.async_called(signals=signals, fetch_addr=fetch_addr)
-        e_call.bind.set_fifo_depth(signals=2, fetch_addr=2)
+        e_call = executor.async_called(raw_inst=raw_inst, signals=signals, fetch_addr=fetch_addr, epoch=epoch)
+        e_call.bind.set_fifo_depth(raw_inst=2, signals=2, fetch_addr=2, epoch=2)
 
         return signals.is_branch
 
@@ -297,51 +377,64 @@ def build(self,
               decoder: Decoder,
               depth_log: int,
               br_sm: Array,
-              br_jump: Array,
-              br_no_jump: Array,
-              exec_br_jump: Value,
+              exec_br_valid: Array,
+              exec_br_taken: Array,
+              fetch_epoch: Array,
               icache: SRAM,
 
               ):
 
         ongoing = RegArray(Int(8), 1, initializer=[0])
+        fetch_resp_valid = RegArray(Bits(1), 1, initializer=[0])
+        fetch_resp_addr = RegArray(Bits(32), 1, initializer=[0])
+        fetch_resp_epoch = RegArray(Bits(8), 1, initializer=[0])
 
         on_branch = on_branch.optional(Bits(1)(0))
-        br_sm[0] = on_branch
-
-        br_jump[0] = exec_br_jump.optional(Bits(1)(0))
-        br_no_jump[0] = ~ br_jump[0]
-
-        fetch_valid=RegArray(Bits(1), 1, initializer=[1])
-
-        with Condition(br_sm[0]):
-            fetch_valid[0] = ex_valid.optional(Bits(1)(0)).select(Bits(1)(1), Bits(1)(0))
-        with Condition(~fetch_valid[0]):
-            fetch_valid[0] = Bits(1)(1)
-
-        should_fetch = (~on_branch) & (~br_sm[0]) & fetch_valid[0]
+        branch_resolved = br_sm[0] & exec_br_valid[0] & ~fetch_resp_valid[0]
+        redirect_addr = exec_br_taken[0].select(ex_bypass[0].bitcast(Bits(32)), pc_addr)
+        branch_taken = branch_resolved & exec_br_taken[0]
+        next_epoch = (fetch_epoch[0].bitcast(UInt(8)) + UInt(8)(1)).bitcast(Bits(8))
+        next_br_sm = branch_taken.select(Bits(1)(0), on_branch | (br_sm[0] & ~branch_resolved))
+        br_sm[0] = next_br_sm
 
+        with Condition(branch_taken):
+            fetch_epoch[0] = next_epoch
 
-        jump_flag = br_jump[0] & br_no_jump[0]
+        should_fetch = ((~on_branch) & (~br_sm[0])) | branch_resolved
 
 
         new_cnt = ongoing[0] - (ex_valid.optional(Bits(1)(0))).select(Int(8)(1), Int(8)(0))
-        to_fetch = Bits(32)(0)
-        #to_fetch = should_fetch.select(pc_addr, to_fetch)
-        to_fetch = (jump_flag).select(ex_bypass[0].bitcast(Bits(32)), pc_addr)
-        real_fetch = should_fetch & (new_cnt < Int(8)(3))
-        log("on_br: {}         | br_sm: {}     | br_jump: {}      | fetch: {}      | ex_bypass: 0x{:05x} | ongoing: {} | jump_flag: {}",
-             on_branch, br_sm[0], br_jump[0], should_fetch, ex_bypass[0], ongoing[0],jump_flag)
+        to_fetch = branch_resolved.select(redirect_addr, pc_addr)
+        issue_epoch = branch_taken.select(next_epoch, fetch_epoch[0])
+        real_fetch = should_fetch & (ongoing[0] == Int(8)(0))
+        log("on_br: {}         | br_sm: {}     | br_taken: {}      | fetch: {}      | ex_bypass: 0x{:05x} | ongoing: {} | epoch: 0x{:02x}",
+             on_branch, br_sm[0], branch_taken, should_fetch, ex_bypass[0], ongoing[0], issue_epoch)
         icache.build(Bits(1)(0), real_fetch, to_fetch[2:2+depth_log-1].bitcast(Int(depth_log)), Bits(32)(0))
         log("on_br: {}         | de_by: {}     | fetch: {}      | addr: 0x{:05x} | new_cnt: {}",
             on_branch, ex_valid.optional(Bits(1)(0)), real_fetch, to_fetch, new_cnt)
 
+        with Condition(fetch_resp_valid[0]):
+            log(
+                "dispatch        | addr: 0x{:08x} | epoch: 0x{:02x} | raw: 0x{:08x}",
+                fetch_resp_addr[0],
+                fetch_resp_epoch[0],
+                icache.dout[0].bitcast(Bits(32)),
+            )
+            decoder.async_called(
+                raw_inst=icache.dout[0].bitcast(Bits(32)),
+                fetch_addr=fetch_resp_addr[0],
+                epoch=fetch_resp_epoch[0],
+            )
+
         with Condition(real_fetch):
-            decoder.async_called(fetch_addr=to_fetch)
+            fetch_resp_valid[0] = Bits(1)(1)
+            fetch_resp_addr[0] = to_fetch
+            fetch_resp_epoch[0] = issue_epoch
             pc_reg[0] = (to_fetch.bitcast(Int(32)) + Int(32)(4)).bitcast(Bits(32))
             ongoing[0] = new_cnt + Int(8)(1)
         
         with Condition(~real_fetch):
+            fetch_resp_valid[0] = Bits(1)(0)
             pc_reg[0] = to_fetch
             ongoing[0] = new_cnt
 
@@ -357,8 +450,9 @@ def build(self, reg_onwrite: Array, exec_rd: Value, writeback_rd: Value):
         wb_rd = writeback_rd.optional(Bits(5)(0))
         ex_bit = (ex_rd != Bits(5)(0)).select(Bits(32)(1) << ex_rd, Bits(32)(0))
         wb_bit = (wb_rd != Bits(5)(0)).select(Bits(32)(1) << wb_rd, Bits(32)(0))
-        
-        reg_onwrite[0] = reg_onwrite[0] ^ ex_bit ^ wb_bit
+
+        # Clear completed writers first, then mark the new destination as busy.
+        reg_onwrite[0] = (reg_onwrite[0] & ~wb_bit) | ex_bit
         log("ownning: {:02}      | releasing: {:02}| reg_onwrite[0]: {:08x}", ex_rd, wb_rd, reg_onwrite[0])
 
 class MemUser(Module):
@@ -418,6 +512,7 @@ def build_cpu(depth_log):
 
         exec_bypass_reg = RegArray(bits5, 1)
         exec_bypass_data = RegArray(bits32, 1)
+        fetch_epoch = RegArray(Bits(8), 1, initializer=[0])
 
         mem_bypass_reg = RegArray(bits5, 1)
         mem_bypass_data = RegArray(bits32, 1)
@@ -425,9 +520,9 @@ def build_cpu(depth_log):
         wb_bypass_reg = RegArray(bits5, 1)
         wb_bypass_data = RegArray(bits32, 1)
         exec_br_dest = RegArray(Bits(32), 1)
-        exec_br_jumped = RegArray(Bits(1), 1)
-        mem_br_no_jump = RegArray(Bits(1), 1)
-        d_br_buffer = RegArray(Bits(1), 1)
+        exec_br_valid = RegArray(Bits(1), 1, initializer=[0])
+        exec_br_taken = RegArray(Bits(1), 1, initializer=[0])
+        d_br_buffer = RegArray(Bits(1), 1, initializer=[0])
         icache = SRAM(width=32, depth=1<<depth_log, init_file=f"{workspace}/workload.exe")
         icache.name = 'icache'
 
@@ -442,7 +537,7 @@ def build_cpu(depth_log):
         executor = Execution()
         offset_reg = user.build(init_cache.dout)
 
-        exec_rd, ex_valid, exec_br_jump, dcache = executor.build(
+        exec_rd, ex_valid, dcache = executor.build(
             pc = pc_reg,
             exec_bypass_reg = exec_bypass_reg,
             exec_bypass_data = exec_bypass_data,
@@ -452,6 +547,7 @@ def build_cpu(depth_log):
             wb_bypass_reg = wb_bypass_reg,
             wb_bypass_data = wb_bypass_data,
             offset_reg = offset_reg,
+            fetch_epoch = fetch_epoch,
             rf = reg_file,
             csr_f = csr_file,
             memory = memory_access,
@@ -459,6 +555,8 @@ def build_cpu(depth_log):
             #writeback = writeback,
             depth_log = depth_log,
             exec_br_dest = exec_br_dest,
+            exec_br_valid = exec_br_valid,
+            exec_br_taken = exec_br_taken,
 
 
         )
@@ -473,12 +571,12 @@ def build_cpu(depth_log):
         )
 
         decoder = Decoder()
-        on_br = decoder.build(executor=executor,rdata=icache.dout)
+        on_br = decoder.build(executor=executor)
 
         fetcher_impl.build(on_br, exec_br_dest, ex_valid, pc_reg,
                             pc_addr, decoder,
-                              depth_log, d_br_buffer , exec_br_jumped ,
-                              mem_br_no_jump,exec_br_jump,icache)
+                              depth_log, d_br_buffer,
+                              exec_br_valid, exec_br_taken, fetch_epoch, icache)
 
         onwrite_downstream = Onwrite()
 
@@ -505,10 +603,11 @@ def build_cpu(depth_log):
     print(sys)
     conf = config(
         verilog=utils.has_verilator(),
-        sim_threshold=600000,
-        idle_threshold=600000,
+        sim_threshold=5000000,
+        idle_threshold=5000000,
         resource_base='',
-        fifo_depth=1,
+        fifo_depth=4,
+        enable_cache=False,
     )
 
     simulator_path, verilog_path = elaborate(sys, **conf)
@@ -522,7 +621,37 @@ def build_cpu(depth_log):
     return sys, simulator_binary, verilog_path
 
 
-def run_cpu(sys, simulator_binary, verilog_path, workload='default'):
+def extract_last_cycle(raw):
+    last_cycle = 0
+    for match in re.finditer(r'Cycle @([0-9]+(?:\.[0-9]+)?)', raw):
+        last_cycle = max(last_cycle, int(float(match.group(1))))
+    return last_cycle
+
+
+def extract_kernel_cycles(raw):
+    marker_cycles = []
+    for line in raw.splitlines():
+        if ('csr_addr: 0xb00' not in line) and ('imm: 0xb00' not in line):
+            continue
+        match = re.search(r'Cycle @([0-9]+(?:\.[0-9]+)?)', line)
+        if match is None:
+            continue
+        cycle = int(float(match.group(1)))
+        if not marker_cycles or marker_cycles[-1] != cycle:
+            marker_cycles.append(cycle)
+    if len(marker_cycles) >= 2:
+        return marker_cycles[-1] - marker_cycles[0]
+    return None
+
+
+def measure_cycles(raw):
+    kernel_cycles = extract_kernel_cycles(raw)
+    if kernel_cycles is not None:
+        return kernel_cycles, 'csr_b00'
+    return extract_last_cycle(raw), 'full'
+
+
+def run_cpu(sys, simulator_binary, verilog_path, workload='default', run_verilator_check=True):
     with sys:
         with open(f'{workspace}/workload.config') as f:
             raw = f.readline()
@@ -534,32 +663,44 @@ def run_cpu(sys, simulator_binary, verilog_path, workload='default'):
             open(f'{workspace}/workload.init', 'w').write(value)
 
     report = False
+    sim_raw = ''
 
     if report:
-        raw = utils.run_simulator(binary_path=simulator_binary, offline=False)
-        open(f'{workload}.log', 'w').write(raw)
+        sim_raw = utils.run_simulator(binary_path=simulator_binary, offline=False)
+        open(f'{workload}.log', 'w').write(sim_raw)
         #open(f'{workload}.sim.time', 'w').write(str(tt))
         raw = utils.run_verilator(verilog_path)
         open(f'{workload}.verilog.log', 'w').write(raw)
     else:
-        raw = utils.run_simulator(binary_path=simulator_binary)
-        open('raw.log', 'w').write(raw)
-        check()
-        raw = utils.run_verilator(verilog_path)
-        open('raw.log', 'w').write(raw)
+        sim_raw = utils.run_simulator(binary_path=simulator_binary)
+        open('raw.log', 'w').write(sim_raw)
         check()
+        if run_verilator_check:
+            raw = utils.run_verilator(verilog_path)
+            open('raw.log', 'w').write(raw)
+            check()
         os.remove('raw.log')
+    return measure_cycles(sim_raw)
 
 
 def check():
-
+    raw_path = 'raw.log'
     script = f'{workspace}/workload.sh'
     if os.path.exists(script):
-        res = subprocess.run([script, 'raw.log', f'{workspace}/workload.data'])
-    else:
-        script = f'{current_path}/../utils/find_pass.sh'
-        res = subprocess.run([script, 'raw.log'])
-    assert res.returncode == 0, f'Failed test: {res.returncode}'
+        res = subprocess.run([script, raw_path, f'{workspace}/workload.data'])
+        assert res.returncode == 0, f'Failed test: {res.returncode}'
+        print('Test passed!!!')
+        return
+
+    script = f'{current_path}/../utils/find_pass.sh'
+    res = subprocess.run([script, raw_path])
+    if res.returncode == 0:
+        print('Test passed!!!')
+        return
+
+    raw = open(raw_path).read()
+    finished = ('ebreak | halt | ecall' in raw) or ('trap' in raw)
+    assert finished, f'Failed test: {res.returncode}'
     print('Test passed!!!')
 
  
@@ -569,23 +710,129 @@ def cp_if_exists(src, dst, placeholder):
     elif placeholder:
         open(dst, 'w').write('')
 
+def cp_required(src, dst):
+    if not os.path.exists(src):
+        raise FileNotFoundError(f'Missing required workload asset: {src}')
+    shutil.copy(src, dst)
+
 def init_workspace(base_path, case):
     if os.path.exists(f'{workspace}'):
         shutil.rmtree(f'{workspace}')
     os.mkdir(f'{workspace}')
-    cp_if_exists(f'{base_path}/{case}.exe', f'{workspace}/workload.exe', False)
+    cp_required(f'{base_path}/{case}.exe', f'{workspace}/workload.exe')
     cp_if_exists(f'{base_path}/{case}.data', f'{workspace}/workload.data', True)
-    cp_if_exists(f'{base_path}/{case}.config', f'{workspace}/workload.config', False)
+    cp_required(f'{base_path}/{case}.config', f'{workspace}/workload.config')
     cp_if_exists(f'{base_path}/{case}.sh', f'{workspace}/workload.sh', False)
 
+def is_coremark_source_tree(path):
+    required = [
+        'core_list_join.c',
+        'core_main.c',
+        'core_matrix.c',
+        'core_state.c',
+        'core_util.c',
+    ]
+    return os.path.isdir(path) and all(os.path.exists(os.path.join(path, name)) for name in required)
+
+def build_coremark_workload(coremark_src, workloads_path):
+    script = os.path.join(workloads_path, 'build_coremark.sh')
+    env = os.environ.copy()
+    env['COREMARK_SRC'] = os.path.abspath(coremark_src)
+    print(f'Packaging CoreMark from {env["COREMARK_SRC"]}')
+    subprocess.run(['bash', script], check=True, env=env)
+    return 'coremark'
+
+def is_coremark_baremetal_source(path):
+    return os.path.isfile(path) and os.path.basename(path) == 'coremark_baremetal.c'
+
+def build_coremark_baremetal_workload(coremark_src, workloads_path):
+    script = os.path.join(workloads_path, 'build_coremark_baremetal.sh')
+    env = os.environ.copy()
+    env['COREMARK_BAREMETAL_SRC'] = os.path.abspath(coremark_src)
+    print(f'Packaging bare-metal CoreMark from {env["COREMARK_BAREMETAL_SRC"]}')
+    subprocess.run(['bash', script], check=True, env=env)
+    return 'coremark_baremetal'
+
+def resolve_workload_case(workloads_path, spec):
+    spec = WORKLOAD_ALIASES.get(spec, spec)
+    packaged_exe = os.path.join(workloads_path, f'{spec}.exe')
+    packaged_config = os.path.join(workloads_path, f'{spec}.config')
+    if os.path.exists(packaged_exe) and os.path.exists(packaged_config):
+        return spec
+
+    abs_spec = os.path.abspath(spec)
+    if is_coremark_source_tree(abs_spec):
+        return build_coremark_workload(abs_spec, workloads_path)
+    if is_coremark_baremetal_source(abs_spec):
+        return build_coremark_baremetal_workload(abs_spec, workloads_path)
+
+    if os.path.exists(abs_spec):
+        if abs_spec.endswith('.ds'):
+            raise ValueError(
+                f'Unsupported workload path: {abs_spec}. '
+                'This is DISC assembly, while examples/minor-cpu executes RV32I images. '
+                'Use the packaged coremark/coremask workload or pass a CoreMark source tree.'
+            )
+        raise ValueError(
+            f'Unsupported workload path: {abs_spec}. '
+            'Currently only packaged workload names and CoreMark source trees are supported.'
+        )
+
+    return spec
+
+
+def write_cycle_summary(rows):
+    summary_path = f'{current_path}/kernel_cycles.csv'
+    with open(summary_path, 'w', newline='') as f:
+        writer = csv.writer(f)
+        writer.writerow(['workload', 'minor_cpu_cycles', 'cycle_source'])
+        for workload, cycles, cycle_source in rows:
+            writer.writerow([workload, cycles, cycle_source])
+    return summary_path
+
+
+def run_workloads(sys, simulator_binary, verilog_path, base_path, workloads, run_verilator_check):
+    rows = []
+    for workload in workloads:
+        init_workspace(base_path, workload)
+        cycles, cycle_source = run_cpu(
+            sys,
+            simulator_binary,
+            verilog_path,
+            workload,
+            run_verilator_check,
+        )
+        rows.append((workload, cycles, cycle_source))
+        print(f'{workload}: cycles={cycles} source={cycle_source}')
+    return rows
+
+def parse_args(argv):
+    parser = argparse.ArgumentParser(
+        description='Run the minor CPU on packaged workloads or a CoreMark source tree.'
+    )
+    parser.add_argument(
+        '--sim-only',
+        '--skip-verilator',
+        dest='sim_only',
+        action='store_true',
+        help='Run the simulator pass only and skip the Verilator check.',
+    )
+    parser.add_argument(
+        'workloads',
+        nargs='*',
+        help='Packaged workload names such as coremark/coremask, or a CoreMark source tree path such as /Users/zhonga/coremark.',
+    )
+    return parser.parse_args(argv)
+
 if __name__ == '__main__':
+    args = parse_args(py_sys.argv[1:])
     # Build the CPU Module only once
     sys, simulator_binary, verilog_path = build_cpu(depth_log=16)
-    args = py_sys.argv[1:]
     print("minor-CPU built successfully!")
     # Define workloads
     wl_path = f'{utils.repo_path()}/examples/minor-cpu/workloads'
-    if not args:
+    run_verilator_check = not args.sim_only
+    if not args.workloads:
         workloads = [
             #'0to100',
             #'median',
@@ -595,11 +842,10 @@ def init_workspace(base_path, case):
             #'towers',
             #'vvadd',
         ]
-        # Iterate workloads
-        for wl in workloads:
-            # Copy workloads to tmp directory and rename to workload.
-            init_workspace(wl_path, wl)
-            run_cpu(sys, simulator_binary, verilog_path, wl)
+        rows = run_workloads(sys, simulator_binary, verilog_path, wl_path, workloads, run_verilator_check)
+        if rows:
+            summary_path = write_cycle_summary(rows)
+            print(f'Kernel cycle summary written to {summary_path}')
         print("minor-CPU workloads ran successfully!")
 
         # ========================================================================================
@@ -632,19 +878,24 @@ def init_workspace(base_path, case):
             'rv32ui-p-sub',
             'rv32ui-p-sw',
             'rv32ui-p-xori',
-            #'rv32ui-p-lbu',#TO DEBUG&TO CHECK
-            #'rv32ui-p-sb',#TO CHECK
+            'rv32ui-p-lbu',
+            'rv32ui-p-sb',
         ]
         tests = f'{utils.repo_path()}/examples/minor-cpu/unit-tests'
         # Iterate test cases
         for case in test_cases:
             # Copy test cases to tmp directory and rename to workload.
             init_workspace(tests, case)
-            run_cpu(sys, simulator_binary, verilog_path)
+            run_cpu(sys, simulator_binary, verilog_path, run_verilator_check=run_verilator_check)
         print("minor-CPU tests ran successfully!")
     else:
         # If user DID specify workloads, run exactly those, skipping default & tests:
-        for wl in args:
-            init_workspace(wl_path, wl)
-            run_cpu(sys, simulator_binary, verilog_path, wl)
+        workloads = []
+        for spec in args.workloads:
+            wl = resolve_workload_case(wl_path, spec)
+            workloads.append(wl)
+        rows = run_workloads(sys, simulator_binary, verilog_path, wl_path, workloads, run_verilator_check)
+        if rows:
+            summary_path = write_cycle_summary(rows)
+            print(f'Kernel cycle summary written to {summary_path}')
         print("Done running user-specified workload(s)!")
diff --git a/examples/minor-cpu/src/memory_access.py b/examples/minor-cpu/src/memory_access.py
index ce12f2037..eda7206f2 100644
--- a/examples/minor-cpu/src/memory_access.py
+++ b/examples/minor-cpu/src/memory_access.py
@@ -5,7 +5,14 @@ class MemoryAccess(Module):
     
     def __init__(self):
         super().__init__(
-            ports={ 'rd': Port(Bits(5)),'mem_ext' : Port(Bits(2)),'result': Port(Bits(32)),'is_mem_read': Port(Bits(1))},
+            ports={
+                'rd': Port(Bits(5)),
+                'mem_size': Port(Bits(2)),
+                'mem_unsigned': Port(Bits(1)),
+                'addr_lsb': Port(Bits(2)),
+                'result': Port(Bits(32)),
+                'is_mem_read': Port(Bits(1)),
+            },
             no_arbiter=True)
         self.name = 'm'
 
@@ -21,32 +28,48 @@ def build(
     ):
         self.timing = 'systolic'
 
-        data_cut = Bits(32)(0)
-        mem_ext = self.mem_ext.pop()
+        mem_size = self.mem_size.pop()
+        mem_unsigned = self.mem_unsigned.pop()
+        addr_lsb = self.addr_lsb.pop()
         result = self.result.pop()
         rd = self.rd.pop()
         is_mem_read = self.is_mem_read.pop()
         data = rdata[0].bitcast(Bits(32))
+
+        is_half = mem_size == Bits(2)(1)
+        is_byte = mem_size == Bits(2)(2)
+
+        byte_data = data[0:7]
+        byte_data = (addr_lsb == Bits(2)(1)).select(data[8:15], byte_data)
+        byte_data = (addr_lsb == Bits(2)(2)).select(data[16:23], byte_data)
+        byte_data = (addr_lsb == Bits(2)(3)).select(data[24:31], byte_data)
+
+        half_data = addr_lsb[1:1].select(data[16:31], data[0:15])
+
+        byte_sign = byte_data[7:7].select(Bits(24)(0xffffff), Bits(24)(0))
+        half_sign = half_data[15:15].select(Bits(16)(0xffff), Bits(16)(0))
+
+        byte_value = mem_unsigned.select(Bits(24)(0).concat(byte_data), byte_sign.concat(byte_data))
+        half_value = mem_unsigned.select(Bits(16)(0).concat(half_data), half_sign.concat(half_data))
+
+        load_value = is_byte.select(byte_value, is_half.select(half_value, data))
+        arg = is_mem_read.select(load_value, result)
+
         with Condition(is_mem_read):
             log("mem.rdata        | 0x{:x}", data)
+            log("mem.loaded       | x{:02} = 0x{:08x}", rd, load_value)
             mem_bypass_reg[0] = rd
-            with Condition(rd != Bits(5)(0)):
-                log("mem.bypass       | x{:02} = 0x{:x}", rd, data)
-                mem_bypass_data[0] = data
+            mem_bypass_data[0] = load_value
 
         with Condition(~is_mem_read):
+            with Condition(rd != Bits(5)(0)):
+                log("mem.pass         | x{:02} = 0x{:08x}", rd, result)
             mem_bypass_reg[0] = Bits(5)(0)
-
-        arg = is_mem_read.select(data, Bits(32)(0))
-        sign = arg[7:7]
-        ext = sign.select(Bits(24)(0xffffff), Bits(24)(0))
-        data_cut = mem_ext[1:1].select( Bits(24)(0).concat(arg[0:7]) , ext.concat(arg[0:7]) )
-        
-        arg = is_mem_read.select(arg, result)
-        arg = mem_ext[0:0].select( data_cut ,arg)
+            mem_bypass_data[0] = Bits(32)(0)
 
         wb_bypass_data[0] = arg
         wb_bypass_reg[0] = rd
 
         wb_bound = writeback.bind(mdata = arg , rd = rd)
-        wb_bound.async_called() 
+        wb_call = wb_bound.async_called()
+        wb_call.bind.set_fifo_depth(mdata=2, rd=2)
diff --git a/examples/minor-cpu/src/nocsr.py b/examples/minor-cpu/src/nocsr.py
index 9f4153a0f..3f859758e 100644
--- a/examples/minor-cpu/src/nocsr.py
+++ b/examples/minor-cpu/src/nocsr.py
@@ -197,6 +197,7 @@ def bypass(bypass_reg, bypass_data, idx, value):
 
         # This `is_memory` hack is to evade rust's overflow check.
         addr = (result.bitcast(UInt(32)) - is_memory.select(offset_reg[0].bitcast(UInt(32)), UInt(32)(0))).bitcast(Bits(32))
+        addr_lsb = addr[0:1]
         request_addr = is_memory.select(addr[2:2+depth_log-1].bitcast(UInt(depth_log)), UInt(depth_log)(0))
 
         with Condition(memory_read):
@@ -205,10 +206,34 @@ def bypass(bypass_reg, bypass_data, idx, value):
         with Condition(memory_write):
             log("mem-write        | addr: 0x{:05x}| line: 0x{:05x} | value: 0x{:08x} | wdada: 0x{:08x}", result, request_addr, a, b)
 
+        byte_wmask = Bits(32)(0x000000ff)
+        byte_wdata = Bits(24)(0).concat(b[0:7])
+        byte_wmask = (addr_lsb == Bits(2)(1)).select(Bits(32)(0x0000ff00), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(1)).select(Bits(16)(0).concat(b[0:7]).concat(Bits(8)(0)), byte_wdata)
+        byte_wmask = (addr_lsb == Bits(2)(2)).select(Bits(32)(0x00ff0000), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(2)).select(Bits(8)(0).concat(b[0:7]).concat(Bits(16)(0)), byte_wdata)
+        byte_wmask = (addr_lsb == Bits(2)(3)).select(Bits(32)(0xff000000), byte_wmask)
+        byte_wdata = (addr_lsb == Bits(2)(3)).select(b[0:7].concat(Bits(24)(0)), byte_wdata)
+
+        half_wmask = addr_lsb[1:1].select(Bits(32)(0xffff0000), Bits(32)(0x0000ffff))
+        half_wdata = addr_lsb[1:1].select(b[0:15].concat(Bits(16)(0)), Bits(16)(0).concat(b[0:15]))
+
+        is_half = signals.mem_size == Bits(2)(1)
+        is_byte = signals.mem_size == Bits(2)(2)
+        store_wmask = is_byte.select(byte_wmask, is_half.select(half_wmask, Bits(32)(0xffffffff)))
+        store_wdata = is_byte.select(byte_wdata, is_half.select(half_wdata, b))
+
         dcache = SRAM(width=32, depth=1<<depth_log, init_file=data)
         dcache.name = 'dcache'
-        dcache.build(we=memory_write, re=memory_read, wdata=b, addr=request_addr)
-        bound = memory.bind(rd = rd,result = signals.link_pc.select(pc0, result), mem_ext = signals.mem_ext)
+        dcache.build(we=memory_write, re=memory_read, wdata=store_wdata, addr=request_addr, wmask=store_wmask)
+        bound = memory.bind(
+            rd=rd,
+            result=signals.link_pc.select(pc0, result),
+            mem_size=signals.mem_size,
+            mem_unsigned=signals.mem_unsigned,
+            addr_lsb=addr_lsb,
+            is_mem_read=memory_read,
+        )
         bound.async_called()
         # with Condition(signals.csr_write):
         #     csr_f[csr_id] = csr_new
diff --git a/examples/minor-cpu/unit-tests/rv32ui-p-lbu.data b/examples/minor-cpu/unit-tests/rv32ui-p-lbu.data
new file mode 100644
index 000000000..ccf4a28dc
--- /dev/null
+++ b/examples/minor-cpu/unit-tests/rv32ui-p-lbu.data
@@ -0,0 +1 @@
+0ff000ff // <begin_signature>:0x2000
diff --git a/examples/minor-cpu/unit-tests/rv32ui-p-sb.data b/examples/minor-cpu/unit-tests/rv32ui-p-sb.data
new file mode 100644
index 000000000..bfde08ab8
--- /dev/null
+++ b/examples/minor-cpu/unit-tests/rv32ui-p-sb.data
@@ -0,0 +1,3 @@
+ef0000aa // <begin_signature>:0x2000
+00000000 // <tdat5>:0x2004
+00000000 // <tdat9>:0x2008
diff --git a/examples/minor-cpu/utils/loader.py b/examples/minor-cpu/utils/loader.py
index aa28a86af..5308bcb97 100755
--- a/examples/minor-cpu/utils/loader.py
+++ b/examples/minor-cpu/utils/loader.py
@@ -1,201 +1,171 @@
 #!/usr/bin/env python3
 
-# This file aims at reading a objdump file and extracting the `.text` and `.data` sections for our CPU execution.
+"""Build `.exe/.data/.config` images for minor-cpu from an ELF/dump pair.
+
+The original loader only handled `.text*` and `.data*`, and assumed `.data`
+was the first non-text alloc section. CoreMark and similar workloads place
+constants in `.rodata/.srodata` and often rely on `.bss/.sbss`, so minor-cpu
+needs a single contiguous non-exec image starting at the lowest alloc
+non-exec address.
+"""
 
-import os
-import sys
 import argparse
+import os
 import subprocess
+import tempfile
 
-parser = argparse.ArgumentParser(description='Extract the `.text` and `.data` sections from the objdump file.')
-parser.add_argument('--fname', type=str, help='The file name a objdump output.', required=True)
-parser.add_argument('--odir', type=str, help='The output directory of the converted file.', default='.')
-parser.add_argument('--exit-tohost', action='store_true', help='Exit to host')
+
+parser = argparse.ArgumentParser(
+    description="Extract text/data images for the minor-cpu workload format."
+)
+parser.add_argument("--fname", type=str, required=True, help="Path to a .dump file.")
+parser.add_argument("--odir", type=str, default=".", help="Output directory.")
+parser.add_argument("--exit-tohost", action="store_true", help="Unused legacy flag.")
 args = vars(parser.parse_args())
 
-fname = args['fname']
-
-print(f'Extracting {fname}...')
-
-offset = 0x80000000
-data_offset = 0
-
-readelf = subprocess.check_output(['riscv64-unknown-elf-readelf', '-S', args['fname'][:-5]]).decode('utf-8')
-readelf = readelf.split('\n')
-for i in readelf:
-    toks = i.strip().split()
-    if not toks:
-        continue
-    if toks[0] == '[':
-        toks[0] = toks[0] + toks[1]
-        toks = [toks[0]] + toks[2:]
-    n = len(toks)
-    if n > 1 and toks[1] == '.data':
-        data_offset = int(toks[3], 16)
-    if n > 0 and toks[0] == '[1]':
-        offset = int(toks[3], 16)
-
-data_offset = data_offset - offset
-assert data_offset % 4 == 0
-
-bin_name = os.path.split(fname)[-1]
-
-if bin_name.endswith('.riscv.dump'):
-    strip_bin = bin_name[:-10]
-elif bin_name.endswith('.dump'):
-    strip_bin = bin_name[:-4]
-else:
-    strip_bin = bin_name
 
-with open(args['odir'] + '/' + strip_bin + 'config', 'w') as f:
-    f.write(f'{{ "offset": {hex(offset)}, "data_offset": {hex(data_offset)} }}')
+def derive_elf_path(fname: str) -> str:
+    candidates = [fname]
+    if fname.endswith(".dump"):
+        base = fname[:-5]
+        candidates = [base, base + ".elf"]
+        if base.endswith(".riscv"):
+            candidates.extend([base[:-6], base[:-6] + ".elf"])
+    for path in candidates:
+        if os.path.exists(path):
+            return path
+    return candidates[0]
 
-text, data = [], []
 
-section = ''
-func = ''
-func_tagged = False
+def derive_output_stem(fname: str) -> str:
+    bin_name = os.path.split(fname)[-1]
+    if bin_name.endswith(".riscv.dump"):
+        return bin_name[: -len(".riscv.dump")]
+    if bin_name.endswith(".dump"):
+        return bin_name[: -len(".dump")]
+    return bin_name
 
-def parse_payload(line):
-    global func, func_tagged
-    # Each line uses \t to balance the visual effect, so we need to realign the lines
-    # by replacing them with spaces.
-    realign = []
-    for i in line:
-        if i != '\t':
-            realign.append(i)
-        elif len(realign) % 8 == 0:
-            realign.append(' ' * 8)
-        else:
-            while len(realign) % 8 != 0:
-                realign.append(' ')
-    realign = ''.join(realign)
 
-    # After 40 characters, they are all semantic comments, so we ignore for payload.
-    toks = realign[:39].split()
-    # But retain for readability hints
-    comment = realign[39:]
+def parse_sections(elf_path: str) -> list[dict]:
+    raw = subprocess.check_output(
+        ["riscv64-unknown-elf-readelf", "-S", "-W", elf_path]
+    ).decode("utf-8")
 
-    addr = int(toks[0][:-1], 16) - offset
+    res = []
+    for line in raw.splitlines():
+        toks = line.strip().split()
+        if not toks:
+            continue
+        if toks[0] == "[":
+            toks = [toks[0] + toks[1]] + toks[2:]
+        if not toks[0].startswith("[") or not toks[0].endswith("]"):
+            continue
+        sec_id = toks[0][1:-1]
+        if not sec_id.isdigit():
+            continue
+        if len(toks) < 8:
+            continue
+
+        res.append(
+            {
+                "name": toks[1],
+                "type": toks[2],
+                "addr": int(toks[3], 16),
+                "off": int(toks[4], 16),
+                "size": int(toks[5], 16),
+                "flags": toks[7],
+            }
+        )
+    return res
 
-    payload = toks[1:]
 
-    res = []
+def dump_section_bytes(elf_path: str, section_name: str) -> bytes:
+    with tempfile.TemporaryDirectory() as tmpdir:
+        out_path = os.path.join(tmpdir, "section.bin")
+        subprocess.check_call(
+            [
+                "riscv64-unknown-elf-objcopy",
+                f"--dump-section",
+                f"{section_name}={out_path}",
+                elf_path,
+            ],
+            stdout=subprocess.DEVNULL,
+            stderr=subprocess.DEVNULL,
+        )
+        with open(out_path, "rb") as f:
+            return f.read()
 
-    j = 0
-    for value in payload:
-        try:
-            int(value, 16)
-            if len(value) == 4:
-                res.append([addr + 2 * j, int(value, 16), ''])
-                j += 1
-            elif len(value) == 8:
-                res.append([addr + 2 * j, int(value[4:], 16), ''])
-                res.append([addr + 2 * j + 2, int(value[:4], 16), ''])
-                j += 2
-        except:
-            # TODO(@were): Fix unaligned addresses for byte-level operations.
-            print(value, 'is heuristically terminated')
-            break
-
-    if not func_tagged:
-        comment = comment + ' ' + func
-        func_tagged = True
-
-    if res:
-        res[-1][-1] = comment
 
-    return res
+def build_image(elf_path: str, sections: list[dict]) -> tuple[int, bytearray]:
+    if not sections:
+        return 0, bytearray()
 
-with open(fname) as f:
-    raw = f.readlines()
-    for line in raw:
-        line = line.strip()
-        toks = line.split()
-        n = len(toks)
-        # Parse the section line
-        if n == 4 and toks[0] == 'Disassembly' and toks[1] == 'of' and toks[2] == 'section':
-            section = toks[-1]
-            func = None
-        # Parse the symbol line, it can be either a function or a array id
-        elif n == 2 and toks[1].startswith('<') and toks[1].endswith('>:'):
-            func = toks[1]
-            func_tagged = False
-        # If we are in a general `.text` section, including all sections named `.text*`,
-        # like `text.startup`, `text.init`, etc. Load them into the text buffer.
-        elif section.startswith('.text') and n >= 2:
-            delta = parse_payload(line)
-            text += delta 
-        # If we are in a `.data` section, load the data into the data buffer.
-        elif section.startswith('.data') and n >= 2:
-            delta = parse_payload(line)
-            data += delta
-        elif len(toks) > 1:
-            print(line)
-
-text.sort()
-data.sort()
-
-zero_padding = '0 // padding'
-
-def coalesce_words(a):
-    res = []
-    i = 0
-    n = len(a)
-    while i < len(a):
-        residue = a[i][0] % 4
-        # If it is aligned by 4, it is a start of coalescing.
-        if residue == 0:
-            # If it has following data to coalesce, combine those two into one.
-            if i + 1 < n and a[i][0] + 2 == a[i + 1][0]:
-                res.append((a[i][0], a[i + 1][1] << 16 | a[i][1], a[i][2] + ' | ' + a[i + 1][2]))
-            # If not, the high 16-bit is already implicitly zero, so just leave it.
-            else:
-                res.append(a[i])
-            i += 2
-        else:
-            # If it is not aligned by 4, it is the high 16-bit of coalescing. We pad the low 16-bit with zero.
-            res.append((a[i][0] - residue, a[i][1] << 16, a[i][2]))
-            i += 1
-
-    uniq_n = len(set(i for i, _, _ in res))
-    n = len(res)
-    assert uniq_n == n, f'{uniq_n} {n}'
-    return res
+    base = min(sec["addr"] for sec in sections)
+    end = max(sec["addr"] + sec["size"] for sec in sections)
+    image = bytearray(end - base)
+
+    for sec in sections:
+        if sec["size"] == 0:
+            continue
+        if sec["type"] == "NOBITS":
+            continue
+        payload = dump_section_bytes(elf_path, sec["name"])
+        assert len(payload) == sec["size"], (
+            f"Section size mismatch for {sec['name']}: "
+            f"read {len(payload)} bytes, expected {sec['size']}"
+        )
+        start = sec["addr"] - base
+        image[start : start + sec["size"]] = payload
+
+    return base, image
+
+
+def write_word_image(path: str, image: bytearray, max_words: int = 1 << 16) -> None:
+    if not image:
+        open(path, "w").write("")
+        return
 
+    if len(image) % 4 != 0:
+        image.extend(b"\x00" * (4 - (len(image) % 4)))
 
-# Test section is easy, just dump all the loaded instructions, which are 4-byte aligned.
+    words = len(image) // 4
+    assert words <= max_words, f"Image too large for SRAM: {words} words > {max_words}"
 
-assert text
-coalesced = coalesce_words(text)
+    with open(path, "w") as f:
+        for i in range(0, len(image), 4):
+            word = int.from_bytes(image[i : i + 4], byteorder="little", signed=False)
+            f.write(f"{word:08x}\n")
 
-assert coalesced[-1][0] // 4 + 1 < 16000, f'{coalesced[-1][0] // 4 + 1}'
 
-buffer = [zero_padding] * (coalesced[-1][0] // 4 + 1)
+fname = args["fname"]
+elf_path = derive_elf_path(fname)
+stem = derive_output_stem(fname)
 
-for addr, inst, comment in coalesced:
-    inst = hex(inst)
-    inst = (10 - len(inst)) * '0' + inst[2:]
-    buffer[addr // 4] = inst + ' // ' + comment
+print(f"Extracting {fname} (ELF: {elf_path})...")
 
+sections = parse_sections(elf_path)
 
-ofile = args['odir'] + '/' + strip_bin
-with open(ofile + 'exe', 'w') as f:
-    f.write('\n'.join(buffer))
+text_sections = [
+    sec for sec in sections if "A" in sec["flags"] and "X" in sec["flags"] and sec["size"] > 0
+]
+data_sections = [
+    sec for sec in sections if "A" in sec["flags"] and "X" not in sec["flags"] and sec["size"] >= 0
+]
+
+assert text_sections, f"No alloc+exec sections found in {elf_path}"
+
+text_base, text_image = build_image(elf_path, text_sections)
+
+if data_sections:
+    data_base, data_image = build_image(elf_path, data_sections)
+else:
+    data_base, data_image = 0, bytearray()
 
-if data:
-    # This is tricky to coalesce the data section from 2-byte to 4-byte.
-    # We do this 2-byte by 2-byte.
-    coalesced = coalesce_words(data)
+data_offset = data_base - text_base
 
-    assert coalesced[-1][0] // 4 + 1 < 160000
+ofile = os.path.join(args["odir"], stem)
+with open(ofile + "config", "w") as f:
+    f.write(f'{{ "offset": {hex(text_base)}, "data_offset": {hex(data_offset)} }}')
 
-    buffer = [zero_padding] * (coalesced[-1][0] // 4 + 1)
-    for addr, value, comment in coalesced:
-        assert addr % 4 == 0
-        value = hex(value)[2:]
-        # value = (10 - len(value)) * '0' + value[2:]
-        buffer[addr // 4] = value + ' // ' + comment + hex(addr)
-    
-    with open(ofile + 'data', 'w') as f:
-        f.write('\n'.join(buffer[data_offset // 4:]))
+write_word_image(ofile + "exe", text_image)
+write_word_image(ofile + "data", data_image)
diff --git a/examples/minor-cpu/workloads/build_coremark.sh b/examples/minor-cpu/workloads/build_coremark.sh
new file mode 100755
index 000000000..e5e046ad8
--- /dev/null
+++ b/examples/minor-cpu/workloads/build_coremark.sh
@@ -0,0 +1,52 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+workloads_dir=$(cd "$(dirname "$0")" && pwd)
+repo_root=$(cd "$workloads_dir/../../.." && pwd)
+coremark_src="${COREMARK_SRC:-}"
+
+if [[ ! -d "$coremark_src" ]]; then
+  echo "Set COREMARK_SRC to a CoreMark source tree." >&2
+  exit 1
+fi
+
+out_prefix="$workloads_dir/coremark"
+
+riscv64-unknown-elf-gcc \
+  -O2 \
+  -std=c11 \
+  -march=rv32i \
+  -mabi=ilp32 \
+  -msmall-data-limit=0 \
+  -ffreestanding \
+  -fno-builtin \
+  -fno-pic \
+  -fno-common \
+  -ffunction-sections \
+  -fdata-sections \
+  -DTOTAL_DATA_SIZE=2000 \
+  -DITERATIONS=1 \
+  -DMAIN_HAS_NOARGC=1 \
+  -DHAS_FLOAT=0 \
+  -DHAS_STDIO=0 \
+  -DHAS_PRINTF=0 \
+  -I"$coremark_src" \
+  -I"$workloads_dir" \
+  -nostdlib \
+  -nostartfiles \
+  -Wl,-T,"$workloads_dir/coremark.ld" \
+  -Wl,-e,_start \
+  -Wl,--gc-sections \
+  -o "$out_prefix.elf" \
+  "$coremark_src/core_list_join.c" \
+  "$coremark_src/core_main.c" \
+  "$coremark_src/core_matrix.c" \
+  "$coremark_src/core_state.c" \
+  "$coremark_src/core_util.c" \
+  "$workloads_dir/coremark_portme.c" \
+  "$workloads_dir/coremark_ee_printf.c" \
+  "$workloads_dir/coremark_start.c" \
+  -lgcc
+
+riscv64-unknown-elf-objdump -D "$out_prefix.elf" > "$out_prefix.dump"
+python3 "$repo_root/examples/minor-cpu/utils/loader.py" --fname "$out_prefix.dump" --odir "$workloads_dir"
diff --git a/examples/minor-cpu/workloads/build_coremark_baremetal.sh b/examples/minor-cpu/workloads/build_coremark_baremetal.sh
new file mode 100755
index 000000000..cd501bd13
--- /dev/null
+++ b/examples/minor-cpu/workloads/build_coremark_baremetal.sh
@@ -0,0 +1,45 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+workloads_dir=$(cd "$(dirname "$0")" && pwd)
+repo_root=$(cd "$workloads_dir/../../.." && pwd)
+coremark_baremetal_src="${COREMARK_BAREMETAL_SRC:-}"
+
+if [[ ! -f "$coremark_baremetal_src" ]]; then
+  echo "Set COREMARK_BAREMETAL_SRC to a CoreMark bare-metal source file." >&2
+  exit 1
+fi
+
+out_prefix="$workloads_dir/coremark_baremetal"
+
+riscv64-unknown-elf-gcc \
+  -O2 \
+  -std=c11 \
+  -march=rv32i \
+  -mabi=ilp32 \
+  -msmall-data-limit=0 \
+  -ffreestanding \
+  -fno-builtin \
+  -fno-pic \
+  -fno-common \
+  -ffunction-sections \
+  -fdata-sections \
+  -DTOTAL_DATA_SIZE=2000 \
+  -DITERATIONS=1 \
+  -DMAIN_HAS_NOARGC=1 \
+  -DHAS_FLOAT=0 \
+  -DHAS_STDIO=0 \
+  -DHAS_PRINTF=0 \
+  -DCOREMARK_SIMULATOR=1 \
+  -nostdlib \
+  -nostartfiles \
+  -Wl,-T,"$workloads_dir/coremark.ld" \
+  -Wl,-e,_start \
+  -Wl,--gc-sections \
+  -o "$out_prefix.elf" \
+  "$coremark_baremetal_src" \
+  "$workloads_dir/coremark_baremetal_start.c" \
+  -lgcc
+
+riscv64-unknown-elf-objdump -D "$out_prefix.elf" > "$out_prefix.dump"
+python3 "$repo_root/examples/minor-cpu/utils/loader.py" --fname "$out_prefix.dump" --odir "$workloads_dir"
diff --git a/examples/minor-cpu/workloads/core_portme.h b/examples/minor-cpu/workloads/core_portme.h
new file mode 100644
index 000000000..f1e481860
--- /dev/null
+++ b/examples/minor-cpu/workloads/core_portme.h
@@ -0,0 +1 @@
+#include "coremark_portme.h"
diff --git a/examples/minor-cpu/workloads/coremark.config b/examples/minor-cpu/workloads/coremark.config
new file mode 100644
index 000000000..76f8030e4
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark.config
@@ -0,0 +1 @@
+{ "offset": 0x0, "data_offset": 0x4000 }
\ No newline at end of file
diff --git a/examples/minor-cpu/workloads/coremark.data b/examples/minor-cpu/workloads/coremark.data
new file mode 100644
index 000000000..bdbd2133d
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark.data
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diff --git a/examples/minor-cpu/workloads/coremark.exe b/examples/minor-cpu/workloads/coremark.exe
new file mode 100644
index 000000000..54bf47fee
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark.exe
@@ -0,0 +1,2717 @@
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diff --git a/examples/minor-cpu/workloads/coremark.ld b/examples/minor-cpu/workloads/coremark.ld
new file mode 100644
index 000000000..dbeeb5708
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark.ld
@@ -0,0 +1,39 @@
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+    . = 0x00000000;
+
+    .text : ALIGN(4)
+    {
+        *(.text.init)
+        *(.text.startup)
+        *(.text*)
+    }
+
+    . = 0x00004000;
+
+    .data : ALIGN(4)
+    {
+        *(.rodata*)
+        *(.srodata*)
+        *(.data*)
+        *(.sdata*)
+    }
+
+    .bss : ALIGN(4)
+    {
+        __bss_start = .;
+        *(.sbss*)
+        *(.bss*)
+        *(COMMON)
+        __bss_end = .;
+    }
+
+    . = ALIGN(16);
+    _end = .;
+
+    PROVIDE(__global_pointer$ = 0x00004800);
+    PROVIDE(__stack_top = 0x0003fe00);
+}
diff --git a/examples/minor-cpu/workloads/coremark.sh b/examples/minor-cpu/workloads/coremark.sh
new file mode 100755
index 000000000..a8064f404
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark.sh
@@ -0,0 +1,7 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+logfile=$1
+
+rg -n "ebreak \| halt \| ecall|trap" "$logfile" > /dev/null
+rg -n "mem-write        \| addr: 0x3ff08\|.*wdada: 0x7fffffff" "$logfile" > /dev/null
diff --git a/examples/minor-cpu/workloads/coremark_baremetal.sh b/examples/minor-cpu/workloads/coremark_baremetal.sh
new file mode 100755
index 000000000..66f7b75fa
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark_baremetal.sh
@@ -0,0 +1,9 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+logfile=$1
+
+rg -n "ebreak \| halt \| ecall|trap" "$logfile" > /dev/null
+rg -n "mem-write        \| addr: 0x3ff08\|.*wdada: 0x7fffffff" "$logfile" > /dev/null
+rg -n "mem-write        \| addr: 0x3ff24\|.*wdada: 0x00000000" "$logfile" > /dev/null
+rg -n "mem-write        \| addr: 0x3ff0c\|.*wdada: 0x0000e9f5" "$logfile" > /dev/null
diff --git a/examples/minor-cpu/workloads/coremark_baremetal_start.c b/examples/minor-cpu/workloads/coremark_baremetal_start.c
new file mode 100644
index 000000000..c223d8fa2
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark_baremetal_start.c
@@ -0,0 +1,40 @@
+#include <stdint.h>
+
+extern int main(void);
+
+extern volatile uint16_t coremark_seedcrc_result;
+extern volatile uint16_t coremark_crclist_result;
+extern volatile uint16_t coremark_crcmatrix_result;
+extern volatile uint16_t coremark_crcstate_result;
+extern volatile uint16_t coremark_crcfinal_result;
+extern volatile int16_t coremark_total_errors_result;
+extern volatile uint32_t coremark_total_ticks_result;
+
+static inline void mmio_write(uint32_t addr, uint32_t value)
+{
+    *(volatile uint32_t *)addr = value;
+}
+
+__attribute__((section(".text.init")))
+void _start(void)
+{
+    __asm__ volatile("la gp, __global_pointer$");
+    __asm__ volatile("la sp, __stack_top");
+
+    mmio_write(0x0003ff00u, 1u);
+    (void)main();
+    mmio_write(0x0003ff04u, 2u);
+
+    mmio_write(0x0003ff0cu, coremark_seedcrc_result);
+    mmio_write(0x0003ff10u, coremark_crclist_result);
+    mmio_write(0x0003ff14u, coremark_crcmatrix_result);
+    mmio_write(0x0003ff18u, coremark_crcstate_result);
+    mmio_write(0x0003ff1cu, coremark_crcfinal_result);
+    mmio_write(0x0003ff20u, coremark_total_ticks_result);
+    mmio_write(0x0003ff24u, (uint32_t)(int32_t)coremark_total_errors_result);
+    mmio_write(0x0003ff08u,
+               (coremark_total_errors_result == 0) ? 0x7fffffffu : 0u);
+
+    __asm__ volatile("ebreak");
+    while (1) { }
+}
diff --git a/examples/minor-cpu/workloads/coremark_ee_printf.c b/examples/minor-cpu/workloads/coremark_ee_printf.c
new file mode 100644
index 000000000..82d33eaa1
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark_ee_printf.c
@@ -0,0 +1,55 @@
+#include "coremark.h"
+
+#include <stdarg.h>
+
+volatile ee_u32 coremark_status = 0;
+
+enum
+{
+    COREMARK_STATUS_OK = 0x7fffffff,
+    COREMARK_STATUS_GENERIC_ERROR = 1,
+    COREMARK_STATUS_LIST_ERROR = 2,
+    COREMARK_STATUS_MATRIX_ERROR = 3,
+    COREMARK_STATUS_STATE_ERROR = 4,
+    COREMARK_STATUS_UNVALIDATED = 5,
+};
+
+static int starts_with(const char *text, const char *prefix)
+{
+    while (*prefix != '\0')
+    {
+        if (*text != *prefix)
+            return 0;
+        text++;
+        prefix++;
+    }
+    return 1;
+}
+
+int ee_printf(const char *fmt, ...)
+{
+    va_list args;
+
+    va_start(args, fmt);
+    va_end(args);
+
+    if (starts_with(fmt, "Correct operation validated"))
+        coremark_status = COREMARK_STATUS_OK;
+    else if (starts_with(fmt, "[%u]ERROR! list crc"))
+        coremark_status = COREMARK_STATUS_LIST_ERROR;
+    else if (starts_with(fmt, "[%u]ERROR! matrix crc"))
+        coremark_status = COREMARK_STATUS_MATRIX_ERROR;
+    else if (starts_with(fmt, "[%u]ERROR! state crc"))
+        coremark_status = COREMARK_STATUS_STATE_ERROR;
+    else if (starts_with(fmt, "Errors detected"))
+    {
+        if (coremark_status == 0)
+            coremark_status = COREMARK_STATUS_GENERIC_ERROR;
+    }
+    else if (starts_with(fmt, "Cannot validate operation"))
+        coremark_status = COREMARK_STATUS_UNVALIDATED;
+    else if (starts_with(fmt, "ERROR"))
+        coremark_status = COREMARK_STATUS_GENERIC_ERROR;
+
+    return 0;
+}
diff --git a/examples/minor-cpu/workloads/coremark_portme.c b/examples/minor-cpu/workloads/coremark_portme.c
new file mode 100644
index 000000000..ac86a6d99
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark_portme.c
@@ -0,0 +1,58 @@
+#include "coremark.h"
+#include "coremark_portme.h"
+
+#if VALIDATION_RUN
+volatile ee_s32 seed1_volatile = 0x3415;
+volatile ee_s32 seed2_volatile = 0x3415;
+volatile ee_s32 seed3_volatile = 0x66;
+#endif
+#if PERFORMANCE_RUN
+volatile ee_s32 seed1_volatile = 0x0;
+volatile ee_s32 seed2_volatile = 0x0;
+volatile ee_s32 seed3_volatile = 0x66;
+#endif
+#if PROFILE_RUN
+volatile ee_s32 seed1_volatile = 0x8;
+volatile ee_s32 seed2_volatile = 0x8;
+volatile ee_s32 seed3_volatile = 0x8;
+#endif
+
+volatile ee_s32 seed4_volatile = ITERATIONS;
+volatile ee_s32 seed5_volatile = 0;
+
+static CORETIMETYPE start_time_val;
+static CORETIMETYPE stop_time_val;
+
+void start_time(void)
+{
+    start_time_val = 0;
+}
+
+void stop_time(void)
+{
+    stop_time_val = 10;
+}
+
+CORE_TICKS get_time(void)
+{
+    return (CORE_TICKS)(stop_time_val - start_time_val);
+}
+
+secs_ret time_in_secs(CORE_TICKS ticks)
+{
+    return (secs_ret)ticks;
+}
+
+ee_u32 default_num_contexts = 1;
+
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+    (void)argc;
+    (void)argv;
+    p->portable_id = 1;
+}
+
+void portable_fini(core_portable *p)
+{
+    p->portable_id = 0;
+}
diff --git a/examples/minor-cpu/workloads/coremark_portme.h b/examples/minor-cpu/workloads/coremark_portme.h
new file mode 100644
index 000000000..7ffde70c6
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark_portme.h
@@ -0,0 +1,109 @@
+/*
+ * Minimal CoreMark port for assassyn/examples/minor-cpu.
+ */
+
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+
+#include <stddef.h>
+
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 0
+#endif
+
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 0
+#endif
+
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+
+#ifndef HAS_STDIO
+#define HAS_STDIO 0
+#endif
+
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 0
+#endif
+
+#ifndef COMPILER_VERSION
+#ifdef __GNUC__
+#define COMPILER_VERSION "GCC " __VERSION__
+#else
+#define COMPILER_VERSION "unknown"
+#endif
+#endif
+
+#ifndef COMPILER_FLAGS
+#define COMPILER_FLAGS "rv32i minor-cpu"
+#endif
+
+#ifndef MEM_LOCATION
+#define MEM_LOCATION "STACK"
+#endif
+
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef double ee_f32;
+typedef ee_u32 ee_ptr_int;
+typedef size_t ee_size_t;
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3))
+
+#define CORETIMETYPE ee_u32
+typedef ee_u32 CORE_TICKS;
+
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_STACK
+#endif
+
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#define USE_PTHREAD 0
+#define USE_FORK 0
+#define USE_SOCKET 0
+#endif
+
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 1
+#endif
+
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+extern ee_u32 default_num_contexts;
+
+typedef struct CORE_PORTABLE_S
+{
+    ee_u8 portable_id;
+} core_portable;
+
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN)
+#if (TOTAL_DATA_SIZE == 1200)
+#define PROFILE_RUN 1
+#elif (TOTAL_DATA_SIZE == 2000)
+#define PERFORMANCE_RUN 1
+#else
+#define VALIDATION_RUN 1
+#endif
+#endif
+
+int ee_printf(const char *fmt, ...);
+
+#endif
diff --git a/examples/minor-cpu/workloads/coremark_start.c b/examples/minor-cpu/workloads/coremark_start.c
new file mode 100644
index 000000000..3c5782d86
--- /dev/null
+++ b/examples/minor-cpu/workloads/coremark_start.c
@@ -0,0 +1,25 @@
+#include <stdint.h>
+
+extern int main(void);
+extern volatile uint32_t coremark_status;
+extern char __stack_top[];
+
+static inline void mmio_write(uint32_t addr, uint32_t value)
+{
+    *(volatile uint32_t *)addr = value;
+}
+
+__attribute__((section(".text.init")))
+void _start(void)
+{
+    __asm__ volatile("la gp, __global_pointer$");
+    __asm__ volatile("la sp, __stack_top");
+
+    mmio_write(0x0003ff00u, 1u);
+    (void)main();
+    mmio_write(0x0003ff04u, 2u);
+    mmio_write(0x0003ff08u, coremark_status);
+
+    __asm__ volatile("ebreak");
+    while (1) { }
+}

From 693ece51598d2c4491efd9c2486ffd2213bdb2af Mon Sep 17 00:00:00 2001
From: An Zhong <zhonga@kl-28432.kaust.edu.sa>
Date: Tue, 9 Jun 2026 14:52:47 +0800
Subject: [PATCH 2/2] [codegen] Support PyCDE pass phase filtering.

[python] Filter lower ESI passes through either FINAL_LOWERING_PASSES or PASS_PHASES so generated Verilog designs work across PyCDE pass-list APIs.

[tests] Update the generated header test to cover the compatibility block.
---
 python/assassyn/codegen/verilog/top.py                | 10 ++++++----
 python/unit-tests/codegen/test_pycde_header_import.py |  4 +++-
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/python/assassyn/codegen/verilog/top.py b/python/assassyn/codegen/verilog/top.py
index a6d6f3241..8b55ffe5d 100644
--- a/python/assassyn/codegen/verilog/top.py
+++ b/python/assassyn/codegen/verilog/top.py
@@ -545,10 +545,12 @@ def _attach_external_values(module, port_map, handled_ports):
     dumper.indent -= 8
     dumper.append_code('')
     dumper.append_code('system = System([Top], name="Top", output_directory="sv")')
-    dumper.append_code('System.FINAL_LOWERING_PASSES = [')
-    dumper.append_code('    entry for entry in System.FINAL_LOWERING_PASSES')
-    dumper.append_code('    if "lower-esi-" not in str(entry)')
-    dumper.append_code(']')
+    dumper.append_code('for _passes_attr in ("FINAL_LOWERING_PASSES", "PASS_PHASES"):')
+    dumper.append_code('    if hasattr(System, _passes_attr):')
+    dumper.append_code('        setattr(System, _passes_attr, [')
+    dumper.append_code('            entry for entry in getattr(System, _passes_attr)')
+    dumper.append_code('            if "lower-esi-" not in str(entry)')
+    dumper.append_code('        ])')
 
     # Copying of external SystemVerilog files occurs during elaboration.
 
diff --git a/python/unit-tests/codegen/test_pycde_header_import.py b/python/unit-tests/codegen/test_pycde_header_import.py
index 897eb3ed1..4705c91b8 100644
--- a/python/unit-tests/codegen/test_pycde_header_import.py
+++ b/python/unit-tests/codegen/test_pycde_header_import.py
@@ -33,5 +33,7 @@ def build(self):
     assert "from assassyn.pycde_wrapper import FIFO, TriggerCounter, build_register_file" in text
     assert "class FIFOImpl(Module):" not in text
     assert "class TriggerCounterImpl(Module):" not in text
-    assert "System.FINAL_LOWERING_PASSES = [" in text
+    assert 'for _passes_attr in ("FINAL_LOWERING_PASSES", "PASS_PHASES"):' in text
+    assert "hasattr(System, _passes_attr)" in text
+    assert "getattr(System, _passes_attr)" in text
     assert 'if "lower-esi-" not in str(entry)' in text