Need better way to handle TP without resorting to DNP of the physical pin

[ringof]

As of 255bd36 I had to do-not-populate all of the test points because they are footprints bound to actual 0.1" header pins. I was driving to the mechanical/3D work, so I just directly DNP'ed them:

Need a better way to handle a non-populated testpoint so these large cross-outs go away

[turnisland]

Agree. These aren't even intended for pins (although pins will fit and can be useful). But the TP is a plated hole, not a real component. I don't know how to fix this, I usually ignore the warning. It looks like the latest schematic now has these as "exclude from BOM", but still "populated". Doesn't JLC complain about a component being in the placement file but not in the BOM?

[ringof]

I sorted something out already - essentially what you say here; I’m behind in my issue updates… David Goncalves

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On Sat, Aug 1, 2026 at 12:34 PM Turn Island Systems < ***@***.***> wrote: *turnisland* left a comment (TAPR/TAPRx888#54) <#54 (comment)> Agree. These aren't even intended for pins (although pins will fit and can be useful). But the TP is a plated hole, not a real component. I don't know how to fix this, I usually ignore the warning. It looks like the latest schematic now has these as "exclude from BOM", but still "populated". Doesn't JLC complain about a component being in the placement file but not in the BOM? — Reply to this email directly, view it on GitHub <#54?email_source=notifications&email_token=ABPGBFWTDVQGGCDAH2OOV4L5HZA27A5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTKMJVGMYDOMBXHA42M4TFMFZW63VGMF2XI2DPOKSWK5TFNZ2KYZTPN52GK4S7MNWGSY3L#issuecomment-5153070789>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABPGBFSFXCDXO5EWSD7GEY35HZA27AVCNFSNUABGKJSXA33TNF2G64TZHMYTENBTHA3DQMZWGY5US43TOVSTWNBZHAZDEOBSHE3DJILWAI> . You are receiving this because you authored the thread.Message ID: ***@***.***>