diff --git a/documentation/README.txt b/documentation/README.txt new file mode 100644 index 00000000..889b3c24 --- /dev/null +++ b/documentation/README.txt @@ -0,0 +1,20 @@ +These files were written by Marco Merlini (marco.merlini@utoronto.ca), who is +not the official maintainer of this repository. They are a summary of his +personal notes from using Galapagos. + +For Galapagos users: + + galapagos_flow.txt explains the design flow of using Galapagos + + +For Galapagos developers: + + file_reference.txt tries to disambiguate the utility of each script + packaged in this reposiitory + + adding_vivado_versions.txt gives a general method for extending Galapagos + to work with new versions of Vivado. Your mileage may vary. + + shell_development.txt explains how to add support for new boards in + Galapagos + diff --git a/documentation/galapagos_flow.txt b/documentation/galapagos_flow.txt new file mode 100644 index 00000000..8d83fca8 --- /dev/null +++ b/documentation/galapagos_flow.txt @@ -0,0 +1,122 @@ +=========================== +DEFINITIONS AND ASSUMPTIONS +=========================== + +In this file, $GALAPDIR will refer to the root directory of the Galapagos +repository. (Note: this is not an environment variable used by Galapagos; it is +a placeholder for you to replace yourself) + +$BOARD will refer to the name of the currently targeted board. + +All commands are assumed to be run from inside $GALAPDIR (unless otherwise +stated). + +A "kernel" means a single user module in the Galapagos cluster, analogous to a +Rank in MPI. + + +======== +OVERVIEW +======== + +The following numbered list explains the brief details of using Galapagos. More +details are provided in the later sections of this document. There is also a +quick blurb on writing kernels in HLS. + +When first installing Galapagos, + + 1) Run `$GALAPDIR/build.sh` and answer all its questions + +For each board you wish to use, + + 2) Use `galapagos_update_board ` to select the board, and + + 3) Run `make hlsmiddleware` from inside $GALAPDIR + +To create a Galapagos project, + + 4) Package kernels as IPs and place them in $GALAPDIR/hlsBuild/$BOARD/ip, + where $BOARD is the board that the IP is targeted for. + -> Use this directory even if your kernel is not written in HLS + + 5) Write a logical file and a mapping file (details provided below) + + 6) Set the LOGICALFILE and MAPFILE environment variables to be the full + path of your logical file and mapping file (repsectively). Also set the + PROJECTNAME environment variable to be the desired project name + + 7) Run `make middleware` from inside $GALAPDIR + + 8) If there were no errors, Galapagos will have created a directory called + $GALAPDIR/projects/$PROJECTNAME which contains a number of TCL scripts + and a bash script called createCluster.sh. Simply run this shell script + and wait for Vivado to produce your bitstream(s). + + +=============================== +WHEN FIRST INSTALLING GALAPAGOS +=============================== + +For the time being, Galapagos works by reading a number of environment +variables. Run + + $ cd $GALAPDIR + $ source build.sh + +This will bring up a snazzy menu. Answer its questions. Don't worry about +making a mistake; you can always try this again if it doesn't work. + +Once you have finished answering the questions, Galapgos will have created a +new file in your home folder. You can take a look at it: + + $ less ~/.galapagos + +This file simply sets Galapagos's environment variables using the answers you +provided earlier. It also defines two bash shell functions: +galapagos-update-board and galapagos-update-version. The first function allows +you ask Galapagos to target a different board without re-running build.sh, and +the second lets you select a different Vivado version. + +Finally, note that build.sh adds a line to your .bashrc: + + $ less ~/.bashrc + +This ensures that .galapagos is called whenever you open a new bash shell. + + +============================== +FOR EACH BOARD YOU PLAN TO USE +============================== + +Galapagos uses a number of custom IP cores written in HLS. These must be +synthesized and packaged as IPs before you can start making your own projects. + +Run the following from inside $GALAPDIR: + + $ galapagos-update-board + $ make hlsmiddleware + +Currently, Galapagos supports the following choices for : + + - zynq-p2 + - zedboard + - sidewinder + - adm-8k5 + - adm-8k5-debug + + +====================== +WRITING KERNELS IN HLS +====================== + +Include the header file in $GALAPDIR/middleware/include/galapagos_packet.h + +The following is a skeleton of an HLS Galapagos kernel: + + (TODO) + + +===================== +CREATING YOUR PROJECT +===================== + diff --git a/examples/hello_world/Makefile b/examples/hello_world/Makefile new file mode 100644 index 00000000..a37a39db --- /dev/null +++ b/examples/hello_world/Makefile @@ -0,0 +1,42 @@ +all: hello_world world middleware pick_up_vivados_dirty_socks + +hello_world: .hello_world +.hello_world: hello_world.cpp + vivado_hls hello_world.tcl + touch .hello_world + +world: .world +.world: world.cpp + vivado_hls world.tcl + touch .world + +middleware: .middleware +.middleware: logical.xml mapping.xml .hello_world .world + export LOGICALFILE=$(shell realpath logical.xml) + export MAPFILE=$(shell realpath mapping.xml) + export PROJECTNAME=hello_world + make -C$(GALAPAGOS_PATH) middleware + touch .middleware + +pick_up_vivados_dirty_socks: + # Cleaning up after Vivado... + rm -rf vivado* + +show_reports: + less $(GALAPAGOS_PATH)/hlsBuild/$(GALAPAGOS_BOARD_NAME)/ip/hello_world/solution1/syn/report/hello_world_csynth.rpt + less $(GALAPAGOS_PATH)/hlsBuild/$(GALAPAGOS_BOARD_NAME)/ip/world/solution1/syn/report/world_csynth.rpt + +clean: + rm -rf $(GALAPAGOS_PATH)/hlsBuild/$(GALAPAGOS_BOARD_NAME)/ip/hello_world/ + rm -rf $(GALAPAGOS_PATH)/hlsBuild/$(GALAPAGOS_BOARD_NAME)/ip/world/ + rm -rf $(GALAPAGOS_PATH)/projects/hello_world + rm -rf .world + rm -rf .hello_world + rm -rf .middleware + rm -rf vivado* + + +# Very bizarre! GNU Make will silently add calls to g++ if you have cpp files +# in your directory (even if none of your rules or dependencies mention it). +# This is because of some implicit rules... 30 minutes I found this solution +.SUFFIXES: diff --git a/examples/hello_world/README.txt b/examples/hello_world/README.txt new file mode 100644 index 00000000..650dbaa0 --- /dev/null +++ b/examples/hello_world/README.txt @@ -0,0 +1,26 @@ +===================== +GALAPAGOS HELLO WORLD +===================== + +This example contains: + + - hello_world.cpp, a Galapagos HLS kernel with DEST = 1 that contantly + broadcasts a message to the kernel with DEST = 2 + + - world.cpp, a Galapagos HLS kernel with DEST = 2 that ignores all + incoming messages + + - hello_world.tcl and world.tcl. Scripts that invoke Vivado HLS to compile + hello_world.cpp and world.cpp into Verilog + + - logical.xml, the logical file + + - mapping.xml, the mapping file + + - A Makefile + + +Make sure you have followed the Galapagos setup instructions (see +documentation/galapagos_flow.txt). This Makefile will generate a Vivado project +in projects/hello_world/0/ + diff --git a/examples/hello_world/hello_world.cpp b/examples/hello_world/hello_world.cpp new file mode 100644 index 00000000..4abf1445 --- /dev/null +++ b/examples/hello_world/hello_world.cpp @@ -0,0 +1,20 @@ +#include "galapagos_packet.h" + +using gp = galapagos::stream_packet<64>; + +void hello_world(hls::stream *out) { + #pragma HLS INTERFACE axis register both port=out + #pragma HLS INTERFACE ap_ctrl_none port=return + + gp tmp; + + tmp.dest = 2; + tmp.data = 0xFEEDBADBEEF2BABE; + tmp.id = 1; + tmp.last = 1; + tmp.keep = 0xFFFF; + + if(!out->full()) out->write(tmp); + + +} diff --git a/examples/hello_world/hello_world.tcl b/examples/hello_world/hello_world.tcl new file mode 100644 index 00000000..a737ad73 --- /dev/null +++ b/examples/hello_world/hello_world.tcl @@ -0,0 +1,23 @@ +set galapagos_path $::env(GALAPAGOS_PATH) +set board_name $::env(GALAPAGOS_BOARD_NAME) +set part_name $::env(GALAPAGOS_PART) + +set src_path_root $galapagos_path/examples/hello_world + +# Does this still work? We'll find out, I guess... +cd $galapagos_path/hlsBuild/${board_name}/ip + +open_project hello_world +set_top hello_world +open_solution "solution1" +set_part ${part_name} +#csynth path +add_files $src_path_root/hello_world.cpp -cflags "-I $galapagos_path/middleware/include -I $galapagos_path/middleware/CPP_lib/Galapagos_lib" +create_clock -period 250MHz -name default +config_interface -expose_global +csynth_design +export_design -format ip_catalog +close_project + +quit + diff --git a/examples/hello_world/logical.xml b/examples/hello_world/logical.xml new file mode 100644 index 00000000..a135f519 --- /dev/null +++ b/examples/hello_world/logical.xml @@ -0,0 +1,51 @@ + + + + + 64 + 1 + 1 + 16 + + + + + hello_world + + xilinx.com + hls + 1.0 + 1 + 1 + + + ap_clk + ap_rst_n + + global + out_r + + + + + world + + xilinx.com + hls + 1.0 + 2 + 1 + + + ap_clk + ap_rst_n + + global + in_r + + + + diff --git a/examples/hello_world/mapping.xml b/examples/hello_world/mapping.xml new file mode 100644 index 00000000..3ccc85fb --- /dev/null +++ b/examples/hello_world/mapping.xml @@ -0,0 +1,17 @@ + + + + + hw + raw + sidewinder + 01:23:45:67:89:AB + 10.10.84.234 + + + 1 + 2 + + + + diff --git a/examples/hello_world/world.cpp b/examples/hello_world/world.cpp new file mode 100644 index 00000000..6129ebe5 --- /dev/null +++ b/examples/hello_world/world.cpp @@ -0,0 +1,11 @@ +#include "galapagos_packet.h" + +using gp = galapagos::stream_packet<64>; + +void world(hls::stream *in) { + #pragma HLS INTERFACE axis register both port=in + #pragma HLS INTERFACE ap_ctrl_none port=return + + gp tmp; + if (!in->empty()) in->read(tmp); +} diff --git a/examples/hello_world/world.tcl b/examples/hello_world/world.tcl new file mode 100644 index 00000000..9b0cbfa2 --- /dev/null +++ b/examples/hello_world/world.tcl @@ -0,0 +1,23 @@ +set galapagos_path $::env(GALAPAGOS_PATH) +set board_name $::env(GALAPAGOS_BOARD_NAME) +set part_name $::env(GALAPAGOS_PART) + +set src_path_root $galapagos_path/examples/hello_world + +# Does this still work? We'll find out, I guess... +cd $galapagos_path/hlsBuild/${board_name}/ip + +open_project world +set_top world +open_solution "solution1" +set_part ${part_name} +#csynth path +add_files $src_path_root/world.cpp -cflags "-I $galapagos_path/middleware/include -I $galapagos_path/middleware/CPP_lib/Galapagos_lib" +create_clock -period 250MHz -name default +config_interface -expose_global +csynth_design +export_design -format ip_catalog +close_project + +quit + diff --git a/middleware/Makefile b/middleware/Makefile index ae4a3bc0..b1b18ac2 100644 --- a/middleware/Makefile +++ b/middleware/Makefile @@ -24,7 +24,7 @@ python_path = $(middleware_path)/python all: middleware hlsmiddleware middleware: guard-LOGICALFILE guard-MAPFILE guard-PROJECTNAME ${LOGICALFILE} ${MAPFILE} - python3.5 ${python_path}/globalFPGAParser.py --logicalFile=${LOGICALFILE} \ + python ${python_path}/globalFPGAParser.py --logicalFile=${LOGICALFILE} \ --mapFile=${MAPFILE} --projectName=${PROJECTNAME} chmod +x $(GALAPAGOS_PATH)/projects/$(PROJECTNAME)/createCluster.sh diff --git a/middleware/hls/axistreamstats/Makefile b/middleware/hls/axistreamstats/Makefile new file mode 100644 index 00000000..c8fe22f8 --- /dev/null +++ b/middleware/hls/axistreamstats/Makefile @@ -0,0 +1,40 @@ +# This file is from tpdp/helpful_scripts/packaging_custom_ip: +# https://github.com/UofT-HPRC/tpdp/tree/master/helpful_scripts/packaging_custom_ip + +# I didn't want to rock the boat too much, so I'm just using Galapagos's +# environment variables for compatibility. However, it would be much better to +# use a more robust method + + +# Edit the following four variables and run `make`. +# After that, follow the instructions in ip_maker.tcl +# +# Alternatively, you could set any of these variables on the command line: +# +# $ make src_dir=/path/to/my/src dst_dir=/path/to/my/output +# +# Just make sure that you don't include a trailing slash on your directories + +dst_dir=$(GALAPAGOS_PATH)/hlsBuild/$(GALAPAGOS_BOARD_NAME) +src_dir=. +ip_name=axistreamstats +part_no=$(GALAPAGOS_PART) + + + +# Makes Makefile easier to read +out_dir=${dst_dir}/${ip_name} + +all: clean + rm -rf ${out_dir} + mkdir -p ${out_dir}/src + cp $(shell find ${src_dir} -name "*.v" -o -name "*vh" -o -name "*sv") ${out_dir}/src + vivado -nolog -nojournal -notrace -mode batch -source ip_maker.tcl -tclargs ${out_dir} ${ip_name} ${part_no} + rm -rf ${ip_name}_tmp_proj + rm -f *log + rm -rf .Xil + rm -f vivado* +clean: + rm -rf ${out_dir} + rm -rf ${ip_name}_tmp_proj + diff --git a/middleware/hls/axistreamstats/README.txt b/middleware/hls/axistreamstats/README.txt new file mode 100644 index 00000000..62f33550 --- /dev/null +++ b/middleware/hls/axistreamstats/README.txt @@ -0,0 +1,4 @@ +A simple test to see if I can figure out how to add new IPs in the Galapagos +middleware. + +This is a simple flit/packet counter for AXI Stream diff --git a/middleware/hls/axistreamstats/axistreamstats.v b/middleware/hls/axistreamstats/axistreamstats.v new file mode 100644 index 00000000..c3209214 --- /dev/null +++ b/middleware/hls/axistreamstats/axistreamstats.v @@ -0,0 +1,111 @@ +`timescale 1ns / 1ps + +`define NO_RESET 0 +`define ACTIVE_HIGH 1 +`define ACTIVE_LOW 2 + +`define genif generate if +`define else_genif end else if +`define endgen end endgenerate + +module axistreamstats #( + parameter DATA_WIDTH = 32, + parameter CNT_WIDTH = 32, + parameter RESET_TYPE = `ACTIVE_LOW +) ( + input wire clk, + //Depending on RESET_TYPE, one or neither of these ports are used + input wire rst, + input wire rstn, + + //Input AXI Stream. This is just so Vivado makes it an interface and keeps + //the block diagram simple + input wire [DATA_WIDTH-1:0] in_TDATA, + input wire in_TVALID, + output wire in_TREADY, + input wire [DATA_WIDTH/8 -1:0] in_TKEEP, + input wire in_TDEST, + input wire in_TID, + input wire in_TLAST, + + //Output AXI Stream. This is just so Vivado makes it an interface and keeps + //the block diagram simple + output wire [DATA_WIDTH-1:0] out_TDATA, + output wire out_TVALID, + input wire out_TREADY, + output wire [DATA_WIDTH/8 -1:0] out_TKEEP, + output wire out_TDEST, + output wire out_TID, + output wire out_TLAST, + + //The flit and packet counts + output wire [CNT_WIDTH-1:0] flit_cnt, + output wire [CNT_WIDTH-1:0] pkt_cnt +); + + //First, directly connect the AXI Streams + assign out_TDATA = in_TDATA; + assign out_TVALID = in_TVALID; + assign in_TREADY = out_TREADY; + assign out_TKEEP = in_TKEEP; + assign out_TDEST = in_TDEST; + assign out_TID = in_TID; + assign out_TLAST = in_TLAST; + + //A few helper signals + wire flit_vld; + assign flit_vld = in_TVALID && in_TREADY; + + wire flit_last; + assign flit_last = flit_vld && in_TLAST; + + //Now do the packet counting + reg [CNT_WIDTH-1:0] flit_cnt_r = 0; + reg [CNT_WIDTH-1:0] pkt_cnt_r = 0; + +`genif (RESET_TYPE == `NO_RESET) begin + + always @(posedge clk) begin + flit_cnt_r <= flit_cnt_r + flit_vld; + pkt_cnt_r <= pkt_cnt_r + flit_last; + end + +`else_genif (RESET_TYPE == `ACTIVE_HIGH) begin + + always @(posedge clk) begin + if (rst) begin + flit_cnt_r <= 0; + pkt_cnt_r <= 0; + end else begin + flit_cnt_r <= flit_cnt_r + flit_vld; + pkt_cnt_r <= pkt_cnt_r + flit_last; + end + end + +`else_genif (RESET_TYPE == `ACTIVE_LOW) begin + + always @(posedge clk) begin + if (!rstn) begin + flit_cnt_r <= 0; + pkt_cnt_r <= 0; + end else begin + flit_cnt_r <= flit_cnt_r + flit_vld; + pkt_cnt_r <= pkt_cnt_r + flit_last; + end + end + +`endgen + + //And of course, don't forget to assign the outputs! + assign flit_cnt = flit_cnt_r; + assign pkt_cnt = pkt_cnt_r; + +endmodule + +`undef genif +`undef else_genif +`undef endgen + +`undef NO_RESET +`undef ACTIVE_HIGH +`undef ACTIVE_LOW diff --git a/middleware/hls/axistreamstats/ip_maker.tcl b/middleware/hls/axistreamstats/ip_maker.tcl new file mode 100644 index 00000000..d998e09d --- /dev/null +++ b/middleware/hls/axistreamstats/ip_maker.tcl @@ -0,0 +1,49 @@ +# Call as: +# vivado -mode tcl -nolog -nojournal -source scripts/ip_package.tcl -tclargs $out_dir $ip_name $part_name + + +# INSTRUCTIONS +# ------------ +# The first time you run this tcl, it will open the Vivado GUI in the IP +# packaging mode. Go ahead and edit your IP the way you normally would, taking +# care to copy and paste all the TCL commands that Vivado generates into the +# location labeled below. +# When you're finished, remove the "start_gui" line and uncomment all the lines +# at the end of this script + + +# start_gui; # Remove this line after copying TCL commands (see below) + +set out_dir [lindex $argv 0] +set ip_name [lindex $argv 1] +set part_name [lindex $argv 2] +set project_name ${ip_name}_tmp_proj +create_project ${project_name} ${project_name} -part ${part_name} +add_files ${out_dir}/src +ipx::package_project -root_dir ${out_dir} -vendor mmerlini.ca -library galapagos -taxonomy /UserIP + +set_property tooltip {Width of AXI Stream channel} [ipgui::get_guiparamspec -name "DATA_WIDTH" -component [ipx::current_core] ] +set_property widget {textEdit} [ipgui::get_guiparamspec -name "DATA_WIDTH" -component [ipx::current_core] ] + +set_property display_name {Counter Width} [ipgui::get_guiparamspec -name "CNT_WIDTH" -component [ipx::current_core] ] +set_property tooltip {Number of bits in packet/flit count} [ipgui::get_guiparamspec -name "CNT_WIDTH" -component [ipx::current_core] ] +set_property widget {textEdit} [ipgui::get_guiparamspec -name "CNT_WIDTH" -component [ipx::current_core] ] + +set_property widget {comboBox} [ipgui::get_guiparamspec -name "RESET_TYPE" -component [ipx::current_core] ] +set_property value_validation_type pairs [ipx::get_user_parameters RESET_TYPE -of_objects [ipx::current_core]] +set_property value_validation_pairs {{No reset} 0 {Active high} 1 {Active low} 2} [ipx::get_user_parameters RESET_TYPE -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RESET_TYPE')) = 1} [ipx::get_bus_interfaces rst -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RESET_TYPE')) = 2} [ipx::get_bus_interfaces rstn -of_objects [ipx::current_core]] + +# Uncomment these lines after copying TCL commands from gui + +ipx::create_xgui_files [ipx::current_core] +ipx::update_checksums [ipx::current_core] +ipx::save_core [ipx::current_core] +close_project +exit + + + diff --git a/middleware/python/cluster.py b/middleware/python/cluster.py index 02e8cc17..c3215cf3 100644 --- a/middleware/python/cluster.py +++ b/middleware/python/cluster.py @@ -107,6 +107,8 @@ def __init__(self, name, kernel_file, map_file, mode='file'): if(mode=='file'): logical_dict = self.getDict(kernel_file)['cluster']['kernel'] map_dict = self.getDict(map_file)['cluster']['node'] + if not isinstance(map_dict, list): + map_dict = [map_dict] else: logical_dict = kernel_file['cluster']['kernel'] map_dict = map_file['cluster']['node'] diff --git a/middleware/python/tclFileGenerator.py b/middleware/python/tclFileGenerator.py index 7d8820a5..21d3dba1 100644 --- a/middleware/python/tclFileGenerator.py +++ b/middleware/python/tclFileGenerator.py @@ -2031,4 +2031,5 @@ def makeTCLFiles(fpga, projectName, output_path, sim): tclMain.addSource(galapagos_path + '/middleware/tclScripts/custom/' + fpga['custom'] + '.tcl') tclMain.tprint('validate_bd_design') + tclMain.tprint('save_bd_design') tclMain.close() diff --git a/setup.py b/setup.py index b2670d2a..d7d7bdb0 100644 --- a/setup.py +++ b/setup.py @@ -23,7 +23,7 @@ class directoryValidator(Validator): def validate(self, document): if not document.text=='': - if not os.path.isdir("/home/el"): + if not os.path.isdir(document.text): raise ValidationError( message='Please enter valid directory for galapagos path', cursor_position=len(document.text) diff --git a/shells/Makefile b/shells/Makefile index 01fd00a8..0c7f0c3d 100644 --- a/shells/Makefile +++ b/shells/Makefile @@ -13,24 +13,31 @@ guard-%: all: example synth = 0 +# This file does not exist... pr_tcl = ./hlsTest/dma_example/tclScripts/pr_bd.tcl +# This target is completely broken dma_example: vivado_hls ./hlsTest/dma_example/generate_hls.tcl vivado -mode gui -source ./tclScripts/make_shell.tcl -tclargs --project_name dma_example --pr_tcl ${pr_tcl} --start_synth ${synth} +# None of these files exist hlsExample: mkdir -p hlsBuild vivado_hls ./hlsTest/generate_hls.tcl ./hlsTest/generate.sh dma_example -example: hlsExample +example: mkdir -p projects - vivado -mode tcl -source ./tclScripts/make_shell.tcl -tclargs --project_name example --pr_tcl ${pr_tcl} --start_synth ${synth} + vivado -mode batch -source ./tclScripts/make_shell.tcl -tclargs --project_name example --start_synth ${synth} + # Get rid of references to nonexistent files + # vivado -mode tcl -source ./tclScripts/make_shell.tcl -tclargs --project_name example --pr_tcl ${pr_tcl} --start_synth ${synth} +# I think this is the target that gets called when you build a project app_dev: guard-PROJECTNAME mkdir -p projects vivado -mode gui -source ./tclScripts/make_shell.tcl -tclargs --project_name ${PROJECTNAME} + # Why do we always make a projects directory? clean: rm -rf projects/project_name diff --git a/shells/pynq-z2/tclScripts/shell_bd.tcl b/shells/pynq-z2/tclScripts/shell_bd.tcl index 7642bddb..e8ab8b1f 100644 --- a/shells/pynq-z2/tclScripts/shell_bd.tcl +++ b/shells/pynq-z2/tclScripts/shell_bd.tcl @@ -10,7 +10,7 @@ set script_folder [_tcl::get_script_folder] set_param synth.vivado.filterDuplicatedIPFiles 0 -set supported_versions {2017.4 2018.1 2018.2} +set supported_versions {2017.4 2018.1 2018.2 2018.3} namespace eval 2017.4 { set ip_list "\ @@ -48,6 +48,18 @@ namespace eval 2018.2 { " } +namespace eval 2018.3 { + set ip_list "\ + xilinx.com:ip:axi_bram_ctrl\ + xilinx.com:ip:axi_dma\ + xilinx.com:ip:axi_gpio\ + xilinx.com:ip:blk_mem_gen\ + xilinx.com:ip:proc_sys_reset\ + xilinx.com:ip:processing_system7\ + xilinx.com:ip:xlconcat\ + " +} + if { [info exists ::env(GALAPAGOS_PATH)] } { set root_path ${::env(GALAPAGOS_PATH)}/shells @@ -217,19 +229,19 @@ proc create_root_design { parentCell } { set sw [ create_bd_port -dir I -from 1 -to 0 sw ] # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_0 ] + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl axi_bram_ctrl_0 ] set_property -dict [ list \ CONFIG.SINGLE_PORT_BRAM {1} \ ] $axi_bram_ctrl_0 # Create instance: axi_bram_ctrl_1, and set properties - set axi_bram_ctrl_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_1 ] + set axi_bram_ctrl_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl axi_bram_ctrl_1 ] set_property -dict [ list \ CONFIG.SINGLE_PORT_BRAM {1} \ ] $axi_bram_ctrl_1 # Create instance: axi_dma_0, and set properties - set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] + set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma axi_dma_0 ] set_property -dict [ list \ CONFIG.c_include_mm2s_dre {1} \ CONFIG.c_include_s2mm_dre {1} \ @@ -242,14 +254,14 @@ proc create_root_design { parentCell } { ] $axi_dma_0 # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_0 ] set_property -dict [ list \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO_WIDTH {4} \ ] $axi_gpio_0 # Create instance: axi_gpio_1, and set properties - set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] + set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_1 ] set_property -dict [ list \ CONFIG.C_ALL_INPUTS {1} \ CONFIG.C_ALL_OUTPUTS {0} \ @@ -258,7 +270,7 @@ proc create_root_design { parentCell } { ] $axi_gpio_1 # Create instance: axi_gpio_2, and set properties - set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] + set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_2 ] set_property -dict [ list \ CONFIG.C_ALL_INPUTS {1} \ CONFIG.C_ALL_OUTPUTS {0} \ @@ -267,41 +279,41 @@ proc create_root_design { parentCell } { ] $axi_gpio_2 # Create instance: axi_interconnect_1, and set properties - set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ] + set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_1 ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ CONFIG.NUM_SI {2} \ ] $axi_interconnect_1 # Create instance: axi_interconnect_2, and set properties - set axi_interconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2 ] + set axi_interconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_2 ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ CONFIG.NUM_SI {1} \ ] $axi_interconnect_2 # Create instance: axi_interconnect_3, and set properties - set axi_interconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_3 ] + set axi_interconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_3 ] set_property -dict [ list \ CONFIG.NUM_MI {2} \ CONFIG.NUM_SI {1} \ ] $axi_interconnect_3 # Create instance: axi_interconnect_4, and set properties - set axi_interconnect_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_4 ] + set axi_interconnect_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_4 ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ CONFIG.NUM_SI {1} \ ] $axi_interconnect_4 # Create instance: axi_interconnect_5, and set properties - set axi_interconnect_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_5 ] + set axi_interconnect_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_5 ] set_property -dict [ list \ CONFIG.NUM_MI {4} \ ] $axi_interconnect_5 # Create instance: blk_mem_gen_0, and set properties - set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ] + set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen blk_mem_gen_0 ] set_property -dict [ list \ CONFIG.Enable_B {Use_ENB_Pin} \ CONFIG.Memory_Type {True_Dual_Port_RAM} \ @@ -312,10 +324,10 @@ proc create_root_design { parentCell } { ] $blk_mem_gen_0 # Create instance: proc_sys_reset_0, and set properties - set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset proc_sys_reset_0 ] # Create instance: ps7_0, and set properties - set ps7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ps7_0 ] + set ps7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7 ps7_0 ] set_property -dict [ list \ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ @@ -1178,7 +1190,7 @@ proc create_root_design { parentCell } { ] $ps7_0 # Create instance: xlconcat_1, and set properties - set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] + set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_1 ] set_property -dict [ list \ CONFIG.NUM_PORTS {4} \ ] $xlconcat_1 diff --git a/shells/sidewinder/tclScripts/shell_bd.tcl b/shells/sidewinder/tclScripts/shell_bd.tcl index 708b1abd..acb09226 100644 --- a/shells/sidewinder/tclScripts/shell_bd.tcl +++ b/shells/sidewinder/tclScripts/shell_bd.tcl @@ -120,6 +120,34 @@ namespace eval 2018.2 { " } +namespace eval 2018.3 { + set ip_list "\ + xilinx.com:ip:axi_bram_ctrl:4.1\ + xilinx.com:ip:axi_gpio:2.0\ + xilinx.com:ip:blk_mem_gen:8.4\ + xilinx.com:ip:clk_wiz:6.0\ + xilinx.com:ip:xlconstant:1.1\ + xilinx.com:ip:system_ila:1.1\ + xilinx.com:ip:util_vector_logic:2.0\ + xilinx.com:ip:vio:3.0\ + xilinx.com:ip:util_ds_buf:2.1\ + xilinx.com:ip:xdma:4.1\ + xilinx.com:ip:mdm:3.2\ + xilinx.com:ip:microblaze:11.0\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:ddr4:2.2\ + xilinx.com:ip:axi_10g_ethernet:3.1\ + dlyma.org:dlyma:network_packet_fifo_rx:1.1\ + dlyma.org:dlyma:network_packet_fifo_tx:1.1\ + xilinx.com:ip:axis_register_slice:1.1\ + xilinx.com:ip:lmb_bram_if_cntlr:4.0\ + xilinx.com:ip:lmb_v10:3.0\ + xilinx.com:ip:fifo_generator:13.2\ + xilinx.com:ip:zynq_ultra_ps_e:3.2\ + xilinx.com:ip:xxv_ethernet:2.5 + " +} + # defines get_design_name if { [info exists ::env(GALAPAGOS_PATH)] } { source ${::env(GALAPAGOS_PATH)}/shells/tclScripts/utilities.tcl @@ -132,6 +160,7 @@ if { [info exists ::env(GALAPAGOS_PATH)] } { } +# ADD CLAUSE HERE TO SUPPORT NEW VERSIONS # determine Vivado version set current_vivado_version [version -short] if { [string first 2017.2 $current_vivado_version] != -1 } { @@ -142,6 +171,9 @@ if { [string first 2017.2 $current_vivado_version] != -1 } { set version 2018.1 } elseif { [string first 2018.2 $current_vivado_version] != -1 } { set version 2018.2 +} elseif { [string first 2018.3 $current_vivado_version] != -1 } { + # MM Jan 28/2020: Added support for 2018.3 + set version 2018.3 } else { puts "" catch {common::send_msg_id "BD_TCL-109" "ERROR" "Unsupported Vivado version:\ @@ -1083,9 +1115,9 @@ connect_bd_net [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ax # Restore current instance current_bd_instance $oldCurInst - # regenerate_bd_layout - # save_bd_design - # validate_bd_design + regenerate_bd_layout + save_bd_design + validate_bd_design } # End of create_root_design() diff --git a/shells/tclScripts/make_shell.tcl b/shells/tclScripts/make_shell.tcl index 735956ac..2341fdd9 100644 --- a/shells/tclScripts/make_shell.tcl +++ b/shells/tclScripts/make_shell.tcl @@ -126,7 +126,7 @@ if {! [catch {glob $shell_path/srcs/*} yikes] } { } create_bd_design "shell" -# open_bd_design $project_path/$project_name.srcs/sources_1/bd/shell/shell.bd +open_bd_design $project_path/$project_name.srcs/sources_1/bd/shell/shell.bd set ret_val [source $shell_path/tclScripts/shell_bd.tcl] if { $ret_val != 0 } { puts "Error in shell_bd script" diff --git a/shells/tclScripts/shell_procs.tcl b/shells/tclScripts/shell_procs.tcl index 92cf5b35..259b4695 100644 --- a/shells/tclScripts/shell_procs.tcl +++ b/shells/tclScripts/shell_procs.tcl @@ -553,8 +553,12 @@ proc create_hier_eth10G_zu { parentCell nameHier } { connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_1/Res] [get_bd_pins util_vector_logic_2/Op1] connect_bd_net -net util_vector_logic_2_Res [get_bd_pins ext_reset_n] [get_bd_pins util_vector_logic_2/Res] connect_bd_net -net xlconstant_0_dout [get_bd_pins CONST_5/dout] [get_bd_pins xxv_ethernet_0/rxoutclksel_in_0] [get_bd_pins xxv_ethernet_0/txoutclksel_in_0] - connect_bd_net -net xxv_ethernet_0_rx_clk_out_0 [get_bd_pins axis_clock_converter_0/s_axis_aclk] [get_bd_pins bit_synchronizer_0/sync_clk] [get_bd_pins xxv_ethernet_0/rx_clk_out_0] - connect_bd_net -net xxv_ethernet_0_tx_clk_out_1 [get_bd_pins tx_clk_out_0] [get_bd_pins axis_clock_converter_0/m_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins xxv_ethernet_0/rx_core_clk_0] [get_bd_pins xxv_ethernet_0/tx_clk_out_0] + # + # MM Jan 28/2020: I don't know how this ever worked before, but this uses the wrong clock for rx_core_clk + connect_bd_net -net xxv_ethernet_0_rx_clk_out_0 [get_bd_pins axis_clock_converter_0/s_axis_aclk] [get_bd_pins bit_synchronizer_0/sync_clk] [get_bd_pins xxv_ethernet_0/rx_core_clk_0] [get_bd_pins xxv_ethernet_0/rx_clk_out_0] + connect_bd_net -net xxv_ethernet_0_tx_clk_out_1 [get_bd_pins tx_clk_out_0] [get_bd_pins axis_clock_converter_0/m_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins xxv_ethernet_0/tx_clk_out_0] + + # connect_bd_net -net xxv_ethernet_0_user_rx_reset_0 [get_bd_pins util_vector_logic_1/Op1] [get_bd_pins xxv_ethernet_0/user_rx_reset_0] connect_bd_net -net xxv_ethernet_0_user_tx_reset_0 [get_bd_pins util_vector_logic_1/Op2] [get_bd_pins xxv_ethernet_0/user_tx_reset_0] diff --git a/shells/zedboard/tclScripts/shell_bd.tcl b/shells/zedboard/tclScripts/shell_bd.tcl index 16b2a571..d985e281 100644 --- a/shells/zedboard/tclScripts/shell_bd.tcl +++ b/shells/zedboard/tclScripts/shell_bd.tcl @@ -8,7 +8,7 @@ proc get_script_folder {} { variable script_folder set script_folder [_tcl::get_script_folder] -set supported_versions {2017.4} +set supported_versions {2017.4 2018.3} namespace eval 2017.4 { set ip_list "\ @@ -22,6 +22,18 @@ namespace eval 2017.4 { " } +namespace eval 2018.3 { + set ip_list "\ + xilinx.com:ip:axi_bram_ctrl:4.1\ + xilinx.com:ip:axi_dma:7.1\ + xilinx.com:ip:axi_gpio:2.0\ + xilinx.com:ip:blk_mem_gen:8.4\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:processing_system7:5.5\ + xilinx.com:ip:xlconcat:2.1\ + " +} + if { [info exists ::env(GALAPAGOS_PATH)] } { set root_path ${::env(GALAPAGOS_PATH)}/shells } elseif [info exists ::env(SHELLS_PATH)] { @@ -68,6 +80,9 @@ if { $nRet != 0 } { # Check IPs set list_check_ips [puts [subst $\{[subst ${version}::ip_list]\}]] +puts "MARCO SEZ" +puts [subst $\{[subst ${version}::ip_list]\}] +puts "MARCO NO LONGER SEZ" set list_ips_missing "" common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { @@ -190,19 +205,19 @@ proc create_root_design { parentCell } { set sw [ create_bd_port -dir I -from 7 -to 0 sw ] # Create instance: axi_bram_ctrl_0, and set properties - set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_0 ] + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl axi_bram_ctrl_0 ] set_property -dict [ list \ CONFIG.SINGLE_PORT_BRAM {1} \ ] $axi_bram_ctrl_0 # Create instance: axi_bram_ctrl_1, and set properties - set axi_bram_ctrl_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 axi_bram_ctrl_1 ] + set axi_bram_ctrl_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl axi_bram_ctrl_1 ] set_property -dict [ list \ CONFIG.SINGLE_PORT_BRAM {1} \ ] $axi_bram_ctrl_1 # Create instance: axi_dma_0, and set properties - set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] + set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma axi_dma_0 ] set_property -dict [ list \ CONFIG.c_include_mm2s_dre {1} \ CONFIG.c_include_s2mm_dre {1} \ @@ -215,14 +230,14 @@ proc create_root_design { parentCell } { ] $axi_dma_0 # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_0 ] set_property -dict [ list \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO_WIDTH {8} \ ] $axi_gpio_0 # Create instance: axi_gpio_1, and set properties - set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] + set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_1 ] set_property -dict [ list \ CONFIG.C_ALL_INPUTS {1} \ CONFIG.C_ALL_OUTPUTS {0} \ @@ -231,7 +246,7 @@ proc create_root_design { parentCell } { ] $axi_gpio_1 # Create instance: axi_gpio_2, and set properties - set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] + set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_2 ] set_property -dict [ list \ CONFIG.C_ALL_INPUTS {1} \ CONFIG.C_ALL_OUTPUTS {0} \ @@ -240,41 +255,41 @@ proc create_root_design { parentCell } { ] $axi_gpio_2 # Create instance: axi_interconnect_1, and set properties - set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ] + set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_1 ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ CONFIG.NUM_SI {2} \ ] $axi_interconnect_1 # Create instance: axi_interconnect_2, and set properties - set axi_interconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2 ] + set axi_interconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_2 ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ CONFIG.NUM_SI {1} \ ] $axi_interconnect_2 # Create instance: axi_interconnect_3, and set properties - set axi_interconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_3 ] + set axi_interconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_3 ] set_property -dict [ list \ CONFIG.NUM_MI {2} \ CONFIG.NUM_SI {1} \ ] $axi_interconnect_3 # Create instance: axi_interconnect_4, and set properties - set axi_interconnect_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_4 ] + set axi_interconnect_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_4 ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ CONFIG.NUM_SI {1} \ ] $axi_interconnect_4 # Create instance: axi_interconnect_5, and set properties - set axi_interconnect_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_5 ] + set axi_interconnect_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_5 ] set_property -dict [ list \ CONFIG.NUM_MI {4} \ ] $axi_interconnect_5 # Create instance: blk_mem_gen_0, and set properties - set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ] + set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen blk_mem_gen_0 ] set_property -dict [ list \ CONFIG.Enable_B {Use_ENB_Pin} \ CONFIG.Memory_Type {True_Dual_Port_RAM} \ @@ -285,10 +300,10 @@ proc create_root_design { parentCell } { ] $blk_mem_gen_0 # Create instance: proc_sys_reset_0, and set properties - set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset proc_sys_reset_0 ] # Create instance: ps7_0, and set properties - set ps7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ps7_0 ] + set ps7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7 ps7_0 ] set_property -dict [ list \ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ @@ -689,7 +704,7 @@ proc create_root_design { parentCell } { ] $ps7_0 # Create instance: xlconcat_1, and set properties - set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] + set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_1 ] set_property -dict [ list \ CONFIG.NUM_PORTS {4} \ ] $xlconcat_1 @@ -731,7 +746,6 @@ proc create_root_design { parentCell } { connect_bd_net -net ps7_0_FCLK_CLK0 [get_bd_ports CLK_DATA] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_1/s_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins axi_interconnect_1/S01_ACLK] [get_bd_pins axi_interconnect_2/ACLK] [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins axi_interconnect_3/ACLK] [get_bd_pins axi_interconnect_3/M00_ACLK] [get_bd_pins axi_interconnect_3/M01_ACLK] [get_bd_pins axi_interconnect_3/S00_ACLK] [get_bd_pins axi_interconnect_4/ACLK] [get_bd_pins axi_interconnect_4/M00_ACLK] [get_bd_pins axi_interconnect_4/S00_ACLK] [get_bd_pins axi_interconnect_5/ACLK] [get_bd_pins axi_interconnect_5/M00_ACLK] [get_bd_pins axi_interconnect_5/M01_ACLK] [get_bd_pins axi_interconnect_5/M02_ACLK] [get_bd_pins axi_interconnect_5/M03_ACLK] [get_bd_pins axi_interconnect_5/S00_ACLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps7_0/FCLK_CLK0] [get_bd_pins ps7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0/M_AXI_GP1_ACLK] [get_bd_pins ps7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0/S_AXI_HP1_ACLK] [get_bd_pins ps7_0/S_AXI_HP2_ACLK] connect_bd_net -net ps7_0_FCLK_RESET0_N [get_bd_ports ARESETN] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins ps7_0/FCLK_RESET0_N] connect_bd_net -net xlconcat_1_dout [get_bd_pins ps7_0/IRQ_F2P] [get_bd_pins xlconcat_1/dout] - connect_bd_net [get_bd_pins xlconcat_1/dout] [get_bd_pins ps7_0/IRQ_F2P # Create address segments create_bd_addr_seg -range 0x00002000 -offset 0x40000000 [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs axi_bram_ctrl_1/S_AXI/Mem0] SEG_axi_bram_ctrl_1_Mem0