From 7cbe55a6a3df43344d01bcd9a20316d00b2a2ec3 Mon Sep 17 00:00:00 2001 From: VABISMO Date: Fri, 30 Oct 2026 18:12:56 +0100 Subject: [PATCH] docs: correct env-knob pointer attribution in README (round-11 audit) The round-10 pointer line claimed all nine PCB-generation overrides were 'documented in docs/agents/project-specs.md' -- only QSSC_PCB_PATH actually is. The pour/rail overrides (QSSC_ZONE_CLEARANCE_NM, QSSC_ZONE_MIN_WIDTH_NM, QSSC_RAIL_MICRO, QSSC_STITCH_STEP) live in hardware/HARDWARE_DESIGN.md, and the via/gap/debug overrides (QSSC_VIA_DIAM_NM, QSSC_VIA_DRILL_NM, QSSC_COPPER_GAP_NM, QSSC_ROUTE_DEBUG) had no doc at all (code comments only). Reworded to state they are read by tools/route_qssc_pcb.py and tools/router/* with the pour/rail ones described in HARDWARE_DESIGN.md -- no false single-file attribution. Round-11 also probed two remaining axes and found no defects: - frontend/dist is NOT committed (0 tracked files; CI builds it) -- no src-vs-dist drift surface. - BOM.csv MPNs vs DATASHEETS.md are consistent: the BTB connectors match exactly (main 61302011121 / head 61002021121), semiconductors match by base part (AD7616, LM358, MCP4921, USB4105 -- BOM carries the orderable package suffix), and the rest are generic passives/headers that need no pinout entry. Green: ruff, env-doc + readme gates. --- README.md | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 668cd09..9051ce9 100644 --- a/README.md +++ b/README.md @@ -238,11 +238,13 @@ what the code falls back to when the variable is unset. | `QSSC_FPGA_PROFILE` | `NV` | Simulation profile for the fallback `SimulatedFPGA` when no board is present. | | `QSSC_SEED` | `42` | Seed for the simulated-FPGA RNG (reproducible sim runs). | -> The PCB-generation knobs (`QSSC_ZONE_CLEARANCE_NM`, `QSSC_ZONE_MIN_WIDTH_NM`, -> `QSSC_VIA_DIAM_NM`, `QSSC_VIA_DRILL_NM`, `QSSC_COPPER_GAP_NM`, -> `QSSC_ROUTE_DEBUG`, `QSSC_RAIL_MICRO`, `QSSC_STITCH_STEP`, `QSSC_PCB_PATH`) -> are development-time router settings, documented in -> [`docs/agents/project-specs.md`](docs/agents/project-specs.md). +> The PCB-generation overrides — `QSSC_ZONE_CLEARANCE_NM`, +> `QSSC_ZONE_MIN_WIDTH_NM`, `QSSC_VIA_DIAM_NM`, `QSSC_VIA_DRILL_NM`, +> `QSSC_COPPER_GAP_NM`, `QSSC_ROUTE_DEBUG`, `QSSC_RAIL_MICRO`, +> `QSSC_STITCH_STEP`, `QSSC_PCB_PATH` — are development-time router settings +> read by `tools/route_qssc_pcb.py` and `tools/router/*` (the pour and rail +> overrides are described in +> [`hardware/HARDWARE_DESIGN.md`](hardware/HARDWARE_DESIGN.md)). ## FPGA control stack