Update to activehdl.py required for VHDL-2019 support

[Andy-Darlington]

Attempting to compile using VHDL-2019 results in the following error:
Invalid VHDL standard 2019.

This can be fixed by updating activehdl.py as follows:

@staticmethod
def _std_str(vhdl_standard):
    """
    Convert standard to format of Active-HDL command line flag
    """
    if vhdl_standard <= VHDL.STD_2019:
        return "-%s" % vhdl_standard

    raise ValueError("Invalid VHDL standard %s" % vhdl_standard)

I'm using vunit 4.5.0 and ActiveHDL 12.0 x64.

[umarcor]

This should be fixed in master. Coming in the next release.

[LarsAsplund]

I tried to run the simple hello world example with VHDL-2019 and it complains about stack size. I think the default is 32 MB and it requires 2048 before it stops complaining. At that point it fails with

KERNEL: Error: E8017 : Internal application error. Please contact Aldec Support.

@Andy-Darlington What is your experience with VHDL-2019 and Active-HDL? Do you know how stable it is?

I think we may have to revert this such that v4.6.0 can be released.

[umarcor]

I think we may have to revert this such that v4.6.0 can be released.

Done.

[Andy-Darlington]

I tried to run the simple hello world example with VHDL-2019 and it complains about stack size. I think the default is 32 MB and it requires 2048 before it stops complaining. At that point it fails with

KERNEL: Error: E8017 : Internal application error. Please contact Aldec Support.

@Andy-Darlington What is your experience with VHDL-2019 and Active-HDL? Do you know how stable it is?

I think we may have to revert this such that v4.6.0 can be released.

@LarsAsplund not a lot of experience yet, still just investigating getting stable build scripts etc before porting over.

Just to double check, are you running ActiveHDL 12.0? This is the only version that supports VHDL 2019. I've included by simulation options below incase this helps.

activeHdlVsimArgs = ["-advdataflow",        # Turns on advance data flow
                         "-acdb",               # Use acdb database for code coverage
                         "-acdb_cov sbecatmpf", # Enable Statement, Branch, expression, Condition, Assertion, Toggle, m = fsm, path & osvvm function coverage options
                         "-exc control",        # Enables expression/Condition coverage in Control mode
                         "-stack 256",
                         "-retval 256",
                         "-pathmode advanced"]  # Advance mode for path coverage

    vu.set_sim_option("activehdl.vsim_flags", activeHdlVsimArgs, allow_empty=True)
    vu.set_sim_option("enable_coverage", True, allow_empty=True)

[LarsAsplund]

@Andy-Darlington I only used -stack and -dbg. I will test -retval to see if that makes a difference. I don't think the others should be needed as long as I don't do coverage.

[LarsAsplund]

@Andy-Darlington It didn't fix it but I dug a bit deeper and found that changing this line to

    if call_path'length >= path_offset + 2 then

removes the problem and there is no reason to increase the stack size anymore. Can you try the same fix locally?

[Andy-Darlington]

Hi Lars, I've run both with your above fix and without and both are working for me. I've not seen any issues with the stack size (I've tested at both 32 and 256 for stack and retval simulation options).