write_bus(...) doesn't check if write address is inside address range of the bus

[creiter64]

Hi all,

I'm not 100% if that's how it's suposed to work, but I feel like it's not.

If I declare an AXI bus master with this statement:

constant AXI4_LITE_BUS : bus_master_t := new_bus(data_length => 32, address_length => 5);

I can later perform:

write_bus(net, AXI4_LITE_BUS, 100, x"01234567");

without an error, even though 100 is outside of the 2^5=32 bytes adressable bytes on this bus. At least for me this hid an error in my testbench.

[LarsAsplund]

This is an unfortunate consequence of standard VHDL libraries treating vector truncation as a warning and not an error. I agree that VUnit should be more strict. I will tag this as an enhancement. I've seen people taking advantage of this behavior, even when working in "integer space" so it would be considered a backward compatibility breaking change that has to be delayed until v5.0.

As a workaround I suggest that you use the method set_sim_option("vhdl_assert_stop_level", "warning") on your VUnit object and see if there are other things being warned about