`if` without `else` is parsed incorrectly

[WorldofKerry]

Describe the bug
if without else in Python source code is parsed incorrectly

To Reproduce

def mod_10(n: int) -> int:
    """
    Computes n % 10
    """
    mod = 0
    quo = -1
    count = 0
    while count < n:
        quo += 1
        count += 10
    mod = n - quo * 10
    if mod == 10:
        return 0
    return mod

Gets the following output with optimization level 0

_state6: begin
    if ((_mod === $signed(10))) begin
        __output_0 <= $signed(0);
        _state <= _state7_assign0;
    end else begin
        __output_0 <= _mod;
        _state <= _state_done_assign0;
    end
end
_state7_assign0: begin
    __output_0 <= _mod;
    _state <= _state_done_assign0;

This Verilog fails when for mod_10(10)

Expected behavior

def mod_10(n: int) -> int:
    """
    Computes n % 10
    """
    mod = 0
    quo = -1
    count = 0
    while count < n:
        quo += 1
        count += 10
    mod = n - quo * 10
    if mod == 10:
        return 0
    else:
        return mod

Parses correctly.

[WorldofKerry]

Looking further, this bug seems to only appear with the Python backend.