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Incorrect comment in ct_idu_ir_rt module - needs correction #40

@MiaoHao-oops

Description

@MiaoHao-oops

Description:
I noticed that there is an error in the comment in the ct_idu_ir_rt module in the ct_idu_ir_rt.v file. The comment does not accurately describe the logic's behavior. The comment is located at ct_idu_ir_rt.v:3714:

//if source register index of instruction 0 is same with
//destination register index of instruction 1, dependency
//information is bypass from instruction 0 value
//the normal source in split instruction with implicit dependency
//should not match split destination

which describes the generation of signal rt_inst1_src0_match_inst0. While, the following logic is:

assign rt_inst1_src0_match_inst0 =
            ctrl_rt_inst1_vld && dp_rt_inst1_src0_vld
         && ctrl_rt_inst0_vld && dp_rt_inst0_dst_vld
         && (dp_rt_inst0_dst_reg[5:0] == dp_rt_inst1_src0_reg[5:0])
            && (dp_rt_inst0_dst_reg[5:0] != 6'd0)
         && !dp_rt_dep_info[DEP_INST01_SRC0_MASK];

which compares the source0 register index of instruction 1 with the destination register index of instruct 0, and is in conflict with the comment shown below. The same error comes with the comments of rt_inst1_src1_match_inst0 and rt_inst1_src2_match_inst0.

From the point of view of design, rt_inst1_src0_match_inst0 controls whether the preg index of instruction 1's src0 register should be bypassed from instruction 0's preg index. Thus, the assign statements are correct while the comments of corresponding statements are wrong.

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