LUT usage regression inside memstreamer/MVAU

[fpjentzsch]

test_build[sanity_bnn_w1_a1_lfc_Pynq-Z1] fails on dev branch.

The failure is due to slice over-utilization on the PYNQ-Z1 board, because each of the 3 memstreamers consumes ~ 2.000 LUTs more than before. Curiously, the memstream width in these cases is 2048 and in the schematic it looks like each output bit is unnecessarily registered when compared to the old state.

Apparently, this happens with Vivado 2024.2 but not 2022.2.

I suspect the recent addition of weight set selection support to be the cause (#1441 or #1443), but more testing is needed.

[fpjentzsch]

Upon closer inspection it turns out there are 2 separate effects that cause test_build[sanity_bnn_w1_a1_lfc_Pynq-Z1] to fail this way:

	2022.2	2022.2	2024.2	2024.2
	Old memstreamer	New memstreamer	Old memstreamer	New memstreamer
MVAU_0	4558	4558	5114 (+12%)	5114 (+12%)
MVAU_1	7382	7382	7496 (+2%)	7496 (+2%)
MVAU_2	6233	6233	8035 (+29%)	8035 (+29%)
MVAU_3	380	380	544 (+43%)	544 (+43%)
WSTRM_0	763	2268 (+3x)	598	2157 (+3.6x)
WSTRM_1	854	2894 (+3.4x)	741	2781 (+3.8x)
WSTRM_2	853	2894 (+3.4x)	740	2781 (+3.8x)
WSTRM_3	244	315 (+29%)	244	315 (+29%)
Top	35375 (PASS)	41030 (PASS)	38275 (PASS)	43984 (FAIL)

In summary, LUT cost increased by +24%.

Effect 1: memstreamer

The new memstreamer implementation (mentioned above) includes additional output registers that were not present in the previous implementation shown in this schematic:
(Old memstreamer, all BRAM outputs directly connected to output weight stream)

In the new implementation this signal goes through a series of FDRE -> SRL16E -> FDRE cells, adding approx. 1 LUT per weight stream bit to the cost.

According to @preusser this is intended behavior, designed to improve timing. I'm not sure if an almost 4x increase in resource cost (in this case) is worth it though. Maybe we should make this behavior optional and/or do further analysis on where the critical paths in typical FINN accelerators lie to gauge the effectiveness of the resource <-> clock frequency trade-off for different operators.

Effect 2: HLS regression

There is a Vitis HLS regression (between 2022.2 and 2024.2) that increases LUT cost of the HLS MVAU (and potentially other FINN HLS operators) by introducing some kind of unnecessary output registers/multiplexers.

This issue is known internally and will hopefully be addressed in a future tool version.