Architectural Guidance Required: Connecting ACE Master to Unified Req/Resp Interconnect #29
Description
Hi,
I'm working with the master-ace.h module and have a question regarding its port configuration.
My specific interconnect IP employs a unified socket that manages simultaneous request and response paths. Given the structure of the ACE master node, could you advise on the standard pattern for connecting these components? Specifically, I am looking to ensure that the synchronization and phase requirements remain TLM-2.0 compliant during this integration.
Are there existing adapter examples or wrappers within the library that you would recommend for this use case?