diff --git a/Makefile b/Makefile
index 74fc674..756c6cb 100644
--- a/Makefile
+++ b/Makefile
@@ -16,7 +16,7 @@
 #  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 #
 
-# All supported SYN_LIST tags: vivado quartus xst yosys verific dc lec
+# All supported SYN_LIST tags: vivado quartus xst yosys verific dc lec circt
 # All supported SIM_LIST tags: xsim isim modelsim icarus verilator yosim
 
 SYN_LIST     := vivado yosys
@@ -28,7 +28,7 @@ IVERILOG_DIR := # /home/clifford/Work/iverilog/instdir/bin
 MODELSIM_DIR := /opt/intelFPGA_lite/17.0/modelsim_ase/linux
 QUARTUS_DIR  := /opt/intelFPGA_lite/17.0/quartus/bin
 VIVADO_DIR   := /opt/Xilinx/Vivado/2018.3/bin
-VERILATOR    := /usr/local/bin/verilator
+VERILATOR    := $(which verilator)
 MAKE_JOBS    := -j4 -l8
 YOSYS_MODE   := default
 REPORT_FULL  :=
diff --git a/README b/README
index 718377d..4dabe0f 100644
--- a/README
+++ b/README
@@ -12,6 +12,7 @@ supported:
 	Altera Quartus II Web Edition (17.0)
 	Cadence Conformal LEC (8.1)
 	Synopsys Design Compiler (C-2009.06)
+	CIRCT (no specific version)
 
 Note: Cadence Conformal and Synopsys Design Compiler are disabled by
 default. Add "lec" and "dc" to SYN_LIST in the Makefile to enable them.
diff --git a/scripts/report.sh b/scripts/report.sh
index 9a04e56..781e3ec 100644
--- a/scripts/report.sh
+++ b/scripts/report.sh
@@ -335,7 +335,7 @@ if [[ " ${SIM_LIST} " == *" verilator "* ]]; then
 		done
 		bash ../../scripts/verilator_tb.sh ${job} $( echo rtl ${SYN_LIST} | tr ' ' , ) $( echo $inputs | tr -d ' ' ) \
 				$( echo $bits\'b0 ~$bits\'b0 $( sort -u fail_patterns.txt | sed "s/^/$bits'b/;" ) $extra_patterns | tr ' ' ',' ) $undef_ref > sim_verilator.cc
-		if ! make -C obj_dir -f Vtestbench.mk || ! g++ -I "$( grep 'VERILATOR_ROOT *=' obj_dir/Vtestbench.mk | sed 's,.*= *,,' )/include" -o sim_verilator sim_verilator.cc obj_dir/Vtestbench__ALL.a; then
+		if ! make -C obj_dir -f Vtestbench.mk || ! g++ -I "$( grep 'VERILATOR_ROOT *=' obj_dir/Vtestbench.mk | sed 's,.*= *,,' )/include" -o sim_verilator sim_verilator.cc obj_dir/Vtestbench__ALL.a obj_dir/libVtestbench.a obj_dir/libverilated.a; then
 			echo -n > sim_verilator.log
 		else
 			./sim_verilator > sim_verilator.log
@@ -496,7 +496,7 @@ fi
 			$y =~ /^(module|input|wire|reg|integer|localparam|output|assign|signed|if|else|for|begin|end|case|endcase|task|endtask|function|endfunction|always|initial|endmodule|\$(display|unsigned|signed))$/ ? "#080" : "#008", $y)!eg' )</small></pre>"
 
 	echo "<!-- VALUES:BEGIN -->"
-	python ../../scripts/valtab.py ${SIM_LIST}
+	python2 ../../scripts/valtab.py ${SIM_LIST}
 	echo "<!-- VALUES:END -->"
 	echo "<!-- REPORT:END -->"
 } > report.html
diff --git a/scripts/syn_circt.sh b/scripts/syn_circt.sh
new file mode 100644
index 0000000..02839d0
--- /dev/null
+++ b/scripts/syn_circt.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+#
+#  VlogHammer -- A Verilog Synthesis Regression Test
+#
+#  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
+#
+#  Permission to use, copy, modify, and/or distribute this software for any
+#  purpose with or without fee is hereby granted, provided that the above
+#  copyright notice and this permission notice appear in all copies.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+#
+
+if [ $# -ne 1 ]; then
+	echo "Usage: $0 <job_name>" >&2
+	exit 1
+fi
+
+job="$1"
+set -e
+set -o pipefail
+
+mkdir -p syn_circt
+
+if ! timeout 180 circt-verilog rtl/$job.v -o syn_circt/$job.mlir 2>syn_circt/$job.txt
+then
+	{
+		echo '// [VLOGHAMMER_SYN_ERROR] circt-verilog crashed'
+		echo "/*"
+		cat syn_circt/$job.txt
+		echo "*/"
+		sed -e '/^ *assign/ s,^ *,//,;' rtl/$job.v
+	} >  syn_circt/$job.v
+elif ! timeout 180 circt-opt --lower-seq-to-sv --export-verilog syn_circt/$job.mlir -o /dev/null >syn_circt/$job.v 2>syn_circt/$job.txt
+then
+	{
+		echo '// [VLOGHAMMER_SYN_ERROR] circt-opt crashed'
+		echo "/*"
+		cat syn_circt/$job.txt
+		echo "*/"
+		sed -e '/^ *assign/ s,^ *,//,;' rtl/$job.v
+	} >  syn_circt/$job.v
+fi
+
+rm -f syn_circt/$job.mlir
+rm -f syn_circt/$job.txt
diff --git a/scripts/verilator_tb.h b/scripts/verilator_tb.h
index 1079089..07bedb9 100644
--- a/scripts/verilator_tb.h
+++ b/scripts/verilator_tb.h
@@ -14,7 +14,7 @@ bool pattern_bits[PATTERN_BITS_N];
 int pattern_cursor, pattern_idx;
 
 std::string input_pat_list;
-std::vector<string> input_patterns_buf;
+std::vector<std::string> input_patterns_buf;
 std::set<int> undef_bits;
 
 static inline void set_pattern(const char *pattern)