<dreg>The operand is stored in an 8-bit data register (A, B, C or D).
<ireg>The operand is stored in an 8-bit index register (X, Y, L or H). These
registers may also participate in address formation.
<r16>The operand is stored in a 16-bit register pair (Z or SP).
<r8>The operand is stored in a 8-bit system register (SR or VBR)
<instruction>or
<instruction> #nThe operand is fully encoded in the opcode. No additional operand bytes are fetched. Some instructions have no operand at all, while others encode small immediate value directly within the opcode.
#imm8
or
#imm16The operand is encoded in the byte/word immediately following the opcode.
rel8
or
rel16The operand is encoded in the byte/word immediately following the opcode. The value contained in the operand is encoded as a signed integer.
abs16The word following the opcode is treated as a 16-bit memory address. The operand is read from or written to that address.
[imm8:<ireg>]
or
imm8:<ireg>A 16-bit address is formed by concatenating the immediate high-byte with the selected index register as the low byte.
Address = (imm8 << 8) | <ireg>[<r16>]The pair-register contains the complete 16-bit memory address. The operand is accessed through the address stored in register-pair.
[<r16>+]The operand is accessed through the address stored in the pair-register. Then immediately after the memory access, the pair-register is incremented.
[-<r16>]The pair-register is immediately decremented before the memory access. Then the operand is accessed through the resulting address.
Instructions may be encoded in more than one byte following the opcode. They may be encoded in one of these formats:
+--------+
| Opcode |
+--------+
The opcode completely defines the instruction and its operands. Examples:
HALT
NOP
TRAP #n3
BIT [<r16>]
MOV <ireg>, VBR
MOV SR, <dreg>
INC <dreg>
MULU <dregx>, <dregy>
DIVS <dregx>, <dregy>
RTS
JMP [<r16>]+--------+------+
| Opcode | Byte |
+--------+------+
After the opcode byte there is an additional byte as an operand. The byte operand can encode either an unsigned or a signed integer. Examples:
BCLR <dreg>, #imm8
BIT <dreg>, #imm8
MOVI <dreg>, #imm8
CMPI <dreg>, #imm8
BRA rel8
Bcc rel8+--------+----------+-----------+
| Opcode | Low Byte | High Byte |
+--------+----------+-----------+
After the opcode byte there is two additional bytes as an operand. The bytes following the opcode form a 16-bit word, which can encode either an unsigned or a signed integer. Examples:
BIT <dreg>, abs16
MOVI <r16>, #imm16
JMP abs16
JSR abs16
BSR rel16+--------+-----+
| Opcode | Ext |
+--------+-----+
The opcode can be extended to 16-bit, which the extension byte encodes additional operands and data. Examples:
EXG <dreg>, <ireg>
MOV <dreg>, <dregy>
MOV <dreg>, [<r16>]
MOV [<r16>+], <dreg>
ADC <dreg>, [-<r16>]
CMP <dreg>, [<r16>]
XOR [<r16>+], <dreg>+--------+-----+------+
| Opcode | Ext | Byte |
+--------+-----+------+
After the extended opcode, there is an additional byte as an operand. This operand encodes an unsigned or signed integer data. Examples:
MOV <dreg>, [imm8:<ireg>]
MOV [imm8:<ireg>], <dreg>
XOR <dreg>, [imm8:<ireg>]
XOR [imm8:<ireg>], <dreg>+--------+-----+----------+-----------+
| Opcode | Ext | Low Byte | High Byte |
+--------+-----+----------+-----------+
After the extended opcode, there are two additional bytes as an operand. The bytes following the extended opcode form a 16-bit word. Examples:
MOV <dreg>, abs16
MOV abs16, <dreg>
MOV <ireg>, abs16
MOV abs16, <ireg>
AND <dreg>, abs16
CMP abs16, <dreg>
OR <ireg>, abs16
SUB abs16, <ireg>NOTE: Addressing modes are independent of instruction encoding. The same addressing mode may appear in different instruction formats. For example, the
BITinstruction uses Immediate, Absolute or Indirect addressing modes without an extension byte, whereas binary arithmetic and data movement use the same addressing mode with an extension byte.
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