Bug: Incorrect bit layout visualization for Motorola (@0) signals

[TheHardy04]

Summary

I might be wrong, but I think that when visualizing a message layout that uses Motorola (Big-Endian, @0) encoding, the Layout tab incorrectly highlights the bit matrix using an Intel (Little-Endian) sequential pattern. The tool highlights the cells contiguously rather than following the correct Motorola byte-boundary wrap-around.

Steps to reproduce

Load a DBC file containing a Motorola signal. Here is the snippet used (from the HV500 datasheet):

BO_ 1028 HV500_ERPM_DUTY_VOLTAGE: 8 HV500_controller
 SG_ Actual_ERPM : 7|32@0- (1,0) [-120000|120000] "ERPM"  HV500_commands
 SG_ Actual_Duty : 39|16@0- (0.1,0) [-100|100] "%"  HV500_commands
 SG_ Actual_InputVoltage : 55|16@0- (1,0) [0|1000] "V"  HV500_commands

Open the message HV500_ERPM_DUTY_VOLTAGE (ID: 1028) in the Candb Studio layout tab.

Or it migh be more relevant in this

BO_ 1156 HV500_MISC: 8 HV500_controller
 SG_ Actual_Throttle : 7|8@0- (1,0) [0|100] "%"  HV500_commands
 SG_ Actual_Brake : 15|8@0- (1,0) [0|100] "%"  HV500_commands
 SG_ Digital_input_1 : 16|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Digital_input_2 : 17|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Digital_input_3 : 18|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Digital_input_4 : 19|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Digital_output_1 : 20|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Digital_output_2 : 21|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Digital_output_3 : 22|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Digital_output_4 : 23|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Drive_enable : 31|8@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Capacitor_temp_limit : 32|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ DC_current_limit : 33|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Drive_enable_limit : 34|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ IGBT_accel_limit : 35|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ IGBT_temp_limit : 36|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Input_voltage_limit : 37|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Motor_accel_limit : 38|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Motor_temp_limit : 39|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ RPM_min_limit : 40|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ RPM_max_limit : 41|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ Power_limit : 42|1@0+ (1,0) [0|1] ""  HV500_commands
 SG_ CAN_map_version : 63|8@0+ (0.1,0) [0|255] "Version"  HV500_commands

Expected behavior

For Actual_ERPM : 7|32@0-, because it is a 32-bit Motorola signal with a start bit of 7 (which is the MSB), it should occupy the following bits:

Byte 0: Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1: Bits 15, 14, 13, 12, 11, 10, 9, 8

Byte 2: Bits 23, 22, 21, 20, 19, 18, 17, 16

Byte 3: Bits 31, 30, 29, 28, 27, 26, 25, 24 (with bit 24 being the LSB).

Actual behavior

The layout tab maps the signal sequentially from bit index 7 all the way through index 38. While it correctly labels the start as msb, the physical cells highlighted (7 through 38 spanning into Byte 4) represent an Intel (@1) Little-Endian allocation.

Where does it show up?

Custom DBC editor (webview)

VS Code version

Version: 1.117.0

CANdb Studio version

0.2.0

OS

Windows 11

Logs / screenshots (optional)

Minimal .dbc or snippet (optional)

[afri-bit]

@TheHardy04

Thanks for the issue.

I will tackle this issue as soon as possible. Currently my schedule is quite packed, i will definitely get back to your issue and fix it.

I hope you enjoy using the tool :)