missing define.v?

I'm trying to synthesize the core in Vivado. It pointed out the fact that in rtl/ao486/memory/avalon_mem.v, it's trying to include "defines.v", but a file name defines.v does not exist in that same directory. What's the correct solution? Does verilog/Vivado have the concept of include paths?

Sorry if the answer is obvious, I'm more of a VHDL user than a Verilog user.