Pin usage ?

[jluke1]

According to Readme.md the pin usages is
Total pins : 108 / 529 ( 20 % )
However when I compile using Quartus II Lite 18.1 I get
Total pins : 207 / 529 (39 % )
I have been trying to recompile for a 10 LP dev board 10CL025YU256I7G
and 207 pins will not fit 108 would be fine.
Am curious why the IO bus has been given separate input and output from
the main bus.

Thank you for the excellent work
John Luke

[alfikpl]

Hello John,
Well, the readme.md contains information about the soc top-level module, not the ao486 module.
The IO and memory buses have separate pins, because it is easier to interface with the Avalon bus this way.

Cheers,
Aleksander Osman

[jluke1]

Dear Aleksander,
Ah. I should have read the file more carefully.

Any advice on how to port to Intel 10 LP dev board 10CL025YU256I7G ?
Quartus tells me 160 pins available.

The frix version of a0486 passes the pin count but then fails on memory
usage "too many m9k" probably because of the VGA code. At this point
would be happy to get just a serial only version running. (I threw out my
last VGA monitor a while ago).

Thanks
John Luke