HMC7044 PLL2 External VCO Issue

[BrentK-ADI]

There looks to be an issue in the way the HMC7044 driver handles the PLL2 External VCO. If the external VCO falls within the internal VCO range (2.4-3.2GHz) and the device tree is configured to have the pll2-output-frequency match, the driver should work correctly. However, the External VCO can range from 400MHz-6GHz. Things of note:

• It appears the PLL2 parameter calculations are done on the pll2-output-frequency value obtained from the device tree and range checked against the internal VCO range. This is the value used in the N2, R2, etc calculations.
  

  linux/drivers/iio/frequency/hmc7044.c

  Lines 1014 to 1015 in 1d30714

  	if (pll2_freq < HMC7044_LOW_VCO_MIN ||
  	pll2_freq > HMC7044_HIGH_VCO_MAX) {

• Following the derivation of N2, R2, etc, the external VCO flag is checked, and the hmc->pll2_freq is reassigned to the external VCO clock frequency. This would effectively invalidate any PLL parameters if the external VCO clock didn't match pll2-output-frequency.
  

  linux/drivers/iio/frequency/hmc7044.c

  Lines 1109 to 1111 in 1d30714

  	if (hmc->clkin1_vcoin_en) {
  	hmc->pll2_freq = hmc->clkin_freq_ccf[1] ?
  	hmc->clkin_freq_ccf[1] : hmc->clkin_freq[1];

I think there are 2 issues here:

1. If the external VCO clock and pll2-output-frequency don't match, the PLL parameters will be incorrectly calculated.
2. If the external VCO is outside the internal range, setting pll2-output-frequency to satisfy problem 1 will fail due to the range check.

I think an update should correctly assign hmc->pll2_freq at the start of hmc7044_setup and dynamically perform the range check based on the source.

Thoughts? Am I interpreting the driver and device functionality correcty?