Increasing payload size to 256K breaks memory training

[sqazi]

Memory training failed very quickly. I also noticed that the build showed a red error message showing that timing constraints were not met.

[kgugala]

bigger payload size will allocate more blockrams for storing the program. This will need more logic to handle this and makes it harder for the tools to route. If you have timing violations the system may simply not work correctly in the end. This can result in failed training.

Can you share the exact command you used for running the build?

Also - new HW revision should make it easier to have more memory in the system. US+ FPGAs have more memory resources.

[sqazi]

Ok, so the timing error message seems to happen even without the increased payload size. This is the message:

"CRITICAL WARNING: [Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports."

Please find attached the timing summary and vivado log.
vivado.log
antmicro_ddr5_tester_timing_synth.rpt.txt

I have only one extra patch in my tree, which is to increment the version of the openFPGALoader, since the old version doesn't work on my system. The rest of the tree is just at commit bd05e52.

This passes memory training, but the first time the board became unreachable during memory testing at the end of mem.py. I am not sure if it's related. Training log is attached.

training_hang.txt

The second time it was fine.

---

I repeated the same experiment with the following command line, increasing the payload size:

make build TARGET_ARGS="--l2-size 256 --build --iodelay-clk-freq 400e6 --bios-lto --rw-bios --module MTC10F1084S1RC --no-sdram-hw-test --payload-size 262144"

Here are the logs:
vivado.2.log
antmicro_ddr5_tester_timing_synth.rpt.2.txt

It hangs here:

$ python ./mem.py
Using generated target files in: ../../build/ddr5_tester
Board info: Row Hammer Tester SoC on xc7k160tffg676-3, git: 81a1b5c5efeedc36a9e92c218ebf5403a3da8dbf 2024-12-19 12:35:56
=== Waiting for CPU to initialize DRAM ===

    __   _ __      _  __
   / /  (_) /____ | |/_/
  / /__/ / __/ -_)>  <
 /____/_/\__/\__/_/|_|

Build your hardware, easily!

(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs

BIOS built on Dec 19 2024 12:36:00

:(.