Unable to run mcf benchmark

[nobueno]

Compiled the 429.mcf benchmark using "riscv-unknown-elf-gcc-4.9.2" compiler and then modified job file to run simulation.
jobfile: rtlsim -s100000 pk -c mcf inp.in

Getting error (no modification was done in RTL source code):

AnyCore Copyright (c) 20011-2016 by Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, and Eric Rotenberg.
AnyCore was derived from AnyCore Copyright (c) 2007-2016 by Niket K. Choudhary, Brandon H. Dwiel,
                            and Eric Rotenberg. All Rights Reserved.


Cycle:       10000 Commit:        2144 IPC:0.21 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 312  Br-Mispredict: X Violation: 0
Cycle:       20000 Commit:        4314 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 627  Br-Mispredict: X Violation: 0
Cycle:       30000 Commit:        6484 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 942  Br-Mispredict: X Violation: 0
Cycle:       40000 Commit:        8661 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 1259  Br-Mispredict: X Violation: 0
Cycle:       50000 Commit:       10856 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 1577  Br-Mispredict: X Violation: 0
Cycle:       60000 Commit:       13030 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 1893  Br-Mispredict: X Violation: 0
Cycle:       70000 Commit:       15200 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 2208  Br-Mispredict: X Violation: 0
Cycle:       80000 Commit:       17370 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 2523  Br-Mispredict: X Violation: 0
Cycle:       90000 Commit:       19554 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 2841  Br-Mispredict: X Violation: 0
Cycle:      100000 Commit:       21724 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 3156  Br-Mispredict: X Violation: 0
Cycle:      110000 Commit:       23882 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 3468  Br-Mispredict: X Violation: 0
Cycle:      120000 Commit:       26064 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 3786  Br-Mispredict: X Violation: 0
Cycle:      130000 Commit:       28234 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 4101  Br-Mispredict: X Violation: 0
Cycle:      140000 Commit:       30404 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 4416  Br-Mispredict: X Violation: 0
Cycle:      150000 Commit:       32586 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 4731  Br-Mispredict: X Violation: 0
Cycle:      160000 Commit:       34756 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 5046  Br-Mispredict: X Violation: 0
Cycle:      170000 Commit:       36926 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 5361  Br-Mispredict: X Violation: 0
Cycle:      180000 Commit:       39098 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 5676  Br-Mispredict: X Violation: 0
Cycle:      190000 Commit:       41291 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 5994  Br-Mispredict: X Violation: 0
Cycle:      200000 Commit:       43446 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 6309  Br-Mispredict: X Violation: 0
Cycle:      210000 Commit:       45641 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 6626  Br-Mispredict: X Violation: 0
Cycle:      220000 Commit:       47812 IPC:0.22 BTB-Miss: 15  BTB-Miss-Rtn: 2  Br-Count: 6942  Br-Mispredict: X Violation: 0
Cycle:      230000 Commit:       52699 IPC:0.23 BTB-Miss: 367  BTB-Miss-Rtn: 75  Br-Count: 8068  Br-Mispredict: X Violation: X
Cycle:      240000 Commit:       54578 IPC:0.23 BTB-Miss: 530  BTB-Miss-Rtn: 88  Br-Count: 8880  Br-Mispredict: X Violation: X
Cycle:      250000 Commit:       56868 IPC:0.23 BTB-Miss: 631  BTB-Miss-Rtn: 97  Br-Count: 9415  Br-Mispredict: X Violation: X
Cycle:      260000 Commit:       61746 IPC:0.24 BTB-Miss: 676  BTB-Miss-Rtn: 102  Br-Count: 10781  Br-Mispredict: X Violation: X
Cycle:      270000 Commit:       71746 IPC:0.27 BTB-Miss: 676  BTB-Miss-Rtn: 102  Br-Count: 13281  Br-Mispredict: X Violation: X
Cycle:      280000 Commit:       80589 IPC:0.29 BTB-Miss: 701  BTB-Miss-Rtn: 106  Br-Count: 15579  Br-Mispredict: X Violation: X
Cycle:      290000 Commit:       85376 IPC:0.29 BTB-Miss: 734  BTB-Miss-Rtn: 114  Br-Count: 17121  Br-Mispredict: X Violation: X
Cycle:      300000 Commit:       87460 IPC:0.29 BTB-Miss: 797  BTB-Miss-Rtn: 138  Br-Count: 17929  Br-Mispredict: X Violation: X
State for DPI_SIM:
pc       : 0x    3288	epc      : 0x   24a98	badvaddr : 0x   24a98	evec     : 0x    405c	ptbr     : 0xff800000	
pcr_k0   : 0x   10044	pcr_k1   : 0x7fffff10	cause    :          1	tohost   : 0x       0	fromhost : 0x       0	
count    :     187684	compare  :          0	sr       : 0x      e9	fflags   : 0x       0	frm      : 0x       0	load_resv:   ffffffffffffffff	


State for isa_sim:
Cycle 0: Seq 87685 PC 0x0000000000003244 (0x0330000f) fence
next_pc    : 3248	Mem addr   : 2ae20	entry_id   : 644	
RS1 Valid  : 0	RS1 Logical: 15	RS1 Value  : 0x28000	RS1 Value  : 163840	RS1 Value  : 163840.000000	
RS2 Valid  : 0	RS2 Logical: 11	RS2 Value  : 0x28000	RS2 Value  : 163840	RS2 Value  : 163840.000000	
RD  Valid  : 0	RD  Logical: 15	RD  Value  : 0x0	RD  Value  : 0	RD  Value  : 0.000000	

pc       : 0x    3244	epc      : 0x   24a98	badvaddr : 0x   24a98	evec     : 0x    405c	ptbr     : 0xff800000	
pcr_k0   : 0x   10044	pcr_k1   : 0x7fffff10	cause    :          1	tohost   : 0x       0	fromhost : 0x       0	
count    :     187684	compare  :          0	sr       : 0x      ed	fflags   : 0x       0	frm      : 0x       0	load_resv:   ffffffffffffffff	

Read CSR 0x506
Write CSR 0x506 ->  0x2DD25
Read CSR 0x503
Read CSR 0x504
Read CSR 0x506
Read CSR 0x508
Read CSR 0x509
Read CSR 0x50a
Instruction 0, Cycle 0: State check failed.
Simulation stopped via $stop(1) at time 3025355 NS + 0
/proj/txace/anycore/anycore-riscv/anycore-riscv-src/testbenches/simulate.sv:1049 	      $stop();
ncsim> 

[nobueno]

Tried to run "sjeng" with the following command:
rtlsim -s10000000000 -l0 -g pk -c sjeng sjeng_test_input.txt

This results following error (truncated; log file attached):

Timing simulator popping entry 1
Debug buffer head: 1 tail 1023 length 1023 active size 1024
Functional simulator hungry
ISA_SIM next timer: 2884900864
Taking interrupt status: 0xfc irqs: 0x0
Starting debug buffer entry 0
Commit Count: 10000001024 core   0: 0x0000000000019520 (0x9dc7a703) lw      a4, -1572(a5)
Pushing operand type: 0 to entry 0
Pushing operand type: 4 to entry 0 addr 747996
Pushing operand type: 3 to entry 0
RS1: 749568 RS2: 3 RD: 0 STATUS: 252
Debug buffer head: 1 tail 0 length 1024 active size 1024
*ER PC MISMATCH!!
 CYCLE: 18  V_PC=0x00000000000285d4   FS_PC=0x00000000000285d8
Cycle 0: Seq 2 PC 0x00000000000285d8 (0xccf512e3) bne     a0, a5, pc - 828
next_pc    : 285dc	Mem addr   : 0	entry_id   : 1	
RS1 Valid  : 1	RS1 Logical: 10	RS1 Value  : 0x1	RS1 Value  : 1	RS1 Value  : 1.000000	
RS2 Valid  : 1	RS2 Logical: 15	RS2 Value  : 0x1	RS2 Value  : 1	RS2 Value  : 1.000000	
RD  Valid  : 0	RD  Logical: 0	RD  Value  : 0x0	RD  Value  : 0	RD  Value  : 0.000000	

Read CSR 0x506
Write CSR 0x506 ->  0x2540BE402
Read CSR 0x503
Read CSR 0x504
Read CSR 0x506
Read CSR 0x508
Read CSR 0x509
Read CSR 0x50a
Simulation stopped via $stop(1) at time 140835 NS + 0
/proj/txace/mxm084100/anycore/anycore-riscv/anycore-riscv-src/testbenches/simulate.sv:1049 	      $stop();

console.log