SPI controller config customization

[pa3gsb]

Running the tinkerboard:

Linux tinkerboard 4.4.103+ #1 SMP Fri Jun 22 16:14:49 CST 2018 armv7l GNU/Linux

linaro@tinkerboard:~/tinker_io/tinkerboard_io/build$ sudo ./spi_example
Successfully initialized
Transfer successful

pin 19 and 20 connected together!

I suspected it not to work due to the config in your code:

struct spi_pin_config_t _spi_configs[] = {
{.clk = 10, .txd = 12, .rxd = 14, .cs0 = 28, .cs1 = 30, .spi_block_offset = RK3288_SPI0_BLOCK_OFFSET, .initialized = 0,
.pll_sel_offset = RK3288_CRU_CLKSEL25_OFFSET,
.clk_src_offset = RK3288_CRU_CLKGATE2_OFFSET, .clk_gate_flag = 9,
.pclk_src_offset = RK3288_CRU_CLKGATE6_OFFSET, .pclk_gate_flag = 4,
.softrst_offset = RK3288_CRU_SOFTRST_OFFSET, .softrst_flag = 3},

{.clk = 22, .txd = 18, .rxd = 20, .cs0 = 23, .cs1 = 25, .spi_block_offset = RK3288_SPI2_BLOCK_OFFSET, .initialized = 0,
	.pll_sel_offset = RK3288_CRU_CLKSEL39_OFFSET,
	.clk_src_offset = RK3288_CRU_CLKGATE2_OFFSET, .clk_gate_flag = 11,
	.pclk_src_offset = RK3288_CRU_CLKGATE6_OFFSET, .pclk_gate_flag = 6,
	.softrst_offset = RK3288_CRU_SOFTRST_OFFSET, .softrst_flag = 5},

};

Why is this working?

Is there an other spi setup config interfering?

Maybe you can help me?

[arne48]

If you use a distribution where the SPI controllers are included in the device tree, then they will be initially configured by the kernel. This is also not recommended because the kernel basically can reconfigure the controller at any time and the library has no check for this and the communication will be corrupted.
I am using a modified version of armbian where I excluded the SPI controllers https://github.com/arne48/armbian_build.

About your other question I didn't really get the point. You connected pin 19 & 20, where I guess you mean 19 & 21. Because 20 is ground.
The numbers for the individual pins within configuration on the other hand are indices so they are all -1 off from what you might expect.

Did this answer your questions? If not, please give me some more information about the exact issue.

best regards.....

[pa3gsb]

Arne

Iam using the latest tinkerboard debian distro.

I do not load the spi driver.

You are right that i was connecting pin 19 and 21.

Your explaination about pin numbers make sense; now i understand why it is working.

I have built a software defined radio, https://github.com/pa3gsb/Radioberry-2.x
iam using the spi bus for getting and setting data in the FPGA. It is working at a raspberry pi with the pigpio library. The wiringPi lib is too slow, so i am looking for higher speed... and i found your implementation.

Ok i will give it another try... will let you know the result.

Tnx Johan

[arne48]

Sounds like an interesting project.
Sure please let me know about your results.

[pa3gsb]

Arne
It is working, however iam getting some buffer overruns.

I had to remove the following method 'tinkerboard_reset_header();'

The .clk_divider = 4 is working; with a divider of 2 it is not working.

struct spi_mode_config_t mode = {
	.clk_mode = 3,
	.clk_divider = 4,
	.data_frame_size = DFS_16,
	.slave_select = 24,
	.transfer_mode = TRANSMIT_RECEIVE,
	.byte_order = MSB_FIRST,
};

tinkerboard_spi_transfer(SPI2, iqdata, rx_buff, 6, mode);

So iam getting 6 bytes per transfer. This 48000 per second.

I do get some buffer overflows in the fpga. So i am searching for the clock...is it possible to change the main clock?

Johan

[arne48]

If I remember right a divider of 2 is equal to 66.7MHz. This might be just too fast your SPI slave.
And in the example I even use just a divider of 8. I am not too surprised that you had to reduce it from the maximum especially because the signal "quality" degrades on higher clock rates.

About the clock source question:
The RK3288 has several PLLs that can be used. I am using the "codec" PLL as this one is not affected by changing the CPUs clock speed. You can change the speed of this PLL if you want, which then changes the frequencies you achieve with the individual divider values for the SPI controller.

Because of IP issues I can't provide you datasheets for the RK3288. But you can find them on the internet using google ;)

[pa3gsb]

Tnx. I thought that the clock was 66.7MHz; but the clock is actual (2 * 66.7); minimum divider is 2 resulting in a max spi clock of 66.7.
Than there is not much to gain!

Because the project was initially intended for the rpi and the rpi did not supported slave SPI i had to make the FPGA slave. But i needed another line to tell the SBC that data is available; i think there is something to improve.

A way to improve is making use of the SPI slave option...

At this moment i do not have too much time but it is on my list to give it a try!

Tnx again for sharing.

Johan