FPGA_Autonomous_Testing/FGPA_IMPLEMENT_map.map at main · ayseidman/FPGA_Autonomous_Testing · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
Release 14.7 Map P.20131013 (lin64)
Xilinx Map Application Log File for Design 'FGPA_IMPLEMENT'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr b -c
100 -o FGPA_IMPLEMENT_map.ncd FGPA_IMPLEMENT.ngd FGPA_IMPLEMENT.pcf
Target Device  : xc3s200
Target Package : ft256
Target Speed   : -5
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date    : Mon Jun 13 14:59:48 2022

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s200' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:           266 out of   3,840    6%
  Number of 4 input LUTs:               160 out of   3,840    4%
Logic Distribution:
  Number of occupied Slices:            219 out of   1,920   11%
    Number of Slices containing only related logic:     219 out of     219 100%
    Number of Slices containing unrelated logic:          0 out of     219   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         357 out of   3,840    9%
    Number used as logic:               157
    Number used as a route-thru:        197
    Number used as Shift registers:       3

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 27 out of     173   15%
    IOB Flip Flops:                       1
  Number of BUFGMUXs:                     4 out of       8   50%

Average Fanout of Non-Clock Nets:                2.95

Peak Memory Usage:  533 MB
Total REAL time to MAP completion:  3 secs
Total CPU time to MAP completion:   3 secs

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "FGPA_IMPLEMENT_map.mrp" for details.