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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | +/dts-v1/; |
| 3 | + |
| 4 | +#include "rtl930x.dtsi" |
| 5 | + |
| 6 | +#include <dt-bindings/input/input.h> |
| 7 | +#include <dt-bindings/gpio/gpio.h> |
| 8 | +#include <dt-bindings/leds/common.h> |
| 9 | + |
| 10 | +/ { |
| 11 | + compatible = "hasivo,fw1100wp-4xs-4xgt", "realtek,rtl930x-soc"; |
| 12 | + model = "Hasivo FW1100WP-4XS-4XGT"; |
| 13 | + |
| 14 | + memory@0 { |
| 15 | + device_type = "memory"; |
| 16 | + reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */ |
| 17 | + <0x20000000 0x10000000>; /* 256 MiB highmem */ |
| 18 | + }; |
| 19 | + |
| 20 | + aliases { |
| 21 | + led-boot = &led_sys; |
| 22 | + led-failsafe = &led_sys; |
| 23 | + led-running = &led_sys; |
| 24 | + led-upgrade = &led_sys; |
| 25 | + }; |
| 26 | + |
| 27 | + chosen { |
| 28 | + stdout-path = "serial0:38400n8"; |
| 29 | + }; |
| 30 | + |
| 31 | + keys { |
| 32 | + compatible = "gpio-keys"; |
| 33 | + |
| 34 | + button-reset { |
| 35 | + label = "reset"; |
| 36 | + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; |
| 37 | + linux,code = <KEY_RESTART>; |
| 38 | + }; |
| 39 | + }; |
| 40 | + |
| 41 | + leds { |
| 42 | + compatible = "gpio-leds"; |
| 43 | + |
| 44 | + led_sys: led-0 { |
| 45 | + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; |
| 46 | + color = <LED_COLOR_ID_GREEN>; |
| 47 | + function = LED_FUNCTION_STATUS; |
| 48 | + }; |
| 49 | + }; |
| 50 | + |
| 51 | + led_set { |
| 52 | + compatible = "realtek,rtl9300-leds"; |
| 53 | + |
| 54 | + led_set0 = < |
| 55 | + ( // RED 10G |
| 56 | + RTL93XX_LED_SET_10G | |
| 57 | + RTL93XX_LED_SET_LINK | |
| 58 | + RTL93XX_LED_SET_ACT |
| 59 | + ) |
| 60 | + ( // GREEN Red indicates 10 Gbit/s, while green indicates 2.5 Gbit/s (and possibly all lower speeds). |
| 61 | + RTL93XX_LED_SET_10M | |
| 62 | + RTL93XX_LED_SET_100M | |
| 63 | + RTL93XX_LED_SET_1G | |
| 64 | + RTL93XX_LED_SET_2P5G | |
| 65 | + RTL93XX_LED_SET_LINK | |
| 66 | + RTL93XX_LED_SET_ACT |
| 67 | + ) |
| 68 | + >; |
| 69 | + }; |
| 70 | + |
| 71 | + sfp0: sfp-p1 { |
| 72 | + compatible = "sff,sfp"; |
| 73 | + i2c-bus = <&i2c0>; |
| 74 | + los-gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; |
| 75 | + mod-def0-gpio = <&gpio0 1 GPIO_ACTIVE_LOW>; |
| 76 | + tx-disable-gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; |
| 77 | + maximum-power-milliwatt = <2000>; |
| 78 | + #thermal-sensor-cells = <0>; |
| 79 | + }; |
| 80 | + |
| 81 | + sfp1: sfp-p2 { |
| 82 | + compatible = "sff,sfp"; |
| 83 | + i2c-bus = <&i2c1>; |
| 84 | + los-gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>; |
| 85 | + mod-def0-gpio = <&gpio0 4 GPIO_ACTIVE_LOW>; |
| 86 | + tx-disable-gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; |
| 87 | + maximum-power-milliwatt = <2000>; |
| 88 | + #thermal-sensor-cells = <0>; |
| 89 | + }; |
| 90 | + |
| 91 | + sfp2: sfp-p3 { |
| 92 | + compatible = "sff,sfp"; |
| 93 | + i2c-bus = <&i2c2>; |
| 94 | + los-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; |
| 95 | + mod-def0-gpio = <&gpio0 7 GPIO_ACTIVE_LOW>; |
| 96 | + tx-disable-gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; |
| 97 | + maximum-power-milliwatt = <2000>; |
| 98 | + #thermal-sensor-cells = <0>; |
| 99 | + }; |
| 100 | + |
| 101 | + sfp3: sfp-p4 { |
| 102 | + compatible = "sff,sfp"; |
| 103 | + i2c-bus = <&i2c3>; |
| 104 | + los-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; |
| 105 | + mod-def0-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>; |
| 106 | + tx-disable-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; |
| 107 | + maximum-power-milliwatt = <2000>; |
| 108 | + #thermal-sensor-cells = <0>; |
| 109 | + }; |
| 110 | +}; |
| 111 | + |
| 112 | +&i2c_mst1 { |
| 113 | + status = "okay"; |
| 114 | + |
| 115 | + /* SDA0-7 correspond to GPIO9-16 */ |
| 116 | + i2c0: i2c@0 { |
| 117 | + reg = <0>; |
| 118 | + }; |
| 119 | + i2c1: i2c@1 { |
| 120 | + reg = <1>; |
| 121 | + }; |
| 122 | + i2c2: i2c@2 { |
| 123 | + reg = <2>; |
| 124 | + }; |
| 125 | + i2c3: i2c@3 { |
| 126 | + reg = <3>; |
| 127 | + }; |
| 128 | +}; |
| 129 | + |
| 130 | +&spi0 { |
| 131 | + status = "okay"; |
| 132 | + |
| 133 | + flash@0 { |
| 134 | + compatible = "jedec,spi-nor"; |
| 135 | + reg = <0>; |
| 136 | + spi-max-frequency = <10000000>; |
| 137 | + |
| 138 | + partitions { |
| 139 | + compatible = "fixed-partitions"; |
| 140 | + #address-cells = <1>; |
| 141 | + #size-cells = <1>; |
| 142 | + |
| 143 | + /* stock is LOADER */ |
| 144 | + partition@0 { |
| 145 | + label = "u-boot"; |
| 146 | + reg = <0x0000000 0x00e0000>; |
| 147 | + read-only; |
| 148 | + }; |
| 149 | + |
| 150 | + /* stock is BDINFO */ |
| 151 | + partition@e0000 { |
| 152 | + label = "u-boot-env"; |
| 153 | + reg = <0x00e0000 0x0010000>; |
| 154 | + }; |
| 155 | + |
| 156 | + /* stock is SYSINFO */ |
| 157 | + partition@f0000 { |
| 158 | + label = "u-boot-env2"; |
| 159 | + reg = <0x00f0000 0x0010000>; |
| 160 | + read-only; |
| 161 | + }; |
| 162 | + |
| 163 | + /* stock is JFFS2_CFG */ |
| 164 | + partition@100000 { |
| 165 | + label = "jffs"; |
| 166 | + reg = <0x0100000 0x0100000>; |
| 167 | + }; |
| 168 | + |
| 169 | + /* stock is JFFS2_LOG */ |
| 170 | + partition@200000 { |
| 171 | + label = "jffs2"; |
| 172 | + reg = <0x0200000 0x0100000>; |
| 173 | + }; |
| 174 | + |
| 175 | + /* stock is RUNTIME */ |
| 176 | + partition@300000 { |
| 177 | + compatible = "openwrt,uimage", "denx,uimage"; |
| 178 | + label = "firmware"; |
| 179 | + reg = <0x0300000 0x0c00000>; |
| 180 | + }; |
| 181 | + |
| 182 | + /* stock is OEMINFO */ |
| 183 | + partition@f00000 { |
| 184 | + label = "oeminfo"; |
| 185 | + reg = <0x0f00000 0x0100000>; |
| 186 | + read-only; |
| 187 | + }; |
| 188 | + }; |
| 189 | + }; |
| 190 | +}; |
| 191 | + |
| 192 | +&mdio_bus0 { |
| 193 | + phy0: ethernet-phy@0 { |
| 194 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 195 | + reg = <0>; |
| 196 | + }; |
| 197 | + |
| 198 | + phy8: ethernet-phy@8 { |
| 199 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 200 | + realtek,smi-address = <1>; |
| 201 | + reg = <8>; |
| 202 | + }; |
| 203 | + |
| 204 | + phy16: ethernet-phy@16 { |
| 205 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 206 | + realtek,smi-address = <2>; |
| 207 | + reg = <16>; |
| 208 | + }; |
| 209 | + |
| 210 | + phy20: ethernet-phy@20 { |
| 211 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 212 | + realtek,smi-address = <3>; |
| 213 | + reg = <20>; |
| 214 | + }; |
| 215 | +}; |
| 216 | + |
| 217 | +&mdio_bus3 { |
| 218 | + phy24: ethernet-phy@24 { |
| 219 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 220 | + realtek,smi-address = <16>; |
| 221 | + reg = <24>; |
| 222 | + }; |
| 223 | + |
| 224 | + phy25: ethernet-phy@25 { |
| 225 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 226 | + realtek,smi-address = <17>; |
| 227 | + reg = <25>; |
| 228 | + }; |
| 229 | + |
| 230 | + phy26: ethernet-phy@26 { |
| 231 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 232 | + realtek,smi-address = <18>; |
| 233 | + reg = <26>; |
| 234 | + }; |
| 235 | + |
| 236 | + phy27: ethernet-phy@27 { |
| 237 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 238 | + realtek,smi-address = <19>; |
| 239 | + reg = <27>; |
| 240 | + }; |
| 241 | +}; |
| 242 | + |
| 243 | +&switch0 { |
| 244 | + ports { |
| 245 | + #address-cells = <1>; |
| 246 | + #size-cells = <0>; |
| 247 | + |
| 248 | + port@0 { |
| 249 | + reg = <0>; |
| 250 | + label = "lan1"; |
| 251 | + pcs-handle = <&serdes2>; |
| 252 | + phy-handle = <&phy0>; |
| 253 | + phy-mode = "1000base-x"; |
| 254 | + sfp = <&sfp0>; |
| 255 | + managed = "in-band-status"; |
| 256 | + led-set = <0>; |
| 257 | + }; |
| 258 | + |
| 259 | + port@8 { |
| 260 | + reg = <8>; |
| 261 | + label = "lan2"; |
| 262 | + pcs-handle = <&serdes3>; |
| 263 | + phy-handle = <&phy8>; |
| 264 | + phy-mode = "1000base-x"; |
| 265 | + sfp = <&sfp1>; |
| 266 | + managed = "in-band-status"; |
| 267 | + led-set = <0>; |
| 268 | + }; |
| 269 | + |
| 270 | + port@16 { |
| 271 | + reg = <16>; |
| 272 | + label = "lan3"; |
| 273 | + pcs-handle = <&serdes4>; |
| 274 | + phy-handle = <&phy16>; |
| 275 | + phy-mode = "1000base-x"; |
| 276 | + sfp = <&sfp2>; |
| 277 | + managed = "in-band-status"; |
| 278 | + led-set = <0>; |
| 279 | + }; |
| 280 | + |
| 281 | + port@20 { |
| 282 | + reg = <20>; |
| 283 | + label = "lan4"; |
| 284 | + pcs-handle = <&serdes5>; |
| 285 | + phy-handle = <&phy20>; |
| 286 | + phy-mode = "1000base-x"; |
| 287 | + sfp = <&sfp3>; |
| 288 | + managed = "in-band-status"; |
| 289 | + led-set = <0>; |
| 290 | + }; |
| 291 | + |
| 292 | + |
| 293 | + |
| 294 | + port@24 { |
| 295 | + reg = <24>; |
| 296 | + label = "lan5"; |
| 297 | + pcs-handle = <&serdes6>; |
| 298 | + phy-handle = <&phy24>; |
| 299 | + phy-mode = "usxgmii"; |
| 300 | + led-set = <0>; |
| 301 | + }; |
| 302 | + |
| 303 | + port@25 { |
| 304 | + reg = <25>; |
| 305 | + label = "lan6"; |
| 306 | + pcs-handle = <&serdes7>; |
| 307 | + phy-handle = <&phy25>; |
| 308 | + phy-mode = "usxgmii"; |
| 309 | + led-set = <0>; |
| 310 | + }; |
| 311 | + |
| 312 | + port@26 { |
| 313 | + reg = <26>; |
| 314 | + label = "lan7"; |
| 315 | + pcs-handle = <&serdes8>; |
| 316 | + phy-handle = <&phy26>; |
| 317 | + phy-mode = "usxgmii"; |
| 318 | + led-set = <0>; |
| 319 | + }; |
| 320 | + |
| 321 | + port@27 { |
| 322 | + reg = <27>; |
| 323 | + label = "lan8"; |
| 324 | + pcs-handle = <&serdes9>; |
| 325 | + phy-handle = <&phy27>; |
| 326 | + phy-mode = "usxgmii"; |
| 327 | + led-set = <0>; |
| 328 | + }; |
| 329 | + |
| 330 | + /* Internal SoC */ |
| 331 | + port@28 { |
| 332 | + ethernet = <ðernet0>; |
| 333 | + reg = <28>; |
| 334 | + phy-mode = "internal"; |
| 335 | + |
| 336 | + fixed-link { |
| 337 | + speed = <10000>; |
| 338 | + full-duplex; |
| 339 | + }; |
| 340 | + }; |
| 341 | + }; |
| 342 | +}; |
| 343 | + |
| 344 | +&thermal_zones { |
| 345 | + sfp-thermal { |
| 346 | + polling-delay-passive = <10000>; |
| 347 | + polling-delay = <10000>; |
| 348 | + thermal-sensors = <&sfp0>, <&sfp1>, <&sfp2>, <&sfp3>; |
| 349 | + trips { |
| 350 | + sfp-crit { |
| 351 | + temperature = <110000>; |
| 352 | + hysteresis = <1000>; |
| 353 | + type = "critical"; |
| 354 | + }; |
| 355 | + }; |
| 356 | + }; |
| 357 | +}; |
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