VOLT uses three analytical models to translate a microarchitectural configuration into real-world metrics without needing RTL synthesis or SPICE simulation. These models are what make the GA possible — evaluating 40 designs × 15 generations would be impractical with real CAD tools.
All models live in src/volt/model/.
The frequency model estimates the maximum clock frequency (Fmax) by computing the critical path delay through the pipeline. It uses FO4 (Fan-Out of 4) inverter delays as the fundamental unit — the standard approach in academic computer architecture.
| Node | FO4 (ps) |
|---|---|
| ≤ 1.5 nm | 1.2 |
| ≤ 3 nm | 1.6 |
| ≤ 5 nm | 2.0 |
| ≤ 7 nm | 2.5 |
| ≤ 10 nm | 3.0 |
| ≤ 14 nm | 4.0 |
| ≤ 22 nm | 5.5 |
| > 22 nm | 7.0 |
The pipeline is divided into 7 stages. Each is estimated with a formula that captures the dominant path:
| Stage | FO4 Formula | 5 nm Example |
|---|---|---|
| Fetch | I$ tag + I$ data*0.5 + BTB + TLB |
14.2 |
| Decode | 4.0 + decode_width * 1.5 |
10.0 |
| Rename | 3 (RAT) + 2 (freelist) + 2 (PRF read) |
7.0 |
| Issue/Sel | CAM_match + wakeup*0.6 + pri_encoder*0.4 |
16.5 |
| Execute | max(ALU, mul, AGU) + bypass_mux |
12.8 |
| Mem | D$ tag + D$ data*0.7 + LSQ CAM*0.5 |
13.1 |
| Commit | ROB_read(entries) |
5.0 |
Real chips are dominated by wire delay, not just gate delay. VOLT models this as:
let wire_fo4 = 25.0 + (cache_mb as f64).sqrt() * 30.0;This captures the growing cost of global wires as cache size increases. Additional overheads:
- Sequential logic: 10 FO4 (flip-flop setup + clk-to-Q)
- Clock skew: 6 FO4
- Complexity penalty:
(fetch_width / 4 - 1).max(0) * 5FO4 - PVT margin: 1.30× (process, voltage, temperature variation)
- Clock jitter: 1.05×
let max_stage_fo4 = max of all 7 stages;
let total_fo4 = max_stage_fo4 + 10 (seq) + 6 (skew) + wire_fo4 + complexity;
let total_delay_ps = total_fo4 * fo4_ps * 1.30 (PVT) * 1.05 (jitter);
let fmax_ghz = 1000.0 / total_delay_ps;For the best GA config (8-wide, 5 nm): 4.71 GHz.
For narrow machines (fetch ≤ 4), the issue/select stage (CAM match + wakeup + priority encoder) is usually the critical path. For wide machines (fetch ≥ 8), fetch (large L1I + BTB + TLB) and wire delay dominate.
The area model sums per-structure area estimates, all scaled by the process node's SRAM density:
| Node | SRAM Density (mm²/KB) |
|---|---|
| 3 nm | 0.015 |
| 5 nm | 0.025 |
| 7 nm | 0.040 |
| 10 nm | 0.065 |
| > 10 nm | 0.100 |
| Structure | Formula | 5 nm, 8-wide Example |
|---|---|---|
| L1I / L1D | size_kb * density * (1 + assoc * 0.05) |
32KB×8a → 1.12 mm² each |
| L2 | size_kb * density * (1 + assoc * 0.05) |
0 KB → 0 mm² |
| ROB | entries * 0.003 |
256 → 0.77 mm² |
| Issue Queue | entries * 16 * 0.0005 |
32 → 0.26 mm² |
| Int PRF | entries * 64 * 0.0002 |
192 → 2.46 mm² |
| FP PRF | entries * 64 * 0.0002 |
192 → 2.46 mm² |
| ALUs | count * 0.02 |
4 → 0.08 mm² |
| Load/Store units | (load + store) * 0.015 |
2+2 → 0.06 mm² |
| FP units | count * 0.08 |
2 → 0.16 mm² |
| BTB | entries * 0.001 |
256 → 0.26 mm² |
| Branch Predictor | entries * 0.0005 |
4096 → 2.05 mm² |
| LSQ | (load + store) * 0.002 |
32+24 → 0.11 mm² |
For the best GA config: 10.65 mm² total.
Memory (L1I+L1D): 2.24 mm² (21%)
Int PRF: 2.46 mm² (23%)
FP PRF: 2.46 mm² (23%)
Branch Predictor: 2.05 mm² (19%)
ROB: 0.77 mm² (7%)
BTB: 0.26 mm² (2%)
IQ: 0.26 mm² (2%)
Other (ALUs, LSQ...): 0.15 mm² (1%)
The PRF and branch predictor dominate — which makes sense for a wide OoO machine.
Power is split into dynamic (switching activity) and leakage (static).
| Node | VDD |
|---|---|
| 3 nm | 0.70 V |
| 5 nm | 0.80 V |
| 7 nm | 0.90 V |
| 10 nm | 1.00 V |
| > 10 nm | 1.10 V |
cache_dynamic = cache_size_kb * 0.01 * (freq / 2.0) * (VDD / 0.9)^2
logic_dynamic = gate_count_k * 0.005 * (freq / 2.0) * (VDD / 0.9)^2 * 0.3Where gate_count_k is estimated from the area of non-cache structures (~20K gates/mm²).
leakage = area_mm2 * 0.05 * leak_factor * (VDD / 0.9)Leakage factor scales with process:
| Node | Leakage Factor |
|---|---|
| 3 nm | 1.8 (higher leakage) |
| 5 nm | 1.4 |
| 7 nm | 1.0 |
| 10 nm | 0.7 |
| > 10 nm | 0.5 |
For the best GA config: 2.42 W total (dynamic + leakage).
These are analytical estimates, not RTL synthesis results. Key simplifications:
- No routing congestion: Wire delay is a global average, not per-net.
- No clock tree power: Dynamic power is estimated from gate count, not a synthesized clock tree.
- Single critical path: The frequency model assumes one critical path per stage; real designs have many.
- No temperature feedback: Power → temperature → leakage feedback loop is not modeled.
- DRAM is instant and free: No DRAM latency or bandwidth model beyond a fixed miss penalty.
Despite these simplifications, the models produce internally consistent rankings — a configuration that scores higher on the VOLT model will generally be better in a real design. The GA optimizes relative fitness, not absolute accuracy.