Added VHDL type-correctness fixes and structural validation tests

- Fixed arithmetic expressions to wrap results in std_logic_vector()
- Fixed numeric literals to emit as to_unsigned/to_signed instead of bare c_N identifiers
- Fixed bitwise ops and unary NOT to return std_logic_vector
- Added per-entity library/use preamble for multi-entity files
- Added 5 structural VHDL validation tests (balanced constructs, declared signals, type wrapping)
- Added ci_validate.c exercising the full supported C subset
- Upgraded actions/checkout@v4 to v5 (Node 20 deprecation fix)

Author: byteshiftlabs

.github/workflows/ci.yml

@@ -13,7 +13,7 @@ jobs:
 
     steps:
       - name: Checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@v5
 
       - name: Install dependencies
         run: |

README.md

@@ -3,7 +3,7 @@
 ![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)
 ![Language: C11](https://img.shields.io/badge/Language-C11-blue.svg)
 ![Build: CMake](https://img.shields.io/badge/Build-CMake_3.14+-orange.svg)
-![Tests: 75 passing](https://img.shields.io/badge/Tests-75_passing-brightgreen.svg)
+![Tests: 81 passing](https://img.shields.io/badge/Tests-81_passing-brightgreen.svg)
 ![cppcheck: clean](https://img.shields.io/badge/cppcheck-clean-brightgreen.svg)
 
 Minimal C subset → VHDL translator
@@ -57,7 +57,7 @@ begin
     if reset = '1' then
       sum <= (others => '0');
     elsif rising_edge(clk) then
-      sum <= a + b;
+      sum <= std_logic_vector(unsigned(a) + unsigned(b));
       result <= sum;
     end if;
   end process;
@@ -73,7 +73,7 @@ Each C function becomes a VHDL entity with clock/reset ports, input parameters a
 - Self-contained functions with return value propagation, plus structs and arrays
 - VHDL entity/architecture generation with clock/reset, signals, and synchronous processes
 - Multi-level error diagnostics (error/warning/note across 5 categories)
-- 76 unit, integration, and edge case tests (GoogleTest)
+- 81 unit, integration, structural validation, and edge case tests (GoogleTest)
 
 ## Requirements
 
@@ -115,7 +115,7 @@ examples/      — Sample C input files
 - No pointer support
 - No `switch/case` or `do-while`
 - Function calls are parsed, but cross-function hardware wiring is not yet synthesized. Multi-function files emit independent entities, so keep hardware-generating examples self-contained.
-- Generated VHDL targets the currently supported C subset, but automated simulator verification is not yet part of the test/CI flow. The output is also unoptimized — no resource sharing, no pipelining, no constant folding (see [ROADMAP.md](ROADMAP.md) Phase 4 for planned optimizations)
+- Generated VHDL targets the currently supported C subset. Structural well-formedness is verified by self-contained validation tests (balanced constructs, declared signals, proper type wrapping). The output is unoptimized — no resource sharing, no pipelining, no constant folding (see [ROADMAP.md](ROADMAP.md) Phase 4 for planned optimizations)
 
 ## Documentation
 

docs/source/index.rst

@@ -30,7 +30,7 @@ Features
 - Self-contained functions with return value propagation, plus structs with field access and arrays with indexing
 - VHDL entity/architecture generation with clock/reset, signals, and synchronous processes
 - Multi-level error diagnostics with colored output (error/warning/note across 5 categories)
-- 76 unit, integration, and edge case tests (GoogleTest)
+- 81 unit, integration, structural validation, and edge case tests (GoogleTest)
 
 See :doc:`examples` for C-to-VHDL translation samples and :doc:`modules` for the
 complete source code reference.

examples/ci_validate.c

@@ -0,0 +1,80 @@
+// CI validation input — each function here must produce analyzable VHDL.
+// This file exercises the core supported C subset: arithmetic, conditionals,
+// loops (while, for, nested), bitwise ops, break/continue, and return values.
+
+int add(int a, int b) {
+    int sum = a + b;
+    return sum;
+}
+
+int bitwise_ops(int x, int y) {
+    int a = x & y;
+    int o = x | y;
+    int xr = x ^ y;
+    return a + o + xr;
+}
+
+int negate(int x) {
+    return -x;
+}
+
+int max_val(int a, int b) {
+    if (a > b) {
+        return a;
+    } else {
+        return b;
+    }
+}
+
+int while_sum(int n) {
+    int sum = 0;
+    int i = 0;
+    while (i < n) {
+        sum = sum + i;
+        i = i + 1;
+    }
+    return sum;
+}
+
+int nested_loops(int outer, int inner) {
+    int total = 0;
+    int i = 0;
+    while (i < outer) {
+        int j = 0;
+        while (j < inner) {
+            total = total + i + j;
+            j = j + 1;
+        }
+        i = i + 1;
+    }
+    return total;
+}
+
+int for_loop(int n) {
+    int s = 0;
+    for (int i = 0; i < n; i++) {
+        s = s + i;
+    }
+    return s;
+}
+
+int break_continue(int n) {
+    int total = 0;
+    int i = 0;
+    while (i < n) {
+        if (i == 3) {
+            i = i + 1;
+            continue;
+        }
+        if (total > 100) {
+            break;
+        }
+        total = total + i;
+        i = i + 1;
+    }
+    return total;
+}
+
+int comparison_return(int a, int b) {
+    return a == b;
+}

src/codegen/codegen_vhdl_expressions.c

@@ -63,61 +63,63 @@ void generate_binary_expression(ASTNode *node, void (*node_generator)(ASTNode*))
         return;
     }
 
-    // Bitwise operations
+    // Bitwise operations — result is unsigned, wrap in std_logic_vector
     if (strcmp(op, OP_BITWISE_AND) == 0)
     {
-        emit_raw("unsigned(");
+        emit_raw("std_logic_vector(unsigned(");
         node_generator(left_operand);
         emit_raw(") and unsigned(");
         node_generator(right_operand);
-        emit_raw(")");
+        emit_raw("))");
         return;
     }
 
     if (strcmp(op, OP_BITWISE_OR) == 0)
     {
-        emit_raw("unsigned(");
+        emit_raw("std_logic_vector(unsigned(");
         node_generator(left_operand);
         emit_raw(") or unsigned(");
         node_generator(right_operand);
-        emit_raw(")");
+        emit_raw("))");
         return;
     }
 
     if (strcmp(op, OP_BITWISE_XOR) == 0)
     {
-        emit_raw("unsigned(");
+        emit_raw("std_logic_vector(unsigned(");
         node_generator(left_operand);
         emit_raw(") xor unsigned(");
         node_generator(right_operand);
-        emit_raw(")");
+        emit_raw("))");
         return;
     }
 
     if (strcmp(op, OP_SHIFT_LEFT) == 0)
     {
-        emit_raw("shift_left(unsigned(");
+        emit_raw("std_logic_vector(shift_left(unsigned(");
         node_generator(left_operand);
         emit_raw("), to_integer(unsigned(");
         node_generator(right_operand);
-        emit_raw("))))");
+        emit_raw(")))))");
         return;
     }
 
     if (strcmp(op, OP_SHIFT_RIGHT) == 0)
     {
-        emit_raw("shift_right(unsigned(");
+        emit_raw("std_logic_vector(shift_right(unsigned(");
         node_generator(left_operand);
         emit_raw("), to_integer(unsigned(");
         node_generator(right_operand);
-        emit_raw("))))");
+        emit_raw(")))))");
         return;
     }
 
-    // Fallback: arithmetic or unknown operators
-    node_generator(left_operand);
+    // Fallback: arithmetic — use typed operands and wrap in std_logic_vector
+    emit_raw("std_logic_vector(");
+    emit_typed_operand(left_operand, 0, node_generator);
     emit_raw(" %s ", op);
-    node_generator(right_operand);
+    emit_typed_operand(right_operand, 0, node_generator);
+    emit_raw(")");
 }
 
 // Map C identifiers, array accesses, struct fields, and literals to VHDL signals.
@@ -141,15 +143,26 @@ void generate_expression(ASTNode *node)
     {
         if (isalpha(node->value[1]) || node->value[1] == '_')
         {
-            emit_raw("-unsigned(%s)", node->value + 1);
+            emit_raw("std_logic_vector(0 - unsigned(%s))", node->value + 1);
         }
         else
         {
+            emit_raw("std_logic_vector(");
             emit_signed_cast(node->value);
+            emit_raw(")");
         }
         return;
     }
 
+    // Positive numeric literals: emit as std_logic_vector(to_unsigned(N, BIT_WIDTH))
+    if (is_numeric_literal(node->value))
+    {
+        emit_raw("std_logic_vector(");
+        emit_unsigned_cast(node->value);
+        emit_raw(")");
+        return;
+    }
+
     // Struct field encoded as a__b -> a.b
     if (strstr(node->value, "__") != NULL)
     {
@@ -204,9 +217,9 @@ void generate_unary_operation(ASTNode *node, void (*node_generator)(ASTNode*))
     }
     else if (strcmp(node->value, OP_BITWISE_NOT) == 0)
     {
-        emit_raw("not unsigned(");
+        emit_raw("std_logic_vector(not unsigned(");
         node_generator(inner_expression);
-        emit_raw(")");
+        emit_raw("))");
     }
     else
     {

src/codegen/codegen_vhdl_main.c

@@ -97,17 +97,15 @@ static void generate_node(ASTNode *node)
     }
 }
 
-// Emit VHDL library imports and struct type declarations, then generate
+// Emit VHDL struct type declarations, then generate
 // each function as an independent entity/architecture pair.
+// Library/use clauses are emitted per-entity so that every design unit
+// in the file has the required imports (VHDL context clauses apply only
+// to the immediately following design unit).
 static void generate_program(ASTNode *node)
 {
-    // Emit VHDL header
     emit_line("-- VHDL generated by gates");
     emit_newline();
-    emit_line("library IEEE;");
-    emit_line("use IEEE.STD_LOGIC_1164.ALL;");
-    emit_line("use IEEE.NUMERIC_STD.ALL;");
-    emit_newline();
 
     // Emit struct type declarations
     emit_all_struct_declarations();
@@ -159,6 +157,11 @@ static void emit_entity_declaration(const char *function_name,
                                     ASTNode *parameters[], int parameter_count,
                                     ASTNode *node)
 {
+    // Each design unit requires its own library/use context clause
+    emit_line("library IEEE;");
+    emit_line("use IEEE.STD_LOGIC_1164.ALL;");
+    emit_line("use IEEE.NUMERIC_STD.ALL;");
+    emit_newline();
     emit_line("-- Function: %s", function_name);
     emit_indented("entity ");
     emit_safe_identifier(function_name);