-
Notifications
You must be signed in to change notification settings - Fork 0
Open
Labels
arch: x86x86 specific featuresx86 specific featurestarget: kernelKernel related featuresKernel related featurestype: enhancementImprove an already existing featureImprove an already existing feature
Description
Message Signaled Interrupts
Message signaled interrupts (MSIs) are explicitely required to support the PCI Express standard. For convenience we currently use the legacy PCI interrupts pins (A,B,C,D), but should eventually switch to the more modern design.
MSIs are not supported by the 8259 PIC (the interrupt controller we currently use on the x86 platform), and require us to add support for the LAPIC.
Questions
- Should we fallback to using legacy interrupts when no APIC is present? (should never be the case but we never know 🤷🏻)
TODO
- Switch to the IO/APIC for interrupt handling
- Add MSI support to the PCI subsystem
Links
- Intel developer's manual - 11: APIC
- PCI specification - 6.8: Message signaled interrupts
Metadata
Metadata
Assignees
Labels
arch: x86x86 specific featuresx86 specific featurestarget: kernelKernel related featuresKernel related featurestype: enhancementImprove an already existing featureImprove an already existing feature