ncr_fix_reference.patch

diff --git a/rtl/ncr5380.sv b/rtl/ncr5380.sv
index 7375443..c804a0d 100644
--- a/rtl/ncr5380.sv
+++ b/rtl/ncr5380.sv
@@ -440,6 +440,7 @@ module ncr5380
 	wire [7:0] empty_cd_dout;
 	wire [15:0] empty_cd_dout_pair;
 	wire [15:0] empty_cd_dout_pair_next;
+	wire [2:0] empty_cd_phase;
 	wire empty_cd_active = ENABLE_EMPTY_CD && empty_cd_bsy;
 
 	scsi_empty_cd #(.ID(3'd3)) empty_cd
@@ -447,6 +448,7 @@ module ncr5380
 		.clk    ( clk ),
 		.rst    ( scsi_rst ),
 		.sel    ( ENABLE_EMPTY_CD ? scsi_sel : 1'b0 ),
+		.bus_busy ( |target_bsy ),
 		.ack    ( scsi_ack ),
 		.bsy    ( empty_cd_bsy  ),
 		.msg    ( empty_cd_msg  ),
@@ -456,7 +458,8 @@ module ncr5380
 		.dout   ( empty_cd_dout ),
 		.dout_pair ( empty_cd_dout_pair ),
 		.dout_pair_next ( empty_cd_dout_pair_next ),
-		.din    ( scsi_bus_data )
+		.din    ( scsi_bus_data ),
+		.dbg_phase ( empty_cd_phase )
 	);
 
 	generate
@@ -468,6 +471,9 @@ module ncr5380
 				.clk    ( clk ),
 				.rst    ( scsi_rst ),
 				.sel    ( scsi_sel ),
+				// Own bsy bit is harmless here: the selection gate is only
+				// evaluated in PHASE_IDLE, where this target's bsy is 0.
+				.bus_busy ( (|target_bsy) | empty_cd_active ),
 				.atn    ( scsi_atn ),
 
 				.ack    ( scsi_ack ),
@@ -525,12 +531,13 @@ module ncr5380
 	                    target_mounted[1:0], icr[`ICR_A_DATA],
 	                    scsi_bus_data };
 
-	// NOTE: the 2'b0 gap at [7:6] makes this a full 16 bits so the phase fields
-	// land at [13:11]/[10:8] as the header comment (and dbg_min) expect. Without
-	// it the 14-bit concat right-justified and shifted the phases down 2 bits,
-	// garbling the decoded phase (the "phase 6/7" red herring, fixed 2026-06-10).
-	assign dbg_scsi2 = { 2'b0, target_phase[1], target_phase[0],
-	                     2'b0, io_rd[1:0], io_wr[1:0], io_ack[1:0] };
+	// NOTE: the previously-spare bits [15:14]/[7:6] now carry the empty-CD
+	// target's live phase + REQ (it had zero probe visibility while it wedged
+	// the 2026-06-10 Welcome hang). Phase fields for the disk targets remain
+	// at [13:11]/[10:8] as dbg_min expects.
+	//   [15:14] = empty_cd_phase[1:0]   [7] = empty_cd_phase[2]   [6] = empty_cd_req
+	assign dbg_scsi2 = { empty_cd_phase[1:0], target_phase[1], target_phase[0],
+	                     empty_cd_phase[2], empty_cd_req, io_rd[1:0], io_wr[1:0], io_ack[1:0] };
 
 	// Capture whichever target is in the WRITE data phase (PHASE_DATA_IN=3).
 	// The bench's disk is actually target1 (ID5), not target0 — the result