From 7487b47ec4034752c2b6e8797e16efe101eeb5a9 Mon Sep 17 00:00:00 2001 From: drewbabel <122849144+drewbabel@users.noreply.github.com> Date: Thu, 30 Jul 2026 23:09:52 -0700 Subject: [PATCH] [docs] Drop the unused waveform assets --- docs/loopback_waveform.py | 90 -- docs/loopback_waveform.svg | 2394 ------------------------------------ docs/wave_tb.sv | 79 -- 3 files changed, 2563 deletions(-) delete mode 100644 docs/loopback_waveform.py delete mode 100644 docs/loopback_waveform.svg delete mode 100644 docs/wave_tb.sv diff --git a/docs/loopback_waveform.py b/docs/loopback_waveform.py deleted file mode 100644 index 63e0da9..0000000 --- a/docs/loopback_waveform.py +++ /dev/null @@ -1,90 +0,0 @@ -# Renders loopback_waveform.svg (the README waveform) from a simulation CSV, wave.csv -# Regenerate the whole figure from the repo root: -# iverilog -g2012 -s wave_tb -o wave.vvp rtl/*.sv docs/wave_tb.sv && vvp wave.vvp -# python3 docs/loopback_waveform.py -import csv -import matplotlib -matplotlib.use('Agg') -import matplotlib.pyplot as plt - -rows = list(csv.DictReader(open('wave.csv'))) -def _si(s): - s = s.strip() - return int(s) if s.lstrip('-').isdigit() else -1 # -1 = unknown (x/z) -def col(n): return [_si(r[n]) for r in rows] -txv, txr, txs = col('tx_valid'), col('tx_ready'), col('tx_serial') -rxv, rxe, rxd = col('rx_valid'), col('rx_error'), col('rx_data') -N = len(rows) - -# Window: a few cycles before tx_valid to a few after rx_valid -first_txv = next((i for i, v in enumerate(txv) if v == 1), 0) -rxv_idx = next((i for i, v in enumerate(rxv) if v == 1), N - 1) -a = max(0, first_txv - 6) -b = min(N, rxv_idx + 12) -x = list(range(a, b + 1)) - -bits = [('tx_valid', txv), ('tx_ready', txr), ('tx_serial', txs), - ('rx_valid', rxv), ('rx_error', rxe)] -nlanes = len(bits) + 1 # + rx_data bus -lane_h, gap = 0.72, 0.55 -pitch = lane_h + gap - -fig, ax = plt.subplots(figsize=(13, 0.62 * nlanes + 1.4)) -SIG, GREY = '#08306b', '#dfe6ee' - -def base_of(lane_from_top): - return (nlanes - 1 - lane_from_top) * pitch - -for i, (name, vals) in enumerate(bits): - base = base_of(i) - seg = vals[a:b] + [vals[b - 1]] - ax.axhline(base, color=GREY, lw=0.8, zorder=0) - ax.step(x, [base + max(v, 0) * lane_h for v in seg], where='post', color=SIG, lw=1.8, zorder=3) - ax.text(a - 20, base + lane_h / 2, name, ha='center', va='center', - fontsize=11, family='monospace') - -# rx_data as a bus lane (bottom) -base = base_of(nlanes - 1) -top, bot = base + lane_h, base -ax.text(a - 20, base + lane_h / 2, 'rx_data', ha='center', va='center', - fontsize=11, family='monospace') -seg_start = a -for i in range(a + 1, b + 1): - if i == b or rxd[i] != rxd[i - 1]: - val = rxd[seg_start] - ax.plot([seg_start, i], [top, top], color=SIG, lw=1.7, zorder=3) - ax.plot([seg_start, i], [bot, bot], color=SIG, lw=1.7, zorder=3) - ax.plot([seg_start, seg_start], [bot, top], color=SIG, lw=1.2, zorder=3) - ax.plot([i, i], [bot, top], color=SIG, lw=1.2, zorder=3) - if i - seg_start >= 4: - label = "0x??" if val < 0 else f"0x{val:02X}" - ax.text((seg_start + i) / 2, base + lane_h / 2, label, - ha='center', va='center', fontsize=9.5, family='monospace', color=SIG) - seg_start = i - -# Annotate the tx_serial frame fields (start / D0..D7 / stop) -CPB = 32 # Clocks per bit in this scaled demo -ts_base = base_of(2) -start_idx = next((i for i in range(a + 1, b) if txs[i] == 0 and txs[i - 1] == 1), None) -if start_idx is not None: - fields = ['start', 'D0', 'D1', 'D2', 'D3', 'D4', 'D5', 'D6', 'D7', 'stop'] - for k, lab in enumerate(fields): - x0 = start_idx + k * CPB - ax.axvline(x0, color='#b7c4d4', lw=0.7, ls=(0, (3, 3)), zorder=1) - ax.text(x0 + CPB / 2, ts_base + lane_h + 0.16, lab, ha='center', va='bottom', - fontsize=7.5, color='#6b7d90', family='monospace') - ax.axvline(start_idx + 10 * CPB, color='#b7c4d4', lw=0.7, ls=(0, (3, 3)), zorder=1) - -ax.set_xlim(a - 34, b + 1) -ax.set_ylim(-0.4, base_of(0) + lane_h + 0.4) -ax.set_yticks([]) -ax.set_xlabel('clock cycles', fontsize=10) -xt = list(range(a, b + 1, 8)) -ax.set_xticks(xt) -ax.set_xticklabels([str(t - a) for t in xt], fontsize=9) -for s in ('top', 'right', 'left'): - ax.spines[s].set_visible(False) -ax.set_title('UART Loopback of a Single Frame', fontsize=13, pad=16) -plt.tight_layout() -plt.savefig('loopback_waveform.svg', bbox_inches='tight', facecolor='white') -print('wrote loopback_waveform.svg; window cycles', a, '..', b, 'rx_valid at', rxv_idx) diff --git a/docs/loopback_waveform.svg b/docs/loopback_waveform.svg deleted file mode 100644 index bae52ba..0000000 --- a/docs/loopback_waveform.svg +++ /dev/null @@ -1,2394 +0,0 @@ - - - - - - - - 2026-07-07T18:44:56.053769 - image/svg+xml - - - Matplotlib v3.10.3, https://matplotlib.org/ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/docs/wave_tb.sv b/docs/wave_tb.sv deleted file mode 100644 index c023c09..0000000 --- a/docs/wave_tb.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ns / 1ps -// Throwaway loopback testbench that generates wave.csv for the README waveform figure -// Baud is scaled to 32 clocks per bit so one whole frame fits in a readable image -// -// Regenerate the CSV from the repo root: -// iverilog -g2012 -s wave_tb -o wave.vvp rtl/*.sv docs/wave_tb.sv && vvp wave.vvp -// then render the PNG with docs/loopback_waveform.py -module wave_tb; - logic clk = 0, rst_n = 0; - logic [7:0] tx_data; - logic tx_valid, tx_ready, serial, rx_valid, rx_error; - logic [7:0] rx_data; - - uart #( - .CLK_FREQ_HZ(320_000), - .BAUD_RATE (10_000), - .OVERSAMPLE (16), - .DATA_BITS (8) - ) dut ( - .clk(clk), - .rst_n(rst_n), - .tx_data(tx_data), - .tx_valid(tx_valid), - .tx_ready(tx_ready), - .tx_serial(serial), - .rx_serial(serial), // External loopback - .rx_data(rx_data), - .rx_valid(rx_valid), - .rx_error(rx_error) - ); - - always #5 clk = ~clk; // 10 ns period - - integer f; - initial begin - f = $fopen("wave.csv", "w"); - $fwrite(f, "t,tx_valid,tx_ready,tx_serial,rx_valid,rx_data,rx_error\n"); - tx_data = 8'hA5; - tx_valid = 1'b0; - repeat (4) @(posedge clk); - rst_n = 1'b1; - @(posedge clk); - wait (tx_ready); - @(posedge clk); - #1 tx_valid = 1'b1; - @(posedge clk); - #1 tx_valid = 1'b0; - end - - // Sample every clock into the CSV - always @(posedge clk) - $fwrite( - f, - "%0t,%b,%b,%b,%b,%0d,%b\n", - $time, - tx_valid, - tx_ready, - serial, - rx_valid, - rx_data, - rx_error - ); - - // Stop a little after the received-byte strobe - initial begin - @(posedge rx_valid); - repeat (20) @(posedge clk); - $fclose(f); - $finish; - end - - // Safety timeout - initial begin - #200000; - $fclose(f); - $display("TIMEOUT: rx_valid never fired"); - $finish; - end -endmodule